arch/tile/kernel/vmlinux.lds.S

   1 #include <asm-generic/vmlinux.lds.h>
   2 #include <asm/page.h>
   3 #include <asm/cache.h>
   4 #include <asm/thread_info.h>
   5 #include <hv/hypervisor.h>
   6
   7 /* Text loads starting from the supervisor interrupt vector address. */
   8 #define TEXT_OFFSET MEM_SV_START
   9
  10 OUTPUT_ARCH(tile)
  11 ENTRY(_start)
  12 jiffies = jiffies_64;
  13
  14 PHDRS
  15 {
  16   intrpt PT_LOAD ;
  17   text PT_LOAD ;
  18   data PT_LOAD ;
  19 }
  20 SECTIONS
  21 {
  22   /* Text is loaded with a different VA than data; start with text. */
  23   #undef LOAD_OFFSET
  24   #define LOAD_OFFSET TEXT_OFFSET
  25
  26   /* Interrupt vectors */
  27   .intrpt (LOAD_OFFSET) : AT ( 0 )   /* put at the start of physical memory */
  28   {
  29     _text = .;
  30     *(.intrpt)
  31   } :intrpt =0
  32
  33   /* Hypervisor call vectors */
  34   . = ALIGN(0x10000);
  35   .hvglue : AT (ADDR(.hvglue) - LOAD_OFFSET) {
  36     *(.hvglue)
  37   } :NONE
  38
  39   /* Now the real code */
  40   . = ALIGN(0x20000);
  41   _stext = .;
  42   .text : AT (ADDR(.text) - LOAD_OFFSET) {
  43     HEAD_TEXT
  44     SCHED_TEXT
  45     LOCK_TEXT
  46     KPROBES_TEXT
  47     IRQENTRY_TEXT
  48     SOFTIRQENTRY_TEXT
  49     __fix_text_end = .;   /* tile-cpack won't rearrange before this */
  50     ALIGN_FUNCTION();
  51     *(.hottext*)
  52     TEXT_TEXT
  53     *(.text.*)
  54     *(.coldtext*)
  55     *(.fixup)
  56     *(.gnu.warning)
  57   } :text =0
  58   _etext = .;
  59
  60   /* "Init" is divided into two areas with very different virtual addresses. */
  61   INIT_TEXT_SECTION(PAGE_SIZE)
  62
  63   /* Now we skip back to PAGE_OFFSET for the data. */
  64   . = (. - TEXT_OFFSET + PAGE_OFFSET);
  65   #undef LOAD_OFFSET
  66   #define LOAD_OFFSET PAGE_OFFSET
  67
  68   . = ALIGN(PAGE_SIZE);
  69   __init_begin = .;
  70   INIT_DATA_SECTION(16) :data =0
  71   PERCPU_SECTION(L2_CACHE_BYTES)
  72   . = ALIGN(PAGE_SIZE);
  73   __init_end = .;
  74
  75   _sdata = .;                   /* Start of data section */
  76   RO_DATA_SECTION(PAGE_SIZE)
  77   RW_DATA_SECTION(L2_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
  78   _edata = .;
  79
  80   EXCEPTION_TABLE(L2_CACHE_BYTES)
  81   NOTES
  82
  83
  84   BSS_SECTION(8, PAGE_SIZE, 1)
  85   _end = . ;
  86
  87   STABS_DEBUG
  88   DWARF_DEBUG
  89
  90   DISCARDS
  91 }