arch/x86/include/asm/mach-default/mach_apic.h

   1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
   2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
   3
   4 #ifdef CONFIG_X86_LOCAL_APIC
   5
   6 #include <mach_apicdef.h>
   7 #include <asm/smp.h>
   8
   9 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
  10
  11 static inline const cpumask_t *target_cpus(void)
  12 {
  13 #ifdef CONFIG_SMP
  14         return &cpu_online_map;
  15 #else
  16         return &cpumask_of_cpu(0);
  17 #endif
  18 }
  19
  20 #define NO_BALANCE_IRQ (0)
  21 #define esr_disable (0)
  22
  23 #ifdef CONFIG_X86_64
  24 #include <asm/genapic.h>
  25 #define INT_DELIVERY_MODE (genapic->int_delivery_mode)
  26 #define INT_DEST_MODE (genapic->int_dest_mode)
  27 #define TARGET_CPUS       (genapic->target_cpus())
  28 #define apic_id_registered (genapic->apic_id_registered)
  29 #define init_apic_ldr (genapic->init_apic_ldr)
  30 #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
  31 #define cpu_mask_to_apicid_and (genapic->cpu_mask_to_apicid_and)
  32 #define phys_pkg_id     (genapic->phys_pkg_id)
  33 #define vector_allocation_domain    (genapic->vector_allocation_domain)
  34 #define read_apic_id()  (GET_APIC_ID(apic_read(APIC_ID)))
  35 #define send_IPI_self (genapic->send_IPI_self)
  36 #define wakeup_secondary_cpu (genapic->wakeup_cpu)
  37 extern void setup_apic_routing(void);
  38 #else
  39 #define INT_DELIVERY_MODE dest_LowestPrio
  40 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
  41 #define TARGET_CPUS (target_cpus())
  42 #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
  43 /*
  44  * Set up the logical destination ID.
  45  *
  46  * Intel recommends to set DFR, LDR and TPR before enabling
  47  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  48  * document number 292116).  So here it goes...
  49  */
  50 static inline void init_apic_ldr(void)
  51 {
  52         unsigned long val;
  53
  54         apic_write(APIC_DFR, APIC_DFR_VALUE);
  55         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  56         val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
  57         apic_write(APIC_LDR, val);
  58 }
  59
  60 static inline int apic_id_registered(void)
  61 {
  62         return physid_isset(read_apic_id(), phys_cpu_present_map);
  63 }
  64
  65 static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
  66 {
  67         return cpus_addr(*cpumask)[0];
  68 }
  69
  70 static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask,
  71                                               const cpumask_t *andmask)
  72 {
  73         unsigned long mask1 = cpus_addr(*cpumask)[0];
  74         unsigned long mask2 = cpus_addr(*andmask)[0];
  75
  76         return (unsigned int)(mask1 & mask2);
  77 }
  78
  79 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
  80 {
  81         return cpuid_apic >> index_msb;
  82 }
  83
  84 static inline void setup_apic_routing(void)
  85 {
  86 #ifdef CONFIG_X86_IO_APIC
  87         printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
  88                                         "Flat", nr_ioapics);
  89 #endif
  90 }
  91
  92 static inline int apicid_to_node(int logical_apicid)
  93 {
  94 #ifdef CONFIG_SMP
  95         return apicid_2_node[hard_smp_processor_id()];
  96 #else
  97         return 0;
  98 #endif
  99 }
 100
 101 static inline void vector_allocation_domain(int cpu, cpumask_t *retmask)
 102 {
 103         /* Careful. Some cpus do not strictly honor the set of cpus
 104          * specified in the interrupt destination when using lowest
 105          * priority interrupt delivery mode.
 106          *
 107          * In particular there was a hyperthreading cpu observed to
 108          * deliver interrupts to the wrong hyperthread when only one
 109          * hyperthread was specified in the interrupt desitination.
 110          */
 111         *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
 112 }
 113 #endif
 114
 115 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
 116 {
 117         return physid_isset(apicid, bitmap);
 118 }
 119
 120 static inline unsigned long check_apicid_present(int bit)
 121 {
 122         return physid_isset(bit, phys_cpu_present_map);
 123 }
 124
 125 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
 126 {
 127         return phys_map;
 128 }
 129
 130 static inline int multi_timer_check(int apic, int irq)
 131 {
 132         return 0;
 133 }
 134
 135 /* Mapping from cpu number to logical apicid */
 136 static inline int cpu_to_logical_apicid(int cpu)
 137 {
 138         return 1 << cpu;
 139 }
 140
 141 static inline int cpu_present_to_apicid(int mps_cpu)
 142 {
 143         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 144                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 145         else
 146                 return BAD_APICID;
 147 }
 148
 149 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
 150 {
 151         return physid_mask_of_physid(phys_apicid);
 152 }
 153
 154 static inline void setup_portio_remap(void)
 155 {
 156 }
 157
 158 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 159 {
 160         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 161 }
 162
 163 static inline void enable_apic_mode(void)
 164 {
 165 }
 166 #endif /* CONFIG_X86_LOCAL_APIC */
 167 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */