1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
26 #include <linux/personality.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
37 * Based on this we disable the IP header alignment in network drivers.
39 #define NET_IP_ALIGN 0
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
46 static inline void *current_text_addr(void)
50 asm volatile("mov $1f, %0; 1:":"=r" (pc
));
56 * These alignment constraints are for performance in the vSMP case,
57 * but in the task_struct case we must also meet hardware imposed
58 * alignment requirements of the FPU state:
60 #ifdef CONFIG_X86_VSMP
61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
65 # define ARCH_MIN_MMSTRUCT_ALIGN 0
73 extern u16 __read_mostly tlb_lli_4k
[NR_INFO
];
74 extern u16 __read_mostly tlb_lli_2m
[NR_INFO
];
75 extern u16 __read_mostly tlb_lli_4m
[NR_INFO
];
76 extern u16 __read_mostly tlb_lld_4k
[NR_INFO
];
77 extern u16 __read_mostly tlb_lld_2m
[NR_INFO
];
78 extern u16 __read_mostly tlb_lld_4m
[NR_INFO
];
79 extern u16 __read_mostly tlb_lld_1g
[NR_INFO
];
82 * CPU type and hardware bug flags. Kept separately for each CPU.
83 * Members of this structure are referenced in head.S, so think twice
84 * before touching them. [mj]
88 __u8 x86
; /* CPU family */
89 __u8 x86_vendor
; /* CPU vendor */
93 char wp_works_ok
; /* It doesn't on 386's */
95 /* Problems on some 486Dx4's and old 386's: */
100 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
105 /* CPUID returned core id bits: */
106 __u8 x86_coreid_bits
;
107 /* Max extended CPUID function supported: */
108 __u32 extended_cpuid_level
;
109 /* Maximum supported CPUID level, -1=no CPUID: */
111 __u32 x86_capability
[NCAPINTS
+ NBUGINTS
];
112 char x86_vendor_id
[16];
113 char x86_model_id
[64];
114 /* in KB - valid for CPUS which support this call: */
116 int x86_cache_alignment
; /* In bytes */
117 /* Cache QoS architectural values: */
118 int x86_cache_max_rmid
; /* max index */
119 int x86_cache_occ_scale
; /* scale to bytes */
121 unsigned long loops_per_jiffy
;
122 /* cpuid returned max cores value: */
126 u16 x86_clflush_size
;
127 /* number of cores as seen by the OS: */
129 /* Physical processor id: */
131 /* Logical processor id: */
135 /* Index into per_cpu list: */
140 #define X86_VENDOR_INTEL 0
141 #define X86_VENDOR_CYRIX 1
142 #define X86_VENDOR_AMD 2
143 #define X86_VENDOR_UMC 3
144 #define X86_VENDOR_CENTAUR 5
145 #define X86_VENDOR_TRANSMETA 7
146 #define X86_VENDOR_NSC 8
147 #define X86_VENDOR_NUM 9
149 #define X86_VENDOR_UNKNOWN 0xff
152 * capabilities of CPUs
154 extern struct cpuinfo_x86 boot_cpu_data
;
155 extern struct cpuinfo_x86 new_cpu_data
;
157 extern struct tss_struct doublefault_tss
;
158 extern __u32 cpu_caps_cleared
[NCAPINTS
];
159 extern __u32 cpu_caps_set
[NCAPINTS
];
162 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
163 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
165 #define cpu_info boot_cpu_data
166 #define cpu_data(cpu) boot_cpu_data
169 extern const struct seq_operations cpuinfo_op
;
171 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
173 extern void cpu_detect(struct cpuinfo_x86
*c
);
175 extern void early_cpu_init(void);
176 extern void identify_boot_cpu(void);
177 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
178 extern void print_cpu_info(struct cpuinfo_x86
*);
179 void print_cpu_msr(struct cpuinfo_x86
*);
180 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
181 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
182 extern void init_amd_cacheinfo(struct cpuinfo_x86
*c
);
184 extern void detect_extended_topology(struct cpuinfo_x86
*c
);
185 extern void detect_ht(struct cpuinfo_x86
*c
);
188 extern int have_cpuid_p(void);
190 static inline int have_cpuid_p(void)
195 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
196 unsigned int *ecx
, unsigned int *edx
)
198 /* ecx is often an input as well as an output. */
204 : "0" (*eax
), "2" (*ecx
)
208 static inline void load_cr3(pgd_t
*pgdir
)
210 write_cr3(__pa(pgdir
));
214 /* This is the TSS defined by the hardware. */
216 unsigned short back_link
, __blh
;
218 unsigned short ss0
, __ss0h
;
222 * We don't use ring 1, so ss1 is a convenient scratch space in
223 * the same cacheline as sp0. We use ss1 to cache the value in
224 * MSR_IA32_SYSENTER_CS. When we context switch
225 * MSR_IA32_SYSENTER_CS, we first check if the new value being
226 * written matches ss1, and, if it's not, then we wrmsr the new
227 * value and update ss1.
229 * The only reason we context switch MSR_IA32_SYSENTER_CS is
230 * that we set it to zero in vm86 tasks to avoid corrupting the
231 * stack if we were to go through the sysenter path from vm86
234 unsigned short ss1
; /* MSR_IA32_SYSENTER_CS */
236 unsigned short __ss1h
;
238 unsigned short ss2
, __ss2h
;
250 unsigned short es
, __esh
;
251 unsigned short cs
, __csh
;
252 unsigned short ss
, __ssh
;
253 unsigned short ds
, __dsh
;
254 unsigned short fs
, __fsh
;
255 unsigned short gs
, __gsh
;
256 unsigned short ldt
, __ldth
;
257 unsigned short trace
;
258 unsigned short io_bitmap_base
;
260 } __attribute__((packed
));
274 } __attribute__((packed
)) ____cacheline_aligned
;
280 #define IO_BITMAP_BITS 65536
281 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
282 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
283 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
284 #define INVALID_IO_BITMAP_OFFSET 0x8000
288 * The hardware state:
290 struct x86_hw_tss x86_tss
;
293 * The extra 1 is there because the CPU will access an
294 * additional byte beyond the end of the IO permission
295 * bitmap. The extra byte must be all 1 bits, and must
296 * be within the limit.
298 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
302 * Space for the temporary SYSENTER stack.
304 unsigned long SYSENTER_stack_canary
;
305 unsigned long SYSENTER_stack
[64];
308 } ____cacheline_aligned
;
310 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, cpu_tss
);
313 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack
);
317 * Save the original ist values for checking stack pointers during debugging
320 unsigned long ist
[7];
324 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
326 union irq_stack_union
{
327 char irq_stack
[IRQ_STACK_SIZE
];
329 * GCC hardcodes the stack canary as %gs:40. Since the
330 * irq_stack is the object at %gs:0, we reserve the bottom
331 * 48 bytes of the irq stack for the canary.
335 unsigned long stack_canary
;
339 DECLARE_PER_CPU_FIRST(union irq_stack_union
, irq_stack_union
) __visible
;
340 DECLARE_INIT_PER_CPU(irq_stack_union
);
342 DECLARE_PER_CPU(char *, irq_stack_ptr
);
343 DECLARE_PER_CPU(unsigned int, irq_count
);
344 extern asmlinkage
void ignore_sysret(void);
346 #ifdef CONFIG_CC_STACKPROTECTOR
348 * Make sure stack canary segment base is cached-aligned:
349 * "For Intel Atom processors, avoid non zero segment base address
350 * that is not aligned to cache line boundary at all cost."
351 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
353 struct stack_canary
{
354 char __pad
[20]; /* canary at %gs:20 */
355 unsigned long canary
;
357 DECLARE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
360 * per-CPU IRQ handling stacks
363 u32 stack
[THREAD_SIZE
/sizeof(u32
)];
364 } __aligned(THREAD_SIZE
);
366 DECLARE_PER_CPU(struct irq_stack
*, hardirq_stack
);
367 DECLARE_PER_CPU(struct irq_stack
*, softirq_stack
);
370 extern unsigned int xstate_size
;
374 struct thread_struct
{
375 /* Cached TLS descriptors: */
376 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
380 unsigned long sysenter_cs
;
384 unsigned short fsindex
;
385 unsigned short gsindex
;
391 unsigned long fsbase
;
392 unsigned long gsbase
;
395 * XXX: this could presumably be unsigned short. Alternatively,
396 * 32-bit kernels could be taught to use fsindex instead.
402 /* Save middle states of ptrace breakpoints */
403 struct perf_event
*ptrace_bps
[HBP_NUM
];
404 /* Debug status used for traps, single steps, etc... */
405 unsigned long debugreg6
;
406 /* Keep track of the exact dr7 value set by the user */
407 unsigned long ptrace_dr7
;
410 unsigned long trap_nr
;
411 unsigned long error_code
;
413 /* Virtual 86 mode info */
416 /* IO permissions: */
417 unsigned long *io_bitmap_ptr
;
419 /* Max allowed port in the bitmap, in bytes: */
420 unsigned io_bitmap_max
;
422 unsigned int sig_on_uaccess_err
:1;
423 unsigned int uaccess_err
:1; /* uaccess failed */
425 /* Floating point and extended processor state */
428 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
434 * Set IOPL bits in EFLAGS from given mask
436 static inline void native_set_iopl_mask(unsigned mask
)
441 asm volatile ("pushfl;"
448 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
453 native_load_sp0(struct tss_struct
*tss
, struct thread_struct
*thread
)
455 tss
->x86_tss
.sp0
= thread
->sp0
;
457 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
458 if (unlikely(tss
->x86_tss
.ss1
!= thread
->sysenter_cs
)) {
459 tss
->x86_tss
.ss1
= thread
->sysenter_cs
;
460 wrmsr(MSR_IA32_SYSENTER_CS
, thread
->sysenter_cs
, 0);
465 static inline void native_swapgs(void)
468 asm volatile("swapgs" ::: "memory");
472 static inline unsigned long current_top_of_stack(void)
475 return this_cpu_read_stable(cpu_tss
.x86_tss
.sp0
);
477 /* sp0 on x86_32 is special in and around vm86 mode. */
478 return this_cpu_read_stable(cpu_current_top_of_stack
);
482 #ifdef CONFIG_PARAVIRT
483 #include <asm/paravirt.h>
485 #define __cpuid native_cpuid
487 static inline void load_sp0(struct tss_struct
*tss
,
488 struct thread_struct
*thread
)
490 native_load_sp0(tss
, thread
);
493 #define set_iopl_mask native_set_iopl_mask
494 #endif /* CONFIG_PARAVIRT */
501 /* Free all resources held by a thread. */
502 extern void release_thread(struct task_struct
*);
504 unsigned long get_wchan(struct task_struct
*p
);
507 * Generic CPUID function
508 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
509 * resulting in stale register contents being returned.
511 static inline void cpuid(unsigned int op
,
512 unsigned int *eax
, unsigned int *ebx
,
513 unsigned int *ecx
, unsigned int *edx
)
517 __cpuid(eax
, ebx
, ecx
, edx
);
520 /* Some CPUID calls want 'count' to be placed in ecx */
521 static inline void cpuid_count(unsigned int op
, int count
,
522 unsigned int *eax
, unsigned int *ebx
,
523 unsigned int *ecx
, unsigned int *edx
)
527 __cpuid(eax
, ebx
, ecx
, edx
);
531 * CPUID functions returning a single datum
533 static inline unsigned int cpuid_eax(unsigned int op
)
535 unsigned int eax
, ebx
, ecx
, edx
;
537 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
542 static inline unsigned int cpuid_ebx(unsigned int op
)
544 unsigned int eax
, ebx
, ecx
, edx
;
546 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
551 static inline unsigned int cpuid_ecx(unsigned int op
)
553 unsigned int eax
, ebx
, ecx
, edx
;
555 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
560 static inline unsigned int cpuid_edx(unsigned int op
)
562 unsigned int eax
, ebx
, ecx
, edx
;
564 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
569 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
570 static __always_inline
void rep_nop(void)
572 asm volatile("rep; nop" ::: "memory");
575 static __always_inline
void cpu_relax(void)
580 #define cpu_relax_lowlatency() cpu_relax()
582 /* Stop speculative execution and prefetching of modified code. */
583 static inline void sync_core(void)
589 * Do a CPUID if available, otherwise do a jump. The jump
590 * can conveniently enough be the jump around CPUID.
592 asm volatile("cmpl %2,%1\n\t"
597 : "rm" (boot_cpu_data
.cpuid_level
), "ri" (0), "0" (1)
598 : "ebx", "ecx", "edx", "memory");
601 * CPUID is a barrier to speculative execution.
602 * Prefetched instructions are automatically
603 * invalidated when modified.
608 : "ebx", "ecx", "edx", "memory");
612 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
613 extern void init_amd_e400_c1e_mask(void);
615 extern unsigned long boot_option_idle_override
;
616 extern bool amd_e400_c1e_detected
;
618 enum idle_boot_override
{IDLE_NO_OVERRIDE
=0, IDLE_HALT
, IDLE_NOMWAIT
,
621 extern void enable_sep_cpu(void);
622 extern int sysenter_setup(void);
624 extern void early_trap_init(void);
625 void early_trap_pf_init(void);
627 /* Defined in head.S */
628 extern struct desc_ptr early_gdt_descr
;
630 extern void cpu_set_gdt(int);
631 extern void switch_to_new_gdt(int);
632 extern void load_percpu_segment(int);
633 extern void cpu_init(void);
635 static inline unsigned long get_debugctlmsr(void)
637 unsigned long debugctlmsr
= 0;
639 #ifndef CONFIG_X86_DEBUGCTLMSR
640 if (boot_cpu_data
.x86
< 6)
643 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
648 static inline void update_debugctlmsr(unsigned long debugctlmsr
)
650 #ifndef CONFIG_X86_DEBUGCTLMSR
651 if (boot_cpu_data
.x86
< 6)
654 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
657 extern void set_task_blockstep(struct task_struct
*task
, bool on
);
659 /* Boot loader type from the setup header: */
660 extern int bootloader_type
;
661 extern int bootloader_version
;
663 extern char ignore_fpu_irq
;
665 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
666 #define ARCH_HAS_PREFETCHW
667 #define ARCH_HAS_SPINLOCK_PREFETCH
670 # define BASE_PREFETCH ""
671 # define ARCH_HAS_PREFETCH
673 # define BASE_PREFETCH "prefetcht0 %P1"
677 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
679 * It's not worth to care about 3dnow prefetches for the K6
680 * because they are microcoded there and very slow.
682 static inline void prefetch(const void *x
)
684 alternative_input(BASE_PREFETCH
, "prefetchnta %P1",
686 "m" (*(const char *)x
));
690 * 3dnow prefetch to get an exclusive cache line.
691 * Useful for spinlocks to avoid one state transition in the
692 * cache coherency protocol:
694 static inline void prefetchw(const void *x
)
696 alternative_input(BASE_PREFETCH
, "prefetchw %P1",
697 X86_FEATURE_3DNOWPREFETCH
,
698 "m" (*(const char *)x
));
701 static inline void spin_lock_prefetch(const void *x
)
706 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
707 TOP_OF_KERNEL_STACK_PADDING)
711 * User space process size: 3GB (default).
713 #define TASK_SIZE PAGE_OFFSET
714 #define TASK_SIZE_MAX TASK_SIZE
715 #define STACK_TOP TASK_SIZE
716 #define STACK_TOP_MAX STACK_TOP
718 #define INIT_THREAD { \
719 .sp0 = TOP_OF_INIT_STACK, \
720 .sysenter_cs = __KERNEL_CS, \
721 .io_bitmap_ptr = NULL, \
724 extern unsigned long thread_saved_pc(struct task_struct
*tsk
);
727 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
728 * This is necessary to guarantee that the entire "struct pt_regs"
729 * is accessible even if the CPU haven't stored the SS/ESP registers
730 * on the stack (interrupt gate does not save these registers
731 * when switching to the same priv ring).
732 * Therefore beware: accessing the ss/esp fields of the
733 * "struct pt_regs" is possible, but they may contain the
734 * completely wrong values.
736 #define task_pt_regs(task) \
738 unsigned long __ptr = (unsigned long)task_stack_page(task); \
739 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
740 ((struct pt_regs *)__ptr) - 1; \
743 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
747 * User space process size. 47bits minus one guard page. The guard
748 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
749 * the highest possible canonical userspace address, then that
750 * syscall will enter the kernel with a non-canonical return
751 * address, and SYSRET will explode dangerously. We avoid this
752 * particular problem by preventing anything from being mapped
753 * at the maximum canonical address.
755 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
757 /* This decides where the kernel will search for a free chunk of vm
758 * space during mmap's.
760 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
761 0xc0000000 : 0xFFFFe000)
763 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
764 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
765 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
766 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
768 #define STACK_TOP TASK_SIZE
769 #define STACK_TOP_MAX TASK_SIZE_MAX
771 #define INIT_THREAD { \
772 .sp0 = TOP_OF_INIT_STACK \
776 * Return saved PC of a blocked thread.
777 * What is this good for? it will be always the scheduler or ret_from_fork.
779 #define thread_saved_pc(t) READ_ONCE_NOCHECK(*(unsigned long *)((t)->thread.sp - 8))
781 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
782 extern unsigned long KSTK_ESP(struct task_struct
*task
);
784 #endif /* CONFIG_X86_64 */
786 extern void start_thread(struct pt_regs
*regs
, unsigned long new_ip
,
787 unsigned long new_sp
);
790 * This decides where the kernel will search for a free chunk of vm
791 * space during mmap's.
793 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
795 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
797 /* Get/set a process' ability to use the timestamp counter instruction */
798 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
799 #define SET_TSC_CTL(val) set_tsc_mode((val))
801 extern int get_tsc_mode(unsigned long adr
);
802 extern int set_tsc_mode(unsigned int val
);
804 /* Register/unregister a process' MPX related resource */
805 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
806 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
808 #ifdef CONFIG_X86_INTEL_MPX
809 extern int mpx_enable_management(void);
810 extern int mpx_disable_management(void);
812 static inline int mpx_enable_management(void)
816 static inline int mpx_disable_management(void)
820 #endif /* CONFIG_X86_INTEL_MPX */
822 extern u16
amd_get_nb_id(int cpu
);
823 extern u32
amd_get_nodes_per_socket(void);
825 static inline uint32_t hypervisor_cpuid_base(const char *sig
, uint32_t leaves
)
827 uint32_t base
, eax
, signature
[3];
829 for (base
= 0x40000000; base
< 0x40010000; base
+= 0x100) {
830 cpuid(base
, &eax
, &signature
[0], &signature
[1], &signature
[2]);
832 if (!memcmp(sig
, signature
, 12) &&
833 (leaves
== 0 || ((eax
- base
) >= leaves
)))
840 extern unsigned long arch_align_stack(unsigned long sp
);
841 extern void free_init_pages(char *what
, unsigned long begin
, unsigned long end
);
843 void default_idle(void);
845 bool xen_set_default_idle(void);
847 #define xen_set_default_idle 0
850 void stop_this_cpu(void *dummy
);
851 void df_debug(struct pt_regs
*regs
, long error_code
);
852 #endif /* _ASM_X86_PROCESSOR_H */