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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[deliverable/linux.git] / arch / x86 / kernel / apic / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63
64 #include <asm/apic.h>
65
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
90
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
93
94 /* # of MP IRQ source entries */
95 int mp_irq_entries;
96
97 /* GSI interrupts */
98 static int nr_irqs_gsi = NR_IRQS_LEGACY;
99
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type[MAX_MP_BUSSES];
102 #endif
103
104 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
105
106 int skip_ioapic_setup;
107
108 void arch_disable_smp_support(void)
109 {
110 #ifdef CONFIG_PCI
111 noioapicquirk = 1;
112 noioapicreroute = -1;
113 #endif
114 skip_ioapic_setup = 1;
115 }
116
117 static int __init parse_noapic(char *str)
118 {
119 /* disable IO-APIC */
120 arch_disable_smp_support();
121 return 0;
122 }
123 early_param("noapic", parse_noapic);
124
125 struct irq_pin_list {
126 int apic, pin;
127 struct irq_pin_list *next;
128 };
129
130 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
131 {
132 struct irq_pin_list *pin;
133
134 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
135
136 return pin;
137 }
138
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
142 #else
143 static struct irq_cfg irq_cfgx[NR_IRQS];
144 #endif
145
146 int __init arch_early_irq_init(void)
147 {
148 struct irq_cfg *cfg;
149 struct irq_desc *desc;
150 int count;
151 int node;
152 int i;
153
154 if (!legacy_pic->nr_legacy_irqs) {
155 nr_irqs_gsi = 0;
156 io_apic_irqs = ~0UL;
157 }
158
159 cfg = irq_cfgx;
160 count = ARRAY_SIZE(irq_cfgx);
161 node= cpu_to_node(boot_cpu_id);
162
163 for (i = 0; i < count; i++) {
164 desc = irq_to_desc(i);
165 desc->chip_data = &cfg[i];
166 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
167 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
168 /*
169 * For legacy IRQ's, start with assigning irq0 to irq15 to
170 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
171 */
172 if (i < legacy_pic->nr_legacy_irqs) {
173 cfg[i].vector = IRQ0_VECTOR + i;
174 cpumask_set_cpu(0, cfg[i].domain);
175 }
176 }
177
178 return 0;
179 }
180
181 #ifdef CONFIG_SPARSE_IRQ
182 struct irq_cfg *irq_cfg(unsigned int irq)
183 {
184 struct irq_cfg *cfg = NULL;
185 struct irq_desc *desc;
186
187 desc = irq_to_desc(irq);
188 if (desc)
189 cfg = desc->chip_data;
190
191 return cfg;
192 }
193
194 static struct irq_cfg *get_one_free_irq_cfg(int node)
195 {
196 struct irq_cfg *cfg;
197
198 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
199 if (cfg) {
200 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
201 kfree(cfg);
202 cfg = NULL;
203 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
204 GFP_ATOMIC, node)) {
205 free_cpumask_var(cfg->domain);
206 kfree(cfg);
207 cfg = NULL;
208 }
209 }
210
211 return cfg;
212 }
213
214 int arch_init_chip_data(struct irq_desc *desc, int node)
215 {
216 struct irq_cfg *cfg;
217
218 cfg = desc->chip_data;
219 if (!cfg) {
220 desc->chip_data = get_one_free_irq_cfg(node);
221 if (!desc->chip_data) {
222 printk(KERN_ERR "can not alloc irq_cfg\n");
223 BUG_ON(1);
224 }
225 }
226
227 return 0;
228 }
229
230 /* for move_irq_desc */
231 static void
232 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
233 {
234 struct irq_pin_list *old_entry, *head, *tail, *entry;
235
236 cfg->irq_2_pin = NULL;
237 old_entry = old_cfg->irq_2_pin;
238 if (!old_entry)
239 return;
240
241 entry = get_one_free_irq_2_pin(node);
242 if (!entry)
243 return;
244
245 entry->apic = old_entry->apic;
246 entry->pin = old_entry->pin;
247 head = entry;
248 tail = entry;
249 old_entry = old_entry->next;
250 while (old_entry) {
251 entry = get_one_free_irq_2_pin(node);
252 if (!entry) {
253 entry = head;
254 while (entry) {
255 head = entry->next;
256 kfree(entry);
257 entry = head;
258 }
259 /* still use the old one */
260 return;
261 }
262 entry->apic = old_entry->apic;
263 entry->pin = old_entry->pin;
264 tail->next = entry;
265 tail = entry;
266 old_entry = old_entry->next;
267 }
268
269 tail->next = NULL;
270 cfg->irq_2_pin = head;
271 }
272
273 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
274 {
275 struct irq_pin_list *entry, *next;
276
277 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
278 return;
279
280 entry = old_cfg->irq_2_pin;
281
282 while (entry) {
283 next = entry->next;
284 kfree(entry);
285 entry = next;
286 }
287 old_cfg->irq_2_pin = NULL;
288 }
289
290 void arch_init_copy_chip_data(struct irq_desc *old_desc,
291 struct irq_desc *desc, int node)
292 {
293 struct irq_cfg *cfg;
294 struct irq_cfg *old_cfg;
295
296 cfg = get_one_free_irq_cfg(node);
297
298 if (!cfg)
299 return;
300
301 desc->chip_data = cfg;
302
303 old_cfg = old_desc->chip_data;
304
305 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
306
307 init_copy_irq_2_pin(old_cfg, cfg, node);
308 }
309
310 static void free_irq_cfg(struct irq_cfg *old_cfg)
311 {
312 kfree(old_cfg);
313 }
314
315 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
316 {
317 struct irq_cfg *old_cfg, *cfg;
318
319 old_cfg = old_desc->chip_data;
320 cfg = desc->chip_data;
321
322 if (old_cfg == cfg)
323 return;
324
325 if (old_cfg) {
326 free_irq_2_pin(old_cfg, cfg);
327 free_irq_cfg(old_cfg);
328 old_desc->chip_data = NULL;
329 }
330 }
331 /* end for move_irq_desc */
332
333 #else
334 struct irq_cfg *irq_cfg(unsigned int irq)
335 {
336 return irq < nr_irqs ? irq_cfgx + irq : NULL;
337 }
338
339 #endif
340
341 struct io_apic {
342 unsigned int index;
343 unsigned int unused[3];
344 unsigned int data;
345 unsigned int unused2[11];
346 unsigned int eoi;
347 };
348
349 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
350 {
351 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
352 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
353 }
354
355 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
356 {
357 struct io_apic __iomem *io_apic = io_apic_base(apic);
358 writel(vector, &io_apic->eoi);
359 }
360
361 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
362 {
363 struct io_apic __iomem *io_apic = io_apic_base(apic);
364 writel(reg, &io_apic->index);
365 return readl(&io_apic->data);
366 }
367
368 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
369 {
370 struct io_apic __iomem *io_apic = io_apic_base(apic);
371 writel(reg, &io_apic->index);
372 writel(value, &io_apic->data);
373 }
374
375 /*
376 * Re-write a value: to be used for read-modify-write
377 * cycles where the read already set up the index register.
378 *
379 * Older SiS APIC requires we rewrite the index register
380 */
381 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
382 {
383 struct io_apic __iomem *io_apic = io_apic_base(apic);
384
385 if (sis_apic_bug)
386 writel(reg, &io_apic->index);
387 writel(value, &io_apic->data);
388 }
389
390 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
391 {
392 struct irq_pin_list *entry;
393 unsigned long flags;
394
395 raw_spin_lock_irqsave(&ioapic_lock, flags);
396 for_each_irq_pin(entry, cfg->irq_2_pin) {
397 unsigned int reg;
398 int pin;
399
400 pin = entry->pin;
401 reg = io_apic_read(entry->apic, 0x10 + pin*2);
402 /* Is the remote IRR bit set? */
403 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
404 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
405 return true;
406 }
407 }
408 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
409
410 return false;
411 }
412
413 union entry_union {
414 struct { u32 w1, w2; };
415 struct IO_APIC_route_entry entry;
416 };
417
418 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
419 {
420 union entry_union eu;
421 unsigned long flags;
422 raw_spin_lock_irqsave(&ioapic_lock, flags);
423 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
424 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
425 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
426 return eu.entry;
427 }
428
429 /*
430 * When we write a new IO APIC routing entry, we need to write the high
431 * word first! If the mask bit in the low word is clear, we will enable
432 * the interrupt, and we need to make sure the entry is fully populated
433 * before that happens.
434 */
435 static void
436 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
437 {
438 union entry_union eu = {{0, 0}};
439
440 eu.entry = e;
441 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
442 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
443 }
444
445 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
446 {
447 unsigned long flags;
448 raw_spin_lock_irqsave(&ioapic_lock, flags);
449 __ioapic_write_entry(apic, pin, e);
450 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
451 }
452
453 /*
454 * When we mask an IO APIC routing entry, we need to write the low
455 * word first, in order to set the mask bit before we change the
456 * high bits!
457 */
458 static void ioapic_mask_entry(int apic, int pin)
459 {
460 unsigned long flags;
461 union entry_union eu = { .entry.mask = 1 };
462
463 raw_spin_lock_irqsave(&ioapic_lock, flags);
464 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
465 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
466 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
467 }
468
469 /*
470 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
471 * shared ISA-space IRQs, so we have to support them. We are super
472 * fast in the common case, and fast for shared ISA-space IRQs.
473 */
474 static int
475 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
476 {
477 struct irq_pin_list **last, *entry;
478
479 /* don't allow duplicates */
480 last = &cfg->irq_2_pin;
481 for_each_irq_pin(entry, cfg->irq_2_pin) {
482 if (entry->apic == apic && entry->pin == pin)
483 return 0;
484 last = &entry->next;
485 }
486
487 entry = get_one_free_irq_2_pin(node);
488 if (!entry) {
489 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
490 node, apic, pin);
491 return -ENOMEM;
492 }
493 entry->apic = apic;
494 entry->pin = pin;
495
496 *last = entry;
497 return 0;
498 }
499
500 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
501 {
502 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
503 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
504 }
505
506 /*
507 * Reroute an IRQ to a different pin.
508 */
509 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
510 int oldapic, int oldpin,
511 int newapic, int newpin)
512 {
513 struct irq_pin_list *entry;
514
515 for_each_irq_pin(entry, cfg->irq_2_pin) {
516 if (entry->apic == oldapic && entry->pin == oldpin) {
517 entry->apic = newapic;
518 entry->pin = newpin;
519 /* every one is different, right? */
520 return;
521 }
522 }
523
524 /* old apic/pin didn't exist, so just add new ones */
525 add_pin_to_irq_node(cfg, node, newapic, newpin);
526 }
527
528 static void __io_apic_modify_irq(struct irq_pin_list *entry,
529 int mask_and, int mask_or,
530 void (*final)(struct irq_pin_list *entry))
531 {
532 unsigned int reg, pin;
533
534 pin = entry->pin;
535 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
536 reg &= mask_and;
537 reg |= mask_or;
538 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
539 if (final)
540 final(entry);
541 }
542
543 static void io_apic_modify_irq(struct irq_cfg *cfg,
544 int mask_and, int mask_or,
545 void (*final)(struct irq_pin_list *entry))
546 {
547 struct irq_pin_list *entry;
548
549 for_each_irq_pin(entry, cfg->irq_2_pin)
550 __io_apic_modify_irq(entry, mask_and, mask_or, final);
551 }
552
553 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
554 {
555 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
556 IO_APIC_REDIR_MASKED, NULL);
557 }
558
559 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
560 {
561 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
562 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
563 }
564
565 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
566 {
567 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
568 }
569
570 static void io_apic_sync(struct irq_pin_list *entry)
571 {
572 /*
573 * Synchronize the IO-APIC and the CPU by doing
574 * a dummy read from the IO-APIC
575 */
576 struct io_apic __iomem *io_apic;
577 io_apic = io_apic_base(entry->apic);
578 readl(&io_apic->data);
579 }
580
581 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
582 {
583 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
584 }
585
586 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
587 {
588 struct irq_cfg *cfg = desc->chip_data;
589 unsigned long flags;
590
591 BUG_ON(!cfg);
592
593 raw_spin_lock_irqsave(&ioapic_lock, flags);
594 __mask_IO_APIC_irq(cfg);
595 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
596 }
597
598 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
599 {
600 struct irq_cfg *cfg = desc->chip_data;
601 unsigned long flags;
602
603 raw_spin_lock_irqsave(&ioapic_lock, flags);
604 __unmask_IO_APIC_irq(cfg);
605 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
606 }
607
608 static void mask_IO_APIC_irq(unsigned int irq)
609 {
610 struct irq_desc *desc = irq_to_desc(irq);
611
612 mask_IO_APIC_irq_desc(desc);
613 }
614 static void unmask_IO_APIC_irq(unsigned int irq)
615 {
616 struct irq_desc *desc = irq_to_desc(irq);
617
618 unmask_IO_APIC_irq_desc(desc);
619 }
620
621 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
622 {
623 struct IO_APIC_route_entry entry;
624
625 /* Check delivery_mode to be sure we're not clearing an SMI pin */
626 entry = ioapic_read_entry(apic, pin);
627 if (entry.delivery_mode == dest_SMI)
628 return;
629 /*
630 * Disable it in the IO-APIC irq-routing table:
631 */
632 ioapic_mask_entry(apic, pin);
633 }
634
635 static void clear_IO_APIC (void)
636 {
637 int apic, pin;
638
639 for (apic = 0; apic < nr_ioapics; apic++)
640 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
641 clear_IO_APIC_pin(apic, pin);
642 }
643
644 #ifdef CONFIG_X86_32
645 /*
646 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
647 * specific CPU-side IRQs.
648 */
649
650 #define MAX_PIRQS 8
651 static int pirq_entries[MAX_PIRQS] = {
652 [0 ... MAX_PIRQS - 1] = -1
653 };
654
655 static int __init ioapic_pirq_setup(char *str)
656 {
657 int i, max;
658 int ints[MAX_PIRQS+1];
659
660 get_options(str, ARRAY_SIZE(ints), ints);
661
662 apic_printk(APIC_VERBOSE, KERN_INFO
663 "PIRQ redirection, working around broken MP-BIOS.\n");
664 max = MAX_PIRQS;
665 if (ints[0] < MAX_PIRQS)
666 max = ints[0];
667
668 for (i = 0; i < max; i++) {
669 apic_printk(APIC_VERBOSE, KERN_DEBUG
670 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
671 /*
672 * PIRQs are mapped upside down, usually.
673 */
674 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
675 }
676 return 1;
677 }
678
679 __setup("pirq=", ioapic_pirq_setup);
680 #endif /* CONFIG_X86_32 */
681
682 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
683 {
684 int apic;
685 struct IO_APIC_route_entry **ioapic_entries;
686
687 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
688 GFP_ATOMIC);
689 if (!ioapic_entries)
690 return 0;
691
692 for (apic = 0; apic < nr_ioapics; apic++) {
693 ioapic_entries[apic] =
694 kzalloc(sizeof(struct IO_APIC_route_entry) *
695 nr_ioapic_registers[apic], GFP_ATOMIC);
696 if (!ioapic_entries[apic])
697 goto nomem;
698 }
699
700 return ioapic_entries;
701
702 nomem:
703 while (--apic >= 0)
704 kfree(ioapic_entries[apic]);
705 kfree(ioapic_entries);
706
707 return 0;
708 }
709
710 /*
711 * Saves all the IO-APIC RTE's
712 */
713 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
714 {
715 int apic, pin;
716
717 if (!ioapic_entries)
718 return -ENOMEM;
719
720 for (apic = 0; apic < nr_ioapics; apic++) {
721 if (!ioapic_entries[apic])
722 return -ENOMEM;
723
724 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
725 ioapic_entries[apic][pin] =
726 ioapic_read_entry(apic, pin);
727 }
728
729 return 0;
730 }
731
732 /*
733 * Mask all IO APIC entries.
734 */
735 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
736 {
737 int apic, pin;
738
739 if (!ioapic_entries)
740 return;
741
742 for (apic = 0; apic < nr_ioapics; apic++) {
743 if (!ioapic_entries[apic])
744 break;
745
746 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
747 struct IO_APIC_route_entry entry;
748
749 entry = ioapic_entries[apic][pin];
750 if (!entry.mask) {
751 entry.mask = 1;
752 ioapic_write_entry(apic, pin, entry);
753 }
754 }
755 }
756 }
757
758 /*
759 * Restore IO APIC entries which was saved in ioapic_entries.
760 */
761 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
762 {
763 int apic, pin;
764
765 if (!ioapic_entries)
766 return -ENOMEM;
767
768 for (apic = 0; apic < nr_ioapics; apic++) {
769 if (!ioapic_entries[apic])
770 return -ENOMEM;
771
772 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
773 ioapic_write_entry(apic, pin,
774 ioapic_entries[apic][pin]);
775 }
776 return 0;
777 }
778
779 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
780 {
781 int apic;
782
783 for (apic = 0; apic < nr_ioapics; apic++)
784 kfree(ioapic_entries[apic]);
785
786 kfree(ioapic_entries);
787 }
788
789 /*
790 * Find the IRQ entry number of a certain pin.
791 */
792 static int find_irq_entry(int apic, int pin, int type)
793 {
794 int i;
795
796 for (i = 0; i < mp_irq_entries; i++)
797 if (mp_irqs[i].irqtype == type &&
798 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
799 mp_irqs[i].dstapic == MP_APIC_ALL) &&
800 mp_irqs[i].dstirq == pin)
801 return i;
802
803 return -1;
804 }
805
806 /*
807 * Find the pin to which IRQ[irq] (ISA) is connected
808 */
809 static int __init find_isa_irq_pin(int irq, int type)
810 {
811 int i;
812
813 for (i = 0; i < mp_irq_entries; i++) {
814 int lbus = mp_irqs[i].srcbus;
815
816 if (test_bit(lbus, mp_bus_not_pci) &&
817 (mp_irqs[i].irqtype == type) &&
818 (mp_irqs[i].srcbusirq == irq))
819
820 return mp_irqs[i].dstirq;
821 }
822 return -1;
823 }
824
825 static int __init find_isa_irq_apic(int irq, int type)
826 {
827 int i;
828
829 for (i = 0; i < mp_irq_entries; i++) {
830 int lbus = mp_irqs[i].srcbus;
831
832 if (test_bit(lbus, mp_bus_not_pci) &&
833 (mp_irqs[i].irqtype == type) &&
834 (mp_irqs[i].srcbusirq == irq))
835 break;
836 }
837 if (i < mp_irq_entries) {
838 int apic;
839 for(apic = 0; apic < nr_ioapics; apic++) {
840 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
841 return apic;
842 }
843 }
844
845 return -1;
846 }
847
848 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
849 /*
850 * EISA Edge/Level control register, ELCR
851 */
852 static int EISA_ELCR(unsigned int irq)
853 {
854 if (irq < legacy_pic->nr_legacy_irqs) {
855 unsigned int port = 0x4d0 + (irq >> 3);
856 return (inb(port) >> (irq & 7)) & 1;
857 }
858 apic_printk(APIC_VERBOSE, KERN_INFO
859 "Broken MPtable reports ISA irq %d\n", irq);
860 return 0;
861 }
862
863 #endif
864
865 /* ISA interrupts are always polarity zero edge triggered,
866 * when listed as conforming in the MP table. */
867
868 #define default_ISA_trigger(idx) (0)
869 #define default_ISA_polarity(idx) (0)
870
871 /* EISA interrupts are always polarity zero and can be edge or level
872 * trigger depending on the ELCR value. If an interrupt is listed as
873 * EISA conforming in the MP table, that means its trigger type must
874 * be read in from the ELCR */
875
876 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
877 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
878
879 /* PCI interrupts are always polarity one level triggered,
880 * when listed as conforming in the MP table. */
881
882 #define default_PCI_trigger(idx) (1)
883 #define default_PCI_polarity(idx) (1)
884
885 /* MCA interrupts are always polarity zero level triggered,
886 * when listed as conforming in the MP table. */
887
888 #define default_MCA_trigger(idx) (1)
889 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
890
891 static int MPBIOS_polarity(int idx)
892 {
893 int bus = mp_irqs[idx].srcbus;
894 int polarity;
895
896 /*
897 * Determine IRQ line polarity (high active or low active):
898 */
899 switch (mp_irqs[idx].irqflag & 3)
900 {
901 case 0: /* conforms, ie. bus-type dependent polarity */
902 if (test_bit(bus, mp_bus_not_pci))
903 polarity = default_ISA_polarity(idx);
904 else
905 polarity = default_PCI_polarity(idx);
906 break;
907 case 1: /* high active */
908 {
909 polarity = 0;
910 break;
911 }
912 case 2: /* reserved */
913 {
914 printk(KERN_WARNING "broken BIOS!!\n");
915 polarity = 1;
916 break;
917 }
918 case 3: /* low active */
919 {
920 polarity = 1;
921 break;
922 }
923 default: /* invalid */
924 {
925 printk(KERN_WARNING "broken BIOS!!\n");
926 polarity = 1;
927 break;
928 }
929 }
930 return polarity;
931 }
932
933 static int MPBIOS_trigger(int idx)
934 {
935 int bus = mp_irqs[idx].srcbus;
936 int trigger;
937
938 /*
939 * Determine IRQ trigger mode (edge or level sensitive):
940 */
941 switch ((mp_irqs[idx].irqflag>>2) & 3)
942 {
943 case 0: /* conforms, ie. bus-type dependent */
944 if (test_bit(bus, mp_bus_not_pci))
945 trigger = default_ISA_trigger(idx);
946 else
947 trigger = default_PCI_trigger(idx);
948 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
949 switch (mp_bus_id_to_type[bus]) {
950 case MP_BUS_ISA: /* ISA pin */
951 {
952 /* set before the switch */
953 break;
954 }
955 case MP_BUS_EISA: /* EISA pin */
956 {
957 trigger = default_EISA_trigger(idx);
958 break;
959 }
960 case MP_BUS_PCI: /* PCI pin */
961 {
962 /* set before the switch */
963 break;
964 }
965 case MP_BUS_MCA: /* MCA pin */
966 {
967 trigger = default_MCA_trigger(idx);
968 break;
969 }
970 default:
971 {
972 printk(KERN_WARNING "broken BIOS!!\n");
973 trigger = 1;
974 break;
975 }
976 }
977 #endif
978 break;
979 case 1: /* edge */
980 {
981 trigger = 0;
982 break;
983 }
984 case 2: /* reserved */
985 {
986 printk(KERN_WARNING "broken BIOS!!\n");
987 trigger = 1;
988 break;
989 }
990 case 3: /* level */
991 {
992 trigger = 1;
993 break;
994 }
995 default: /* invalid */
996 {
997 printk(KERN_WARNING "broken BIOS!!\n");
998 trigger = 0;
999 break;
1000 }
1001 }
1002 return trigger;
1003 }
1004
1005 static inline int irq_polarity(int idx)
1006 {
1007 return MPBIOS_polarity(idx);
1008 }
1009
1010 static inline int irq_trigger(int idx)
1011 {
1012 return MPBIOS_trigger(idx);
1013 }
1014
1015 int (*ioapic_renumber_irq)(int ioapic, int irq);
1016 static int pin_2_irq(int idx, int apic, int pin)
1017 {
1018 int irq, i;
1019 int bus = mp_irqs[idx].srcbus;
1020
1021 /*
1022 * Debugging check, we are in big trouble if this message pops up!
1023 */
1024 if (mp_irqs[idx].dstirq != pin)
1025 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1026
1027 if (test_bit(bus, mp_bus_not_pci)) {
1028 irq = mp_irqs[idx].srcbusirq;
1029 } else {
1030 /*
1031 * PCI IRQs are mapped in order
1032 */
1033 i = irq = 0;
1034 while (i < apic)
1035 irq += nr_ioapic_registers[i++];
1036 irq += pin;
1037 /*
1038 * For MPS mode, so far only needed by ES7000 platform
1039 */
1040 if (ioapic_renumber_irq)
1041 irq = ioapic_renumber_irq(apic, irq);
1042 }
1043
1044 #ifdef CONFIG_X86_32
1045 /*
1046 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1047 */
1048 if ((pin >= 16) && (pin <= 23)) {
1049 if (pirq_entries[pin-16] != -1) {
1050 if (!pirq_entries[pin-16]) {
1051 apic_printk(APIC_VERBOSE, KERN_DEBUG
1052 "disabling PIRQ%d\n", pin-16);
1053 } else {
1054 irq = pirq_entries[pin-16];
1055 apic_printk(APIC_VERBOSE, KERN_DEBUG
1056 "using PIRQ%d -> IRQ %d\n",
1057 pin-16, irq);
1058 }
1059 }
1060 }
1061 #endif
1062
1063 return irq;
1064 }
1065
1066 /*
1067 * Find a specific PCI IRQ entry.
1068 * Not an __init, possibly needed by modules
1069 */
1070 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1071 struct io_apic_irq_attr *irq_attr)
1072 {
1073 int apic, i, best_guess = -1;
1074
1075 apic_printk(APIC_DEBUG,
1076 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1077 bus, slot, pin);
1078 if (test_bit(bus, mp_bus_not_pci)) {
1079 apic_printk(APIC_VERBOSE,
1080 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1081 return -1;
1082 }
1083 for (i = 0; i < mp_irq_entries; i++) {
1084 int lbus = mp_irqs[i].srcbus;
1085
1086 for (apic = 0; apic < nr_ioapics; apic++)
1087 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1088 mp_irqs[i].dstapic == MP_APIC_ALL)
1089 break;
1090
1091 if (!test_bit(lbus, mp_bus_not_pci) &&
1092 !mp_irqs[i].irqtype &&
1093 (bus == lbus) &&
1094 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1095 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1096
1097 if (!(apic || IO_APIC_IRQ(irq)))
1098 continue;
1099
1100 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1101 set_io_apic_irq_attr(irq_attr, apic,
1102 mp_irqs[i].dstirq,
1103 irq_trigger(i),
1104 irq_polarity(i));
1105 return irq;
1106 }
1107 /*
1108 * Use the first all-but-pin matching entry as a
1109 * best-guess fuzzy result for broken mptables.
1110 */
1111 if (best_guess < 0) {
1112 set_io_apic_irq_attr(irq_attr, apic,
1113 mp_irqs[i].dstirq,
1114 irq_trigger(i),
1115 irq_polarity(i));
1116 best_guess = irq;
1117 }
1118 }
1119 }
1120 return best_guess;
1121 }
1122 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1123
1124 void lock_vector_lock(void)
1125 {
1126 /* Used to the online set of cpus does not change
1127 * during assign_irq_vector.
1128 */
1129 raw_spin_lock(&vector_lock);
1130 }
1131
1132 void unlock_vector_lock(void)
1133 {
1134 raw_spin_unlock(&vector_lock);
1135 }
1136
1137 static int
1138 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1139 {
1140 /*
1141 * NOTE! The local APIC isn't very good at handling
1142 * multiple interrupts at the same interrupt level.
1143 * As the interrupt level is determined by taking the
1144 * vector number and shifting that right by 4, we
1145 * want to spread these out a bit so that they don't
1146 * all fall in the same interrupt level.
1147 *
1148 * Also, we've got to be careful not to trash gate
1149 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1150 */
1151 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1152 static int current_offset = VECTOR_OFFSET_START % 8;
1153 unsigned int old_vector;
1154 int cpu, err;
1155 cpumask_var_t tmp_mask;
1156
1157 if (cfg->move_in_progress)
1158 return -EBUSY;
1159
1160 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1161 return -ENOMEM;
1162
1163 old_vector = cfg->vector;
1164 if (old_vector) {
1165 cpumask_and(tmp_mask, mask, cpu_online_mask);
1166 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1167 if (!cpumask_empty(tmp_mask)) {
1168 free_cpumask_var(tmp_mask);
1169 return 0;
1170 }
1171 }
1172
1173 /* Only try and allocate irqs on cpus that are present */
1174 err = -ENOSPC;
1175 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1176 int new_cpu;
1177 int vector, offset;
1178
1179 apic->vector_allocation_domain(cpu, tmp_mask);
1180
1181 vector = current_vector;
1182 offset = current_offset;
1183 next:
1184 vector += 8;
1185 if (vector >= first_system_vector) {
1186 /* If out of vectors on large boxen, must share them. */
1187 offset = (offset + 1) % 8;
1188 vector = FIRST_EXTERNAL_VECTOR + offset;
1189 }
1190 if (unlikely(current_vector == vector))
1191 continue;
1192
1193 if (test_bit(vector, used_vectors))
1194 goto next;
1195
1196 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1197 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1198 goto next;
1199 /* Found one! */
1200 current_vector = vector;
1201 current_offset = offset;
1202 if (old_vector) {
1203 cfg->move_in_progress = 1;
1204 cpumask_copy(cfg->old_domain, cfg->domain);
1205 }
1206 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1207 per_cpu(vector_irq, new_cpu)[vector] = irq;
1208 cfg->vector = vector;
1209 cpumask_copy(cfg->domain, tmp_mask);
1210 err = 0;
1211 break;
1212 }
1213 free_cpumask_var(tmp_mask);
1214 return err;
1215 }
1216
1217 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1218 {
1219 int err;
1220 unsigned long flags;
1221
1222 raw_spin_lock_irqsave(&vector_lock, flags);
1223 err = __assign_irq_vector(irq, cfg, mask);
1224 raw_spin_unlock_irqrestore(&vector_lock, flags);
1225 return err;
1226 }
1227
1228 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1229 {
1230 int cpu, vector;
1231
1232 BUG_ON(!cfg->vector);
1233
1234 vector = cfg->vector;
1235 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1236 per_cpu(vector_irq, cpu)[vector] = -1;
1237
1238 cfg->vector = 0;
1239 cpumask_clear(cfg->domain);
1240
1241 if (likely(!cfg->move_in_progress))
1242 return;
1243 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1244 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1245 vector++) {
1246 if (per_cpu(vector_irq, cpu)[vector] != irq)
1247 continue;
1248 per_cpu(vector_irq, cpu)[vector] = -1;
1249 break;
1250 }
1251 }
1252 cfg->move_in_progress = 0;
1253 }
1254
1255 void __setup_vector_irq(int cpu)
1256 {
1257 /* Initialize vector_irq on a new cpu */
1258 int irq, vector;
1259 struct irq_cfg *cfg;
1260 struct irq_desc *desc;
1261
1262 /*
1263 * vector_lock will make sure that we don't run into irq vector
1264 * assignments that might be happening on another cpu in parallel,
1265 * while we setup our initial vector to irq mappings.
1266 */
1267 raw_spin_lock(&vector_lock);
1268 /* Mark the inuse vectors */
1269 for_each_irq_desc(irq, desc) {
1270 cfg = desc->chip_data;
1271 if (!cpumask_test_cpu(cpu, cfg->domain))
1272 continue;
1273 vector = cfg->vector;
1274 per_cpu(vector_irq, cpu)[vector] = irq;
1275 }
1276 /* Mark the free vectors */
1277 for (vector = 0; vector < NR_VECTORS; ++vector) {
1278 irq = per_cpu(vector_irq, cpu)[vector];
1279 if (irq < 0)
1280 continue;
1281
1282 cfg = irq_cfg(irq);
1283 if (!cpumask_test_cpu(cpu, cfg->domain))
1284 per_cpu(vector_irq, cpu)[vector] = -1;
1285 }
1286 raw_spin_unlock(&vector_lock);
1287 }
1288
1289 static struct irq_chip ioapic_chip;
1290 static struct irq_chip ir_ioapic_chip;
1291
1292 #define IOAPIC_AUTO -1
1293 #define IOAPIC_EDGE 0
1294 #define IOAPIC_LEVEL 1
1295
1296 #ifdef CONFIG_X86_32
1297 static inline int IO_APIC_irq_trigger(int irq)
1298 {
1299 int apic, idx, pin;
1300
1301 for (apic = 0; apic < nr_ioapics; apic++) {
1302 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1303 idx = find_irq_entry(apic, pin, mp_INT);
1304 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1305 return irq_trigger(idx);
1306 }
1307 }
1308 /*
1309 * nonexistent IRQs are edge default
1310 */
1311 return 0;
1312 }
1313 #else
1314 static inline int IO_APIC_irq_trigger(int irq)
1315 {
1316 return 1;
1317 }
1318 #endif
1319
1320 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1321 {
1322
1323 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1324 trigger == IOAPIC_LEVEL)
1325 desc->status |= IRQ_LEVEL;
1326 else
1327 desc->status &= ~IRQ_LEVEL;
1328
1329 if (irq_remapped(irq)) {
1330 desc->status |= IRQ_MOVE_PCNTXT;
1331 if (trigger)
1332 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1333 handle_fasteoi_irq,
1334 "fasteoi");
1335 else
1336 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1337 handle_edge_irq, "edge");
1338 return;
1339 }
1340
1341 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1342 trigger == IOAPIC_LEVEL)
1343 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1344 handle_fasteoi_irq,
1345 "fasteoi");
1346 else
1347 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1348 handle_edge_irq, "edge");
1349 }
1350
1351 int setup_ioapic_entry(int apic_id, int irq,
1352 struct IO_APIC_route_entry *entry,
1353 unsigned int destination, int trigger,
1354 int polarity, int vector, int pin)
1355 {
1356 /*
1357 * add it to the IO-APIC irq-routing table:
1358 */
1359 memset(entry,0,sizeof(*entry));
1360
1361 if (intr_remapping_enabled) {
1362 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1363 struct irte irte;
1364 struct IR_IO_APIC_route_entry *ir_entry =
1365 (struct IR_IO_APIC_route_entry *) entry;
1366 int index;
1367
1368 if (!iommu)
1369 panic("No mapping iommu for ioapic %d\n", apic_id);
1370
1371 index = alloc_irte(iommu, irq, 1);
1372 if (index < 0)
1373 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1374
1375 memset(&irte, 0, sizeof(irte));
1376
1377 irte.present = 1;
1378 irte.dst_mode = apic->irq_dest_mode;
1379 /*
1380 * Trigger mode in the IRTE will always be edge, and the
1381 * actual level or edge trigger will be setup in the IO-APIC
1382 * RTE. This will help simplify level triggered irq migration.
1383 * For more details, see the comments above explainig IO-APIC
1384 * irq migration in the presence of interrupt-remapping.
1385 */
1386 irte.trigger_mode = 0;
1387 irte.dlvry_mode = apic->irq_delivery_mode;
1388 irte.vector = vector;
1389 irte.dest_id = IRTE_DEST(destination);
1390
1391 /* Set source-id of interrupt request */
1392 set_ioapic_sid(&irte, apic_id);
1393
1394 modify_irte(irq, &irte);
1395
1396 ir_entry->index2 = (index >> 15) & 0x1;
1397 ir_entry->zero = 0;
1398 ir_entry->format = 1;
1399 ir_entry->index = (index & 0x7fff);
1400 /*
1401 * IO-APIC RTE will be configured with virtual vector.
1402 * irq handler will do the explicit EOI to the io-apic.
1403 */
1404 ir_entry->vector = pin;
1405 } else {
1406 entry->delivery_mode = apic->irq_delivery_mode;
1407 entry->dest_mode = apic->irq_dest_mode;
1408 entry->dest = destination;
1409 entry->vector = vector;
1410 }
1411
1412 entry->mask = 0; /* enable IRQ */
1413 entry->trigger = trigger;
1414 entry->polarity = polarity;
1415
1416 /* Mask level triggered irqs.
1417 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1418 */
1419 if (trigger)
1420 entry->mask = 1;
1421 return 0;
1422 }
1423
1424 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1425 int trigger, int polarity)
1426 {
1427 struct irq_cfg *cfg;
1428 struct IO_APIC_route_entry entry;
1429 unsigned int dest;
1430
1431 if (!IO_APIC_IRQ(irq))
1432 return;
1433
1434 cfg = desc->chip_data;
1435
1436 /*
1437 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1438 * controllers like 8259. Now that IO-APIC can handle this irq, update
1439 * the cfg->domain.
1440 */
1441 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1442 apic->vector_allocation_domain(0, cfg->domain);
1443
1444 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1445 return;
1446
1447 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1448
1449 apic_printk(APIC_VERBOSE,KERN_DEBUG
1450 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1451 "IRQ %d Mode:%i Active:%i)\n",
1452 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1453 irq, trigger, polarity);
1454
1455
1456 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1457 dest, trigger, polarity, cfg->vector, pin)) {
1458 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1459 mp_ioapics[apic_id].apicid, pin);
1460 __clear_irq_vector(irq, cfg);
1461 return;
1462 }
1463
1464 ioapic_register_intr(irq, desc, trigger);
1465 if (irq < legacy_pic->nr_legacy_irqs)
1466 legacy_pic->chip->mask(irq);
1467
1468 ioapic_write_entry(apic_id, pin, entry);
1469 }
1470
1471 static struct {
1472 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1473 } mp_ioapic_routing[MAX_IO_APICS];
1474
1475 static void __init setup_IO_APIC_irqs(void)
1476 {
1477 int apic_id, pin, idx, irq;
1478 int notcon = 0;
1479 struct irq_desc *desc;
1480 struct irq_cfg *cfg;
1481 int node = cpu_to_node(boot_cpu_id);
1482
1483 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1484
1485 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1486 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1487 idx = find_irq_entry(apic_id, pin, mp_INT);
1488 if (idx == -1) {
1489 if (!notcon) {
1490 notcon = 1;
1491 apic_printk(APIC_VERBOSE,
1492 KERN_DEBUG " %d-%d",
1493 mp_ioapics[apic_id].apicid, pin);
1494 } else
1495 apic_printk(APIC_VERBOSE, " %d-%d",
1496 mp_ioapics[apic_id].apicid, pin);
1497 continue;
1498 }
1499 if (notcon) {
1500 apic_printk(APIC_VERBOSE,
1501 " (apicid-pin) not connected\n");
1502 notcon = 0;
1503 }
1504
1505 irq = pin_2_irq(idx, apic_id, pin);
1506
1507 if ((apic_id > 0) && (irq > 16))
1508 continue;
1509
1510 /*
1511 * Skip the timer IRQ if there's a quirk handler
1512 * installed and if it returns 1:
1513 */
1514 if (apic->multi_timer_check &&
1515 apic->multi_timer_check(apic_id, irq))
1516 continue;
1517
1518 desc = irq_to_desc_alloc_node(irq, node);
1519 if (!desc) {
1520 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1521 continue;
1522 }
1523 cfg = desc->chip_data;
1524 add_pin_to_irq_node(cfg, node, apic_id, pin);
1525 /*
1526 * don't mark it in pin_programmed, so later acpi could
1527 * set it correctly when irq < 16
1528 */
1529 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1530 irq_trigger(idx), irq_polarity(idx));
1531 }
1532
1533 if (notcon)
1534 apic_printk(APIC_VERBOSE,
1535 " (apicid-pin) not connected\n");
1536 }
1537
1538 /*
1539 * for the gsit that is not in first ioapic
1540 * but could not use acpi_register_gsi()
1541 * like some special sci in IBM x3330
1542 */
1543 void setup_IO_APIC_irq_extra(u32 gsi)
1544 {
1545 int apic_id = 0, pin, idx, irq;
1546 int node = cpu_to_node(boot_cpu_id);
1547 struct irq_desc *desc;
1548 struct irq_cfg *cfg;
1549
1550 /*
1551 * Convert 'gsi' to 'ioapic.pin'.
1552 */
1553 apic_id = mp_find_ioapic(gsi);
1554 if (apic_id < 0)
1555 return;
1556
1557 pin = mp_find_ioapic_pin(apic_id, gsi);
1558 idx = find_irq_entry(apic_id, pin, mp_INT);
1559 if (idx == -1)
1560 return;
1561
1562 irq = pin_2_irq(idx, apic_id, pin);
1563 #ifdef CONFIG_SPARSE_IRQ
1564 desc = irq_to_desc(irq);
1565 if (desc)
1566 return;
1567 #endif
1568 desc = irq_to_desc_alloc_node(irq, node);
1569 if (!desc) {
1570 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1571 return;
1572 }
1573
1574 cfg = desc->chip_data;
1575 add_pin_to_irq_node(cfg, node, apic_id, pin);
1576
1577 if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
1578 pr_debug("Pin %d-%d already programmed\n",
1579 mp_ioapics[apic_id].apicid, pin);
1580 return;
1581 }
1582 set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
1583
1584 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1585 irq_trigger(idx), irq_polarity(idx));
1586 }
1587
1588 /*
1589 * Set up the timer pin, possibly with the 8259A-master behind.
1590 */
1591 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1592 int vector)
1593 {
1594 struct IO_APIC_route_entry entry;
1595
1596 if (intr_remapping_enabled)
1597 return;
1598
1599 memset(&entry, 0, sizeof(entry));
1600
1601 /*
1602 * We use logical delivery to get the timer IRQ
1603 * to the first CPU.
1604 */
1605 entry.dest_mode = apic->irq_dest_mode;
1606 entry.mask = 0; /* don't mask IRQ for edge */
1607 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1608 entry.delivery_mode = apic->irq_delivery_mode;
1609 entry.polarity = 0;
1610 entry.trigger = 0;
1611 entry.vector = vector;
1612
1613 /*
1614 * The timer IRQ doesn't have to know that behind the
1615 * scene we may have a 8259A-master in AEOI mode ...
1616 */
1617 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1618
1619 /*
1620 * Add it to the IO-APIC irq-routing table:
1621 */
1622 ioapic_write_entry(apic_id, pin, entry);
1623 }
1624
1625
1626 __apicdebuginit(void) print_IO_APIC(void)
1627 {
1628 int apic, i;
1629 union IO_APIC_reg_00 reg_00;
1630 union IO_APIC_reg_01 reg_01;
1631 union IO_APIC_reg_02 reg_02;
1632 union IO_APIC_reg_03 reg_03;
1633 unsigned long flags;
1634 struct irq_cfg *cfg;
1635 struct irq_desc *desc;
1636 unsigned int irq;
1637
1638 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1639 for (i = 0; i < nr_ioapics; i++)
1640 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1641 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1642
1643 /*
1644 * We are a bit conservative about what we expect. We have to
1645 * know about every hardware change ASAP.
1646 */
1647 printk(KERN_INFO "testing the IO APIC.......................\n");
1648
1649 for (apic = 0; apic < nr_ioapics; apic++) {
1650
1651 raw_spin_lock_irqsave(&ioapic_lock, flags);
1652 reg_00.raw = io_apic_read(apic, 0);
1653 reg_01.raw = io_apic_read(apic, 1);
1654 if (reg_01.bits.version >= 0x10)
1655 reg_02.raw = io_apic_read(apic, 2);
1656 if (reg_01.bits.version >= 0x20)
1657 reg_03.raw = io_apic_read(apic, 3);
1658 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1659
1660 printk("\n");
1661 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1662 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1663 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1664 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1665 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1666
1667 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1668 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1669
1670 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1671 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1672
1673 /*
1674 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1675 * but the value of reg_02 is read as the previous read register
1676 * value, so ignore it if reg_02 == reg_01.
1677 */
1678 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1679 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1680 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1681 }
1682
1683 /*
1684 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1685 * or reg_03, but the value of reg_0[23] is read as the previous read
1686 * register value, so ignore it if reg_03 == reg_0[12].
1687 */
1688 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1689 reg_03.raw != reg_01.raw) {
1690 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1691 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1692 }
1693
1694 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1695
1696 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1697 " Stat Dmod Deli Vect:\n");
1698
1699 for (i = 0; i <= reg_01.bits.entries; i++) {
1700 struct IO_APIC_route_entry entry;
1701
1702 entry = ioapic_read_entry(apic, i);
1703
1704 printk(KERN_DEBUG " %02x %03X ",
1705 i,
1706 entry.dest
1707 );
1708
1709 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1710 entry.mask,
1711 entry.trigger,
1712 entry.irr,
1713 entry.polarity,
1714 entry.delivery_status,
1715 entry.dest_mode,
1716 entry.delivery_mode,
1717 entry.vector
1718 );
1719 }
1720 }
1721 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1722 for_each_irq_desc(irq, desc) {
1723 struct irq_pin_list *entry;
1724
1725 cfg = desc->chip_data;
1726 entry = cfg->irq_2_pin;
1727 if (!entry)
1728 continue;
1729 printk(KERN_DEBUG "IRQ%d ", irq);
1730 for_each_irq_pin(entry, cfg->irq_2_pin)
1731 printk("-> %d:%d", entry->apic, entry->pin);
1732 printk("\n");
1733 }
1734
1735 printk(KERN_INFO ".................................... done.\n");
1736
1737 return;
1738 }
1739
1740 __apicdebuginit(void) print_APIC_field(int base)
1741 {
1742 int i;
1743
1744 printk(KERN_DEBUG);
1745
1746 for (i = 0; i < 8; i++)
1747 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1748
1749 printk(KERN_CONT "\n");
1750 }
1751
1752 __apicdebuginit(void) print_local_APIC(void *dummy)
1753 {
1754 unsigned int i, v, ver, maxlvt;
1755 u64 icr;
1756
1757 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1758 smp_processor_id(), hard_smp_processor_id());
1759 v = apic_read(APIC_ID);
1760 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1761 v = apic_read(APIC_LVR);
1762 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1763 ver = GET_APIC_VERSION(v);
1764 maxlvt = lapic_get_maxlvt();
1765
1766 v = apic_read(APIC_TASKPRI);
1767 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1768
1769 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1770 if (!APIC_XAPIC(ver)) {
1771 v = apic_read(APIC_ARBPRI);
1772 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1773 v & APIC_ARBPRI_MASK);
1774 }
1775 v = apic_read(APIC_PROCPRI);
1776 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1777 }
1778
1779 /*
1780 * Remote read supported only in the 82489DX and local APIC for
1781 * Pentium processors.
1782 */
1783 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1784 v = apic_read(APIC_RRR);
1785 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1786 }
1787
1788 v = apic_read(APIC_LDR);
1789 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1790 if (!x2apic_enabled()) {
1791 v = apic_read(APIC_DFR);
1792 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1793 }
1794 v = apic_read(APIC_SPIV);
1795 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1796
1797 printk(KERN_DEBUG "... APIC ISR field:\n");
1798 print_APIC_field(APIC_ISR);
1799 printk(KERN_DEBUG "... APIC TMR field:\n");
1800 print_APIC_field(APIC_TMR);
1801 printk(KERN_DEBUG "... APIC IRR field:\n");
1802 print_APIC_field(APIC_IRR);
1803
1804 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1805 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1806 apic_write(APIC_ESR, 0);
1807
1808 v = apic_read(APIC_ESR);
1809 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1810 }
1811
1812 icr = apic_icr_read();
1813 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1814 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1815
1816 v = apic_read(APIC_LVTT);
1817 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1818
1819 if (maxlvt > 3) { /* PC is LVT#4. */
1820 v = apic_read(APIC_LVTPC);
1821 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1822 }
1823 v = apic_read(APIC_LVT0);
1824 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1825 v = apic_read(APIC_LVT1);
1826 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1827
1828 if (maxlvt > 2) { /* ERR is LVT#3. */
1829 v = apic_read(APIC_LVTERR);
1830 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1831 }
1832
1833 v = apic_read(APIC_TMICT);
1834 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1835 v = apic_read(APIC_TMCCT);
1836 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1837 v = apic_read(APIC_TDCR);
1838 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1839
1840 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1841 v = apic_read(APIC_EFEAT);
1842 maxlvt = (v >> 16) & 0xff;
1843 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1844 v = apic_read(APIC_ECTRL);
1845 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1846 for (i = 0; i < maxlvt; i++) {
1847 v = apic_read(APIC_EILVTn(i));
1848 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1849 }
1850 }
1851 printk("\n");
1852 }
1853
1854 __apicdebuginit(void) print_local_APICs(int maxcpu)
1855 {
1856 int cpu;
1857
1858 if (!maxcpu)
1859 return;
1860
1861 preempt_disable();
1862 for_each_online_cpu(cpu) {
1863 if (cpu >= maxcpu)
1864 break;
1865 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1866 }
1867 preempt_enable();
1868 }
1869
1870 __apicdebuginit(void) print_PIC(void)
1871 {
1872 unsigned int v;
1873 unsigned long flags;
1874
1875 if (!legacy_pic->nr_legacy_irqs)
1876 return;
1877
1878 printk(KERN_DEBUG "\nprinting PIC contents\n");
1879
1880 raw_spin_lock_irqsave(&i8259A_lock, flags);
1881
1882 v = inb(0xa1) << 8 | inb(0x21);
1883 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1884
1885 v = inb(0xa0) << 8 | inb(0x20);
1886 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1887
1888 outb(0x0b,0xa0);
1889 outb(0x0b,0x20);
1890 v = inb(0xa0) << 8 | inb(0x20);
1891 outb(0x0a,0xa0);
1892 outb(0x0a,0x20);
1893
1894 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1895
1896 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1897
1898 v = inb(0x4d1) << 8 | inb(0x4d0);
1899 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1900 }
1901
1902 static int __initdata show_lapic = 1;
1903 static __init int setup_show_lapic(char *arg)
1904 {
1905 int num = -1;
1906
1907 if (strcmp(arg, "all") == 0) {
1908 show_lapic = CONFIG_NR_CPUS;
1909 } else {
1910 get_option(&arg, &num);
1911 if (num >= 0)
1912 show_lapic = num;
1913 }
1914
1915 return 1;
1916 }
1917 __setup("show_lapic=", setup_show_lapic);
1918
1919 __apicdebuginit(int) print_ICs(void)
1920 {
1921 if (apic_verbosity == APIC_QUIET)
1922 return 0;
1923
1924 print_PIC();
1925
1926 /* don't print out if apic is not there */
1927 if (!cpu_has_apic && !apic_from_smp_config())
1928 return 0;
1929
1930 print_local_APICs(show_lapic);
1931 print_IO_APIC();
1932
1933 return 0;
1934 }
1935
1936 fs_initcall(print_ICs);
1937
1938
1939 /* Where if anywhere is the i8259 connect in external int mode */
1940 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1941
1942 void __init enable_IO_APIC(void)
1943 {
1944 union IO_APIC_reg_01 reg_01;
1945 int i8259_apic, i8259_pin;
1946 int apic;
1947 unsigned long flags;
1948
1949 /*
1950 * The number of IO-APIC IRQ registers (== #pins):
1951 */
1952 for (apic = 0; apic < nr_ioapics; apic++) {
1953 raw_spin_lock_irqsave(&ioapic_lock, flags);
1954 reg_01.raw = io_apic_read(apic, 1);
1955 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1956 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1957 }
1958
1959 if (!legacy_pic->nr_legacy_irqs)
1960 return;
1961
1962 for(apic = 0; apic < nr_ioapics; apic++) {
1963 int pin;
1964 /* See if any of the pins is in ExtINT mode */
1965 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1966 struct IO_APIC_route_entry entry;
1967 entry = ioapic_read_entry(apic, pin);
1968
1969 /* If the interrupt line is enabled and in ExtInt mode
1970 * I have found the pin where the i8259 is connected.
1971 */
1972 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1973 ioapic_i8259.apic = apic;
1974 ioapic_i8259.pin = pin;
1975 goto found_i8259;
1976 }
1977 }
1978 }
1979 found_i8259:
1980 /* Look to see what if the MP table has reported the ExtINT */
1981 /* If we could not find the appropriate pin by looking at the ioapic
1982 * the i8259 probably is not connected the ioapic but give the
1983 * mptable a chance anyway.
1984 */
1985 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1986 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1987 /* Trust the MP table if nothing is setup in the hardware */
1988 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1989 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1990 ioapic_i8259.pin = i8259_pin;
1991 ioapic_i8259.apic = i8259_apic;
1992 }
1993 /* Complain if the MP table and the hardware disagree */
1994 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1995 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1996 {
1997 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1998 }
1999
2000 /*
2001 * Do not trust the IO-APIC being empty at bootup
2002 */
2003 clear_IO_APIC();
2004 }
2005
2006 /*
2007 * Not an __init, needed by the reboot code
2008 */
2009 void disable_IO_APIC(void)
2010 {
2011 /*
2012 * Clear the IO-APIC before rebooting:
2013 */
2014 clear_IO_APIC();
2015
2016 if (!legacy_pic->nr_legacy_irqs)
2017 return;
2018
2019 /*
2020 * If the i8259 is routed through an IOAPIC
2021 * Put that IOAPIC in virtual wire mode
2022 * so legacy interrupts can be delivered.
2023 *
2024 * With interrupt-remapping, for now we will use virtual wire A mode,
2025 * as virtual wire B is little complex (need to configure both
2026 * IOAPIC RTE aswell as interrupt-remapping table entry).
2027 * As this gets called during crash dump, keep this simple for now.
2028 */
2029 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2030 struct IO_APIC_route_entry entry;
2031
2032 memset(&entry, 0, sizeof(entry));
2033 entry.mask = 0; /* Enabled */
2034 entry.trigger = 0; /* Edge */
2035 entry.irr = 0;
2036 entry.polarity = 0; /* High */
2037 entry.delivery_status = 0;
2038 entry.dest_mode = 0; /* Physical */
2039 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2040 entry.vector = 0;
2041 entry.dest = read_apic_id();
2042
2043 /*
2044 * Add it to the IO-APIC irq-routing table:
2045 */
2046 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2047 }
2048
2049 /*
2050 * Use virtual wire A mode when interrupt remapping is enabled.
2051 */
2052 if (cpu_has_apic || apic_from_smp_config())
2053 disconnect_bsp_APIC(!intr_remapping_enabled &&
2054 ioapic_i8259.pin != -1);
2055 }
2056
2057 #ifdef CONFIG_X86_32
2058 /*
2059 * function to set the IO-APIC physical IDs based on the
2060 * values stored in the MPC table.
2061 *
2062 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2063 */
2064
2065 void __init setup_ioapic_ids_from_mpc(void)
2066 {
2067 union IO_APIC_reg_00 reg_00;
2068 physid_mask_t phys_id_present_map;
2069 int apic_id;
2070 int i;
2071 unsigned char old_id;
2072 unsigned long flags;
2073
2074 if (acpi_ioapic)
2075 return;
2076 /*
2077 * Don't check I/O APIC IDs for xAPIC systems. They have
2078 * no meaning without the serial APIC bus.
2079 */
2080 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2081 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2082 return;
2083 /*
2084 * This is broken; anything with a real cpu count has to
2085 * circumvent this idiocy regardless.
2086 */
2087 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2088
2089 /*
2090 * Set the IOAPIC ID to the value stored in the MPC table.
2091 */
2092 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2093
2094 /* Read the register 0 value */
2095 raw_spin_lock_irqsave(&ioapic_lock, flags);
2096 reg_00.raw = io_apic_read(apic_id, 0);
2097 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2098
2099 old_id = mp_ioapics[apic_id].apicid;
2100
2101 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2102 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2103 apic_id, mp_ioapics[apic_id].apicid);
2104 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2105 reg_00.bits.ID);
2106 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2107 }
2108
2109 /*
2110 * Sanity check, is the ID really free? Every APIC in a
2111 * system must have a unique ID or we get lots of nice
2112 * 'stuck on smp_invalidate_needed IPI wait' messages.
2113 */
2114 if (apic->check_apicid_used(&phys_id_present_map,
2115 mp_ioapics[apic_id].apicid)) {
2116 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2117 apic_id, mp_ioapics[apic_id].apicid);
2118 for (i = 0; i < get_physical_broadcast(); i++)
2119 if (!physid_isset(i, phys_id_present_map))
2120 break;
2121 if (i >= get_physical_broadcast())
2122 panic("Max APIC ID exceeded!\n");
2123 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2124 i);
2125 physid_set(i, phys_id_present_map);
2126 mp_ioapics[apic_id].apicid = i;
2127 } else {
2128 physid_mask_t tmp;
2129 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2130 apic_printk(APIC_VERBOSE, "Setting %d in the "
2131 "phys_id_present_map\n",
2132 mp_ioapics[apic_id].apicid);
2133 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2134 }
2135
2136
2137 /*
2138 * We need to adjust the IRQ routing table
2139 * if the ID changed.
2140 */
2141 if (old_id != mp_ioapics[apic_id].apicid)
2142 for (i = 0; i < mp_irq_entries; i++)
2143 if (mp_irqs[i].dstapic == old_id)
2144 mp_irqs[i].dstapic
2145 = mp_ioapics[apic_id].apicid;
2146
2147 /*
2148 * Read the right value from the MPC table and
2149 * write it into the ID register.
2150 */
2151 apic_printk(APIC_VERBOSE, KERN_INFO
2152 "...changing IO-APIC physical APIC ID to %d ...",
2153 mp_ioapics[apic_id].apicid);
2154
2155 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2156 raw_spin_lock_irqsave(&ioapic_lock, flags);
2157 io_apic_write(apic_id, 0, reg_00.raw);
2158 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2159
2160 /*
2161 * Sanity check
2162 */
2163 raw_spin_lock_irqsave(&ioapic_lock, flags);
2164 reg_00.raw = io_apic_read(apic_id, 0);
2165 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2166 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2167 printk("could not set ID!\n");
2168 else
2169 apic_printk(APIC_VERBOSE, " ok.\n");
2170 }
2171 }
2172 #endif
2173
2174 int no_timer_check __initdata;
2175
2176 static int __init notimercheck(char *s)
2177 {
2178 no_timer_check = 1;
2179 return 1;
2180 }
2181 __setup("no_timer_check", notimercheck);
2182
2183 /*
2184 * There is a nasty bug in some older SMP boards, their mptable lies
2185 * about the timer IRQ. We do the following to work around the situation:
2186 *
2187 * - timer IRQ defaults to IO-APIC IRQ
2188 * - if this function detects that timer IRQs are defunct, then we fall
2189 * back to ISA timer IRQs
2190 */
2191 static int __init timer_irq_works(void)
2192 {
2193 unsigned long t1 = jiffies;
2194 unsigned long flags;
2195
2196 if (no_timer_check)
2197 return 1;
2198
2199 local_save_flags(flags);
2200 local_irq_enable();
2201 /* Let ten ticks pass... */
2202 mdelay((10 * 1000) / HZ);
2203 local_irq_restore(flags);
2204
2205 /*
2206 * Expect a few ticks at least, to be sure some possible
2207 * glue logic does not lock up after one or two first
2208 * ticks in a non-ExtINT mode. Also the local APIC
2209 * might have cached one ExtINT interrupt. Finally, at
2210 * least one tick may be lost due to delays.
2211 */
2212
2213 /* jiffies wrap? */
2214 if (time_after(jiffies, t1 + 4))
2215 return 1;
2216 return 0;
2217 }
2218
2219 /*
2220 * In the SMP+IOAPIC case it might happen that there are an unspecified
2221 * number of pending IRQ events unhandled. These cases are very rare,
2222 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2223 * better to do it this way as thus we do not have to be aware of
2224 * 'pending' interrupts in the IRQ path, except at this point.
2225 */
2226 /*
2227 * Edge triggered needs to resend any interrupt
2228 * that was delayed but this is now handled in the device
2229 * independent code.
2230 */
2231
2232 /*
2233 * Starting up a edge-triggered IO-APIC interrupt is
2234 * nasty - we need to make sure that we get the edge.
2235 * If it is already asserted for some reason, we need
2236 * return 1 to indicate that is was pending.
2237 *
2238 * This is not complete - we should be able to fake
2239 * an edge even if it isn't on the 8259A...
2240 */
2241
2242 static unsigned int startup_ioapic_irq(unsigned int irq)
2243 {
2244 int was_pending = 0;
2245 unsigned long flags;
2246 struct irq_cfg *cfg;
2247
2248 raw_spin_lock_irqsave(&ioapic_lock, flags);
2249 if (irq < legacy_pic->nr_legacy_irqs) {
2250 legacy_pic->chip->mask(irq);
2251 if (legacy_pic->irq_pending(irq))
2252 was_pending = 1;
2253 }
2254 cfg = irq_cfg(irq);
2255 __unmask_IO_APIC_irq(cfg);
2256 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2257
2258 return was_pending;
2259 }
2260
2261 static int ioapic_retrigger_irq(unsigned int irq)
2262 {
2263
2264 struct irq_cfg *cfg = irq_cfg(irq);
2265 unsigned long flags;
2266
2267 raw_spin_lock_irqsave(&vector_lock, flags);
2268 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2269 raw_spin_unlock_irqrestore(&vector_lock, flags);
2270
2271 return 1;
2272 }
2273
2274 /*
2275 * Level and edge triggered IO-APIC interrupts need different handling,
2276 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2277 * handled with the level-triggered descriptor, but that one has slightly
2278 * more overhead. Level-triggered interrupts cannot be handled with the
2279 * edge-triggered handler, without risking IRQ storms and other ugly
2280 * races.
2281 */
2282
2283 #ifdef CONFIG_SMP
2284 void send_cleanup_vector(struct irq_cfg *cfg)
2285 {
2286 cpumask_var_t cleanup_mask;
2287
2288 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2289 unsigned int i;
2290 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2291 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2292 } else {
2293 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2294 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2295 free_cpumask_var(cleanup_mask);
2296 }
2297 cfg->move_in_progress = 0;
2298 }
2299
2300 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2301 {
2302 int apic, pin;
2303 struct irq_pin_list *entry;
2304 u8 vector = cfg->vector;
2305
2306 for_each_irq_pin(entry, cfg->irq_2_pin) {
2307 unsigned int reg;
2308
2309 apic = entry->apic;
2310 pin = entry->pin;
2311 /*
2312 * With interrupt-remapping, destination information comes
2313 * from interrupt-remapping table entry.
2314 */
2315 if (!irq_remapped(irq))
2316 io_apic_write(apic, 0x11 + pin*2, dest);
2317 reg = io_apic_read(apic, 0x10 + pin*2);
2318 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2319 reg |= vector;
2320 io_apic_modify(apic, 0x10 + pin*2, reg);
2321 }
2322 }
2323
2324 /*
2325 * Either sets desc->affinity to a valid value, and returns
2326 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2327 * leaves desc->affinity untouched.
2328 */
2329 unsigned int
2330 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2331 unsigned int *dest_id)
2332 {
2333 struct irq_cfg *cfg;
2334 unsigned int irq;
2335
2336 if (!cpumask_intersects(mask, cpu_online_mask))
2337 return -1;
2338
2339 irq = desc->irq;
2340 cfg = desc->chip_data;
2341 if (assign_irq_vector(irq, cfg, mask))
2342 return -1;
2343
2344 cpumask_copy(desc->affinity, mask);
2345
2346 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2347 return 0;
2348 }
2349
2350 static int
2351 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2352 {
2353 struct irq_cfg *cfg;
2354 unsigned long flags;
2355 unsigned int dest;
2356 unsigned int irq;
2357 int ret = -1;
2358
2359 irq = desc->irq;
2360 cfg = desc->chip_data;
2361
2362 raw_spin_lock_irqsave(&ioapic_lock, flags);
2363 ret = set_desc_affinity(desc, mask, &dest);
2364 if (!ret) {
2365 /* Only the high 8 bits are valid. */
2366 dest = SET_APIC_LOGICAL_ID(dest);
2367 __target_IO_APIC_irq(irq, dest, cfg);
2368 }
2369 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2370
2371 return ret;
2372 }
2373
2374 static int
2375 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2376 {
2377 struct irq_desc *desc;
2378
2379 desc = irq_to_desc(irq);
2380
2381 return set_ioapic_affinity_irq_desc(desc, mask);
2382 }
2383
2384 #ifdef CONFIG_INTR_REMAP
2385
2386 /*
2387 * Migrate the IO-APIC irq in the presence of intr-remapping.
2388 *
2389 * For both level and edge triggered, irq migration is a simple atomic
2390 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2391 *
2392 * For level triggered, we eliminate the io-apic RTE modification (with the
2393 * updated vector information), by using a virtual vector (io-apic pin number).
2394 * Real vector that is used for interrupting cpu will be coming from
2395 * the interrupt-remapping table entry.
2396 */
2397 static int
2398 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2399 {
2400 struct irq_cfg *cfg;
2401 struct irte irte;
2402 unsigned int dest;
2403 unsigned int irq;
2404 int ret = -1;
2405
2406 if (!cpumask_intersects(mask, cpu_online_mask))
2407 return ret;
2408
2409 irq = desc->irq;
2410 if (get_irte(irq, &irte))
2411 return ret;
2412
2413 cfg = desc->chip_data;
2414 if (assign_irq_vector(irq, cfg, mask))
2415 return ret;
2416
2417 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2418
2419 irte.vector = cfg->vector;
2420 irte.dest_id = IRTE_DEST(dest);
2421
2422 /*
2423 * Modified the IRTE and flushes the Interrupt entry cache.
2424 */
2425 modify_irte(irq, &irte);
2426
2427 if (cfg->move_in_progress)
2428 send_cleanup_vector(cfg);
2429
2430 cpumask_copy(desc->affinity, mask);
2431
2432 return 0;
2433 }
2434
2435 /*
2436 * Migrates the IRQ destination in the process context.
2437 */
2438 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2439 const struct cpumask *mask)
2440 {
2441 return migrate_ioapic_irq_desc(desc, mask);
2442 }
2443 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2444 const struct cpumask *mask)
2445 {
2446 struct irq_desc *desc = irq_to_desc(irq);
2447
2448 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2449 }
2450 #else
2451 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2452 const struct cpumask *mask)
2453 {
2454 return 0;
2455 }
2456 #endif
2457
2458 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2459 {
2460 unsigned vector, me;
2461
2462 ack_APIC_irq();
2463 exit_idle();
2464 irq_enter();
2465
2466 me = smp_processor_id();
2467 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2468 unsigned int irq;
2469 unsigned int irr;
2470 struct irq_desc *desc;
2471 struct irq_cfg *cfg;
2472 irq = __get_cpu_var(vector_irq)[vector];
2473
2474 if (irq == -1)
2475 continue;
2476
2477 desc = irq_to_desc(irq);
2478 if (!desc)
2479 continue;
2480
2481 cfg = irq_cfg(irq);
2482 raw_spin_lock(&desc->lock);
2483
2484 /*
2485 * Check if the irq migration is in progress. If so, we
2486 * haven't received the cleanup request yet for this irq.
2487 */
2488 if (cfg->move_in_progress)
2489 goto unlock;
2490
2491 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2492 goto unlock;
2493
2494 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2495 /*
2496 * Check if the vector that needs to be cleanedup is
2497 * registered at the cpu's IRR. If so, then this is not
2498 * the best time to clean it up. Lets clean it up in the
2499 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2500 * to myself.
2501 */
2502 if (irr & (1 << (vector % 32))) {
2503 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2504 goto unlock;
2505 }
2506 __get_cpu_var(vector_irq)[vector] = -1;
2507 unlock:
2508 raw_spin_unlock(&desc->lock);
2509 }
2510
2511 irq_exit();
2512 }
2513
2514 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2515 {
2516 struct irq_desc *desc = *descp;
2517 struct irq_cfg *cfg = desc->chip_data;
2518 unsigned me;
2519
2520 if (likely(!cfg->move_in_progress))
2521 return;
2522
2523 me = smp_processor_id();
2524
2525 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2526 send_cleanup_vector(cfg);
2527 }
2528
2529 static void irq_complete_move(struct irq_desc **descp)
2530 {
2531 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2532 }
2533
2534 void irq_force_complete_move(int irq)
2535 {
2536 struct irq_desc *desc = irq_to_desc(irq);
2537 struct irq_cfg *cfg = desc->chip_data;
2538
2539 __irq_complete_move(&desc, cfg->vector);
2540 }
2541 #else
2542 static inline void irq_complete_move(struct irq_desc **descp) {}
2543 #endif
2544
2545 static void ack_apic_edge(unsigned int irq)
2546 {
2547 struct irq_desc *desc = irq_to_desc(irq);
2548
2549 irq_complete_move(&desc);
2550 move_native_irq(irq);
2551 ack_APIC_irq();
2552 }
2553
2554 atomic_t irq_mis_count;
2555
2556 /*
2557 * IO-APIC versions below 0x20 don't support EOI register.
2558 * For the record, here is the information about various versions:
2559 * 0Xh 82489DX
2560 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2561 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2562 * 30h-FFh Reserved
2563 *
2564 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2565 * version as 0x2. This is an error with documentation and these ICH chips
2566 * use io-apic's of version 0x20.
2567 *
2568 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2569 * Otherwise, we simulate the EOI message manually by changing the trigger
2570 * mode to edge and then back to level, with RTE being masked during this.
2571 */
2572 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2573 {
2574 struct irq_pin_list *entry;
2575
2576 for_each_irq_pin(entry, cfg->irq_2_pin) {
2577 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2578 /*
2579 * Intr-remapping uses pin number as the virtual vector
2580 * in the RTE. Actual vector is programmed in
2581 * intr-remapping table entry. Hence for the io-apic
2582 * EOI we use the pin number.
2583 */
2584 if (irq_remapped(irq))
2585 io_apic_eoi(entry->apic, entry->pin);
2586 else
2587 io_apic_eoi(entry->apic, cfg->vector);
2588 } else {
2589 __mask_and_edge_IO_APIC_irq(entry);
2590 __unmask_and_level_IO_APIC_irq(entry);
2591 }
2592 }
2593 }
2594
2595 static void eoi_ioapic_irq(struct irq_desc *desc)
2596 {
2597 struct irq_cfg *cfg;
2598 unsigned long flags;
2599 unsigned int irq;
2600
2601 irq = desc->irq;
2602 cfg = desc->chip_data;
2603
2604 raw_spin_lock_irqsave(&ioapic_lock, flags);
2605 __eoi_ioapic_irq(irq, cfg);
2606 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2607 }
2608
2609 static void ack_apic_level(unsigned int irq)
2610 {
2611 struct irq_desc *desc = irq_to_desc(irq);
2612 unsigned long v;
2613 int i;
2614 struct irq_cfg *cfg;
2615 int do_unmask_irq = 0;
2616
2617 irq_complete_move(&desc);
2618 #ifdef CONFIG_GENERIC_PENDING_IRQ
2619 /* If we are moving the irq we need to mask it */
2620 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2621 do_unmask_irq = 1;
2622 mask_IO_APIC_irq_desc(desc);
2623 }
2624 #endif
2625
2626 /*
2627 * It appears there is an erratum which affects at least version 0x11
2628 * of I/O APIC (that's the 82093AA and cores integrated into various
2629 * chipsets). Under certain conditions a level-triggered interrupt is
2630 * erroneously delivered as edge-triggered one but the respective IRR
2631 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2632 * message but it will never arrive and further interrupts are blocked
2633 * from the source. The exact reason is so far unknown, but the
2634 * phenomenon was observed when two consecutive interrupt requests
2635 * from a given source get delivered to the same CPU and the source is
2636 * temporarily disabled in between.
2637 *
2638 * A workaround is to simulate an EOI message manually. We achieve it
2639 * by setting the trigger mode to edge and then to level when the edge
2640 * trigger mode gets detected in the TMR of a local APIC for a
2641 * level-triggered interrupt. We mask the source for the time of the
2642 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2643 * The idea is from Manfred Spraul. --macro
2644 *
2645 * Also in the case when cpu goes offline, fixup_irqs() will forward
2646 * any unhandled interrupt on the offlined cpu to the new cpu
2647 * destination that is handling the corresponding interrupt. This
2648 * interrupt forwarding is done via IPI's. Hence, in this case also
2649 * level-triggered io-apic interrupt will be seen as an edge
2650 * interrupt in the IRR. And we can't rely on the cpu's EOI
2651 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2652 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2653 * supporting EOI register, we do an explicit EOI to clear the
2654 * remote IRR and on IO-APIC's which don't have an EOI register,
2655 * we use the above logic (mask+edge followed by unmask+level) from
2656 * Manfred Spraul to clear the remote IRR.
2657 */
2658 cfg = desc->chip_data;
2659 i = cfg->vector;
2660 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2661
2662 /*
2663 * We must acknowledge the irq before we move it or the acknowledge will
2664 * not propagate properly.
2665 */
2666 ack_APIC_irq();
2667
2668 /*
2669 * Tail end of clearing remote IRR bit (either by delivering the EOI
2670 * message via io-apic EOI register write or simulating it using
2671 * mask+edge followed by unnask+level logic) manually when the
2672 * level triggered interrupt is seen as the edge triggered interrupt
2673 * at the cpu.
2674 */
2675 if (!(v & (1 << (i & 0x1f)))) {
2676 atomic_inc(&irq_mis_count);
2677
2678 eoi_ioapic_irq(desc);
2679 }
2680
2681 /* Now we can move and renable the irq */
2682 if (unlikely(do_unmask_irq)) {
2683 /* Only migrate the irq if the ack has been received.
2684 *
2685 * On rare occasions the broadcast level triggered ack gets
2686 * delayed going to ioapics, and if we reprogram the
2687 * vector while Remote IRR is still set the irq will never
2688 * fire again.
2689 *
2690 * To prevent this scenario we read the Remote IRR bit
2691 * of the ioapic. This has two effects.
2692 * - On any sane system the read of the ioapic will
2693 * flush writes (and acks) going to the ioapic from
2694 * this cpu.
2695 * - We get to see if the ACK has actually been delivered.
2696 *
2697 * Based on failed experiments of reprogramming the
2698 * ioapic entry from outside of irq context starting
2699 * with masking the ioapic entry and then polling until
2700 * Remote IRR was clear before reprogramming the
2701 * ioapic I don't trust the Remote IRR bit to be
2702 * completey accurate.
2703 *
2704 * However there appears to be no other way to plug
2705 * this race, so if the Remote IRR bit is not
2706 * accurate and is causing problems then it is a hardware bug
2707 * and you can go talk to the chipset vendor about it.
2708 */
2709 cfg = desc->chip_data;
2710 if (!io_apic_level_ack_pending(cfg))
2711 move_masked_irq(irq);
2712 unmask_IO_APIC_irq_desc(desc);
2713 }
2714 }
2715
2716 #ifdef CONFIG_INTR_REMAP
2717 static void ir_ack_apic_edge(unsigned int irq)
2718 {
2719 ack_APIC_irq();
2720 }
2721
2722 static void ir_ack_apic_level(unsigned int irq)
2723 {
2724 struct irq_desc *desc = irq_to_desc(irq);
2725
2726 ack_APIC_irq();
2727 eoi_ioapic_irq(desc);
2728 }
2729 #endif /* CONFIG_INTR_REMAP */
2730
2731 static struct irq_chip ioapic_chip __read_mostly = {
2732 .name = "IO-APIC",
2733 .startup = startup_ioapic_irq,
2734 .mask = mask_IO_APIC_irq,
2735 .unmask = unmask_IO_APIC_irq,
2736 .ack = ack_apic_edge,
2737 .eoi = ack_apic_level,
2738 #ifdef CONFIG_SMP
2739 .set_affinity = set_ioapic_affinity_irq,
2740 #endif
2741 .retrigger = ioapic_retrigger_irq,
2742 };
2743
2744 static struct irq_chip ir_ioapic_chip __read_mostly = {
2745 .name = "IR-IO-APIC",
2746 .startup = startup_ioapic_irq,
2747 .mask = mask_IO_APIC_irq,
2748 .unmask = unmask_IO_APIC_irq,
2749 #ifdef CONFIG_INTR_REMAP
2750 .ack = ir_ack_apic_edge,
2751 .eoi = ir_ack_apic_level,
2752 #ifdef CONFIG_SMP
2753 .set_affinity = set_ir_ioapic_affinity_irq,
2754 #endif
2755 #endif
2756 .retrigger = ioapic_retrigger_irq,
2757 };
2758
2759 static inline void init_IO_APIC_traps(void)
2760 {
2761 int irq;
2762 struct irq_desc *desc;
2763 struct irq_cfg *cfg;
2764
2765 /*
2766 * NOTE! The local APIC isn't very good at handling
2767 * multiple interrupts at the same interrupt level.
2768 * As the interrupt level is determined by taking the
2769 * vector number and shifting that right by 4, we
2770 * want to spread these out a bit so that they don't
2771 * all fall in the same interrupt level.
2772 *
2773 * Also, we've got to be careful not to trash gate
2774 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2775 */
2776 for_each_irq_desc(irq, desc) {
2777 cfg = desc->chip_data;
2778 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2779 /*
2780 * Hmm.. We don't have an entry for this,
2781 * so default to an old-fashioned 8259
2782 * interrupt if we can..
2783 */
2784 if (irq < legacy_pic->nr_legacy_irqs)
2785 legacy_pic->make_irq(irq);
2786 else
2787 /* Strange. Oh, well.. */
2788 desc->chip = &no_irq_chip;
2789 }
2790 }
2791 }
2792
2793 /*
2794 * The local APIC irq-chip implementation:
2795 */
2796
2797 static void mask_lapic_irq(unsigned int irq)
2798 {
2799 unsigned long v;
2800
2801 v = apic_read(APIC_LVT0);
2802 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2803 }
2804
2805 static void unmask_lapic_irq(unsigned int irq)
2806 {
2807 unsigned long v;
2808
2809 v = apic_read(APIC_LVT0);
2810 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2811 }
2812
2813 static void ack_lapic_irq(unsigned int irq)
2814 {
2815 ack_APIC_irq();
2816 }
2817
2818 static struct irq_chip lapic_chip __read_mostly = {
2819 .name = "local-APIC",
2820 .mask = mask_lapic_irq,
2821 .unmask = unmask_lapic_irq,
2822 .ack = ack_lapic_irq,
2823 };
2824
2825 static void lapic_register_intr(int irq, struct irq_desc *desc)
2826 {
2827 desc->status &= ~IRQ_LEVEL;
2828 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2829 "edge");
2830 }
2831
2832 static void __init setup_nmi(void)
2833 {
2834 /*
2835 * Dirty trick to enable the NMI watchdog ...
2836 * We put the 8259A master into AEOI mode and
2837 * unmask on all local APICs LVT0 as NMI.
2838 *
2839 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2840 * is from Maciej W. Rozycki - so we do not have to EOI from
2841 * the NMI handler or the timer interrupt.
2842 */
2843 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2844
2845 enable_NMI_through_LVT0();
2846
2847 apic_printk(APIC_VERBOSE, " done.\n");
2848 }
2849
2850 /*
2851 * This looks a bit hackish but it's about the only one way of sending
2852 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2853 * not support the ExtINT mode, unfortunately. We need to send these
2854 * cycles as some i82489DX-based boards have glue logic that keeps the
2855 * 8259A interrupt line asserted until INTA. --macro
2856 */
2857 static inline void __init unlock_ExtINT_logic(void)
2858 {
2859 int apic, pin, i;
2860 struct IO_APIC_route_entry entry0, entry1;
2861 unsigned char save_control, save_freq_select;
2862
2863 pin = find_isa_irq_pin(8, mp_INT);
2864 if (pin == -1) {
2865 WARN_ON_ONCE(1);
2866 return;
2867 }
2868 apic = find_isa_irq_apic(8, mp_INT);
2869 if (apic == -1) {
2870 WARN_ON_ONCE(1);
2871 return;
2872 }
2873
2874 entry0 = ioapic_read_entry(apic, pin);
2875 clear_IO_APIC_pin(apic, pin);
2876
2877 memset(&entry1, 0, sizeof(entry1));
2878
2879 entry1.dest_mode = 0; /* physical delivery */
2880 entry1.mask = 0; /* unmask IRQ now */
2881 entry1.dest = hard_smp_processor_id();
2882 entry1.delivery_mode = dest_ExtINT;
2883 entry1.polarity = entry0.polarity;
2884 entry1.trigger = 0;
2885 entry1.vector = 0;
2886
2887 ioapic_write_entry(apic, pin, entry1);
2888
2889 save_control = CMOS_READ(RTC_CONTROL);
2890 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2891 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2892 RTC_FREQ_SELECT);
2893 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2894
2895 i = 100;
2896 while (i-- > 0) {
2897 mdelay(10);
2898 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2899 i -= 10;
2900 }
2901
2902 CMOS_WRITE(save_control, RTC_CONTROL);
2903 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2904 clear_IO_APIC_pin(apic, pin);
2905
2906 ioapic_write_entry(apic, pin, entry0);
2907 }
2908
2909 static int disable_timer_pin_1 __initdata;
2910 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2911 static int __init disable_timer_pin_setup(char *arg)
2912 {
2913 disable_timer_pin_1 = 1;
2914 return 0;
2915 }
2916 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2917
2918 int timer_through_8259 __initdata;
2919
2920 /*
2921 * This code may look a bit paranoid, but it's supposed to cooperate with
2922 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2923 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2924 * fanatically on his truly buggy board.
2925 *
2926 * FIXME: really need to revamp this for all platforms.
2927 */
2928 static inline void __init check_timer(void)
2929 {
2930 struct irq_desc *desc = irq_to_desc(0);
2931 struct irq_cfg *cfg = desc->chip_data;
2932 int node = cpu_to_node(boot_cpu_id);
2933 int apic1, pin1, apic2, pin2;
2934 unsigned long flags;
2935 int no_pin1 = 0;
2936
2937 local_irq_save(flags);
2938
2939 /*
2940 * get/set the timer IRQ vector:
2941 */
2942 legacy_pic->chip->mask(0);
2943 assign_irq_vector(0, cfg, apic->target_cpus());
2944
2945 /*
2946 * As IRQ0 is to be enabled in the 8259A, the virtual
2947 * wire has to be disabled in the local APIC. Also
2948 * timer interrupts need to be acknowledged manually in
2949 * the 8259A for the i82489DX when using the NMI
2950 * watchdog as that APIC treats NMIs as level-triggered.
2951 * The AEOI mode will finish them in the 8259A
2952 * automatically.
2953 */
2954 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2955 legacy_pic->init(1);
2956 #ifdef CONFIG_X86_32
2957 {
2958 unsigned int ver;
2959
2960 ver = apic_read(APIC_LVR);
2961 ver = GET_APIC_VERSION(ver);
2962 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2963 }
2964 #endif
2965
2966 pin1 = find_isa_irq_pin(0, mp_INT);
2967 apic1 = find_isa_irq_apic(0, mp_INT);
2968 pin2 = ioapic_i8259.pin;
2969 apic2 = ioapic_i8259.apic;
2970
2971 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2972 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2973 cfg->vector, apic1, pin1, apic2, pin2);
2974
2975 /*
2976 * Some BIOS writers are clueless and report the ExtINTA
2977 * I/O APIC input from the cascaded 8259A as the timer
2978 * interrupt input. So just in case, if only one pin
2979 * was found above, try it both directly and through the
2980 * 8259A.
2981 */
2982 if (pin1 == -1) {
2983 if (intr_remapping_enabled)
2984 panic("BIOS bug: timer not connected to IO-APIC");
2985 pin1 = pin2;
2986 apic1 = apic2;
2987 no_pin1 = 1;
2988 } else if (pin2 == -1) {
2989 pin2 = pin1;
2990 apic2 = apic1;
2991 }
2992
2993 if (pin1 != -1) {
2994 /*
2995 * Ok, does IRQ0 through the IOAPIC work?
2996 */
2997 if (no_pin1) {
2998 add_pin_to_irq_node(cfg, node, apic1, pin1);
2999 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
3000 } else {
3001 /* for edge trigger, setup_IO_APIC_irq already
3002 * leave it unmasked.
3003 * so only need to unmask if it is level-trigger
3004 * do we really have level trigger timer?
3005 */
3006 int idx;
3007 idx = find_irq_entry(apic1, pin1, mp_INT);
3008 if (idx != -1 && irq_trigger(idx))
3009 unmask_IO_APIC_irq_desc(desc);
3010 }
3011 if (timer_irq_works()) {
3012 if (nmi_watchdog == NMI_IO_APIC) {
3013 setup_nmi();
3014 legacy_pic->chip->unmask(0);
3015 }
3016 if (disable_timer_pin_1 > 0)
3017 clear_IO_APIC_pin(0, pin1);
3018 goto out;
3019 }
3020 if (intr_remapping_enabled)
3021 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3022 local_irq_disable();
3023 clear_IO_APIC_pin(apic1, pin1);
3024 if (!no_pin1)
3025 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
3026 "8254 timer not connected to IO-APIC\n");
3027
3028 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3029 "(IRQ0) through the 8259A ...\n");
3030 apic_printk(APIC_QUIET, KERN_INFO
3031 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3032 /*
3033 * legacy devices should be connected to IO APIC #0
3034 */
3035 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
3036 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3037 legacy_pic->chip->unmask(0);
3038 if (timer_irq_works()) {
3039 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3040 timer_through_8259 = 1;
3041 if (nmi_watchdog == NMI_IO_APIC) {
3042 legacy_pic->chip->mask(0);
3043 setup_nmi();
3044 legacy_pic->chip->unmask(0);
3045 }
3046 goto out;
3047 }
3048 /*
3049 * Cleanup, just in case ...
3050 */
3051 local_irq_disable();
3052 legacy_pic->chip->mask(0);
3053 clear_IO_APIC_pin(apic2, pin2);
3054 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3055 }
3056
3057 if (nmi_watchdog == NMI_IO_APIC) {
3058 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3059 "through the IO-APIC - disabling NMI Watchdog!\n");
3060 nmi_watchdog = NMI_NONE;
3061 }
3062 #ifdef CONFIG_X86_32
3063 timer_ack = 0;
3064 #endif
3065
3066 apic_printk(APIC_QUIET, KERN_INFO
3067 "...trying to set up timer as Virtual Wire IRQ...\n");
3068
3069 lapic_register_intr(0, desc);
3070 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3071 legacy_pic->chip->unmask(0);
3072
3073 if (timer_irq_works()) {
3074 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3075 goto out;
3076 }
3077 local_irq_disable();
3078 legacy_pic->chip->mask(0);
3079 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3080 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3081
3082 apic_printk(APIC_QUIET, KERN_INFO
3083 "...trying to set up timer as ExtINT IRQ...\n");
3084
3085 legacy_pic->init(0);
3086 legacy_pic->make_irq(0);
3087 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3088
3089 unlock_ExtINT_logic();
3090
3091 if (timer_irq_works()) {
3092 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3093 goto out;
3094 }
3095 local_irq_disable();
3096 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3097 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3098 "report. Then try booting with the 'noapic' option.\n");
3099 out:
3100 local_irq_restore(flags);
3101 }
3102
3103 /*
3104 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3105 * to devices. However there may be an I/O APIC pin available for
3106 * this interrupt regardless. The pin may be left unconnected, but
3107 * typically it will be reused as an ExtINT cascade interrupt for
3108 * the master 8259A. In the MPS case such a pin will normally be
3109 * reported as an ExtINT interrupt in the MP table. With ACPI
3110 * there is no provision for ExtINT interrupts, and in the absence
3111 * of an override it would be treated as an ordinary ISA I/O APIC
3112 * interrupt, that is edge-triggered and unmasked by default. We
3113 * used to do this, but it caused problems on some systems because
3114 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3115 * the same ExtINT cascade interrupt to drive the local APIC of the
3116 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3117 * the I/O APIC in all cases now. No actual device should request
3118 * it anyway. --macro
3119 */
3120 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3121
3122 void __init setup_IO_APIC(void)
3123 {
3124
3125 /*
3126 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3127 */
3128 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3129
3130 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3131 /*
3132 * Set up IO-APIC IRQ routing.
3133 */
3134 x86_init.mpparse.setup_ioapic_ids();
3135
3136 sync_Arb_IDs();
3137 setup_IO_APIC_irqs();
3138 init_IO_APIC_traps();
3139 if (legacy_pic->nr_legacy_irqs)
3140 check_timer();
3141 }
3142
3143 /*
3144 * Called after all the initialization is done. If we didnt find any
3145 * APIC bugs then we can allow the modify fast path
3146 */
3147
3148 static int __init io_apic_bug_finalize(void)
3149 {
3150 if (sis_apic_bug == -1)
3151 sis_apic_bug = 0;
3152 return 0;
3153 }
3154
3155 late_initcall(io_apic_bug_finalize);
3156
3157 struct sysfs_ioapic_data {
3158 struct sys_device dev;
3159 struct IO_APIC_route_entry entry[0];
3160 };
3161 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3162
3163 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3164 {
3165 struct IO_APIC_route_entry *entry;
3166 struct sysfs_ioapic_data *data;
3167 int i;
3168
3169 data = container_of(dev, struct sysfs_ioapic_data, dev);
3170 entry = data->entry;
3171 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3172 *entry = ioapic_read_entry(dev->id, i);
3173
3174 return 0;
3175 }
3176
3177 static int ioapic_resume(struct sys_device *dev)
3178 {
3179 struct IO_APIC_route_entry *entry;
3180 struct sysfs_ioapic_data *data;
3181 unsigned long flags;
3182 union IO_APIC_reg_00 reg_00;
3183 int i;
3184
3185 data = container_of(dev, struct sysfs_ioapic_data, dev);
3186 entry = data->entry;
3187
3188 raw_spin_lock_irqsave(&ioapic_lock, flags);
3189 reg_00.raw = io_apic_read(dev->id, 0);
3190 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3191 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3192 io_apic_write(dev->id, 0, reg_00.raw);
3193 }
3194 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3195 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3196 ioapic_write_entry(dev->id, i, entry[i]);
3197
3198 return 0;
3199 }
3200
3201 static struct sysdev_class ioapic_sysdev_class = {
3202 .name = "ioapic",
3203 .suspend = ioapic_suspend,
3204 .resume = ioapic_resume,
3205 };
3206
3207 static int __init ioapic_init_sysfs(void)
3208 {
3209 struct sys_device * dev;
3210 int i, size, error;
3211
3212 error = sysdev_class_register(&ioapic_sysdev_class);
3213 if (error)
3214 return error;
3215
3216 for (i = 0; i < nr_ioapics; i++ ) {
3217 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3218 * sizeof(struct IO_APIC_route_entry);
3219 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3220 if (!mp_ioapic_data[i]) {
3221 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3222 continue;
3223 }
3224 dev = &mp_ioapic_data[i]->dev;
3225 dev->id = i;
3226 dev->cls = &ioapic_sysdev_class;
3227 error = sysdev_register(dev);
3228 if (error) {
3229 kfree(mp_ioapic_data[i]);
3230 mp_ioapic_data[i] = NULL;
3231 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3232 continue;
3233 }
3234 }
3235
3236 return 0;
3237 }
3238
3239 device_initcall(ioapic_init_sysfs);
3240
3241 /*
3242 * Dynamic irq allocate and deallocation
3243 */
3244 unsigned int create_irq_nr(unsigned int irq_want, int node)
3245 {
3246 /* Allocate an unused irq */
3247 unsigned int irq;
3248 unsigned int new;
3249 unsigned long flags;
3250 struct irq_cfg *cfg_new = NULL;
3251 struct irq_desc *desc_new = NULL;
3252
3253 irq = 0;
3254 if (irq_want < nr_irqs_gsi)
3255 irq_want = nr_irqs_gsi;
3256
3257 raw_spin_lock_irqsave(&vector_lock, flags);
3258 for (new = irq_want; new < nr_irqs; new++) {
3259 desc_new = irq_to_desc_alloc_node(new, node);
3260 if (!desc_new) {
3261 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3262 continue;
3263 }
3264 cfg_new = desc_new->chip_data;
3265
3266 if (cfg_new->vector != 0)
3267 continue;
3268
3269 desc_new = move_irq_desc(desc_new, node);
3270 cfg_new = desc_new->chip_data;
3271
3272 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3273 irq = new;
3274 break;
3275 }
3276 raw_spin_unlock_irqrestore(&vector_lock, flags);
3277
3278 if (irq > 0)
3279 dynamic_irq_init_keep_chip_data(irq);
3280
3281 return irq;
3282 }
3283
3284 int create_irq(void)
3285 {
3286 int node = cpu_to_node(boot_cpu_id);
3287 unsigned int irq_want;
3288 int irq;
3289
3290 irq_want = nr_irqs_gsi;
3291 irq = create_irq_nr(irq_want, node);
3292
3293 if (irq == 0)
3294 irq = -1;
3295
3296 return irq;
3297 }
3298
3299 void destroy_irq(unsigned int irq)
3300 {
3301 unsigned long flags;
3302
3303 dynamic_irq_cleanup_keep_chip_data(irq);
3304
3305 free_irte(irq);
3306 raw_spin_lock_irqsave(&vector_lock, flags);
3307 __clear_irq_vector(irq, get_irq_chip_data(irq));
3308 raw_spin_unlock_irqrestore(&vector_lock, flags);
3309 }
3310
3311 /*
3312 * MSI message composition
3313 */
3314 #ifdef CONFIG_PCI_MSI
3315 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3316 struct msi_msg *msg, u8 hpet_id)
3317 {
3318 struct irq_cfg *cfg;
3319 int err;
3320 unsigned dest;
3321
3322 if (disable_apic)
3323 return -ENXIO;
3324
3325 cfg = irq_cfg(irq);
3326 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3327 if (err)
3328 return err;
3329
3330 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3331
3332 if (irq_remapped(irq)) {
3333 struct irte irte;
3334 int ir_index;
3335 u16 sub_handle;
3336
3337 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3338 BUG_ON(ir_index == -1);
3339
3340 memset (&irte, 0, sizeof(irte));
3341
3342 irte.present = 1;
3343 irte.dst_mode = apic->irq_dest_mode;
3344 irte.trigger_mode = 0; /* edge */
3345 irte.dlvry_mode = apic->irq_delivery_mode;
3346 irte.vector = cfg->vector;
3347 irte.dest_id = IRTE_DEST(dest);
3348
3349 /* Set source-id of interrupt request */
3350 if (pdev)
3351 set_msi_sid(&irte, pdev);
3352 else
3353 set_hpet_sid(&irte, hpet_id);
3354
3355 modify_irte(irq, &irte);
3356
3357 msg->address_hi = MSI_ADDR_BASE_HI;
3358 msg->data = sub_handle;
3359 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3360 MSI_ADDR_IR_SHV |
3361 MSI_ADDR_IR_INDEX1(ir_index) |
3362 MSI_ADDR_IR_INDEX2(ir_index);
3363 } else {
3364 if (x2apic_enabled())
3365 msg->address_hi = MSI_ADDR_BASE_HI |
3366 MSI_ADDR_EXT_DEST_ID(dest);
3367 else
3368 msg->address_hi = MSI_ADDR_BASE_HI;
3369
3370 msg->address_lo =
3371 MSI_ADDR_BASE_LO |
3372 ((apic->irq_dest_mode == 0) ?
3373 MSI_ADDR_DEST_MODE_PHYSICAL:
3374 MSI_ADDR_DEST_MODE_LOGICAL) |
3375 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3376 MSI_ADDR_REDIRECTION_CPU:
3377 MSI_ADDR_REDIRECTION_LOWPRI) |
3378 MSI_ADDR_DEST_ID(dest);
3379
3380 msg->data =
3381 MSI_DATA_TRIGGER_EDGE |
3382 MSI_DATA_LEVEL_ASSERT |
3383 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3384 MSI_DATA_DELIVERY_FIXED:
3385 MSI_DATA_DELIVERY_LOWPRI) |
3386 MSI_DATA_VECTOR(cfg->vector);
3387 }
3388 return err;
3389 }
3390
3391 #ifdef CONFIG_SMP
3392 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3393 {
3394 struct irq_desc *desc = irq_to_desc(irq);
3395 struct irq_cfg *cfg;
3396 struct msi_msg msg;
3397 unsigned int dest;
3398
3399 if (set_desc_affinity(desc, mask, &dest))
3400 return -1;
3401
3402 cfg = desc->chip_data;
3403
3404 read_msi_msg_desc(desc, &msg);
3405
3406 msg.data &= ~MSI_DATA_VECTOR_MASK;
3407 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3408 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3409 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3410
3411 write_msi_msg_desc(desc, &msg);
3412
3413 return 0;
3414 }
3415 #ifdef CONFIG_INTR_REMAP
3416 /*
3417 * Migrate the MSI irq to another cpumask. This migration is
3418 * done in the process context using interrupt-remapping hardware.
3419 */
3420 static int
3421 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3422 {
3423 struct irq_desc *desc = irq_to_desc(irq);
3424 struct irq_cfg *cfg = desc->chip_data;
3425 unsigned int dest;
3426 struct irte irte;
3427
3428 if (get_irte(irq, &irte))
3429 return -1;
3430
3431 if (set_desc_affinity(desc, mask, &dest))
3432 return -1;
3433
3434 irte.vector = cfg->vector;
3435 irte.dest_id = IRTE_DEST(dest);
3436
3437 /*
3438 * atomically update the IRTE with the new destination and vector.
3439 */
3440 modify_irte(irq, &irte);
3441
3442 /*
3443 * After this point, all the interrupts will start arriving
3444 * at the new destination. So, time to cleanup the previous
3445 * vector allocation.
3446 */
3447 if (cfg->move_in_progress)
3448 send_cleanup_vector(cfg);
3449
3450 return 0;
3451 }
3452
3453 #endif
3454 #endif /* CONFIG_SMP */
3455
3456 /*
3457 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3458 * which implement the MSI or MSI-X Capability Structure.
3459 */
3460 static struct irq_chip msi_chip = {
3461 .name = "PCI-MSI",
3462 .unmask = unmask_msi_irq,
3463 .mask = mask_msi_irq,
3464 .ack = ack_apic_edge,
3465 #ifdef CONFIG_SMP
3466 .set_affinity = set_msi_irq_affinity,
3467 #endif
3468 .retrigger = ioapic_retrigger_irq,
3469 };
3470
3471 static struct irq_chip msi_ir_chip = {
3472 .name = "IR-PCI-MSI",
3473 .unmask = unmask_msi_irq,
3474 .mask = mask_msi_irq,
3475 #ifdef CONFIG_INTR_REMAP
3476 .ack = ir_ack_apic_edge,
3477 #ifdef CONFIG_SMP
3478 .set_affinity = ir_set_msi_irq_affinity,
3479 #endif
3480 #endif
3481 .retrigger = ioapic_retrigger_irq,
3482 };
3483
3484 /*
3485 * Map the PCI dev to the corresponding remapping hardware unit
3486 * and allocate 'nvec' consecutive interrupt-remapping table entries
3487 * in it.
3488 */
3489 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3490 {
3491 struct intel_iommu *iommu;
3492 int index;
3493
3494 iommu = map_dev_to_ir(dev);
3495 if (!iommu) {
3496 printk(KERN_ERR
3497 "Unable to map PCI %s to iommu\n", pci_name(dev));
3498 return -ENOENT;
3499 }
3500
3501 index = alloc_irte(iommu, irq, nvec);
3502 if (index < 0) {
3503 printk(KERN_ERR
3504 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3505 pci_name(dev));
3506 return -ENOSPC;
3507 }
3508 return index;
3509 }
3510
3511 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3512 {
3513 int ret;
3514 struct msi_msg msg;
3515
3516 ret = msi_compose_msg(dev, irq, &msg, -1);
3517 if (ret < 0)
3518 return ret;
3519
3520 set_irq_msi(irq, msidesc);
3521 write_msi_msg(irq, &msg);
3522
3523 if (irq_remapped(irq)) {
3524 struct irq_desc *desc = irq_to_desc(irq);
3525 /*
3526 * irq migration in process context
3527 */
3528 desc->status |= IRQ_MOVE_PCNTXT;
3529 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3530 } else
3531 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3532
3533 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3534
3535 return 0;
3536 }
3537
3538 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3539 {
3540 unsigned int irq;
3541 int ret, sub_handle;
3542 struct msi_desc *msidesc;
3543 unsigned int irq_want;
3544 struct intel_iommu *iommu = NULL;
3545 int index = 0;
3546 int node;
3547
3548 /* x86 doesn't support multiple MSI yet */
3549 if (type == PCI_CAP_ID_MSI && nvec > 1)
3550 return 1;
3551
3552 node = dev_to_node(&dev->dev);
3553 irq_want = nr_irqs_gsi;
3554 sub_handle = 0;
3555 list_for_each_entry(msidesc, &dev->msi_list, list) {
3556 irq = create_irq_nr(irq_want, node);
3557 if (irq == 0)
3558 return -1;
3559 irq_want = irq + 1;
3560 if (!intr_remapping_enabled)
3561 goto no_ir;
3562
3563 if (!sub_handle) {
3564 /*
3565 * allocate the consecutive block of IRTE's
3566 * for 'nvec'
3567 */
3568 index = msi_alloc_irte(dev, irq, nvec);
3569 if (index < 0) {
3570 ret = index;
3571 goto error;
3572 }
3573 } else {
3574 iommu = map_dev_to_ir(dev);
3575 if (!iommu) {
3576 ret = -ENOENT;
3577 goto error;
3578 }
3579 /*
3580 * setup the mapping between the irq and the IRTE
3581 * base index, the sub_handle pointing to the
3582 * appropriate interrupt remap table entry.
3583 */
3584 set_irte_irq(irq, iommu, index, sub_handle);
3585 }
3586 no_ir:
3587 ret = setup_msi_irq(dev, msidesc, irq);
3588 if (ret < 0)
3589 goto error;
3590 sub_handle++;
3591 }
3592 return 0;
3593
3594 error:
3595 destroy_irq(irq);
3596 return ret;
3597 }
3598
3599 void arch_teardown_msi_irq(unsigned int irq)
3600 {
3601 destroy_irq(irq);
3602 }
3603
3604 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3605 #ifdef CONFIG_SMP
3606 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3607 {
3608 struct irq_desc *desc = irq_to_desc(irq);
3609 struct irq_cfg *cfg;
3610 struct msi_msg msg;
3611 unsigned int dest;
3612
3613 if (set_desc_affinity(desc, mask, &dest))
3614 return -1;
3615
3616 cfg = desc->chip_data;
3617
3618 dmar_msi_read(irq, &msg);
3619
3620 msg.data &= ~MSI_DATA_VECTOR_MASK;
3621 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3622 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3623 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3624
3625 dmar_msi_write(irq, &msg);
3626
3627 return 0;
3628 }
3629
3630 #endif /* CONFIG_SMP */
3631
3632 static struct irq_chip dmar_msi_type = {
3633 .name = "DMAR_MSI",
3634 .unmask = dmar_msi_unmask,
3635 .mask = dmar_msi_mask,
3636 .ack = ack_apic_edge,
3637 #ifdef CONFIG_SMP
3638 .set_affinity = dmar_msi_set_affinity,
3639 #endif
3640 .retrigger = ioapic_retrigger_irq,
3641 };
3642
3643 int arch_setup_dmar_msi(unsigned int irq)
3644 {
3645 int ret;
3646 struct msi_msg msg;
3647
3648 ret = msi_compose_msg(NULL, irq, &msg, -1);
3649 if (ret < 0)
3650 return ret;
3651 dmar_msi_write(irq, &msg);
3652 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3653 "edge");
3654 return 0;
3655 }
3656 #endif
3657
3658 #ifdef CONFIG_HPET_TIMER
3659
3660 #ifdef CONFIG_SMP
3661 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3662 {
3663 struct irq_desc *desc = irq_to_desc(irq);
3664 struct irq_cfg *cfg;
3665 struct msi_msg msg;
3666 unsigned int dest;
3667
3668 if (set_desc_affinity(desc, mask, &dest))
3669 return -1;
3670
3671 cfg = desc->chip_data;
3672
3673 hpet_msi_read(irq, &msg);
3674
3675 msg.data &= ~MSI_DATA_VECTOR_MASK;
3676 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3677 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3678 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3679
3680 hpet_msi_write(irq, &msg);
3681
3682 return 0;
3683 }
3684
3685 #endif /* CONFIG_SMP */
3686
3687 static struct irq_chip ir_hpet_msi_type = {
3688 .name = "IR-HPET_MSI",
3689 .unmask = hpet_msi_unmask,
3690 .mask = hpet_msi_mask,
3691 #ifdef CONFIG_INTR_REMAP
3692 .ack = ir_ack_apic_edge,
3693 #ifdef CONFIG_SMP
3694 .set_affinity = ir_set_msi_irq_affinity,
3695 #endif
3696 #endif
3697 .retrigger = ioapic_retrigger_irq,
3698 };
3699
3700 static struct irq_chip hpet_msi_type = {
3701 .name = "HPET_MSI",
3702 .unmask = hpet_msi_unmask,
3703 .mask = hpet_msi_mask,
3704 .ack = ack_apic_edge,
3705 #ifdef CONFIG_SMP
3706 .set_affinity = hpet_msi_set_affinity,
3707 #endif
3708 .retrigger = ioapic_retrigger_irq,
3709 };
3710
3711 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3712 {
3713 int ret;
3714 struct msi_msg msg;
3715 struct irq_desc *desc = irq_to_desc(irq);
3716
3717 if (intr_remapping_enabled) {
3718 struct intel_iommu *iommu = map_hpet_to_ir(id);
3719 int index;
3720
3721 if (!iommu)
3722 return -1;
3723
3724 index = alloc_irte(iommu, irq, 1);
3725 if (index < 0)
3726 return -1;
3727 }
3728
3729 ret = msi_compose_msg(NULL, irq, &msg, id);
3730 if (ret < 0)
3731 return ret;
3732
3733 hpet_msi_write(irq, &msg);
3734 desc->status |= IRQ_MOVE_PCNTXT;
3735 if (irq_remapped(irq))
3736 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3737 handle_edge_irq, "edge");
3738 else
3739 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3740 handle_edge_irq, "edge");
3741
3742 return 0;
3743 }
3744 #endif
3745
3746 #endif /* CONFIG_PCI_MSI */
3747 /*
3748 * Hypertransport interrupt support
3749 */
3750 #ifdef CONFIG_HT_IRQ
3751
3752 #ifdef CONFIG_SMP
3753
3754 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3755 {
3756 struct ht_irq_msg msg;
3757 fetch_ht_irq_msg(irq, &msg);
3758
3759 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3760 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3761
3762 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3763 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3764
3765 write_ht_irq_msg(irq, &msg);
3766 }
3767
3768 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3769 {
3770 struct irq_desc *desc = irq_to_desc(irq);
3771 struct irq_cfg *cfg;
3772 unsigned int dest;
3773
3774 if (set_desc_affinity(desc, mask, &dest))
3775 return -1;
3776
3777 cfg = desc->chip_data;
3778
3779 target_ht_irq(irq, dest, cfg->vector);
3780
3781 return 0;
3782 }
3783
3784 #endif
3785
3786 static struct irq_chip ht_irq_chip = {
3787 .name = "PCI-HT",
3788 .mask = mask_ht_irq,
3789 .unmask = unmask_ht_irq,
3790 .ack = ack_apic_edge,
3791 #ifdef CONFIG_SMP
3792 .set_affinity = set_ht_irq_affinity,
3793 #endif
3794 .retrigger = ioapic_retrigger_irq,
3795 };
3796
3797 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3798 {
3799 struct irq_cfg *cfg;
3800 int err;
3801
3802 if (disable_apic)
3803 return -ENXIO;
3804
3805 cfg = irq_cfg(irq);
3806 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3807 if (!err) {
3808 struct ht_irq_msg msg;
3809 unsigned dest;
3810
3811 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3812 apic->target_cpus());
3813
3814 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3815
3816 msg.address_lo =
3817 HT_IRQ_LOW_BASE |
3818 HT_IRQ_LOW_DEST_ID(dest) |
3819 HT_IRQ_LOW_VECTOR(cfg->vector) |
3820 ((apic->irq_dest_mode == 0) ?
3821 HT_IRQ_LOW_DM_PHYSICAL :
3822 HT_IRQ_LOW_DM_LOGICAL) |
3823 HT_IRQ_LOW_RQEOI_EDGE |
3824 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3825 HT_IRQ_LOW_MT_FIXED :
3826 HT_IRQ_LOW_MT_ARBITRATED) |
3827 HT_IRQ_LOW_IRQ_MASKED;
3828
3829 write_ht_irq_msg(irq, &msg);
3830
3831 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3832 handle_edge_irq, "edge");
3833
3834 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3835 }
3836 return err;
3837 }
3838 #endif /* CONFIG_HT_IRQ */
3839
3840 int __init io_apic_get_redir_entries (int ioapic)
3841 {
3842 union IO_APIC_reg_01 reg_01;
3843 unsigned long flags;
3844
3845 raw_spin_lock_irqsave(&ioapic_lock, flags);
3846 reg_01.raw = io_apic_read(ioapic, 1);
3847 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3848
3849 return reg_01.bits.entries;
3850 }
3851
3852 void __init probe_nr_irqs_gsi(void)
3853 {
3854 int nr = 0;
3855
3856 nr = acpi_probe_gsi();
3857 if (nr > nr_irqs_gsi) {
3858 nr_irqs_gsi = nr;
3859 } else {
3860 /* for acpi=off or acpi is not compiled in */
3861 int idx;
3862
3863 nr = 0;
3864 for (idx = 0; idx < nr_ioapics; idx++)
3865 nr += io_apic_get_redir_entries(idx) + 1;
3866
3867 if (nr > nr_irqs_gsi)
3868 nr_irqs_gsi = nr;
3869 }
3870
3871 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3872 }
3873
3874 #ifdef CONFIG_SPARSE_IRQ
3875 int __init arch_probe_nr_irqs(void)
3876 {
3877 int nr;
3878
3879 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3880 nr_irqs = NR_VECTORS * nr_cpu_ids;
3881
3882 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3883 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3884 /*
3885 * for MSI and HT dyn irq
3886 */
3887 nr += nr_irqs_gsi * 16;
3888 #endif
3889 if (nr < nr_irqs)
3890 nr_irqs = nr;
3891
3892 return 0;
3893 }
3894 #endif
3895
3896 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3897 struct io_apic_irq_attr *irq_attr)
3898 {
3899 struct irq_desc *desc;
3900 struct irq_cfg *cfg;
3901 int node;
3902 int ioapic, pin;
3903 int trigger, polarity;
3904
3905 ioapic = irq_attr->ioapic;
3906 if (!IO_APIC_IRQ(irq)) {
3907 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3908 ioapic);
3909 return -EINVAL;
3910 }
3911
3912 if (dev)
3913 node = dev_to_node(dev);
3914 else
3915 node = cpu_to_node(boot_cpu_id);
3916
3917 desc = irq_to_desc_alloc_node(irq, node);
3918 if (!desc) {
3919 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3920 return 0;
3921 }
3922
3923 pin = irq_attr->ioapic_pin;
3924 trigger = irq_attr->trigger;
3925 polarity = irq_attr->polarity;
3926
3927 /*
3928 * IRQs < 16 are already in the irq_2_pin[] map
3929 */
3930 if (irq >= legacy_pic->nr_legacy_irqs) {
3931 cfg = desc->chip_data;
3932 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3933 printk(KERN_INFO "can not add pin %d for irq %d\n",
3934 pin, irq);
3935 return 0;
3936 }
3937 }
3938
3939 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3940
3941 return 0;
3942 }
3943
3944 int io_apic_set_pci_routing(struct device *dev, int irq,
3945 struct io_apic_irq_attr *irq_attr)
3946 {
3947 int ioapic, pin;
3948 /*
3949 * Avoid pin reprogramming. PRTs typically include entries
3950 * with redundant pin->gsi mappings (but unique PCI devices);
3951 * we only program the IOAPIC on the first.
3952 */
3953 ioapic = irq_attr->ioapic;
3954 pin = irq_attr->ioapic_pin;
3955 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3956 pr_debug("Pin %d-%d already programmed\n",
3957 mp_ioapics[ioapic].apicid, pin);
3958 return 0;
3959 }
3960 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3961
3962 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3963 }
3964
3965 u8 __init io_apic_unique_id(u8 id)
3966 {
3967 #ifdef CONFIG_X86_32
3968 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3969 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3970 return io_apic_get_unique_id(nr_ioapics, id);
3971 else
3972 return id;
3973 #else
3974 int i;
3975 DECLARE_BITMAP(used, 256);
3976
3977 bitmap_zero(used, 256);
3978 for (i = 0; i < nr_ioapics; i++) {
3979 struct mpc_ioapic *ia = &mp_ioapics[i];
3980 __set_bit(ia->apicid, used);
3981 }
3982 if (!test_bit(id, used))
3983 return id;
3984 return find_first_zero_bit(used, 256);
3985 #endif
3986 }
3987
3988 #ifdef CONFIG_X86_32
3989 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3990 {
3991 union IO_APIC_reg_00 reg_00;
3992 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3993 physid_mask_t tmp;
3994 unsigned long flags;
3995 int i = 0;
3996
3997 /*
3998 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3999 * buses (one for LAPICs, one for IOAPICs), where predecessors only
4000 * supports up to 16 on one shared APIC bus.
4001 *
4002 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
4003 * advantage of new APIC bus architecture.
4004 */
4005
4006 if (physids_empty(apic_id_map))
4007 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
4008
4009 raw_spin_lock_irqsave(&ioapic_lock, flags);
4010 reg_00.raw = io_apic_read(ioapic, 0);
4011 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4012
4013 if (apic_id >= get_physical_broadcast()) {
4014 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
4015 "%d\n", ioapic, apic_id, reg_00.bits.ID);
4016 apic_id = reg_00.bits.ID;
4017 }
4018
4019 /*
4020 * Every APIC in a system must have a unique ID or we get lots of nice
4021 * 'stuck on smp_invalidate_needed IPI wait' messages.
4022 */
4023 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
4024
4025 for (i = 0; i < get_physical_broadcast(); i++) {
4026 if (!apic->check_apicid_used(&apic_id_map, i))
4027 break;
4028 }
4029
4030 if (i == get_physical_broadcast())
4031 panic("Max apic_id exceeded!\n");
4032
4033 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
4034 "trying %d\n", ioapic, apic_id, i);
4035
4036 apic_id = i;
4037 }
4038
4039 apic->apicid_to_cpu_present(apic_id, &tmp);
4040 physids_or(apic_id_map, apic_id_map, tmp);
4041
4042 if (reg_00.bits.ID != apic_id) {
4043 reg_00.bits.ID = apic_id;
4044
4045 raw_spin_lock_irqsave(&ioapic_lock, flags);
4046 io_apic_write(ioapic, 0, reg_00.raw);
4047 reg_00.raw = io_apic_read(ioapic, 0);
4048 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4049
4050 /* Sanity check */
4051 if (reg_00.bits.ID != apic_id) {
4052 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4053 return -1;
4054 }
4055 }
4056
4057 apic_printk(APIC_VERBOSE, KERN_INFO
4058 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4059
4060 return apic_id;
4061 }
4062 #endif
4063
4064 int __init io_apic_get_version(int ioapic)
4065 {
4066 union IO_APIC_reg_01 reg_01;
4067 unsigned long flags;
4068
4069 raw_spin_lock_irqsave(&ioapic_lock, flags);
4070 reg_01.raw = io_apic_read(ioapic, 1);
4071 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4072
4073 return reg_01.bits.version;
4074 }
4075
4076 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4077 {
4078 int i;
4079
4080 if (skip_ioapic_setup)
4081 return -1;
4082
4083 for (i = 0; i < mp_irq_entries; i++)
4084 if (mp_irqs[i].irqtype == mp_INT &&
4085 mp_irqs[i].srcbusirq == bus_irq)
4086 break;
4087 if (i >= mp_irq_entries)
4088 return -1;
4089
4090 *trigger = irq_trigger(i);
4091 *polarity = irq_polarity(i);
4092 return 0;
4093 }
4094
4095 /*
4096 * This function currently is only a helper for the i386 smp boot process where
4097 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4098 * so mask in all cases should simply be apic->target_cpus()
4099 */
4100 #ifdef CONFIG_SMP
4101 void __init setup_ioapic_dest(void)
4102 {
4103 int pin, ioapic, irq, irq_entry;
4104 struct irq_desc *desc;
4105 const struct cpumask *mask;
4106
4107 if (skip_ioapic_setup == 1)
4108 return;
4109
4110 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
4111 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4112 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4113 if (irq_entry == -1)
4114 continue;
4115 irq = pin_2_irq(irq_entry, ioapic, pin);
4116
4117 if ((ioapic > 0) && (irq > 16))
4118 continue;
4119
4120 desc = irq_to_desc(irq);
4121
4122 /*
4123 * Honour affinities which have been set in early boot
4124 */
4125 if (desc->status &
4126 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4127 mask = desc->affinity;
4128 else
4129 mask = apic->target_cpus();
4130
4131 if (intr_remapping_enabled)
4132 set_ir_ioapic_affinity_irq_desc(desc, mask);
4133 else
4134 set_ioapic_affinity_irq_desc(desc, mask);
4135 }
4136
4137 }
4138 #endif
4139
4140 #define IOAPIC_RESOURCE_NAME_SIZE 11
4141
4142 static struct resource *ioapic_resources;
4143
4144 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4145 {
4146 unsigned long n;
4147 struct resource *res;
4148 char *mem;
4149 int i;
4150
4151 if (nr_ioapics <= 0)
4152 return NULL;
4153
4154 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4155 n *= nr_ioapics;
4156
4157 mem = alloc_bootmem(n);
4158 res = (void *)mem;
4159
4160 mem += sizeof(struct resource) * nr_ioapics;
4161
4162 for (i = 0; i < nr_ioapics; i++) {
4163 res[i].name = mem;
4164 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4165 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4166 mem += IOAPIC_RESOURCE_NAME_SIZE;
4167 }
4168
4169 ioapic_resources = res;
4170
4171 return res;
4172 }
4173
4174 void __init ioapic_init_mappings(void)
4175 {
4176 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4177 struct resource *ioapic_res;
4178 int i;
4179
4180 ioapic_res = ioapic_setup_resources(nr_ioapics);
4181 for (i = 0; i < nr_ioapics; i++) {
4182 if (smp_found_config) {
4183 ioapic_phys = mp_ioapics[i].apicaddr;
4184 #ifdef CONFIG_X86_32
4185 if (!ioapic_phys) {
4186 printk(KERN_ERR
4187 "WARNING: bogus zero IO-APIC "
4188 "address found in MPTABLE, "
4189 "disabling IO/APIC support!\n");
4190 smp_found_config = 0;
4191 skip_ioapic_setup = 1;
4192 goto fake_ioapic_page;
4193 }
4194 #endif
4195 } else {
4196 #ifdef CONFIG_X86_32
4197 fake_ioapic_page:
4198 #endif
4199 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4200 ioapic_phys = __pa(ioapic_phys);
4201 }
4202 set_fixmap_nocache(idx, ioapic_phys);
4203 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4204 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4205 ioapic_phys);
4206 idx++;
4207
4208 ioapic_res->start = ioapic_phys;
4209 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4210 ioapic_res++;
4211 }
4212 }
4213
4214 void __init ioapic_insert_resources(void)
4215 {
4216 int i;
4217 struct resource *r = ioapic_resources;
4218
4219 if (!r) {
4220 if (nr_ioapics > 0)
4221 printk(KERN_ERR
4222 "IO APIC resources couldn't be allocated.\n");
4223 return;
4224 }
4225
4226 for (i = 0; i < nr_ioapics; i++) {
4227 insert_resource(&iomem_resource, r);
4228 r++;
4229 }
4230 }
4231
4232 int mp_find_ioapic(int gsi)
4233 {
4234 int i = 0;
4235
4236 /* Find the IOAPIC that manages this GSI. */
4237 for (i = 0; i < nr_ioapics; i++) {
4238 if ((gsi >= mp_gsi_routing[i].gsi_base)
4239 && (gsi <= mp_gsi_routing[i].gsi_end))
4240 return i;
4241 }
4242
4243 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4244 return -1;
4245 }
4246
4247 int mp_find_ioapic_pin(int ioapic, int gsi)
4248 {
4249 if (WARN_ON(ioapic == -1))
4250 return -1;
4251 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4252 return -1;
4253
4254 return gsi - mp_gsi_routing[ioapic].gsi_base;
4255 }
4256
4257 static int bad_ioapic(unsigned long address)
4258 {
4259 if (nr_ioapics >= MAX_IO_APICS) {
4260 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4261 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4262 return 1;
4263 }
4264 if (!address) {
4265 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4266 " found in table, skipping!\n");
4267 return 1;
4268 }
4269 return 0;
4270 }
4271
4272 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4273 {
4274 int idx = 0;
4275
4276 if (bad_ioapic(address))
4277 return;
4278
4279 idx = nr_ioapics;
4280
4281 mp_ioapics[idx].type = MP_IOAPIC;
4282 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4283 mp_ioapics[idx].apicaddr = address;
4284
4285 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4286 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4287 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4288
4289 /*
4290 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4291 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4292 */
4293 mp_gsi_routing[idx].gsi_base = gsi_base;
4294 mp_gsi_routing[idx].gsi_end = gsi_base +
4295 io_apic_get_redir_entries(idx);
4296
4297 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4298 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4299 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4300 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
4301
4302 nr_ioapics++;
4303 }
4304
4305 /* Enable IOAPIC early just for system timer */
4306 void __init pre_init_apic_IRQ0(void)
4307 {
4308 struct irq_cfg *cfg;
4309 struct irq_desc *desc;
4310
4311 printk(KERN_INFO "Early APIC setup for system timer0\n");
4312 #ifndef CONFIG_SMP
4313 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
4314 #endif
4315 desc = irq_to_desc_alloc_node(0, 0);
4316
4317 setup_local_APIC();
4318
4319 cfg = irq_cfg(0);
4320 add_pin_to_irq_node(cfg, 0, 0, 0);
4321 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
4322
4323 setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);
4324 }
Linux kernel - Deliverables
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