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x86, MCE, AMD: Replace shared_bank array with is_shared_bank() helper
[deliverable/linux.git] / arch / x86 / kernel / cpu / mcheck / mce_amd.c
1 /*
2 * (c) 2005-2012 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
6 *
7 * Written by Jacob Shin - AMD, Inc.
8 *
9 * Maintained by: Borislav Petkov <bp@alien8.de>
10 *
11 * April 2006
12 * - added support for AMD Family 0x10 processors
13 * May 2012
14 * - major scrubbing
15 *
16 * All MC4_MISCi registers are shared between multi-cores
17 */
18 #include <linux/interrupt.h>
19 #include <linux/notifier.h>
20 #include <linux/kobject.h>
21 #include <linux/percpu.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/sysfs.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
27 #include <linux/cpu.h>
28 #include <linux/smp.h>
29
30 #include <asm/amd_nb.h>
31 #include <asm/apic.h>
32 #include <asm/idle.h>
33 #include <asm/mce.h>
34 #include <asm/msr.h>
35
36 #define NR_BANKS 6
37 #define NR_BLOCKS 9
38 #define THRESHOLD_MAX 0xFFF
39 #define INT_TYPE_APIC 0x00020000
40 #define MASK_VALID_HI 0x80000000
41 #define MASK_CNTP_HI 0x40000000
42 #define MASK_LOCKED_HI 0x20000000
43 #define MASK_LVTOFF_HI 0x00F00000
44 #define MASK_COUNT_EN_HI 0x00080000
45 #define MASK_INT_TYPE_HI 0x00060000
46 #define MASK_OVERFLOW_HI 0x00010000
47 #define MASK_ERR_COUNT_HI 0x00000FFF
48 #define MASK_BLKPTR_LO 0xFF000000
49 #define MCG_XBLK_ADDR 0xC0000400
50
51 static const char * const th_names[] = {
52 "load_store",
53 "insn_fetch",
54 "combined_unit",
55 "",
56 "northbridge",
57 "execution_unit",
58 };
59
60 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
61 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
62
63 static void amd_threshold_interrupt(void);
64
65 /*
66 * CPU Initialization
67 */
68
69 struct thresh_restart {
70 struct threshold_block *b;
71 int reset;
72 int set_lvt_off;
73 int lvt_off;
74 u16 old_limit;
75 };
76
77 static inline bool is_shared_bank(int bank)
78 {
79 /* Bank 4 is for northbridge reporting and is thus shared */
80 return (bank == 4);
81 }
82
83 static const char * const bank4_names(struct threshold_block *b)
84 {
85 switch (b->address) {
86 /* MSR4_MISC0 */
87 case 0x00000413:
88 return "dram";
89
90 case 0xc0000408:
91 return "ht_links";
92
93 case 0xc0000409:
94 return "l3_cache";
95
96 default:
97 WARN(1, "Funny MSR: 0x%08x\n", b->address);
98 return "";
99 }
100 };
101
102
103 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
104 {
105 /*
106 * bank 4 supports APIC LVT interrupts implicitly since forever.
107 */
108 if (bank == 4)
109 return true;
110
111 /*
112 * IntP: interrupt present; if this bit is set, the thresholding
113 * bank can generate APIC LVT interrupts
114 */
115 return msr_high_bits & BIT(28);
116 }
117
118 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
119 {
120 int msr = (hi & MASK_LVTOFF_HI) >> 20;
121
122 if (apic < 0) {
123 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
124 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
125 b->bank, b->block, b->address, hi, lo);
126 return 0;
127 }
128
129 if (apic != msr) {
130 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
131 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
132 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
133 return 0;
134 }
135
136 return 1;
137 };
138
139 /*
140 * Called via smp_call_function_single(), must be called with correct
141 * cpu affinity.
142 */
143 static void threshold_restart_bank(void *_tr)
144 {
145 struct thresh_restart *tr = _tr;
146 u32 hi, lo;
147
148 rdmsr(tr->b->address, lo, hi);
149
150 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
151 tr->reset = 1; /* limit cannot be lower than err count */
152
153 if (tr->reset) { /* reset err count and overflow bit */
154 hi =
155 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
156 (THRESHOLD_MAX - tr->b->threshold_limit);
157 } else if (tr->old_limit) { /* change limit w/o reset */
158 int new_count = (hi & THRESHOLD_MAX) +
159 (tr->old_limit - tr->b->threshold_limit);
160
161 hi = (hi & ~MASK_ERR_COUNT_HI) |
162 (new_count & THRESHOLD_MAX);
163 }
164
165 /* clear IntType */
166 hi &= ~MASK_INT_TYPE_HI;
167
168 if (!tr->b->interrupt_capable)
169 goto done;
170
171 if (tr->set_lvt_off) {
172 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
173 /* set new lvt offset */
174 hi &= ~MASK_LVTOFF_HI;
175 hi |= tr->lvt_off << 20;
176 }
177 }
178
179 if (tr->b->interrupt_enable)
180 hi |= INT_TYPE_APIC;
181
182 done:
183
184 hi |= MASK_COUNT_EN_HI;
185 wrmsr(tr->b->address, lo, hi);
186 }
187
188 static void mce_threshold_block_init(struct threshold_block *b, int offset)
189 {
190 struct thresh_restart tr = {
191 .b = b,
192 .set_lvt_off = 1,
193 .lvt_off = offset,
194 };
195
196 b->threshold_limit = THRESHOLD_MAX;
197 threshold_restart_bank(&tr);
198 };
199
200 static int setup_APIC_mce(int reserved, int new)
201 {
202 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
203 APIC_EILVT_MSG_FIX, 0))
204 return new;
205
206 return reserved;
207 }
208
209 /* cpu init entry point, called from mce.c with preempt off */
210 void mce_amd_feature_init(struct cpuinfo_x86 *c)
211 {
212 struct threshold_block b;
213 unsigned int cpu = smp_processor_id();
214 u32 low = 0, high = 0, address = 0;
215 unsigned int bank, block;
216 int offset = -1;
217
218 for (bank = 0; bank < NR_BANKS; ++bank) {
219 for (block = 0; block < NR_BLOCKS; ++block) {
220 if (block == 0)
221 address = MSR_IA32_MC0_MISC + bank * 4;
222 else if (block == 1) {
223 address = (low & MASK_BLKPTR_LO) >> 21;
224 if (!address)
225 break;
226
227 address += MCG_XBLK_ADDR;
228 } else
229 ++address;
230
231 if (rdmsr_safe(address, &low, &high))
232 break;
233
234 if (!(high & MASK_VALID_HI))
235 continue;
236
237 if (!(high & MASK_CNTP_HI) ||
238 (high & MASK_LOCKED_HI))
239 continue;
240
241 if (!block)
242 per_cpu(bank_map, cpu) |= (1 << bank);
243
244 memset(&b, 0, sizeof(b));
245 b.cpu = cpu;
246 b.bank = bank;
247 b.block = block;
248 b.address = address;
249 b.interrupt_capable = lvt_interrupt_supported(bank, high);
250
251 if (b.interrupt_capable) {
252 int new = (high & MASK_LVTOFF_HI) >> 20;
253 offset = setup_APIC_mce(offset, new);
254 }
255
256 mce_threshold_block_init(&b, offset);
257 mce_threshold_vector = amd_threshold_interrupt;
258 }
259 }
260 }
261
262 /*
263 * APIC Interrupt Handler
264 */
265
266 /*
267 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
268 * the interrupt goes off when error_count reaches threshold_limit.
269 * the handler will simply log mcelog w/ software defined bank number.
270 */
271 static void amd_threshold_interrupt(void)
272 {
273 u32 low = 0, high = 0, address = 0;
274 unsigned int bank, block;
275 struct mce m;
276
277 mce_setup(&m);
278
279 /* assume first bank caused it */
280 for (bank = 0; bank < NR_BANKS; ++bank) {
281 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
282 continue;
283 for (block = 0; block < NR_BLOCKS; ++block) {
284 if (block == 0) {
285 address = MSR_IA32_MC0_MISC + bank * 4;
286 } else if (block == 1) {
287 address = (low & MASK_BLKPTR_LO) >> 21;
288 if (!address)
289 break;
290 address += MCG_XBLK_ADDR;
291 } else {
292 ++address;
293 }
294
295 if (rdmsr_safe(address, &low, &high))
296 break;
297
298 if (!(high & MASK_VALID_HI)) {
299 if (block)
300 continue;
301 else
302 break;
303 }
304
305 if (!(high & MASK_CNTP_HI) ||
306 (high & MASK_LOCKED_HI))
307 continue;
308
309 /*
310 * Log the machine check that caused the threshold
311 * event.
312 */
313 machine_check_poll(MCP_TIMESTAMP,
314 &__get_cpu_var(mce_poll_banks));
315
316 if (high & MASK_OVERFLOW_HI) {
317 rdmsrl(address, m.misc);
318 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
319 m.status);
320 m.bank = K8_MCE_THRESHOLD_BASE
321 + bank * NR_BLOCKS
322 + block;
323 mce_log(&m);
324 return;
325 }
326 }
327 }
328 }
329
330 /*
331 * Sysfs Interface
332 */
333
334 struct threshold_attr {
335 struct attribute attr;
336 ssize_t (*show) (struct threshold_block *, char *);
337 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
338 };
339
340 #define SHOW_FIELDS(name) \
341 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
342 { \
343 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
344 }
345 SHOW_FIELDS(interrupt_enable)
346 SHOW_FIELDS(threshold_limit)
347
348 static ssize_t
349 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
350 {
351 struct thresh_restart tr;
352 unsigned long new;
353
354 if (!b->interrupt_capable)
355 return -EINVAL;
356
357 if (strict_strtoul(buf, 0, &new) < 0)
358 return -EINVAL;
359
360 b->interrupt_enable = !!new;
361
362 memset(&tr, 0, sizeof(tr));
363 tr.b = b;
364
365 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
366
367 return size;
368 }
369
370 static ssize_t
371 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
372 {
373 struct thresh_restart tr;
374 unsigned long new;
375
376 if (strict_strtoul(buf, 0, &new) < 0)
377 return -EINVAL;
378
379 if (new > THRESHOLD_MAX)
380 new = THRESHOLD_MAX;
381 if (new < 1)
382 new = 1;
383
384 memset(&tr, 0, sizeof(tr));
385 tr.old_limit = b->threshold_limit;
386 b->threshold_limit = new;
387 tr.b = b;
388
389 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
390
391 return size;
392 }
393
394 static ssize_t show_error_count(struct threshold_block *b, char *buf)
395 {
396 u32 lo, hi;
397
398 rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
399
400 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
401 (THRESHOLD_MAX - b->threshold_limit)));
402 }
403
404 static struct threshold_attr error_count = {
405 .attr = {.name = __stringify(error_count), .mode = 0444 },
406 .show = show_error_count,
407 };
408
409 #define RW_ATTR(val) \
410 static struct threshold_attr val = { \
411 .attr = {.name = __stringify(val), .mode = 0644 }, \
412 .show = show_## val, \
413 .store = store_## val, \
414 };
415
416 RW_ATTR(interrupt_enable);
417 RW_ATTR(threshold_limit);
418
419 static struct attribute *default_attrs[] = {
420 &threshold_limit.attr,
421 &error_count.attr,
422 NULL, /* possibly interrupt_enable if supported, see below */
423 NULL,
424 };
425
426 #define to_block(k) container_of(k, struct threshold_block, kobj)
427 #define to_attr(a) container_of(a, struct threshold_attr, attr)
428
429 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
430 {
431 struct threshold_block *b = to_block(kobj);
432 struct threshold_attr *a = to_attr(attr);
433 ssize_t ret;
434
435 ret = a->show ? a->show(b, buf) : -EIO;
436
437 return ret;
438 }
439
440 static ssize_t store(struct kobject *kobj, struct attribute *attr,
441 const char *buf, size_t count)
442 {
443 struct threshold_block *b = to_block(kobj);
444 struct threshold_attr *a = to_attr(attr);
445 ssize_t ret;
446
447 ret = a->store ? a->store(b, buf, count) : -EIO;
448
449 return ret;
450 }
451
452 static const struct sysfs_ops threshold_ops = {
453 .show = show,
454 .store = store,
455 };
456
457 static struct kobj_type threshold_ktype = {
458 .sysfs_ops = &threshold_ops,
459 .default_attrs = default_attrs,
460 };
461
462 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
463 unsigned int bank,
464 unsigned int block,
465 u32 address)
466 {
467 struct threshold_block *b = NULL;
468 u32 low, high;
469 int err;
470
471 if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
472 return 0;
473
474 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
475 return 0;
476
477 if (!(high & MASK_VALID_HI)) {
478 if (block)
479 goto recurse;
480 else
481 return 0;
482 }
483
484 if (!(high & MASK_CNTP_HI) ||
485 (high & MASK_LOCKED_HI))
486 goto recurse;
487
488 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
489 if (!b)
490 return -ENOMEM;
491
492 b->block = block;
493 b->bank = bank;
494 b->cpu = cpu;
495 b->address = address;
496 b->interrupt_enable = 0;
497 b->interrupt_capable = lvt_interrupt_supported(bank, high);
498 b->threshold_limit = THRESHOLD_MAX;
499
500 if (b->interrupt_capable)
501 threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
502 else
503 threshold_ktype.default_attrs[2] = NULL;
504
505 INIT_LIST_HEAD(&b->miscj);
506
507 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
508 list_add(&b->miscj,
509 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
510 } else {
511 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
512 }
513
514 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
515 per_cpu(threshold_banks, cpu)[bank]->kobj,
516 (bank == 4 ? bank4_names(b) : th_names[bank]));
517 if (err)
518 goto out_free;
519 recurse:
520 if (!block) {
521 address = (low & MASK_BLKPTR_LO) >> 21;
522 if (!address)
523 return 0;
524 address += MCG_XBLK_ADDR;
525 } else {
526 ++address;
527 }
528
529 err = allocate_threshold_blocks(cpu, bank, ++block, address);
530 if (err)
531 goto out_free;
532
533 if (b)
534 kobject_uevent(&b->kobj, KOBJ_ADD);
535
536 return err;
537
538 out_free:
539 if (b) {
540 kobject_put(&b->kobj);
541 list_del(&b->miscj);
542 kfree(b);
543 }
544 return err;
545 }
546
547 static __cpuinit int __threshold_add_blocks(struct threshold_bank *b)
548 {
549 struct list_head *head = &b->blocks->miscj;
550 struct threshold_block *pos = NULL;
551 struct threshold_block *tmp = NULL;
552 int err = 0;
553
554 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
555 if (err)
556 return err;
557
558 list_for_each_entry_safe(pos, tmp, head, miscj) {
559
560 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
561 if (err) {
562 list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
563 kobject_del(&pos->kobj);
564
565 return err;
566 }
567 }
568 return err;
569 }
570
571 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
572 {
573 struct device *dev = per_cpu(mce_device, cpu);
574 struct amd_northbridge *nb = NULL;
575 struct threshold_bank *b = NULL;
576 const char *name = th_names[bank];
577 int err = 0;
578
579 if (is_shared_bank(bank)) {
580 nb = node_to_amd_nb(amd_get_nb_id(cpu));
581
582 /* threshold descriptor already initialized on this node? */
583 if (nb && nb->bank4) {
584 /* yes, use it */
585 b = nb->bank4;
586 err = kobject_add(b->kobj, &dev->kobj, name);
587 if (err)
588 goto out;
589
590 per_cpu(threshold_banks, cpu)[bank] = b;
591 atomic_inc(&b->cpus);
592
593 err = __threshold_add_blocks(b);
594
595 goto out;
596 }
597 }
598
599 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
600 if (!b) {
601 err = -ENOMEM;
602 goto out;
603 }
604
605 b->kobj = kobject_create_and_add(name, &dev->kobj);
606 if (!b->kobj) {
607 err = -EINVAL;
608 goto out_free;
609 }
610
611 per_cpu(threshold_banks, cpu)[bank] = b;
612
613 if (is_shared_bank(bank)) {
614 atomic_set(&b->cpus, 1);
615
616 /* nb is already initialized, see above */
617 if (nb) {
618 WARN_ON(nb->bank4);
619 nb->bank4 = b;
620 }
621 }
622
623 err = allocate_threshold_blocks(cpu, bank, 0,
624 MSR_IA32_MC0_MISC + bank * 4);
625 if (!err)
626 goto out;
627
628 out_free:
629 kfree(b);
630
631 out:
632 return err;
633 }
634
635 /* create dir/files for all valid threshold banks */
636 static __cpuinit int threshold_create_device(unsigned int cpu)
637 {
638 unsigned int bank;
639 int err = 0;
640
641 for (bank = 0; bank < NR_BANKS; ++bank) {
642 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
643 continue;
644 err = threshold_create_bank(cpu, bank);
645 if (err)
646 return err;
647 }
648
649 return err;
650 }
651
652 static void deallocate_threshold_block(unsigned int cpu,
653 unsigned int bank)
654 {
655 struct threshold_block *pos = NULL;
656 struct threshold_block *tmp = NULL;
657 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
658
659 if (!head)
660 return;
661
662 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
663 kobject_put(&pos->kobj);
664 list_del(&pos->miscj);
665 kfree(pos);
666 }
667
668 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
669 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
670 }
671
672 static void __threshold_remove_blocks(struct threshold_bank *b)
673 {
674 struct threshold_block *pos = NULL;
675 struct threshold_block *tmp = NULL;
676
677 kobject_del(b->kobj);
678
679 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
680 kobject_del(&pos->kobj);
681 }
682
683 static void threshold_remove_bank(unsigned int cpu, int bank)
684 {
685 struct amd_northbridge *nb;
686 struct threshold_bank *b;
687
688 b = per_cpu(threshold_banks, cpu)[bank];
689 if (!b)
690 return;
691
692 if (!b->blocks)
693 goto free_out;
694
695 if (is_shared_bank(bank)) {
696 if (!atomic_dec_and_test(&b->cpus)) {
697 __threshold_remove_blocks(b);
698 per_cpu(threshold_banks, cpu)[bank] = NULL;
699 return;
700 } else {
701 /*
702 * the last CPU on this node using the shared bank is
703 * going away, remove that bank now.
704 */
705 nb = node_to_amd_nb(amd_get_nb_id(cpu));
706 nb->bank4 = NULL;
707 }
708 }
709
710 deallocate_threshold_block(cpu, bank);
711
712 free_out:
713 kobject_del(b->kobj);
714 kobject_put(b->kobj);
715 kfree(b);
716 per_cpu(threshold_banks, cpu)[bank] = NULL;
717 }
718
719 static void threshold_remove_device(unsigned int cpu)
720 {
721 unsigned int bank;
722
723 for (bank = 0; bank < NR_BANKS; ++bank) {
724 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
725 continue;
726 threshold_remove_bank(cpu, bank);
727 }
728 }
729
730 /* get notified when a cpu comes on/off */
731 static void __cpuinit
732 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
733 {
734 switch (action) {
735 case CPU_ONLINE:
736 case CPU_ONLINE_FROZEN:
737 threshold_create_device(cpu);
738 break;
739 case CPU_DEAD:
740 case CPU_DEAD_FROZEN:
741 threshold_remove_device(cpu);
742 break;
743 default:
744 break;
745 }
746 }
747
748 static __init int threshold_init_device(void)
749 {
750 unsigned lcpu = 0;
751
752 /* to hit CPUs online before the notifier is up */
753 for_each_online_cpu(lcpu) {
754 int err = threshold_create_device(lcpu);
755
756 if (err)
757 return err;
758 }
759 threshold_cpu_callback = amd_64_threshold_cpu_callback;
760
761 return 0;
762 }
763 /*
764 * there are 3 funcs which need to be _initcalled in a logic sequence:
765 * 1. xen_late_init_mcelog
766 * 2. mcheck_init_device
767 * 3. threshold_init_device
768 *
769 * xen_late_init_mcelog must register xen_mce_chrdev_device before
770 * native mce_chrdev_device registration if running under xen platform;
771 *
772 * mcheck_init_device should be inited before threshold_init_device to
773 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
774 *
775 * so we use following _initcalls
776 * 1. device_initcall(xen_late_init_mcelog);
777 * 2. device_initcall_sync(mcheck_init_device);
778 * 3. late_initcall(threshold_init_device);
779 *
780 * when running under xen, the initcall order is 1,2,3;
781 * on baremetal, we skip 1 and we do only 2 and 3.
782 */
783 late_initcall(threshold_init_device);
Linux kernel - Deliverables
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