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perf/x86/intel: Add Intel Skylake PMU support
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel_ds.c
1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 static const u64 pebs_data_source[] = {
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
57 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
66 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
67 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
70 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
71 };
72
73 static u64 precise_store_data(u64 status)
74 {
75 union intel_x86_pebs_dse dse;
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
77
78 dse.val = status;
79
80 /*
81 * bit 4: TLB access
82 * 1 = stored missed 2nd level TLB
83 *
84 * so it either hit the walker or the OS
85 * otherwise hit 2nd level TLB
86 */
87 if (dse.st_stlb_miss)
88 val |= P(TLB, MISS);
89 else
90 val |= P(TLB, HIT);
91
92 /*
93 * bit 0: hit L1 data cache
94 * if not set, then all we know is that
95 * it missed L1D
96 */
97 if (dse.st_l1d_hit)
98 val |= P(LVL, HIT);
99 else
100 val |= P(LVL, MISS);
101
102 /*
103 * bit 5: Locked prefix
104 */
105 if (dse.st_locked)
106 val |= P(LOCK, LOCKED);
107
108 return val;
109 }
110
111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
112 {
113 union perf_mem_data_src dse;
114
115 dse.val = PERF_MEM_NA;
116
117 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
118 dse.mem_op = PERF_MEM_OP_STORE;
119 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
120 dse.mem_op = PERF_MEM_OP_LOAD;
121
122 /*
123 * L1 info only valid for following events:
124 *
125 * MEM_UOPS_RETIRED.STLB_MISS_STORES
126 * MEM_UOPS_RETIRED.LOCK_STORES
127 * MEM_UOPS_RETIRED.SPLIT_STORES
128 * MEM_UOPS_RETIRED.ALL_STORES
129 */
130 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
131 if (status & 1)
132 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
133 else
134 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
135 }
136 return dse.val;
137 }
138
139 static u64 load_latency_data(u64 status)
140 {
141 union intel_x86_pebs_dse dse;
142 u64 val;
143 int model = boot_cpu_data.x86_model;
144 int fam = boot_cpu_data.x86;
145
146 dse.val = status;
147
148 /*
149 * use the mapping table for bit 0-3
150 */
151 val = pebs_data_source[dse.ld_dse];
152
153 /*
154 * Nehalem models do not support TLB, Lock infos
155 */
156 if (fam == 0x6 && (model == 26 || model == 30
157 || model == 31 || model == 46)) {
158 val |= P(TLB, NA) | P(LOCK, NA);
159 return val;
160 }
161 /*
162 * bit 4: TLB access
163 * 0 = did not miss 2nd level TLB
164 * 1 = missed 2nd level TLB
165 */
166 if (dse.ld_stlb_miss)
167 val |= P(TLB, MISS) | P(TLB, L2);
168 else
169 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
170
171 /*
172 * bit 5: locked prefix
173 */
174 if (dse.ld_locked)
175 val |= P(LOCK, LOCKED);
176
177 return val;
178 }
179
180 struct pebs_record_core {
181 u64 flags, ip;
182 u64 ax, bx, cx, dx;
183 u64 si, di, bp, sp;
184 u64 r8, r9, r10, r11;
185 u64 r12, r13, r14, r15;
186 };
187
188 struct pebs_record_nhm {
189 u64 flags, ip;
190 u64 ax, bx, cx, dx;
191 u64 si, di, bp, sp;
192 u64 r8, r9, r10, r11;
193 u64 r12, r13, r14, r15;
194 u64 status, dla, dse, lat;
195 };
196
197 /*
198 * Same as pebs_record_nhm, with two additional fields.
199 */
200 struct pebs_record_hsw {
201 u64 flags, ip;
202 u64 ax, bx, cx, dx;
203 u64 si, di, bp, sp;
204 u64 r8, r9, r10, r11;
205 u64 r12, r13, r14, r15;
206 u64 status, dla, dse, lat;
207 u64 real_ip, tsx_tuning;
208 };
209
210 union hsw_tsx_tuning {
211 struct {
212 u32 cycles_last_block : 32,
213 hle_abort : 1,
214 rtm_abort : 1,
215 instruction_abort : 1,
216 non_instruction_abort : 1,
217 retry : 1,
218 data_conflict : 1,
219 capacity_writes : 1,
220 capacity_reads : 1;
221 };
222 u64 value;
223 };
224
225 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
226
227 /* Same as HSW, plus TSC */
228
229 struct pebs_record_skl {
230 u64 flags, ip;
231 u64 ax, bx, cx, dx;
232 u64 si, di, bp, sp;
233 u64 r8, r9, r10, r11;
234 u64 r12, r13, r14, r15;
235 u64 status, dla, dse, lat;
236 u64 real_ip, tsx_tuning;
237 u64 tsc;
238 };
239
240 void init_debug_store_on_cpu(int cpu)
241 {
242 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
243
244 if (!ds)
245 return;
246
247 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
248 (u32)((u64)(unsigned long)ds),
249 (u32)((u64)(unsigned long)ds >> 32));
250 }
251
252 void fini_debug_store_on_cpu(int cpu)
253 {
254 if (!per_cpu(cpu_hw_events, cpu).ds)
255 return;
256
257 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
258 }
259
260 static DEFINE_PER_CPU(void *, insn_buffer);
261
262 static int alloc_pebs_buffer(int cpu)
263 {
264 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
265 int node = cpu_to_node(cpu);
266 int max;
267 void *buffer, *ibuffer;
268
269 if (!x86_pmu.pebs)
270 return 0;
271
272 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
273 if (unlikely(!buffer))
274 return -ENOMEM;
275
276 /*
277 * HSW+ already provides us the eventing ip; no need to allocate this
278 * buffer then.
279 */
280 if (x86_pmu.intel_cap.pebs_format < 2) {
281 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
282 if (!ibuffer) {
283 kfree(buffer);
284 return -ENOMEM;
285 }
286 per_cpu(insn_buffer, cpu) = ibuffer;
287 }
288
289 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
290
291 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
292 ds->pebs_index = ds->pebs_buffer_base;
293 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
294 max * x86_pmu.pebs_record_size;
295
296 return 0;
297 }
298
299 static void release_pebs_buffer(int cpu)
300 {
301 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
302
303 if (!ds || !x86_pmu.pebs)
304 return;
305
306 kfree(per_cpu(insn_buffer, cpu));
307 per_cpu(insn_buffer, cpu) = NULL;
308
309 kfree((void *)(unsigned long)ds->pebs_buffer_base);
310 ds->pebs_buffer_base = 0;
311 }
312
313 static int alloc_bts_buffer(int cpu)
314 {
315 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
316 int node = cpu_to_node(cpu);
317 int max, thresh;
318 void *buffer;
319
320 if (!x86_pmu.bts)
321 return 0;
322
323 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
324 if (unlikely(!buffer)) {
325 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
326 return -ENOMEM;
327 }
328
329 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
330 thresh = max / 16;
331
332 ds->bts_buffer_base = (u64)(unsigned long)buffer;
333 ds->bts_index = ds->bts_buffer_base;
334 ds->bts_absolute_maximum = ds->bts_buffer_base +
335 max * BTS_RECORD_SIZE;
336 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
337 thresh * BTS_RECORD_SIZE;
338
339 return 0;
340 }
341
342 static void release_bts_buffer(int cpu)
343 {
344 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
345
346 if (!ds || !x86_pmu.bts)
347 return;
348
349 kfree((void *)(unsigned long)ds->bts_buffer_base);
350 ds->bts_buffer_base = 0;
351 }
352
353 static int alloc_ds_buffer(int cpu)
354 {
355 int node = cpu_to_node(cpu);
356 struct debug_store *ds;
357
358 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
359 if (unlikely(!ds))
360 return -ENOMEM;
361
362 per_cpu(cpu_hw_events, cpu).ds = ds;
363
364 return 0;
365 }
366
367 static void release_ds_buffer(int cpu)
368 {
369 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
370
371 if (!ds)
372 return;
373
374 per_cpu(cpu_hw_events, cpu).ds = NULL;
375 kfree(ds);
376 }
377
378 void release_ds_buffers(void)
379 {
380 int cpu;
381
382 if (!x86_pmu.bts && !x86_pmu.pebs)
383 return;
384
385 get_online_cpus();
386 for_each_online_cpu(cpu)
387 fini_debug_store_on_cpu(cpu);
388
389 for_each_possible_cpu(cpu) {
390 release_pebs_buffer(cpu);
391 release_bts_buffer(cpu);
392 release_ds_buffer(cpu);
393 }
394 put_online_cpus();
395 }
396
397 void reserve_ds_buffers(void)
398 {
399 int bts_err = 0, pebs_err = 0;
400 int cpu;
401
402 x86_pmu.bts_active = 0;
403 x86_pmu.pebs_active = 0;
404
405 if (!x86_pmu.bts && !x86_pmu.pebs)
406 return;
407
408 if (!x86_pmu.bts)
409 bts_err = 1;
410
411 if (!x86_pmu.pebs)
412 pebs_err = 1;
413
414 get_online_cpus();
415
416 for_each_possible_cpu(cpu) {
417 if (alloc_ds_buffer(cpu)) {
418 bts_err = 1;
419 pebs_err = 1;
420 }
421
422 if (!bts_err && alloc_bts_buffer(cpu))
423 bts_err = 1;
424
425 if (!pebs_err && alloc_pebs_buffer(cpu))
426 pebs_err = 1;
427
428 if (bts_err && pebs_err)
429 break;
430 }
431
432 if (bts_err) {
433 for_each_possible_cpu(cpu)
434 release_bts_buffer(cpu);
435 }
436
437 if (pebs_err) {
438 for_each_possible_cpu(cpu)
439 release_pebs_buffer(cpu);
440 }
441
442 if (bts_err && pebs_err) {
443 for_each_possible_cpu(cpu)
444 release_ds_buffer(cpu);
445 } else {
446 if (x86_pmu.bts && !bts_err)
447 x86_pmu.bts_active = 1;
448
449 if (x86_pmu.pebs && !pebs_err)
450 x86_pmu.pebs_active = 1;
451
452 for_each_online_cpu(cpu)
453 init_debug_store_on_cpu(cpu);
454 }
455
456 put_online_cpus();
457 }
458
459 /*
460 * BTS
461 */
462
463 struct event_constraint bts_constraint =
464 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
465
466 void intel_pmu_enable_bts(u64 config)
467 {
468 unsigned long debugctlmsr;
469
470 debugctlmsr = get_debugctlmsr();
471
472 debugctlmsr |= DEBUGCTLMSR_TR;
473 debugctlmsr |= DEBUGCTLMSR_BTS;
474 if (config & ARCH_PERFMON_EVENTSEL_INT)
475 debugctlmsr |= DEBUGCTLMSR_BTINT;
476
477 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
478 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
479
480 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
481 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
482
483 update_debugctlmsr(debugctlmsr);
484 }
485
486 void intel_pmu_disable_bts(void)
487 {
488 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
489 unsigned long debugctlmsr;
490
491 if (!cpuc->ds)
492 return;
493
494 debugctlmsr = get_debugctlmsr();
495
496 debugctlmsr &=
497 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
498 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
499
500 update_debugctlmsr(debugctlmsr);
501 }
502
503 int intel_pmu_drain_bts_buffer(void)
504 {
505 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
506 struct debug_store *ds = cpuc->ds;
507 struct bts_record {
508 u64 from;
509 u64 to;
510 u64 flags;
511 };
512 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
513 struct bts_record *at, *top;
514 struct perf_output_handle handle;
515 struct perf_event_header header;
516 struct perf_sample_data data;
517 struct pt_regs regs;
518
519 if (!event)
520 return 0;
521
522 if (!x86_pmu.bts_active)
523 return 0;
524
525 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
526 top = (struct bts_record *)(unsigned long)ds->bts_index;
527
528 if (top <= at)
529 return 0;
530
531 memset(&regs, 0, sizeof(regs));
532
533 ds->bts_index = ds->bts_buffer_base;
534
535 perf_sample_data_init(&data, 0, event->hw.last_period);
536
537 /*
538 * Prepare a generic sample, i.e. fill in the invariant fields.
539 * We will overwrite the from and to address before we output
540 * the sample.
541 */
542 perf_prepare_sample(&header, &data, event, &regs);
543
544 if (perf_output_begin(&handle, event, header.size * (top - at)))
545 return 1;
546
547 for (; at < top; at++) {
548 data.ip = at->from;
549 data.addr = at->to;
550
551 perf_output_sample(&handle, &header, &data, event);
552 }
553
554 perf_output_end(&handle);
555
556 /* There's new data available. */
557 event->hw.interrupts++;
558 event->pending_kill = POLL_IN;
559 return 1;
560 }
561
562 static inline void intel_pmu_drain_pebs_buffer(void)
563 {
564 struct pt_regs regs;
565
566 x86_pmu.drain_pebs(&regs);
567 }
568
569 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
570 {
571 if (!sched_in)
572 intel_pmu_drain_pebs_buffer();
573 }
574
575 /*
576 * PEBS
577 */
578 struct event_constraint intel_core2_pebs_event_constraints[] = {
579 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
580 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
581 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
582 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
583 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
584 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
585 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
586 EVENT_CONSTRAINT_END
587 };
588
589 struct event_constraint intel_atom_pebs_event_constraints[] = {
590 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
591 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
592 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
593 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
594 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
595 EVENT_CONSTRAINT_END
596 };
597
598 struct event_constraint intel_slm_pebs_event_constraints[] = {
599 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
600 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
601 /* Allow all events as PEBS with no flags */
602 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
603 EVENT_CONSTRAINT_END
604 };
605
606 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
607 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
608 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
609 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
610 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
611 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
612 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
613 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
614 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
615 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
616 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
617 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
618 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
619 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
620 EVENT_CONSTRAINT_END
621 };
622
623 struct event_constraint intel_westmere_pebs_event_constraints[] = {
624 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
626 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
627 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
628 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
629 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
630 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
631 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
632 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
633 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
634 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
635 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
636 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
637 EVENT_CONSTRAINT_END
638 };
639
640 struct event_constraint intel_snb_pebs_event_constraints[] = {
641 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
642 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
643 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
644 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
645 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
646 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
647 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
648 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
649 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
650 /* Allow all events as PEBS with no flags */
651 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
652 EVENT_CONSTRAINT_END
653 };
654
655 struct event_constraint intel_ivb_pebs_event_constraints[] = {
656 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
657 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
658 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
659 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
660 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
661 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
662 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
663 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
664 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
665 /* Allow all events as PEBS with no flags */
666 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
667 EVENT_CONSTRAINT_END
668 };
669
670 struct event_constraint intel_hsw_pebs_event_constraints[] = {
671 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
672 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
673 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
674 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
675 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
676 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
677 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
678 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
679 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
680 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
681 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
682 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
683 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
684 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
685 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
686 /* Allow all events as PEBS with no flags */
687 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
688 EVENT_CONSTRAINT_END
689 };
690
691 struct event_constraint intel_skl_pebs_event_constraints[] = {
692 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
693 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
694 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
695 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
696 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
697 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
698 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
699 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
700 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
701 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
702 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
703 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
704 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
705 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
706 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
707 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
708 /* Allow all events as PEBS with no flags */
709 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
710 EVENT_CONSTRAINT_END
711 };
712
713 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
714 {
715 struct event_constraint *c;
716
717 if (!event->attr.precise_ip)
718 return NULL;
719
720 if (x86_pmu.pebs_constraints) {
721 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
722 if ((event->hw.config & c->cmask) == c->code) {
723 event->hw.flags |= c->flags;
724 return c;
725 }
726 }
727 }
728
729 return &emptyconstraint;
730 }
731
732 static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
733 {
734 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
735 }
736
737 void intel_pmu_pebs_enable(struct perf_event *event)
738 {
739 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
740 struct hw_perf_event *hwc = &event->hw;
741 struct debug_store *ds = cpuc->ds;
742 bool first_pebs;
743 u64 threshold;
744
745 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
746
747 first_pebs = !pebs_is_enabled(cpuc);
748 cpuc->pebs_enabled |= 1ULL << hwc->idx;
749
750 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
751 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
752 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
753 cpuc->pebs_enabled |= 1ULL << 63;
754
755 /*
756 * When the event is constrained enough we can use a larger
757 * threshold and run the event with less frequent PMI.
758 */
759 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
760 threshold = ds->pebs_absolute_maximum -
761 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
762
763 if (first_pebs)
764 perf_sched_cb_inc(event->ctx->pmu);
765 } else {
766 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
767
768 /*
769 * If not all events can use larger buffer,
770 * roll back to threshold = 1
771 */
772 if (!first_pebs &&
773 (ds->pebs_interrupt_threshold > threshold))
774 perf_sched_cb_dec(event->ctx->pmu);
775 }
776
777 /* Use auto-reload if possible to save a MSR write in the PMI */
778 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
779 ds->pebs_event_reset[hwc->idx] =
780 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
781 }
782
783 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
784 ds->pebs_interrupt_threshold = threshold;
785 }
786
787 void intel_pmu_pebs_disable(struct perf_event *event)
788 {
789 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
790 struct hw_perf_event *hwc = &event->hw;
791 struct debug_store *ds = cpuc->ds;
792
793 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
794
795 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
796 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
797 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
798 cpuc->pebs_enabled &= ~(1ULL << 63);
799
800 if (ds->pebs_interrupt_threshold >
801 ds->pebs_buffer_base + x86_pmu.pebs_record_size) {
802 intel_pmu_drain_pebs_buffer();
803 if (!pebs_is_enabled(cpuc))
804 perf_sched_cb_dec(event->ctx->pmu);
805 }
806
807 if (cpuc->enabled)
808 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
809
810 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
811 }
812
813 void intel_pmu_pebs_enable_all(void)
814 {
815 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
816
817 if (cpuc->pebs_enabled)
818 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
819 }
820
821 void intel_pmu_pebs_disable_all(void)
822 {
823 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
824
825 if (cpuc->pebs_enabled)
826 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
827 }
828
829 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
830 {
831 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
832 unsigned long from = cpuc->lbr_entries[0].from;
833 unsigned long old_to, to = cpuc->lbr_entries[0].to;
834 unsigned long ip = regs->ip;
835 int is_64bit = 0;
836 void *kaddr;
837 int size;
838
839 /*
840 * We don't need to fixup if the PEBS assist is fault like
841 */
842 if (!x86_pmu.intel_cap.pebs_trap)
843 return 1;
844
845 /*
846 * No LBR entry, no basic block, no rewinding
847 */
848 if (!cpuc->lbr_stack.nr || !from || !to)
849 return 0;
850
851 /*
852 * Basic blocks should never cross user/kernel boundaries
853 */
854 if (kernel_ip(ip) != kernel_ip(to))
855 return 0;
856
857 /*
858 * unsigned math, either ip is before the start (impossible) or
859 * the basic block is larger than 1 page (sanity)
860 */
861 if ((ip - to) > PEBS_FIXUP_SIZE)
862 return 0;
863
864 /*
865 * We sampled a branch insn, rewind using the LBR stack
866 */
867 if (ip == to) {
868 set_linear_ip(regs, from);
869 return 1;
870 }
871
872 size = ip - to;
873 if (!kernel_ip(ip)) {
874 int bytes;
875 u8 *buf = this_cpu_read(insn_buffer);
876
877 /* 'size' must fit our buffer, see above */
878 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
879 if (bytes != 0)
880 return 0;
881
882 kaddr = buf;
883 } else {
884 kaddr = (void *)to;
885 }
886
887 do {
888 struct insn insn;
889
890 old_to = to;
891
892 #ifdef CONFIG_X86_64
893 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
894 #endif
895 insn_init(&insn, kaddr, size, is_64bit);
896 insn_get_length(&insn);
897 /*
898 * Make sure there was not a problem decoding the
899 * instruction and getting the length. This is
900 * doubly important because we have an infinite
901 * loop if insn.length=0.
902 */
903 if (!insn.length)
904 break;
905
906 to += insn.length;
907 kaddr += insn.length;
908 size -= insn.length;
909 } while (to < ip);
910
911 if (to == ip) {
912 set_linear_ip(regs, old_to);
913 return 1;
914 }
915
916 /*
917 * Even though we decoded the basic block, the instruction stream
918 * never matched the given IP, either the TO or the IP got corrupted.
919 */
920 return 0;
921 }
922
923 static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
924 {
925 if (pebs->tsx_tuning) {
926 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
927 return tsx.cycles_last_block;
928 }
929 return 0;
930 }
931
932 static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
933 {
934 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
935
936 /* For RTM XABORTs also log the abort code from AX */
937 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
938 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
939 return txn;
940 }
941
942 static void setup_pebs_sample_data(struct perf_event *event,
943 struct pt_regs *iregs, void *__pebs,
944 struct perf_sample_data *data,
945 struct pt_regs *regs)
946 {
947 #define PERF_X86_EVENT_PEBS_HSW_PREC \
948 (PERF_X86_EVENT_PEBS_ST_HSW | \
949 PERF_X86_EVENT_PEBS_LD_HSW | \
950 PERF_X86_EVENT_PEBS_NA_HSW)
951 /*
952 * We cast to the biggest pebs_record but are careful not to
953 * unconditionally access the 'extra' entries.
954 */
955 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
956 struct pebs_record_skl *pebs = __pebs;
957 u64 sample_type;
958 int fll, fst, dsrc;
959 int fl = event->hw.flags;
960
961 if (pebs == NULL)
962 return;
963
964 sample_type = event->attr.sample_type;
965 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
966
967 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
968 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
969
970 perf_sample_data_init(data, 0, event->hw.last_period);
971
972 data->period = event->hw.last_period;
973
974 /*
975 * Use latency for weight (only avail with PEBS-LL)
976 */
977 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
978 data->weight = pebs->lat;
979
980 /*
981 * data.data_src encodes the data source
982 */
983 if (dsrc) {
984 u64 val = PERF_MEM_NA;
985 if (fll)
986 val = load_latency_data(pebs->dse);
987 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
988 val = precise_datala_hsw(event, pebs->dse);
989 else if (fst)
990 val = precise_store_data(pebs->dse);
991 data->data_src.val = val;
992 }
993
994 /*
995 * We use the interrupt regs as a base because the PEBS record
996 * does not contain a full regs set, specifically it seems to
997 * lack segment descriptors, which get used by things like
998 * user_mode().
999 *
1000 * In the simple case fix up only the IP and BP,SP regs, for
1001 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
1002 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
1003 */
1004 *regs = *iregs;
1005 regs->flags = pebs->flags;
1006 set_linear_ip(regs, pebs->ip);
1007 regs->bp = pebs->bp;
1008 regs->sp = pebs->sp;
1009
1010 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1011 regs->ax = pebs->ax;
1012 regs->bx = pebs->bx;
1013 regs->cx = pebs->cx;
1014 regs->dx = pebs->dx;
1015 regs->si = pebs->si;
1016 regs->di = pebs->di;
1017 regs->bp = pebs->bp;
1018 regs->sp = pebs->sp;
1019
1020 regs->flags = pebs->flags;
1021 #ifndef CONFIG_X86_32
1022 regs->r8 = pebs->r8;
1023 regs->r9 = pebs->r9;
1024 regs->r10 = pebs->r10;
1025 regs->r11 = pebs->r11;
1026 regs->r12 = pebs->r12;
1027 regs->r13 = pebs->r13;
1028 regs->r14 = pebs->r14;
1029 regs->r15 = pebs->r15;
1030 #endif
1031 }
1032
1033 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1034 regs->ip = pebs->real_ip;
1035 regs->flags |= PERF_EFLAGS_EXACT;
1036 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1037 regs->flags |= PERF_EFLAGS_EXACT;
1038 else
1039 regs->flags &= ~PERF_EFLAGS_EXACT;
1040
1041 if ((sample_type & PERF_SAMPLE_ADDR) &&
1042 x86_pmu.intel_cap.pebs_format >= 1)
1043 data->addr = pebs->dla;
1044
1045 if (x86_pmu.intel_cap.pebs_format >= 2) {
1046 /* Only set the TSX weight when no memory weight. */
1047 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1048 data->weight = intel_hsw_weight(pebs);
1049
1050 if (sample_type & PERF_SAMPLE_TRANSACTION)
1051 data->txn = intel_hsw_transaction(pebs);
1052 }
1053
1054 /*
1055 * v3 supplies an accurate time stamp, so we use that
1056 * for the time stamp.
1057 *
1058 * We can only do this for the default trace clock.
1059 */
1060 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1061 event->attr.use_clockid == 0)
1062 data->time = native_sched_clock_from_tsc(pebs->tsc);
1063
1064 if (has_branch_stack(event))
1065 data->br_stack = &cpuc->lbr_stack;
1066 }
1067
1068 static inline void *
1069 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1070 {
1071 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1072 void *at;
1073 u64 pebs_status;
1074
1075 if (base == NULL)
1076 return NULL;
1077
1078 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1079 struct pebs_record_nhm *p = at;
1080
1081 if (test_bit(bit, (unsigned long *)&p->status)) {
1082 /* PEBS v3 has accurate status bits */
1083 if (x86_pmu.intel_cap.pebs_format >= 3)
1084 return at;
1085
1086 if (p->status == (1 << bit))
1087 return at;
1088
1089 /* clear non-PEBS bit and re-check */
1090 pebs_status = p->status & cpuc->pebs_enabled;
1091 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1092 if (pebs_status == (1 << bit))
1093 return at;
1094 }
1095 }
1096 return NULL;
1097 }
1098
1099 static void __intel_pmu_pebs_event(struct perf_event *event,
1100 struct pt_regs *iregs,
1101 void *base, void *top,
1102 int bit, int count)
1103 {
1104 struct perf_sample_data data;
1105 struct pt_regs regs;
1106 void *at = get_next_pebs_record_by_bit(base, top, bit);
1107
1108 if (!intel_pmu_save_and_restart(event) &&
1109 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1110 return;
1111
1112 while (count > 1) {
1113 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1114 perf_event_output(event, &data, &regs);
1115 at += x86_pmu.pebs_record_size;
1116 at = get_next_pebs_record_by_bit(at, top, bit);
1117 count--;
1118 }
1119
1120 setup_pebs_sample_data(event, iregs, at, &data, &regs);
1121
1122 /*
1123 * All but the last records are processed.
1124 * The last one is left to be able to call the overflow handler.
1125 */
1126 if (perf_event_overflow(event, &data, &regs)) {
1127 x86_pmu_stop(event, 0);
1128 return;
1129 }
1130
1131 }
1132
1133 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1134 {
1135 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1136 struct debug_store *ds = cpuc->ds;
1137 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1138 struct pebs_record_core *at, *top;
1139 int n;
1140
1141 if (!x86_pmu.pebs_active)
1142 return;
1143
1144 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1145 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1146
1147 /*
1148 * Whatever else happens, drain the thing
1149 */
1150 ds->pebs_index = ds->pebs_buffer_base;
1151
1152 if (!test_bit(0, cpuc->active_mask))
1153 return;
1154
1155 WARN_ON_ONCE(!event);
1156
1157 if (!event->attr.precise_ip)
1158 return;
1159
1160 n = (top - at) / x86_pmu.pebs_record_size;
1161 if (n <= 0)
1162 return;
1163
1164 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1165 }
1166
1167 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1168 {
1169 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1170 struct debug_store *ds = cpuc->ds;
1171 struct perf_event *event;
1172 void *base, *at, *top;
1173 short counts[MAX_PEBS_EVENTS] = {};
1174 short error[MAX_PEBS_EVENTS] = {};
1175 int bit, i;
1176
1177 if (!x86_pmu.pebs_active)
1178 return;
1179
1180 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1181 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1182
1183 ds->pebs_index = ds->pebs_buffer_base;
1184
1185 if (unlikely(base >= top))
1186 return;
1187
1188 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1189 struct pebs_record_nhm *p = at;
1190
1191 /* PEBS v3 has accurate status bits */
1192 if (x86_pmu.intel_cap.pebs_format >= 3) {
1193 for_each_set_bit(bit, (unsigned long *)&p->status,
1194 MAX_PEBS_EVENTS)
1195 counts[bit]++;
1196
1197 continue;
1198 }
1199
1200 bit = find_first_bit((unsigned long *)&p->status,
1201 x86_pmu.max_pebs_events);
1202 if (bit >= x86_pmu.max_pebs_events)
1203 continue;
1204 if (!test_bit(bit, cpuc->active_mask))
1205 continue;
1206 /*
1207 * The PEBS hardware does not deal well with the situation
1208 * when events happen near to each other and multiple bits
1209 * are set. But it should happen rarely.
1210 *
1211 * If these events include one PEBS and multiple non-PEBS
1212 * events, it doesn't impact PEBS record. The record will
1213 * be handled normally. (slow path)
1214 *
1215 * If these events include two or more PEBS events, the
1216 * records for the events can be collapsed into a single
1217 * one, and it's not possible to reconstruct all events
1218 * that caused the PEBS record. It's called collision.
1219 * If collision happened, the record will be dropped.
1220 *
1221 */
1222 if (p->status != (1 << bit)) {
1223 u64 pebs_status;
1224
1225 /* slow path */
1226 pebs_status = p->status & cpuc->pebs_enabled;
1227 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1228 if (pebs_status != (1 << bit)) {
1229 for_each_set_bit(i, (unsigned long *)&pebs_status,
1230 MAX_PEBS_EVENTS)
1231 error[i]++;
1232 continue;
1233 }
1234 }
1235 counts[bit]++;
1236 }
1237
1238 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1239 if ((counts[bit] == 0) && (error[bit] == 0))
1240 continue;
1241 event = cpuc->events[bit];
1242 WARN_ON_ONCE(!event);
1243 WARN_ON_ONCE(!event->attr.precise_ip);
1244
1245 /* log dropped samples number */
1246 if (error[bit])
1247 perf_log_lost_samples(event, error[bit]);
1248
1249 if (counts[bit]) {
1250 __intel_pmu_pebs_event(event, iregs, base,
1251 top, bit, counts[bit]);
1252 }
1253 }
1254 }
1255
1256 /*
1257 * BTS, PEBS probe and setup
1258 */
1259
1260 void __init intel_ds_init(void)
1261 {
1262 /*
1263 * No support for 32bit formats
1264 */
1265 if (!boot_cpu_has(X86_FEATURE_DTES64))
1266 return;
1267
1268 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1269 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1270 if (x86_pmu.pebs) {
1271 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1272 int format = x86_pmu.intel_cap.pebs_format;
1273
1274 switch (format) {
1275 case 0:
1276 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1277 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1278 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1279 break;
1280
1281 case 1:
1282 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1283 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1284 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1285 break;
1286
1287 case 2:
1288 pr_cont("PEBS fmt2%c, ", pebs_type);
1289 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1290 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1291 break;
1292
1293 case 3:
1294 pr_cont("PEBS fmt3%c, ", pebs_type);
1295 x86_pmu.pebs_record_size =
1296 sizeof(struct pebs_record_skl);
1297 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1298 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1299 break;
1300
1301 default:
1302 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1303 x86_pmu.pebs = 0;
1304 }
1305 }
1306 }
1307
1308 void perf_restore_debug_store(void)
1309 {
1310 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1311
1312 if (!x86_pmu.bts && !x86_pmu.pebs)
1313 return;
1314
1315 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1316 }
Linux kernel - Deliverables
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