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[deliverable/linux.git] / arch / x86 / kvm / lapic.c
1
2 /*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
23 #include <linux/mm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
27 #include <linux/io.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
32 #include <asm/msr.h>
33 #include <asm/page.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <linux/atomic.h>
37 #include <linux/jump_label.h>
38 #include "kvm_cache_regs.h"
39 #include "irq.h"
40 #include "trace.h"
41 #include "x86.h"
42 #include "cpuid.h"
43
44 #ifndef CONFIG_X86_64
45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
46 #else
47 #define mod_64(x, y) ((x) % (y))
48 #endif
49
50 #define PRId64 "d"
51 #define PRIx64 "llx"
52 #define PRIu64 "u"
53 #define PRIo64 "o"
54
55 #define APIC_BUS_CYCLE_NS 1
56
57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58 #define apic_debug(fmt, arg...)
59
60 #define APIC_LVT_NUM 6
61 /* 14 is the version for Xeon and Pentium 8.4.8*/
62 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
63 #define LAPIC_MMIO_LENGTH (1 << 12)
64 /* followed define is not in apicdef.h */
65 #define APIC_SHORT_MASK 0xc0000
66 #define APIC_DEST_NOSHORT 0x0
67 #define APIC_DEST_MASK 0x800
68 #define MAX_APIC_VECTOR 256
69 #define APIC_VECTORS_PER_REG 32
70
71 #define APIC_BROADCAST 0xFF
72 #define X2APIC_BROADCAST 0xFFFFFFFFul
73
74 #define VEC_POS(v) ((v) & (32 - 1))
75 #define REG_POS(v) (((v) >> 5) << 4)
76
77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
78 {
79 *((u32 *) (apic->regs + reg_off)) = val;
80 }
81
82 static inline int apic_test_vector(int vec, void *bitmap)
83 {
84 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
85 }
86
87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
88 {
89 struct kvm_lapic *apic = vcpu->arch.apic;
90
91 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
92 apic_test_vector(vector, apic->regs + APIC_IRR);
93 }
94
95 static inline void apic_set_vector(int vec, void *bitmap)
96 {
97 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98 }
99
100 static inline void apic_clear_vector(int vec, void *bitmap)
101 {
102 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103 }
104
105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
106 {
107 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
108 }
109
110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
111 {
112 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
113 }
114
115 struct static_key_deferred apic_hw_disabled __read_mostly;
116 struct static_key_deferred apic_sw_disabled __read_mostly;
117
118 static inline int apic_enabled(struct kvm_lapic *apic)
119 {
120 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
121 }
122
123 #define LVT_MASK \
124 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
125
126 #define LINT_MASK \
127 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
128 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
129
130 static inline int kvm_apic_id(struct kvm_lapic *apic)
131 {
132 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
133 }
134
135 #define KVM_X2APIC_CID_BITS 0
136
137 static void recalculate_apic_map(struct kvm *kvm)
138 {
139 struct kvm_apic_map *new, *old = NULL;
140 struct kvm_vcpu *vcpu;
141 int i;
142
143 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
144
145 mutex_lock(&kvm->arch.apic_map_lock);
146
147 if (!new)
148 goto out;
149
150 new->ldr_bits = 8;
151 /* flat mode is default */
152 new->cid_shift = 8;
153 new->cid_mask = 0;
154 new->lid_mask = 0xff;
155 new->broadcast = APIC_BROADCAST;
156
157 kvm_for_each_vcpu(i, vcpu, kvm) {
158 struct kvm_lapic *apic = vcpu->arch.apic;
159
160 if (!kvm_apic_present(vcpu))
161 continue;
162
163 if (apic_x2apic_mode(apic)) {
164 new->ldr_bits = 32;
165 new->cid_shift = 16;
166 new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
167 new->lid_mask = 0xffff;
168 new->broadcast = X2APIC_BROADCAST;
169 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
170 if (kvm_apic_get_reg(apic, APIC_DFR) ==
171 APIC_DFR_CLUSTER) {
172 new->cid_shift = 4;
173 new->cid_mask = 0xf;
174 new->lid_mask = 0xf;
175 } else {
176 new->cid_shift = 8;
177 new->cid_mask = 0;
178 new->lid_mask = 0xff;
179 }
180 }
181
182 /*
183 * All APICs have to be configured in the same mode by an OS.
184 * We take advatage of this while building logical id loockup
185 * table. After reset APICs are in software disabled mode, so if
186 * we find apic with different setting we assume this is the mode
187 * OS wants all apics to be in; build lookup table accordingly.
188 */
189 if (kvm_apic_sw_enabled(apic))
190 break;
191 }
192
193 kvm_for_each_vcpu(i, vcpu, kvm) {
194 struct kvm_lapic *apic = vcpu->arch.apic;
195 u16 cid, lid;
196 u32 ldr, aid;
197
198 aid = kvm_apic_id(apic);
199 ldr = kvm_apic_get_reg(apic, APIC_LDR);
200 cid = apic_cluster_id(new, ldr);
201 lid = apic_logical_id(new, ldr);
202
203 if (aid < ARRAY_SIZE(new->phys_map))
204 new->phys_map[aid] = apic;
205 if (lid && cid < ARRAY_SIZE(new->logical_map))
206 new->logical_map[cid][ffs(lid) - 1] = apic;
207 }
208 out:
209 old = rcu_dereference_protected(kvm->arch.apic_map,
210 lockdep_is_held(&kvm->arch.apic_map_lock));
211 rcu_assign_pointer(kvm->arch.apic_map, new);
212 mutex_unlock(&kvm->arch.apic_map_lock);
213
214 if (old)
215 kfree_rcu(old, rcu);
216
217 kvm_vcpu_request_scan_ioapic(kvm);
218 }
219
220 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
221 {
222 bool enabled = val & APIC_SPIV_APIC_ENABLED;
223
224 apic_set_reg(apic, APIC_SPIV, val);
225
226 if (enabled != apic->sw_enabled) {
227 apic->sw_enabled = enabled;
228 if (enabled) {
229 static_key_slow_dec_deferred(&apic_sw_disabled);
230 recalculate_apic_map(apic->vcpu->kvm);
231 } else
232 static_key_slow_inc(&apic_sw_disabled.key);
233 }
234 }
235
236 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
237 {
238 apic_set_reg(apic, APIC_ID, id << 24);
239 recalculate_apic_map(apic->vcpu->kvm);
240 }
241
242 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
243 {
244 apic_set_reg(apic, APIC_LDR, id);
245 recalculate_apic_map(apic->vcpu->kvm);
246 }
247
248 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
249 {
250 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
251 }
252
253 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
254 {
255 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
256 }
257
258 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
259 {
260 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
261 }
262
263 static inline int apic_lvtt_period(struct kvm_lapic *apic)
264 {
265 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
266 }
267
268 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
269 {
270 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
271 }
272
273 static inline int apic_lvt_nmi_mode(u32 lvt_val)
274 {
275 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
276 }
277
278 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
279 {
280 struct kvm_lapic *apic = vcpu->arch.apic;
281 struct kvm_cpuid_entry2 *feat;
282 u32 v = APIC_VERSION;
283
284 if (!kvm_vcpu_has_lapic(vcpu))
285 return;
286
287 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
288 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
289 v |= APIC_LVR_DIRECTED_EOI;
290 apic_set_reg(apic, APIC_LVR, v);
291 }
292
293 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
294 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
295 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
296 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
297 LINT_MASK, LINT_MASK, /* LVT0-1 */
298 LVT_MASK /* LVTERR */
299 };
300
301 static int find_highest_vector(void *bitmap)
302 {
303 int vec;
304 u32 *reg;
305
306 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
307 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
308 reg = bitmap + REG_POS(vec);
309 if (*reg)
310 return fls(*reg) - 1 + vec;
311 }
312
313 return -1;
314 }
315
316 static u8 count_vectors(void *bitmap)
317 {
318 int vec;
319 u32 *reg;
320 u8 count = 0;
321
322 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
323 reg = bitmap + REG_POS(vec);
324 count += hweight32(*reg);
325 }
326
327 return count;
328 }
329
330 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
331 {
332 u32 i, pir_val;
333 struct kvm_lapic *apic = vcpu->arch.apic;
334
335 for (i = 0; i <= 7; i++) {
336 pir_val = xchg(&pir[i], 0);
337 if (pir_val)
338 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
339 }
340 }
341 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
342
343 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
344 {
345 apic_set_vector(vec, apic->regs + APIC_IRR);
346 /*
347 * irr_pending must be true if any interrupt is pending; set it after
348 * APIC_IRR to avoid race with apic_clear_irr
349 */
350 apic->irr_pending = true;
351 }
352
353 static inline int apic_search_irr(struct kvm_lapic *apic)
354 {
355 return find_highest_vector(apic->regs + APIC_IRR);
356 }
357
358 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
359 {
360 int result;
361
362 /*
363 * Note that irr_pending is just a hint. It will be always
364 * true with virtual interrupt delivery enabled.
365 */
366 if (!apic->irr_pending)
367 return -1;
368
369 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
370 result = apic_search_irr(apic);
371 ASSERT(result == -1 || result >= 16);
372
373 return result;
374 }
375
376 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
377 {
378 struct kvm_vcpu *vcpu;
379
380 vcpu = apic->vcpu;
381
382 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
383 /* try to update RVI */
384 apic_clear_vector(vec, apic->regs + APIC_IRR);
385 kvm_make_request(KVM_REQ_EVENT, vcpu);
386 } else {
387 apic->irr_pending = false;
388 apic_clear_vector(vec, apic->regs + APIC_IRR);
389 if (apic_search_irr(apic) != -1)
390 apic->irr_pending = true;
391 }
392 }
393
394 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
395 {
396 struct kvm_vcpu *vcpu;
397
398 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
399 return;
400
401 vcpu = apic->vcpu;
402
403 /*
404 * With APIC virtualization enabled, all caching is disabled
405 * because the processor can modify ISR under the hood. Instead
406 * just set SVI.
407 */
408 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
409 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
410 else {
411 ++apic->isr_count;
412 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
413 /*
414 * ISR (in service register) bit is set when injecting an interrupt.
415 * The highest vector is injected. Thus the latest bit set matches
416 * the highest bit in ISR.
417 */
418 apic->highest_isr_cache = vec;
419 }
420 }
421
422 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
423 {
424 int result;
425
426 /*
427 * Note that isr_count is always 1, and highest_isr_cache
428 * is always -1, with APIC virtualization enabled.
429 */
430 if (!apic->isr_count)
431 return -1;
432 if (likely(apic->highest_isr_cache != -1))
433 return apic->highest_isr_cache;
434
435 result = find_highest_vector(apic->regs + APIC_ISR);
436 ASSERT(result == -1 || result >= 16);
437
438 return result;
439 }
440
441 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
442 {
443 struct kvm_vcpu *vcpu;
444 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
445 return;
446
447 vcpu = apic->vcpu;
448
449 /*
450 * We do get here for APIC virtualization enabled if the guest
451 * uses the Hyper-V APIC enlightenment. In this case we may need
452 * to trigger a new interrupt delivery by writing the SVI field;
453 * on the other hand isr_count and highest_isr_cache are unused
454 * and must be left alone.
455 */
456 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
457 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
458 apic_find_highest_isr(apic));
459 else {
460 --apic->isr_count;
461 BUG_ON(apic->isr_count < 0);
462 apic->highest_isr_cache = -1;
463 }
464 }
465
466 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
467 {
468 int highest_irr;
469
470 /* This may race with setting of irr in __apic_accept_irq() and
471 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
472 * will cause vmexit immediately and the value will be recalculated
473 * on the next vmentry.
474 */
475 if (!kvm_vcpu_has_lapic(vcpu))
476 return 0;
477 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
478
479 return highest_irr;
480 }
481
482 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
483 int vector, int level, int trig_mode,
484 unsigned long *dest_map);
485
486 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
487 unsigned long *dest_map)
488 {
489 struct kvm_lapic *apic = vcpu->arch.apic;
490
491 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
492 irq->level, irq->trig_mode, dest_map);
493 }
494
495 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
496 {
497
498 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
499 sizeof(val));
500 }
501
502 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
503 {
504
505 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
506 sizeof(*val));
507 }
508
509 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
510 {
511 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
512 }
513
514 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
515 {
516 u8 val;
517 if (pv_eoi_get_user(vcpu, &val) < 0)
518 apic_debug("Can't read EOI MSR value: 0x%llx\n",
519 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
520 return val & 0x1;
521 }
522
523 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
524 {
525 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
526 apic_debug("Can't set EOI MSR value: 0x%llx\n",
527 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
528 return;
529 }
530 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
531 }
532
533 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
534 {
535 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
536 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
537 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
538 return;
539 }
540 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
541 }
542
543 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
544 {
545 struct kvm_lapic *apic = vcpu->arch.apic;
546 int i;
547
548 for (i = 0; i < 8; i++)
549 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
550 }
551
552 static void apic_update_ppr(struct kvm_lapic *apic)
553 {
554 u32 tpr, isrv, ppr, old_ppr;
555 int isr;
556
557 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
558 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
559 isr = apic_find_highest_isr(apic);
560 isrv = (isr != -1) ? isr : 0;
561
562 if ((tpr & 0xf0) >= (isrv & 0xf0))
563 ppr = tpr & 0xff;
564 else
565 ppr = isrv & 0xf0;
566
567 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
568 apic, ppr, isr, isrv);
569
570 if (old_ppr != ppr) {
571 apic_set_reg(apic, APIC_PROCPRI, ppr);
572 if (ppr < old_ppr)
573 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
574 }
575 }
576
577 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
578 {
579 apic_set_reg(apic, APIC_TASKPRI, tpr);
580 apic_update_ppr(apic);
581 }
582
583 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
584 {
585 return dest == (apic_x2apic_mode(apic) ?
586 X2APIC_BROADCAST : APIC_BROADCAST);
587 }
588
589 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
590 {
591 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
592 }
593
594 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
595 {
596 int result = 0;
597 u32 logical_id;
598
599 if (kvm_apic_broadcast(apic, mda))
600 return 1;
601
602 if (apic_x2apic_mode(apic)) {
603 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
604 return logical_id & mda;
605 }
606
607 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
608
609 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
610 case APIC_DFR_FLAT:
611 if (logical_id & mda)
612 result = 1;
613 break;
614 case APIC_DFR_CLUSTER:
615 if (((logical_id >> 4) == (mda >> 0x4))
616 && (logical_id & mda & 0xf))
617 result = 1;
618 break;
619 default:
620 apic_debug("Bad DFR vcpu %d: %08x\n",
621 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
622 break;
623 }
624
625 return result;
626 }
627
628 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
629 int short_hand, unsigned int dest, int dest_mode)
630 {
631 int result = 0;
632 struct kvm_lapic *target = vcpu->arch.apic;
633
634 apic_debug("target %p, source %p, dest 0x%x, "
635 "dest_mode 0x%x, short_hand 0x%x\n",
636 target, source, dest, dest_mode, short_hand);
637
638 ASSERT(target);
639 switch (short_hand) {
640 case APIC_DEST_NOSHORT:
641 if (dest_mode == 0)
642 /* Physical mode. */
643 result = kvm_apic_match_physical_addr(target, dest);
644 else
645 /* Logical mode. */
646 result = kvm_apic_match_logical_addr(target, dest);
647 break;
648 case APIC_DEST_SELF:
649 result = (target == source);
650 break;
651 case APIC_DEST_ALLINC:
652 result = 1;
653 break;
654 case APIC_DEST_ALLBUT:
655 result = (target != source);
656 break;
657 default:
658 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
659 short_hand);
660 break;
661 }
662
663 return result;
664 }
665
666 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
667 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
668 {
669 struct kvm_apic_map *map;
670 unsigned long bitmap = 1;
671 struct kvm_lapic **dst;
672 int i;
673 bool ret = false;
674
675 *r = -1;
676
677 if (irq->shorthand == APIC_DEST_SELF) {
678 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
679 return true;
680 }
681
682 if (irq->shorthand)
683 return false;
684
685 rcu_read_lock();
686 map = rcu_dereference(kvm->arch.apic_map);
687
688 if (!map)
689 goto out;
690
691 if (irq->dest_id == map->broadcast)
692 goto out;
693
694 ret = true;
695
696 if (irq->dest_mode == 0) { /* physical mode */
697 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
698 goto out;
699
700 dst = &map->phys_map[irq->dest_id];
701 } else {
702 u32 mda = irq->dest_id << (32 - map->ldr_bits);
703
704 dst = map->logical_map[apic_cluster_id(map, mda)];
705
706 bitmap = apic_logical_id(map, mda);
707
708 if (irq->delivery_mode == APIC_DM_LOWEST) {
709 int l = -1;
710 for_each_set_bit(i, &bitmap, 16) {
711 if (!dst[i])
712 continue;
713 if (l < 0)
714 l = i;
715 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
716 l = i;
717 }
718
719 bitmap = (l >= 0) ? 1 << l : 0;
720 }
721 }
722
723 for_each_set_bit(i, &bitmap, 16) {
724 if (!dst[i])
725 continue;
726 if (*r < 0)
727 *r = 0;
728 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
729 }
730 out:
731 rcu_read_unlock();
732 return ret;
733 }
734
735 /*
736 * Add a pending IRQ into lapic.
737 * Return 1 if successfully added and 0 if discarded.
738 */
739 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
740 int vector, int level, int trig_mode,
741 unsigned long *dest_map)
742 {
743 int result = 0;
744 struct kvm_vcpu *vcpu = apic->vcpu;
745
746 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
747 trig_mode, vector);
748 switch (delivery_mode) {
749 case APIC_DM_LOWEST:
750 vcpu->arch.apic_arb_prio++;
751 case APIC_DM_FIXED:
752 /* FIXME add logic for vcpu on reset */
753 if (unlikely(!apic_enabled(apic)))
754 break;
755
756 result = 1;
757
758 if (dest_map)
759 __set_bit(vcpu->vcpu_id, dest_map);
760
761 if (kvm_x86_ops->deliver_posted_interrupt)
762 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
763 else {
764 apic_set_irr(vector, apic);
765
766 kvm_make_request(KVM_REQ_EVENT, vcpu);
767 kvm_vcpu_kick(vcpu);
768 }
769 break;
770
771 case APIC_DM_REMRD:
772 result = 1;
773 vcpu->arch.pv.pv_unhalted = 1;
774 kvm_make_request(KVM_REQ_EVENT, vcpu);
775 kvm_vcpu_kick(vcpu);
776 break;
777
778 case APIC_DM_SMI:
779 apic_debug("Ignoring guest SMI\n");
780 break;
781
782 case APIC_DM_NMI:
783 result = 1;
784 kvm_inject_nmi(vcpu);
785 kvm_vcpu_kick(vcpu);
786 break;
787
788 case APIC_DM_INIT:
789 if (!trig_mode || level) {
790 result = 1;
791 /* assumes that there are only KVM_APIC_INIT/SIPI */
792 apic->pending_events = (1UL << KVM_APIC_INIT);
793 /* make sure pending_events is visible before sending
794 * the request */
795 smp_wmb();
796 kvm_make_request(KVM_REQ_EVENT, vcpu);
797 kvm_vcpu_kick(vcpu);
798 } else {
799 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
800 vcpu->vcpu_id);
801 }
802 break;
803
804 case APIC_DM_STARTUP:
805 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
806 vcpu->vcpu_id, vector);
807 result = 1;
808 apic->sipi_vector = vector;
809 /* make sure sipi_vector is visible for the receiver */
810 smp_wmb();
811 set_bit(KVM_APIC_SIPI, &apic->pending_events);
812 kvm_make_request(KVM_REQ_EVENT, vcpu);
813 kvm_vcpu_kick(vcpu);
814 break;
815
816 case APIC_DM_EXTINT:
817 /*
818 * Should only be called by kvm_apic_local_deliver() with LVT0,
819 * before NMI watchdog was enabled. Already handled by
820 * kvm_apic_accept_pic_intr().
821 */
822 break;
823
824 default:
825 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
826 delivery_mode);
827 break;
828 }
829 return result;
830 }
831
832 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
833 {
834 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
835 }
836
837 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
838 {
839 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
840 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
841 int trigger_mode;
842 if (apic_test_vector(vector, apic->regs + APIC_TMR))
843 trigger_mode = IOAPIC_LEVEL_TRIG;
844 else
845 trigger_mode = IOAPIC_EDGE_TRIG;
846 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
847 }
848 }
849
850 static int apic_set_eoi(struct kvm_lapic *apic)
851 {
852 int vector = apic_find_highest_isr(apic);
853
854 trace_kvm_eoi(apic, vector);
855
856 /*
857 * Not every write EOI will has corresponding ISR,
858 * one example is when Kernel check timer on setup_IO_APIC
859 */
860 if (vector == -1)
861 return vector;
862
863 apic_clear_isr(vector, apic);
864 apic_update_ppr(apic);
865
866 kvm_ioapic_send_eoi(apic, vector);
867 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
868 return vector;
869 }
870
871 /*
872 * this interface assumes a trap-like exit, which has already finished
873 * desired side effect including vISR and vPPR update.
874 */
875 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
876 {
877 struct kvm_lapic *apic = vcpu->arch.apic;
878
879 trace_kvm_eoi(apic, vector);
880
881 kvm_ioapic_send_eoi(apic, vector);
882 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
883 }
884 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
885
886 static void apic_send_ipi(struct kvm_lapic *apic)
887 {
888 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
889 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
890 struct kvm_lapic_irq irq;
891
892 irq.vector = icr_low & APIC_VECTOR_MASK;
893 irq.delivery_mode = icr_low & APIC_MODE_MASK;
894 irq.dest_mode = icr_low & APIC_DEST_MASK;
895 irq.level = icr_low & APIC_INT_ASSERT;
896 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
897 irq.shorthand = icr_low & APIC_SHORT_MASK;
898 if (apic_x2apic_mode(apic))
899 irq.dest_id = icr_high;
900 else
901 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
902
903 trace_kvm_apic_ipi(icr_low, irq.dest_id);
904
905 apic_debug("icr_high 0x%x, icr_low 0x%x, "
906 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
907 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
908 icr_high, icr_low, irq.shorthand, irq.dest_id,
909 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
910 irq.vector);
911
912 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
913 }
914
915 static u32 apic_get_tmcct(struct kvm_lapic *apic)
916 {
917 ktime_t remaining;
918 s64 ns;
919 u32 tmcct;
920
921 ASSERT(apic != NULL);
922
923 /* if initial count is 0, current count should also be 0 */
924 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
925 apic->lapic_timer.period == 0)
926 return 0;
927
928 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
929 if (ktime_to_ns(remaining) < 0)
930 remaining = ktime_set(0, 0);
931
932 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
933 tmcct = div64_u64(ns,
934 (APIC_BUS_CYCLE_NS * apic->divide_count));
935
936 return tmcct;
937 }
938
939 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
940 {
941 struct kvm_vcpu *vcpu = apic->vcpu;
942 struct kvm_run *run = vcpu->run;
943
944 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
945 run->tpr_access.rip = kvm_rip_read(vcpu);
946 run->tpr_access.is_write = write;
947 }
948
949 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
950 {
951 if (apic->vcpu->arch.tpr_access_reporting)
952 __report_tpr_access(apic, write);
953 }
954
955 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
956 {
957 u32 val = 0;
958
959 if (offset >= LAPIC_MMIO_LENGTH)
960 return 0;
961
962 switch (offset) {
963 case APIC_ID:
964 if (apic_x2apic_mode(apic))
965 val = kvm_apic_id(apic);
966 else
967 val = kvm_apic_id(apic) << 24;
968 break;
969 case APIC_ARBPRI:
970 apic_debug("Access APIC ARBPRI register which is for P6\n");
971 break;
972
973 case APIC_TMCCT: /* Timer CCR */
974 if (apic_lvtt_tscdeadline(apic))
975 return 0;
976
977 val = apic_get_tmcct(apic);
978 break;
979 case APIC_PROCPRI:
980 apic_update_ppr(apic);
981 val = kvm_apic_get_reg(apic, offset);
982 break;
983 case APIC_TASKPRI:
984 report_tpr_access(apic, false);
985 /* fall thru */
986 default:
987 val = kvm_apic_get_reg(apic, offset);
988 break;
989 }
990
991 return val;
992 }
993
994 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
995 {
996 return container_of(dev, struct kvm_lapic, dev);
997 }
998
999 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1000 void *data)
1001 {
1002 unsigned char alignment = offset & 0xf;
1003 u32 result;
1004 /* this bitmask has a bit cleared for each reserved register */
1005 static const u64 rmask = 0x43ff01ffffffe70cULL;
1006
1007 if ((alignment + len) > 4) {
1008 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1009 offset, len);
1010 return 1;
1011 }
1012
1013 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1014 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1015 offset);
1016 return 1;
1017 }
1018
1019 result = __apic_read(apic, offset & ~0xf);
1020
1021 trace_kvm_apic_read(offset, result);
1022
1023 switch (len) {
1024 case 1:
1025 case 2:
1026 case 4:
1027 memcpy(data, (char *)&result + alignment, len);
1028 break;
1029 default:
1030 printk(KERN_ERR "Local APIC read with len = %x, "
1031 "should be 1,2, or 4 instead\n", len);
1032 break;
1033 }
1034 return 0;
1035 }
1036
1037 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1038 {
1039 return kvm_apic_hw_enabled(apic) &&
1040 addr >= apic->base_address &&
1041 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1042 }
1043
1044 static int apic_mmio_read(struct kvm_io_device *this,
1045 gpa_t address, int len, void *data)
1046 {
1047 struct kvm_lapic *apic = to_lapic(this);
1048 u32 offset = address - apic->base_address;
1049
1050 if (!apic_mmio_in_range(apic, address))
1051 return -EOPNOTSUPP;
1052
1053 apic_reg_read(apic, offset, len, data);
1054
1055 return 0;
1056 }
1057
1058 static void update_divide_count(struct kvm_lapic *apic)
1059 {
1060 u32 tmp1, tmp2, tdcr;
1061
1062 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1063 tmp1 = tdcr & 0xf;
1064 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1065 apic->divide_count = 0x1 << (tmp2 & 0x7);
1066
1067 apic_debug("timer divide count is 0x%x\n",
1068 apic->divide_count);
1069 }
1070
1071 static void apic_timer_expired(struct kvm_lapic *apic)
1072 {
1073 struct kvm_vcpu *vcpu = apic->vcpu;
1074 wait_queue_head_t *q = &vcpu->wq;
1075
1076 /*
1077 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1078 * vcpu_enter_guest.
1079 */
1080 if (atomic_read(&apic->lapic_timer.pending))
1081 return;
1082
1083 atomic_inc(&apic->lapic_timer.pending);
1084 /* FIXME: this code should not know anything about vcpus */
1085 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1086
1087 if (waitqueue_active(q))
1088 wake_up_interruptible(q);
1089 }
1090
1091 static void start_apic_timer(struct kvm_lapic *apic)
1092 {
1093 ktime_t now;
1094 atomic_set(&apic->lapic_timer.pending, 0);
1095
1096 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1097 /* lapic timer in oneshot or periodic mode */
1098 now = apic->lapic_timer.timer.base->get_time();
1099 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1100 * APIC_BUS_CYCLE_NS * apic->divide_count;
1101
1102 if (!apic->lapic_timer.period)
1103 return;
1104 /*
1105 * Do not allow the guest to program periodic timers with small
1106 * interval, since the hrtimers are not throttled by the host
1107 * scheduler.
1108 */
1109 if (apic_lvtt_period(apic)) {
1110 s64 min_period = min_timer_period_us * 1000LL;
1111
1112 if (apic->lapic_timer.period < min_period) {
1113 pr_info_ratelimited(
1114 "kvm: vcpu %i: requested %lld ns "
1115 "lapic timer period limited to %lld ns\n",
1116 apic->vcpu->vcpu_id,
1117 apic->lapic_timer.period, min_period);
1118 apic->lapic_timer.period = min_period;
1119 }
1120 }
1121
1122 hrtimer_start(&apic->lapic_timer.timer,
1123 ktime_add_ns(now, apic->lapic_timer.period),
1124 HRTIMER_MODE_ABS);
1125
1126 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1127 PRIx64 ", "
1128 "timer initial count 0x%x, period %lldns, "
1129 "expire @ 0x%016" PRIx64 ".\n", __func__,
1130 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1131 kvm_apic_get_reg(apic, APIC_TMICT),
1132 apic->lapic_timer.period,
1133 ktime_to_ns(ktime_add_ns(now,
1134 apic->lapic_timer.period)));
1135 } else if (apic_lvtt_tscdeadline(apic)) {
1136 /* lapic timer in tsc deadline mode */
1137 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1138 u64 ns = 0;
1139 struct kvm_vcpu *vcpu = apic->vcpu;
1140 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1141 unsigned long flags;
1142
1143 if (unlikely(!tscdeadline || !this_tsc_khz))
1144 return;
1145
1146 local_irq_save(flags);
1147
1148 now = apic->lapic_timer.timer.base->get_time();
1149 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1150 if (likely(tscdeadline > guest_tsc)) {
1151 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1152 do_div(ns, this_tsc_khz);
1153 hrtimer_start(&apic->lapic_timer.timer,
1154 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1155 } else
1156 apic_timer_expired(apic);
1157
1158 local_irq_restore(flags);
1159 }
1160 }
1161
1162 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1163 {
1164 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1165
1166 if (apic_lvt_nmi_mode(lvt0_val)) {
1167 if (!nmi_wd_enabled) {
1168 apic_debug("Receive NMI setting on APIC_LVT0 "
1169 "for cpu %d\n", apic->vcpu->vcpu_id);
1170 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1171 }
1172 } else if (nmi_wd_enabled)
1173 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1174 }
1175
1176 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1177 {
1178 int ret = 0;
1179
1180 trace_kvm_apic_write(reg, val);
1181
1182 switch (reg) {
1183 case APIC_ID: /* Local APIC ID */
1184 if (!apic_x2apic_mode(apic))
1185 kvm_apic_set_id(apic, val >> 24);
1186 else
1187 ret = 1;
1188 break;
1189
1190 case APIC_TASKPRI:
1191 report_tpr_access(apic, true);
1192 apic_set_tpr(apic, val & 0xff);
1193 break;
1194
1195 case APIC_EOI:
1196 apic_set_eoi(apic);
1197 break;
1198
1199 case APIC_LDR:
1200 if (!apic_x2apic_mode(apic))
1201 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1202 else
1203 ret = 1;
1204 break;
1205
1206 case APIC_DFR:
1207 if (!apic_x2apic_mode(apic)) {
1208 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1209 recalculate_apic_map(apic->vcpu->kvm);
1210 } else
1211 ret = 1;
1212 break;
1213
1214 case APIC_SPIV: {
1215 u32 mask = 0x3ff;
1216 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1217 mask |= APIC_SPIV_DIRECTED_EOI;
1218 apic_set_spiv(apic, val & mask);
1219 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1220 int i;
1221 u32 lvt_val;
1222
1223 for (i = 0; i < APIC_LVT_NUM; i++) {
1224 lvt_val = kvm_apic_get_reg(apic,
1225 APIC_LVTT + 0x10 * i);
1226 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1227 lvt_val | APIC_LVT_MASKED);
1228 }
1229 atomic_set(&apic->lapic_timer.pending, 0);
1230
1231 }
1232 break;
1233 }
1234 case APIC_ICR:
1235 /* No delay here, so we always clear the pending bit */
1236 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1237 apic_send_ipi(apic);
1238 break;
1239
1240 case APIC_ICR2:
1241 if (!apic_x2apic_mode(apic))
1242 val &= 0xff000000;
1243 apic_set_reg(apic, APIC_ICR2, val);
1244 break;
1245
1246 case APIC_LVT0:
1247 apic_manage_nmi_watchdog(apic, val);
1248 case APIC_LVTTHMR:
1249 case APIC_LVTPC:
1250 case APIC_LVT1:
1251 case APIC_LVTERR:
1252 /* TODO: Check vector */
1253 if (!kvm_apic_sw_enabled(apic))
1254 val |= APIC_LVT_MASKED;
1255
1256 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1257 apic_set_reg(apic, reg, val);
1258
1259 break;
1260
1261 case APIC_LVTT: {
1262 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1263
1264 if (apic->lapic_timer.timer_mode != timer_mode) {
1265 apic->lapic_timer.timer_mode = timer_mode;
1266 hrtimer_cancel(&apic->lapic_timer.timer);
1267 }
1268
1269 if (!kvm_apic_sw_enabled(apic))
1270 val |= APIC_LVT_MASKED;
1271 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1272 apic_set_reg(apic, APIC_LVTT, val);
1273 break;
1274 }
1275
1276 case APIC_TMICT:
1277 if (apic_lvtt_tscdeadline(apic))
1278 break;
1279
1280 hrtimer_cancel(&apic->lapic_timer.timer);
1281 apic_set_reg(apic, APIC_TMICT, val);
1282 start_apic_timer(apic);
1283 break;
1284
1285 case APIC_TDCR:
1286 if (val & 4)
1287 apic_debug("KVM_WRITE:TDCR %x\n", val);
1288 apic_set_reg(apic, APIC_TDCR, val);
1289 update_divide_count(apic);
1290 break;
1291
1292 case APIC_ESR:
1293 if (apic_x2apic_mode(apic) && val != 0) {
1294 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1295 ret = 1;
1296 }
1297 break;
1298
1299 case APIC_SELF_IPI:
1300 if (apic_x2apic_mode(apic)) {
1301 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1302 } else
1303 ret = 1;
1304 break;
1305 default:
1306 ret = 1;
1307 break;
1308 }
1309 if (ret)
1310 apic_debug("Local APIC Write to read-only register %x\n", reg);
1311 return ret;
1312 }
1313
1314 static int apic_mmio_write(struct kvm_io_device *this,
1315 gpa_t address, int len, const void *data)
1316 {
1317 struct kvm_lapic *apic = to_lapic(this);
1318 unsigned int offset = address - apic->base_address;
1319 u32 val;
1320
1321 if (!apic_mmio_in_range(apic, address))
1322 return -EOPNOTSUPP;
1323
1324 /*
1325 * APIC register must be aligned on 128-bits boundary.
1326 * 32/64/128 bits registers must be accessed thru 32 bits.
1327 * Refer SDM 8.4.1
1328 */
1329 if (len != 4 || (offset & 0xf)) {
1330 /* Don't shout loud, $infamous_os would cause only noise. */
1331 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1332 return 0;
1333 }
1334
1335 val = *(u32*)data;
1336
1337 /* too common printing */
1338 if (offset != APIC_EOI)
1339 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1340 "0x%x\n", __func__, offset, len, val);
1341
1342 apic_reg_write(apic, offset & 0xff0, val);
1343
1344 return 0;
1345 }
1346
1347 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1348 {
1349 if (kvm_vcpu_has_lapic(vcpu))
1350 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1351 }
1352 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1353
1354 /* emulate APIC access in a trap manner */
1355 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1356 {
1357 u32 val = 0;
1358
1359 /* hw has done the conditional check and inst decode */
1360 offset &= 0xff0;
1361
1362 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1363
1364 /* TODO: optimize to just emulate side effect w/o one more write */
1365 apic_reg_write(vcpu->arch.apic, offset, val);
1366 }
1367 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1368
1369 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1370 {
1371 struct kvm_lapic *apic = vcpu->arch.apic;
1372
1373 if (!vcpu->arch.apic)
1374 return;
1375
1376 hrtimer_cancel(&apic->lapic_timer.timer);
1377
1378 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1379 static_key_slow_dec_deferred(&apic_hw_disabled);
1380
1381 if (!apic->sw_enabled)
1382 static_key_slow_dec_deferred(&apic_sw_disabled);
1383
1384 if (apic->regs)
1385 free_page((unsigned long)apic->regs);
1386
1387 kfree(apic);
1388 }
1389
1390 /*
1391 *----------------------------------------------------------------------
1392 * LAPIC interface
1393 *----------------------------------------------------------------------
1394 */
1395
1396 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1397 {
1398 struct kvm_lapic *apic = vcpu->arch.apic;
1399
1400 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1401 apic_lvtt_period(apic))
1402 return 0;
1403
1404 return apic->lapic_timer.tscdeadline;
1405 }
1406
1407 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1408 {
1409 struct kvm_lapic *apic = vcpu->arch.apic;
1410
1411 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1412 apic_lvtt_period(apic))
1413 return;
1414
1415 hrtimer_cancel(&apic->lapic_timer.timer);
1416 apic->lapic_timer.tscdeadline = data;
1417 start_apic_timer(apic);
1418 }
1419
1420 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1421 {
1422 struct kvm_lapic *apic = vcpu->arch.apic;
1423
1424 if (!kvm_vcpu_has_lapic(vcpu))
1425 return;
1426
1427 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1428 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1429 }
1430
1431 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1432 {
1433 u64 tpr;
1434
1435 if (!kvm_vcpu_has_lapic(vcpu))
1436 return 0;
1437
1438 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1439
1440 return (tpr & 0xf0) >> 4;
1441 }
1442
1443 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1444 {
1445 u64 old_value = vcpu->arch.apic_base;
1446 struct kvm_lapic *apic = vcpu->arch.apic;
1447
1448 if (!apic) {
1449 value |= MSR_IA32_APICBASE_BSP;
1450 vcpu->arch.apic_base = value;
1451 return;
1452 }
1453
1454 if (!kvm_vcpu_is_bsp(apic->vcpu))
1455 value &= ~MSR_IA32_APICBASE_BSP;
1456 vcpu->arch.apic_base = value;
1457
1458 /* update jump label if enable bit changes */
1459 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1460 if (value & MSR_IA32_APICBASE_ENABLE)
1461 static_key_slow_dec_deferred(&apic_hw_disabled);
1462 else
1463 static_key_slow_inc(&apic_hw_disabled.key);
1464 recalculate_apic_map(vcpu->kvm);
1465 }
1466
1467 if ((old_value ^ value) & X2APIC_ENABLE) {
1468 if (value & X2APIC_ENABLE) {
1469 u32 id = kvm_apic_id(apic);
1470 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1471 kvm_apic_set_ldr(apic, ldr);
1472 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1473 } else
1474 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1475 }
1476
1477 apic->base_address = apic->vcpu->arch.apic_base &
1478 MSR_IA32_APICBASE_BASE;
1479
1480 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1481 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1482 pr_warn_once("APIC base relocation is unsupported by KVM");
1483
1484 /* with FSB delivery interrupt, we can restart APIC functionality */
1485 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1486 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1487
1488 }
1489
1490 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1491 {
1492 struct kvm_lapic *apic;
1493 int i;
1494
1495 apic_debug("%s\n", __func__);
1496
1497 ASSERT(vcpu);
1498 apic = vcpu->arch.apic;
1499 ASSERT(apic != NULL);
1500
1501 /* Stop the timer in case it's a reset to an active apic */
1502 hrtimer_cancel(&apic->lapic_timer.timer);
1503
1504 kvm_apic_set_id(apic, vcpu->vcpu_id);
1505 kvm_apic_set_version(apic->vcpu);
1506
1507 for (i = 0; i < APIC_LVT_NUM; i++)
1508 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1509 apic->lapic_timer.timer_mode = 0;
1510 apic_set_reg(apic, APIC_LVT0,
1511 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1512
1513 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1514 apic_set_spiv(apic, 0xff);
1515 apic_set_reg(apic, APIC_TASKPRI, 0);
1516 kvm_apic_set_ldr(apic, 0);
1517 apic_set_reg(apic, APIC_ESR, 0);
1518 apic_set_reg(apic, APIC_ICR, 0);
1519 apic_set_reg(apic, APIC_ICR2, 0);
1520 apic_set_reg(apic, APIC_TDCR, 0);
1521 apic_set_reg(apic, APIC_TMICT, 0);
1522 for (i = 0; i < 8; i++) {
1523 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1524 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1525 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1526 }
1527 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1528 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1529 apic->highest_isr_cache = -1;
1530 update_divide_count(apic);
1531 atomic_set(&apic->lapic_timer.pending, 0);
1532 if (kvm_vcpu_is_bsp(vcpu))
1533 kvm_lapic_set_base(vcpu,
1534 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1535 vcpu->arch.pv_eoi.msr_val = 0;
1536 apic_update_ppr(apic);
1537
1538 vcpu->arch.apic_arb_prio = 0;
1539 vcpu->arch.apic_attention = 0;
1540
1541 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1542 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1543 vcpu, kvm_apic_id(apic),
1544 vcpu->arch.apic_base, apic->base_address);
1545 }
1546
1547 /*
1548 *----------------------------------------------------------------------
1549 * timer interface
1550 *----------------------------------------------------------------------
1551 */
1552
1553 static bool lapic_is_periodic(struct kvm_lapic *apic)
1554 {
1555 return apic_lvtt_period(apic);
1556 }
1557
1558 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1559 {
1560 struct kvm_lapic *apic = vcpu->arch.apic;
1561
1562 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1563 apic_lvt_enabled(apic, APIC_LVTT))
1564 return atomic_read(&apic->lapic_timer.pending);
1565
1566 return 0;
1567 }
1568
1569 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1570 {
1571 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1572 int vector, mode, trig_mode;
1573
1574 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1575 vector = reg & APIC_VECTOR_MASK;
1576 mode = reg & APIC_MODE_MASK;
1577 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1578 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1579 NULL);
1580 }
1581 return 0;
1582 }
1583
1584 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1585 {
1586 struct kvm_lapic *apic = vcpu->arch.apic;
1587
1588 if (apic)
1589 kvm_apic_local_deliver(apic, APIC_LVT0);
1590 }
1591
1592 static const struct kvm_io_device_ops apic_mmio_ops = {
1593 .read = apic_mmio_read,
1594 .write = apic_mmio_write,
1595 };
1596
1597 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1598 {
1599 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1600 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1601
1602 apic_timer_expired(apic);
1603
1604 if (lapic_is_periodic(apic)) {
1605 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1606 return HRTIMER_RESTART;
1607 } else
1608 return HRTIMER_NORESTART;
1609 }
1610
1611 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1612 {
1613 struct kvm_lapic *apic;
1614
1615 ASSERT(vcpu != NULL);
1616 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1617
1618 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1619 if (!apic)
1620 goto nomem;
1621
1622 vcpu->arch.apic = apic;
1623
1624 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1625 if (!apic->regs) {
1626 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1627 vcpu->vcpu_id);
1628 goto nomem_free_apic;
1629 }
1630 apic->vcpu = vcpu;
1631
1632 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1633 HRTIMER_MODE_ABS);
1634 apic->lapic_timer.timer.function = apic_timer_fn;
1635
1636 /*
1637 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1638 * thinking that APIC satet has changed.
1639 */
1640 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1641 kvm_lapic_set_base(vcpu,
1642 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1643
1644 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1645 kvm_lapic_reset(vcpu);
1646 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1647
1648 return 0;
1649 nomem_free_apic:
1650 kfree(apic);
1651 nomem:
1652 return -ENOMEM;
1653 }
1654
1655 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1656 {
1657 struct kvm_lapic *apic = vcpu->arch.apic;
1658 int highest_irr;
1659
1660 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1661 return -1;
1662
1663 apic_update_ppr(apic);
1664 highest_irr = apic_find_highest_irr(apic);
1665 if ((highest_irr == -1) ||
1666 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1667 return -1;
1668 return highest_irr;
1669 }
1670
1671 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1672 {
1673 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1674 int r = 0;
1675
1676 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1677 r = 1;
1678 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1679 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1680 r = 1;
1681 return r;
1682 }
1683
1684 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1685 {
1686 struct kvm_lapic *apic = vcpu->arch.apic;
1687
1688 if (!kvm_vcpu_has_lapic(vcpu))
1689 return;
1690
1691 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1692 kvm_apic_local_deliver(apic, APIC_LVTT);
1693 if (apic_lvtt_tscdeadline(apic))
1694 apic->lapic_timer.tscdeadline = 0;
1695 atomic_set(&apic->lapic_timer.pending, 0);
1696 }
1697 }
1698
1699 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1700 {
1701 int vector = kvm_apic_has_interrupt(vcpu);
1702 struct kvm_lapic *apic = vcpu->arch.apic;
1703
1704 if (vector == -1)
1705 return -1;
1706
1707 /*
1708 * We get here even with APIC virtualization enabled, if doing
1709 * nested virtualization and L1 runs with the "acknowledge interrupt
1710 * on exit" mode. Then we cannot inject the interrupt via RVI,
1711 * because the process would deliver it through the IDT.
1712 */
1713
1714 apic_set_isr(vector, apic);
1715 apic_update_ppr(apic);
1716 apic_clear_irr(vector, apic);
1717 return vector;
1718 }
1719
1720 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1721 struct kvm_lapic_state *s)
1722 {
1723 struct kvm_lapic *apic = vcpu->arch.apic;
1724
1725 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1726 /* set SPIV separately to get count of SW disabled APICs right */
1727 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1728 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1729 /* call kvm_apic_set_id() to put apic into apic_map */
1730 kvm_apic_set_id(apic, kvm_apic_id(apic));
1731 kvm_apic_set_version(vcpu);
1732
1733 apic_update_ppr(apic);
1734 hrtimer_cancel(&apic->lapic_timer.timer);
1735 update_divide_count(apic);
1736 start_apic_timer(apic);
1737 apic->irr_pending = true;
1738 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1739 1 : count_vectors(apic->regs + APIC_ISR);
1740 apic->highest_isr_cache = -1;
1741 if (kvm_x86_ops->hwapic_irr_update)
1742 kvm_x86_ops->hwapic_irr_update(vcpu,
1743 apic_find_highest_irr(apic));
1744 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1745 kvm_make_request(KVM_REQ_EVENT, vcpu);
1746 kvm_rtc_eoi_tracking_restore_one(vcpu);
1747 }
1748
1749 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1750 {
1751 struct hrtimer *timer;
1752
1753 if (!kvm_vcpu_has_lapic(vcpu))
1754 return;
1755
1756 timer = &vcpu->arch.apic->lapic_timer.timer;
1757 if (hrtimer_cancel(timer))
1758 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1759 }
1760
1761 /*
1762 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1763 *
1764 * Detect whether guest triggered PV EOI since the
1765 * last entry. If yes, set EOI on guests's behalf.
1766 * Clear PV EOI in guest memory in any case.
1767 */
1768 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1769 struct kvm_lapic *apic)
1770 {
1771 bool pending;
1772 int vector;
1773 /*
1774 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1775 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1776 *
1777 * KVM_APIC_PV_EOI_PENDING is unset:
1778 * -> host disabled PV EOI.
1779 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1780 * -> host enabled PV EOI, guest did not execute EOI yet.
1781 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1782 * -> host enabled PV EOI, guest executed EOI.
1783 */
1784 BUG_ON(!pv_eoi_enabled(vcpu));
1785 pending = pv_eoi_get_pending(vcpu);
1786 /*
1787 * Clear pending bit in any case: it will be set again on vmentry.
1788 * While this might not be ideal from performance point of view,
1789 * this makes sure pv eoi is only enabled when we know it's safe.
1790 */
1791 pv_eoi_clr_pending(vcpu);
1792 if (pending)
1793 return;
1794 vector = apic_set_eoi(apic);
1795 trace_kvm_pv_eoi(apic, vector);
1796 }
1797
1798 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1799 {
1800 u32 data;
1801
1802 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1803 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1804
1805 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1806 return;
1807
1808 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1809 sizeof(u32));
1810
1811 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1812 }
1813
1814 /*
1815 * apic_sync_pv_eoi_to_guest - called before vmentry
1816 *
1817 * Detect whether it's safe to enable PV EOI and
1818 * if yes do so.
1819 */
1820 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1821 struct kvm_lapic *apic)
1822 {
1823 if (!pv_eoi_enabled(vcpu) ||
1824 /* IRR set or many bits in ISR: could be nested. */
1825 apic->irr_pending ||
1826 /* Cache not set: could be safe but we don't bother. */
1827 apic->highest_isr_cache == -1 ||
1828 /* Need EOI to update ioapic. */
1829 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1830 /*
1831 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1832 * so we need not do anything here.
1833 */
1834 return;
1835 }
1836
1837 pv_eoi_set_pending(apic->vcpu);
1838 }
1839
1840 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1841 {
1842 u32 data, tpr;
1843 int max_irr, max_isr;
1844 struct kvm_lapic *apic = vcpu->arch.apic;
1845
1846 apic_sync_pv_eoi_to_guest(vcpu, apic);
1847
1848 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1849 return;
1850
1851 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1852 max_irr = apic_find_highest_irr(apic);
1853 if (max_irr < 0)
1854 max_irr = 0;
1855 max_isr = apic_find_highest_isr(apic);
1856 if (max_isr < 0)
1857 max_isr = 0;
1858 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1859
1860 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1861 sizeof(u32));
1862 }
1863
1864 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1865 {
1866 if (vapic_addr) {
1867 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1868 &vcpu->arch.apic->vapic_cache,
1869 vapic_addr, sizeof(u32)))
1870 return -EINVAL;
1871 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1872 } else {
1873 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1874 }
1875
1876 vcpu->arch.apic->vapic_addr = vapic_addr;
1877 return 0;
1878 }
1879
1880 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1881 {
1882 struct kvm_lapic *apic = vcpu->arch.apic;
1883 u32 reg = (msr - APIC_BASE_MSR) << 4;
1884
1885 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1886 return 1;
1887
1888 if (reg == APIC_ICR2)
1889 return 1;
1890
1891 /* if this is ICR write vector before command */
1892 if (reg == APIC_ICR)
1893 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1894 return apic_reg_write(apic, reg, (u32)data);
1895 }
1896
1897 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1898 {
1899 struct kvm_lapic *apic = vcpu->arch.apic;
1900 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1901
1902 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1903 return 1;
1904
1905 if (reg == APIC_DFR || reg == APIC_ICR2) {
1906 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1907 reg);
1908 return 1;
1909 }
1910
1911 if (apic_reg_read(apic, reg, 4, &low))
1912 return 1;
1913 if (reg == APIC_ICR)
1914 apic_reg_read(apic, APIC_ICR2, 4, &high);
1915
1916 *data = (((u64)high) << 32) | low;
1917
1918 return 0;
1919 }
1920
1921 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1922 {
1923 struct kvm_lapic *apic = vcpu->arch.apic;
1924
1925 if (!kvm_vcpu_has_lapic(vcpu))
1926 return 1;
1927
1928 /* if this is ICR write vector before command */
1929 if (reg == APIC_ICR)
1930 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1931 return apic_reg_write(apic, reg, (u32)data);
1932 }
1933
1934 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1935 {
1936 struct kvm_lapic *apic = vcpu->arch.apic;
1937 u32 low, high = 0;
1938
1939 if (!kvm_vcpu_has_lapic(vcpu))
1940 return 1;
1941
1942 if (apic_reg_read(apic, reg, 4, &low))
1943 return 1;
1944 if (reg == APIC_ICR)
1945 apic_reg_read(apic, APIC_ICR2, 4, &high);
1946
1947 *data = (((u64)high) << 32) | low;
1948
1949 return 0;
1950 }
1951
1952 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1953 {
1954 u64 addr = data & ~KVM_MSR_ENABLED;
1955 if (!IS_ALIGNED(addr, 4))
1956 return 1;
1957
1958 vcpu->arch.pv_eoi.msr_val = data;
1959 if (!pv_eoi_enabled(vcpu))
1960 return 0;
1961 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1962 addr, sizeof(u8));
1963 }
1964
1965 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1966 {
1967 struct kvm_lapic *apic = vcpu->arch.apic;
1968 u8 sipi_vector;
1969 unsigned long pe;
1970
1971 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1972 return;
1973
1974 pe = xchg(&apic->pending_events, 0);
1975
1976 if (test_bit(KVM_APIC_INIT, &pe)) {
1977 kvm_lapic_reset(vcpu);
1978 kvm_vcpu_reset(vcpu);
1979 if (kvm_vcpu_is_bsp(apic->vcpu))
1980 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1981 else
1982 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1983 }
1984 if (test_bit(KVM_APIC_SIPI, &pe) &&
1985 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1986 /* evaluate pending_events before reading the vector */
1987 smp_rmb();
1988 sipi_vector = apic->sipi_vector;
1989 apic_debug("vcpu %d received sipi with vector # %x\n",
1990 vcpu->vcpu_id, sipi_vector);
1991 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1992 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1993 }
1994 }
1995
1996 void kvm_lapic_init(void)
1997 {
1998 /* do not patch jump label more than once per second */
1999 jump_label_rate_limit(&apic_hw_disabled, HZ);
2000 jump_label_rate_limit(&apic_sw_disabled, HZ);
2001 }
Linux kernel - Deliverables
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