2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id
[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
65 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
67 static bool __read_mostly enable_vpid
= 1;
68 module_param_named(vpid
, enable_vpid
, bool, 0444);
70 static bool __read_mostly flexpriority_enabled
= 1;
71 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
73 static bool __read_mostly enable_ept
= 1;
74 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
76 static bool __read_mostly enable_unrestricted_guest
= 1;
77 module_param_named(unrestricted_guest
,
78 enable_unrestricted_guest
, bool, S_IRUGO
);
80 static bool __read_mostly enable_ept_ad_bits
= 1;
81 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
83 static bool __read_mostly emulate_invalid_guest_state
= true;
84 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
86 static bool __read_mostly vmm_exclusive
= 1;
87 module_param(vmm_exclusive
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
111 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
112 #define KVM_VM_CR0_ALWAYS_ON \
113 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
114 #define KVM_CR4_GUEST_OWNED_BITS \
115 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
116 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
118 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
119 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
121 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
123 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
126 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
127 * ple_gap: upper bound on the amount of time between two successive
128 * executions of PAUSE in a loop. Also indicate if ple enabled.
129 * According to test, this time is usually smaller than 128 cycles.
130 * ple_window: upper bound on the amount of time a guest is allowed to execute
131 * in a PAUSE loop. Tests indicate that most spinlocks are held for
132 * less than 2^12 cycles
133 * Time is measured based on a counter that runs at the same rate as the TSC,
134 * refer SDM volume 3b section 21.6.13 & 22.1.3.
136 #define KVM_VMX_DEFAULT_PLE_GAP 128
137 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
139 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
141 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
143 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
144 module_param(ple_gap
, int, S_IRUGO
);
146 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
147 module_param(ple_window
, int, S_IRUGO
);
149 /* Default doubles per-vcpu window every exit. */
150 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
151 module_param(ple_window_grow
, int, S_IRUGO
);
153 /* Default resets per-vcpu window every exit to ple_window. */
154 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
155 module_param(ple_window_shrink
, int, S_IRUGO
);
157 /* Default is to compute the maximum so we can never overflow. */
158 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
159 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
160 module_param(ple_window_max
, int, S_IRUGO
);
162 extern const ulong vmx_return
;
164 #define NR_AUTOLOAD_MSRS 8
165 #define VMCS02_POOL_SIZE 1
174 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
175 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
176 * loaded on this CPU (so we can clear them if the CPU goes down).
182 struct list_head loaded_vmcss_on_cpu_link
;
185 struct shared_msr_entry
{
192 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
193 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
194 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
195 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
196 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
197 * More than one of these structures may exist, if L1 runs multiple L2 guests.
198 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
199 * underlying hardware which will be used to run L2.
200 * This structure is packed to ensure that its layout is identical across
201 * machines (necessary for live migration).
202 * If there are changes in this struct, VMCS12_REVISION must be changed.
204 typedef u64 natural_width
;
205 struct __packed vmcs12
{
206 /* According to the Intel spec, a VMCS region must start with the
207 * following two fields. Then follow implementation-specific data.
212 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
213 u32 padding
[7]; /* room for future expansion */
218 u64 vm_exit_msr_store_addr
;
219 u64 vm_exit_msr_load_addr
;
220 u64 vm_entry_msr_load_addr
;
222 u64 virtual_apic_page_addr
;
223 u64 apic_access_addr
;
224 u64 posted_intr_desc_addr
;
226 u64 eoi_exit_bitmap0
;
227 u64 eoi_exit_bitmap1
;
228 u64 eoi_exit_bitmap2
;
229 u64 eoi_exit_bitmap3
;
231 u64 guest_physical_address
;
232 u64 vmcs_link_pointer
;
233 u64 guest_ia32_debugctl
;
236 u64 guest_ia32_perf_global_ctrl
;
244 u64 host_ia32_perf_global_ctrl
;
245 u64 padding64
[8]; /* room for future expansion */
247 * To allow migration of L1 (complete with its L2 guests) between
248 * machines of different natural widths (32 or 64 bit), we cannot have
249 * unsigned long fields with no explict size. We use u64 (aliased
250 * natural_width) instead. Luckily, x86 is little-endian.
252 natural_width cr0_guest_host_mask
;
253 natural_width cr4_guest_host_mask
;
254 natural_width cr0_read_shadow
;
255 natural_width cr4_read_shadow
;
256 natural_width cr3_target_value0
;
257 natural_width cr3_target_value1
;
258 natural_width cr3_target_value2
;
259 natural_width cr3_target_value3
;
260 natural_width exit_qualification
;
261 natural_width guest_linear_address
;
262 natural_width guest_cr0
;
263 natural_width guest_cr3
;
264 natural_width guest_cr4
;
265 natural_width guest_es_base
;
266 natural_width guest_cs_base
;
267 natural_width guest_ss_base
;
268 natural_width guest_ds_base
;
269 natural_width guest_fs_base
;
270 natural_width guest_gs_base
;
271 natural_width guest_ldtr_base
;
272 natural_width guest_tr_base
;
273 natural_width guest_gdtr_base
;
274 natural_width guest_idtr_base
;
275 natural_width guest_dr7
;
276 natural_width guest_rsp
;
277 natural_width guest_rip
;
278 natural_width guest_rflags
;
279 natural_width guest_pending_dbg_exceptions
;
280 natural_width guest_sysenter_esp
;
281 natural_width guest_sysenter_eip
;
282 natural_width host_cr0
;
283 natural_width host_cr3
;
284 natural_width host_cr4
;
285 natural_width host_fs_base
;
286 natural_width host_gs_base
;
287 natural_width host_tr_base
;
288 natural_width host_gdtr_base
;
289 natural_width host_idtr_base
;
290 natural_width host_ia32_sysenter_esp
;
291 natural_width host_ia32_sysenter_eip
;
292 natural_width host_rsp
;
293 natural_width host_rip
;
294 natural_width paddingl
[8]; /* room for future expansion */
295 u32 pin_based_vm_exec_control
;
296 u32 cpu_based_vm_exec_control
;
297 u32 exception_bitmap
;
298 u32 page_fault_error_code_mask
;
299 u32 page_fault_error_code_match
;
300 u32 cr3_target_count
;
301 u32 vm_exit_controls
;
302 u32 vm_exit_msr_store_count
;
303 u32 vm_exit_msr_load_count
;
304 u32 vm_entry_controls
;
305 u32 vm_entry_msr_load_count
;
306 u32 vm_entry_intr_info_field
;
307 u32 vm_entry_exception_error_code
;
308 u32 vm_entry_instruction_len
;
310 u32 secondary_vm_exec_control
;
311 u32 vm_instruction_error
;
313 u32 vm_exit_intr_info
;
314 u32 vm_exit_intr_error_code
;
315 u32 idt_vectoring_info_field
;
316 u32 idt_vectoring_error_code
;
317 u32 vm_exit_instruction_len
;
318 u32 vmx_instruction_info
;
325 u32 guest_ldtr_limit
;
327 u32 guest_gdtr_limit
;
328 u32 guest_idtr_limit
;
329 u32 guest_es_ar_bytes
;
330 u32 guest_cs_ar_bytes
;
331 u32 guest_ss_ar_bytes
;
332 u32 guest_ds_ar_bytes
;
333 u32 guest_fs_ar_bytes
;
334 u32 guest_gs_ar_bytes
;
335 u32 guest_ldtr_ar_bytes
;
336 u32 guest_tr_ar_bytes
;
337 u32 guest_interruptibility_info
;
338 u32 guest_activity_state
;
339 u32 guest_sysenter_cs
;
340 u32 host_ia32_sysenter_cs
;
341 u32 vmx_preemption_timer_value
;
342 u32 padding32
[7]; /* room for future expansion */
343 u16 virtual_processor_id
;
345 u16 guest_es_selector
;
346 u16 guest_cs_selector
;
347 u16 guest_ss_selector
;
348 u16 guest_ds_selector
;
349 u16 guest_fs_selector
;
350 u16 guest_gs_selector
;
351 u16 guest_ldtr_selector
;
352 u16 guest_tr_selector
;
353 u16 guest_intr_status
;
354 u16 host_es_selector
;
355 u16 host_cs_selector
;
356 u16 host_ss_selector
;
357 u16 host_ds_selector
;
358 u16 host_fs_selector
;
359 u16 host_gs_selector
;
360 u16 host_tr_selector
;
364 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
365 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
366 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
368 #define VMCS12_REVISION 0x11e57ed0
371 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
372 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
373 * current implementation, 4K are reserved to avoid future complications.
375 #define VMCS12_SIZE 0x1000
377 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
379 struct list_head list
;
381 struct loaded_vmcs vmcs02
;
385 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
386 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
389 /* Has the level1 guest done vmxon? */
393 /* The guest-physical address of the current VMCS L1 keeps for L2 */
395 /* The host-usable pointer to the above */
396 struct page
*current_vmcs12_page
;
397 struct vmcs12
*current_vmcs12
;
398 struct vmcs
*current_shadow_vmcs
;
400 * Indicates if the shadow vmcs must be updated with the
401 * data hold by vmcs12
403 bool sync_shadow_vmcs
;
405 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
406 struct list_head vmcs02_pool
;
408 u64 vmcs01_tsc_offset
;
409 /* L2 must run next, and mustn't decide to exit to L1. */
410 bool nested_run_pending
;
412 * Guest pages referred to in vmcs02 with host-physical pointers, so
413 * we must keep them pinned while L2 runs.
415 struct page
*apic_access_page
;
416 struct page
*virtual_apic_page
;
417 struct page
*pi_desc_page
;
418 struct pi_desc
*pi_desc
;
421 u64 msr_ia32_feature_control
;
423 struct hrtimer preemption_timer
;
424 bool preemption_timer_expired
;
426 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
429 u32 nested_vmx_procbased_ctls_low
;
430 u32 nested_vmx_procbased_ctls_high
;
431 u32 nested_vmx_true_procbased_ctls_low
;
432 u32 nested_vmx_secondary_ctls_low
;
433 u32 nested_vmx_secondary_ctls_high
;
434 u32 nested_vmx_pinbased_ctls_low
;
435 u32 nested_vmx_pinbased_ctls_high
;
436 u32 nested_vmx_exit_ctls_low
;
437 u32 nested_vmx_exit_ctls_high
;
438 u32 nested_vmx_true_exit_ctls_low
;
439 u32 nested_vmx_entry_ctls_low
;
440 u32 nested_vmx_entry_ctls_high
;
441 u32 nested_vmx_true_entry_ctls_low
;
442 u32 nested_vmx_misc_low
;
443 u32 nested_vmx_misc_high
;
444 u32 nested_vmx_ept_caps
;
447 #define POSTED_INTR_ON 0
448 #define POSTED_INTR_SN 1
450 /* Posted-Interrupt Descriptor */
452 u32 pir
[8]; /* Posted interrupt requested */
455 /* bit 256 - Outstanding Notification */
457 /* bit 257 - Suppress Notification */
459 /* bit 271:258 - Reserved */
461 /* bit 279:272 - Notification Vector */
463 /* bit 287:280 - Reserved */
465 /* bit 319:288 - Notification Destination */
473 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
475 return test_and_set_bit(POSTED_INTR_ON
,
476 (unsigned long *)&pi_desc
->control
);
479 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
481 return test_and_clear_bit(POSTED_INTR_ON
,
482 (unsigned long *)&pi_desc
->control
);
485 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
487 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
490 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
492 return clear_bit(POSTED_INTR_SN
,
493 (unsigned long *)&pi_desc
->control
);
496 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
498 return set_bit(POSTED_INTR_SN
,
499 (unsigned long *)&pi_desc
->control
);
502 static inline int pi_test_on(struct pi_desc
*pi_desc
)
504 return test_bit(POSTED_INTR_ON
,
505 (unsigned long *)&pi_desc
->control
);
508 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
510 return test_bit(POSTED_INTR_SN
,
511 (unsigned long *)&pi_desc
->control
);
515 struct kvm_vcpu vcpu
;
516 unsigned long host_rsp
;
518 bool nmi_known_unmasked
;
520 u32 idt_vectoring_info
;
522 struct shared_msr_entry
*guest_msrs
;
525 unsigned long host_idt_base
;
527 u64 msr_host_kernel_gs_base
;
528 u64 msr_guest_kernel_gs_base
;
530 u32 vm_entry_controls_shadow
;
531 u32 vm_exit_controls_shadow
;
533 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
534 * non-nested (L1) guest, it always points to vmcs01. For a nested
535 * guest (L2), it points to a different VMCS.
537 struct loaded_vmcs vmcs01
;
538 struct loaded_vmcs
*loaded_vmcs
;
539 bool __launched
; /* temporary, used in vmx_vcpu_run */
540 struct msr_autoload
{
542 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
543 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
547 u16 fs_sel
, gs_sel
, ldt_sel
;
551 int gs_ldt_reload_needed
;
552 int fs_reload_needed
;
553 u64 msr_host_bndcfgs
;
554 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
559 struct kvm_segment segs
[8];
562 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
563 struct kvm_save_segment
{
571 bool emulation_required
;
573 /* Support for vnmi-less CPUs */
574 int soft_vnmi_blocked
;
576 s64 vnmi_blocked_time
;
579 /* Posted interrupt descriptor */
580 struct pi_desc pi_desc
;
582 /* Support for a guest hypervisor (nested VMX) */
583 struct nested_vmx nested
;
585 /* Dynamic PLE window. */
587 bool ple_window_dirty
;
589 /* Support for PML */
590 #define PML_ENTITY_NUM 512
594 enum segment_cache_field
{
603 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
605 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
608 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
610 return &(to_vmx(vcpu
)->pi_desc
);
613 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
614 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
615 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
616 [number##_HIGH] = VMCS12_OFFSET(name)+4
619 static unsigned long shadow_read_only_fields
[] = {
621 * We do NOT shadow fields that are modified when L0
622 * traps and emulates any vmx instruction (e.g. VMPTRLD,
623 * VMXON...) executed by L1.
624 * For example, VM_INSTRUCTION_ERROR is read
625 * by L1 if a vmx instruction fails (part of the error path).
626 * Note the code assumes this logic. If for some reason
627 * we start shadowing these fields then we need to
628 * force a shadow sync when L0 emulates vmx instructions
629 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
630 * by nested_vmx_failValid)
634 VM_EXIT_INSTRUCTION_LEN
,
635 IDT_VECTORING_INFO_FIELD
,
636 IDT_VECTORING_ERROR_CODE
,
637 VM_EXIT_INTR_ERROR_CODE
,
639 GUEST_LINEAR_ADDRESS
,
640 GUEST_PHYSICAL_ADDRESS
642 static int max_shadow_read_only_fields
=
643 ARRAY_SIZE(shadow_read_only_fields
);
645 static unsigned long shadow_read_write_fields
[] = {
652 GUEST_INTERRUPTIBILITY_INFO
,
665 CPU_BASED_VM_EXEC_CONTROL
,
666 VM_ENTRY_EXCEPTION_ERROR_CODE
,
667 VM_ENTRY_INTR_INFO_FIELD
,
668 VM_ENTRY_INSTRUCTION_LEN
,
669 VM_ENTRY_EXCEPTION_ERROR_CODE
,
675 static int max_shadow_read_write_fields
=
676 ARRAY_SIZE(shadow_read_write_fields
);
678 static const unsigned short vmcs_field_to_offset_table
[] = {
679 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
680 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
681 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
682 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
683 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
684 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
685 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
686 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
687 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
688 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
689 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
690 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
691 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
692 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
693 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
694 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
695 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
696 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
697 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
698 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
699 FIELD64(MSR_BITMAP
, msr_bitmap
),
700 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
701 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
702 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
703 FIELD64(TSC_OFFSET
, tsc_offset
),
704 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
705 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
706 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
707 FIELD64(EPT_POINTER
, ept_pointer
),
708 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
709 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
710 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
711 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
712 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
713 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
714 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
715 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
716 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
717 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
718 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
719 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
720 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
721 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
722 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
723 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
724 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
725 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
726 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
727 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
728 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
729 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
730 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
731 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
732 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
733 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
734 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
735 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
736 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
737 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
738 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
739 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
740 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
741 FIELD(TPR_THRESHOLD
, tpr_threshold
),
742 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
743 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
744 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
745 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
746 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
747 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
748 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
749 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
750 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
751 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
752 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
753 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
754 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
755 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
756 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
757 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
758 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
759 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
760 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
761 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
762 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
763 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
764 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
765 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
766 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
767 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
768 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
769 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
770 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
771 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
772 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
773 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
774 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
775 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
776 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
777 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
778 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
779 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
780 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
781 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
782 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
783 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
784 FIELD(GUEST_CR0
, guest_cr0
),
785 FIELD(GUEST_CR3
, guest_cr3
),
786 FIELD(GUEST_CR4
, guest_cr4
),
787 FIELD(GUEST_ES_BASE
, guest_es_base
),
788 FIELD(GUEST_CS_BASE
, guest_cs_base
),
789 FIELD(GUEST_SS_BASE
, guest_ss_base
),
790 FIELD(GUEST_DS_BASE
, guest_ds_base
),
791 FIELD(GUEST_FS_BASE
, guest_fs_base
),
792 FIELD(GUEST_GS_BASE
, guest_gs_base
),
793 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
794 FIELD(GUEST_TR_BASE
, guest_tr_base
),
795 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
796 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
797 FIELD(GUEST_DR7
, guest_dr7
),
798 FIELD(GUEST_RSP
, guest_rsp
),
799 FIELD(GUEST_RIP
, guest_rip
),
800 FIELD(GUEST_RFLAGS
, guest_rflags
),
801 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
802 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
803 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
804 FIELD(HOST_CR0
, host_cr0
),
805 FIELD(HOST_CR3
, host_cr3
),
806 FIELD(HOST_CR4
, host_cr4
),
807 FIELD(HOST_FS_BASE
, host_fs_base
),
808 FIELD(HOST_GS_BASE
, host_gs_base
),
809 FIELD(HOST_TR_BASE
, host_tr_base
),
810 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
811 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
812 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
813 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
814 FIELD(HOST_RSP
, host_rsp
),
815 FIELD(HOST_RIP
, host_rip
),
818 static inline short vmcs_field_to_offset(unsigned long field
)
820 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
822 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
823 vmcs_field_to_offset_table
[field
] == 0)
826 return vmcs_field_to_offset_table
[field
];
829 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
831 return to_vmx(vcpu
)->nested
.current_vmcs12
;
834 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
836 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
837 if (is_error_page(page
))
843 static void nested_release_page(struct page
*page
)
845 kvm_release_page_dirty(page
);
848 static void nested_release_page_clean(struct page
*page
)
850 kvm_release_page_clean(page
);
853 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
854 static u64
construct_eptp(unsigned long root_hpa
);
855 static void kvm_cpu_vmxon(u64 addr
);
856 static void kvm_cpu_vmxoff(void);
857 static bool vmx_mpx_supported(void);
858 static bool vmx_xsaves_supported(void);
859 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
);
860 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
861 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
862 struct kvm_segment
*var
, int seg
);
863 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
864 struct kvm_segment
*var
, int seg
);
865 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
866 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
867 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
868 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
869 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
870 static int alloc_identity_pagetable(struct kvm
*kvm
);
872 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
873 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
875 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
876 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
878 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
879 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
882 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
883 * can find which vCPU should be waken up.
885 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
886 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
888 static unsigned long *vmx_io_bitmap_a
;
889 static unsigned long *vmx_io_bitmap_b
;
890 static unsigned long *vmx_msr_bitmap_legacy
;
891 static unsigned long *vmx_msr_bitmap_longmode
;
892 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
893 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
894 static unsigned long *vmx_msr_bitmap_nested
;
895 static unsigned long *vmx_vmread_bitmap
;
896 static unsigned long *vmx_vmwrite_bitmap
;
898 static bool cpu_has_load_ia32_efer
;
899 static bool cpu_has_load_perf_global_ctrl
;
901 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
902 static DEFINE_SPINLOCK(vmx_vpid_lock
);
904 static struct vmcs_config
{
908 u32 pin_based_exec_ctrl
;
909 u32 cpu_based_exec_ctrl
;
910 u32 cpu_based_2nd_exec_ctrl
;
915 static struct vmx_capability
{
920 #define VMX_SEGMENT_FIELD(seg) \
921 [VCPU_SREG_##seg] = { \
922 .selector = GUEST_##seg##_SELECTOR, \
923 .base = GUEST_##seg##_BASE, \
924 .limit = GUEST_##seg##_LIMIT, \
925 .ar_bytes = GUEST_##seg##_AR_BYTES, \
928 static const struct kvm_vmx_segment_field
{
933 } kvm_vmx_segment_fields
[] = {
934 VMX_SEGMENT_FIELD(CS
),
935 VMX_SEGMENT_FIELD(DS
),
936 VMX_SEGMENT_FIELD(ES
),
937 VMX_SEGMENT_FIELD(FS
),
938 VMX_SEGMENT_FIELD(GS
),
939 VMX_SEGMENT_FIELD(SS
),
940 VMX_SEGMENT_FIELD(TR
),
941 VMX_SEGMENT_FIELD(LDTR
),
944 static u64 host_efer
;
946 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
949 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
950 * away by decrementing the array size.
952 static const u32 vmx_msr_index
[] = {
954 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
956 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
959 static inline bool is_page_fault(u32 intr_info
)
961 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
962 INTR_INFO_VALID_MASK
)) ==
963 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
966 static inline bool is_no_device(u32 intr_info
)
968 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
969 INTR_INFO_VALID_MASK
)) ==
970 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
973 static inline bool is_invalid_opcode(u32 intr_info
)
975 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
976 INTR_INFO_VALID_MASK
)) ==
977 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
980 static inline bool is_external_interrupt(u32 intr_info
)
982 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
983 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
986 static inline bool is_machine_check(u32 intr_info
)
988 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
989 INTR_INFO_VALID_MASK
)) ==
990 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
993 static inline bool cpu_has_vmx_msr_bitmap(void)
995 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
998 static inline bool cpu_has_vmx_tpr_shadow(void)
1000 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1003 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1005 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1008 static inline bool cpu_has_secondary_exec_ctrls(void)
1010 return vmcs_config
.cpu_based_exec_ctrl
&
1011 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1014 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1016 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1017 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1020 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1022 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1023 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1026 static inline bool cpu_has_vmx_apic_register_virt(void)
1028 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1029 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1032 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1034 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1038 static inline bool cpu_has_vmx_posted_intr(void)
1040 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1041 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1044 static inline bool cpu_has_vmx_apicv(void)
1046 return cpu_has_vmx_apic_register_virt() &&
1047 cpu_has_vmx_virtual_intr_delivery() &&
1048 cpu_has_vmx_posted_intr();
1051 static inline bool cpu_has_vmx_flexpriority(void)
1053 return cpu_has_vmx_tpr_shadow() &&
1054 cpu_has_vmx_virtualize_apic_accesses();
1057 static inline bool cpu_has_vmx_ept_execute_only(void)
1059 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1062 static inline bool cpu_has_vmx_ept_2m_page(void)
1064 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1067 static inline bool cpu_has_vmx_ept_1g_page(void)
1069 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1072 static inline bool cpu_has_vmx_ept_4levels(void)
1074 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1077 static inline bool cpu_has_vmx_ept_ad_bits(void)
1079 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1082 static inline bool cpu_has_vmx_invept_context(void)
1084 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1087 static inline bool cpu_has_vmx_invept_global(void)
1089 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1092 static inline bool cpu_has_vmx_invvpid_single(void)
1094 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1097 static inline bool cpu_has_vmx_invvpid_global(void)
1099 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1102 static inline bool cpu_has_vmx_ept(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_ENABLE_EPT
;
1108 static inline bool cpu_has_vmx_unrestricted_guest(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1114 static inline bool cpu_has_vmx_ple(void)
1116 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1117 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1120 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1122 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1125 static inline bool cpu_has_vmx_vpid(void)
1127 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1128 SECONDARY_EXEC_ENABLE_VPID
;
1131 static inline bool cpu_has_vmx_rdtscp(void)
1133 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1134 SECONDARY_EXEC_RDTSCP
;
1137 static inline bool cpu_has_vmx_invpcid(void)
1139 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1140 SECONDARY_EXEC_ENABLE_INVPCID
;
1143 static inline bool cpu_has_virtual_nmis(void)
1145 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1148 static inline bool cpu_has_vmx_wbinvd_exit(void)
1150 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1151 SECONDARY_EXEC_WBINVD_EXITING
;
1154 static inline bool cpu_has_vmx_shadow_vmcs(void)
1157 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1158 /* check if the cpu supports writing r/o exit information fields */
1159 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1162 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1163 SECONDARY_EXEC_SHADOW_VMCS
;
1166 static inline bool cpu_has_vmx_pml(void)
1168 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1171 static inline bool report_flexpriority(void)
1173 return flexpriority_enabled
;
1176 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1178 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1181 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1183 return (vmcs12
->cpu_based_vm_exec_control
&
1184 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1185 (vmcs12
->secondary_vm_exec_control
& bit
);
1188 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1190 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1193 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1195 return vmcs12
->pin_based_vm_exec_control
&
1196 PIN_BASED_VMX_PREEMPTION_TIMER
;
1199 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1201 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1204 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1206 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1207 vmx_xsaves_supported();
1210 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1212 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1215 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1217 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1220 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1222 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1225 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1227 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1230 static inline bool is_exception(u32 intr_info
)
1232 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1233 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1236 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1238 unsigned long exit_qualification
);
1239 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1240 struct vmcs12
*vmcs12
,
1241 u32 reason
, unsigned long qualification
);
1243 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1247 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1248 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1253 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1259 } operand
= { vpid
, 0, gva
};
1261 asm volatile (__ex(ASM_VMX_INVVPID
)
1262 /* CF==1 or ZF==1 --> rc = -1 */
1263 "; ja 1f ; ud2 ; 1:"
1264 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1267 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1271 } operand
= {eptp
, gpa
};
1273 asm volatile (__ex(ASM_VMX_INVEPT
)
1274 /* CF==1 or ZF==1 --> rc = -1 */
1275 "; ja 1f ; ud2 ; 1:\n"
1276 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1279 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1283 i
= __find_msr_index(vmx
, msr
);
1285 return &vmx
->guest_msrs
[i
];
1289 static void vmcs_clear(struct vmcs
*vmcs
)
1291 u64 phys_addr
= __pa(vmcs
);
1294 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1295 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1298 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1302 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1304 vmcs_clear(loaded_vmcs
->vmcs
);
1305 loaded_vmcs
->cpu
= -1;
1306 loaded_vmcs
->launched
= 0;
1309 static void vmcs_load(struct vmcs
*vmcs
)
1311 u64 phys_addr
= __pa(vmcs
);
1314 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1315 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1318 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1322 #ifdef CONFIG_KEXEC_CORE
1324 * This bitmap is used to indicate whether the vmclear
1325 * operation is enabled on all cpus. All disabled by
1328 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1330 static inline void crash_enable_local_vmclear(int cpu
)
1332 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1335 static inline void crash_disable_local_vmclear(int cpu
)
1337 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1340 static inline int crash_local_vmclear_enabled(int cpu
)
1342 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1345 static void crash_vmclear_local_loaded_vmcss(void)
1347 int cpu
= raw_smp_processor_id();
1348 struct loaded_vmcs
*v
;
1350 if (!crash_local_vmclear_enabled(cpu
))
1353 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1354 loaded_vmcss_on_cpu_link
)
1355 vmcs_clear(v
->vmcs
);
1358 static inline void crash_enable_local_vmclear(int cpu
) { }
1359 static inline void crash_disable_local_vmclear(int cpu
) { }
1360 #endif /* CONFIG_KEXEC_CORE */
1362 static void __loaded_vmcs_clear(void *arg
)
1364 struct loaded_vmcs
*loaded_vmcs
= arg
;
1365 int cpu
= raw_smp_processor_id();
1367 if (loaded_vmcs
->cpu
!= cpu
)
1368 return; /* vcpu migration can race with cpu offline */
1369 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1370 per_cpu(current_vmcs
, cpu
) = NULL
;
1371 crash_disable_local_vmclear(cpu
);
1372 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1375 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1376 * is before setting loaded_vmcs->vcpu to -1 which is done in
1377 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1378 * then adds the vmcs into percpu list before it is deleted.
1382 loaded_vmcs_init(loaded_vmcs
);
1383 crash_enable_local_vmclear(cpu
);
1386 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1388 int cpu
= loaded_vmcs
->cpu
;
1391 smp_call_function_single(cpu
,
1392 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1395 static inline void vpid_sync_vcpu_single(int vpid
)
1400 if (cpu_has_vmx_invvpid_single())
1401 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1404 static inline void vpid_sync_vcpu_global(void)
1406 if (cpu_has_vmx_invvpid_global())
1407 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1410 static inline void vpid_sync_context(int vpid
)
1412 if (cpu_has_vmx_invvpid_single())
1413 vpid_sync_vcpu_single(vpid
);
1415 vpid_sync_vcpu_global();
1418 static inline void ept_sync_global(void)
1420 if (cpu_has_vmx_invept_global())
1421 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1424 static inline void ept_sync_context(u64 eptp
)
1427 if (cpu_has_vmx_invept_context())
1428 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1434 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1436 unsigned long value
;
1438 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1439 : "=a"(value
) : "d"(field
) : "cc");
1443 static __always_inline u16
vmcs_read16(unsigned long field
)
1445 return vmcs_readl(field
);
1448 static __always_inline u32
vmcs_read32(unsigned long field
)
1450 return vmcs_readl(field
);
1453 static __always_inline u64
vmcs_read64(unsigned long field
)
1455 #ifdef CONFIG_X86_64
1456 return vmcs_readl(field
);
1458 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1462 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1464 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1465 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1469 static void vmcs_writel(unsigned long field
, unsigned long value
)
1473 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1474 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1475 if (unlikely(error
))
1476 vmwrite_error(field
, value
);
1479 static void vmcs_write16(unsigned long field
, u16 value
)
1481 vmcs_writel(field
, value
);
1484 static void vmcs_write32(unsigned long field
, u32 value
)
1486 vmcs_writel(field
, value
);
1489 static void vmcs_write64(unsigned long field
, u64 value
)
1491 vmcs_writel(field
, value
);
1492 #ifndef CONFIG_X86_64
1494 vmcs_writel(field
+1, value
>> 32);
1498 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1500 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1503 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1505 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1508 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1510 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1511 vmx
->vm_entry_controls_shadow
= val
;
1514 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1516 if (vmx
->vm_entry_controls_shadow
!= val
)
1517 vm_entry_controls_init(vmx
, val
);
1520 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1522 return vmx
->vm_entry_controls_shadow
;
1526 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1528 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1531 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1533 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1536 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1538 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1539 vmx
->vm_exit_controls_shadow
= val
;
1542 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1544 if (vmx
->vm_exit_controls_shadow
!= val
)
1545 vm_exit_controls_init(vmx
, val
);
1548 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1550 return vmx
->vm_exit_controls_shadow
;
1554 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1556 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1559 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1561 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1564 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1566 vmx
->segment_cache
.bitmask
= 0;
1569 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1573 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1575 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1576 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1577 vmx
->segment_cache
.bitmask
= 0;
1579 ret
= vmx
->segment_cache
.bitmask
& mask
;
1580 vmx
->segment_cache
.bitmask
|= mask
;
1584 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1586 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1588 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1589 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1593 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1595 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1597 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1598 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1602 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1604 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1606 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1607 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1611 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1613 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1615 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1616 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1620 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1624 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1625 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1626 if ((vcpu
->guest_debug
&
1627 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1628 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1629 eb
|= 1u << BP_VECTOR
;
1630 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1633 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1634 if (vcpu
->fpu_active
)
1635 eb
&= ~(1u << NM_VECTOR
);
1637 /* When we are running a nested L2 guest and L1 specified for it a
1638 * certain exception bitmap, we must trap the same exceptions and pass
1639 * them to L1. When running L2, we will only handle the exceptions
1640 * specified above if L1 did not want them.
1642 if (is_guest_mode(vcpu
))
1643 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1645 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1648 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1649 unsigned long entry
, unsigned long exit
)
1651 vm_entry_controls_clearbit(vmx
, entry
);
1652 vm_exit_controls_clearbit(vmx
, exit
);
1655 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1658 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1662 if (cpu_has_load_ia32_efer
) {
1663 clear_atomic_switch_msr_special(vmx
,
1664 VM_ENTRY_LOAD_IA32_EFER
,
1665 VM_EXIT_LOAD_IA32_EFER
);
1669 case MSR_CORE_PERF_GLOBAL_CTRL
:
1670 if (cpu_has_load_perf_global_ctrl
) {
1671 clear_atomic_switch_msr_special(vmx
,
1672 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1673 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1679 for (i
= 0; i
< m
->nr
; ++i
)
1680 if (m
->guest
[i
].index
== msr
)
1686 m
->guest
[i
] = m
->guest
[m
->nr
];
1687 m
->host
[i
] = m
->host
[m
->nr
];
1688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1692 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1693 unsigned long entry
, unsigned long exit
,
1694 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1695 u64 guest_val
, u64 host_val
)
1697 vmcs_write64(guest_val_vmcs
, guest_val
);
1698 vmcs_write64(host_val_vmcs
, host_val
);
1699 vm_entry_controls_setbit(vmx
, entry
);
1700 vm_exit_controls_setbit(vmx
, exit
);
1703 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1704 u64 guest_val
, u64 host_val
)
1707 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1711 if (cpu_has_load_ia32_efer
) {
1712 add_atomic_switch_msr_special(vmx
,
1713 VM_ENTRY_LOAD_IA32_EFER
,
1714 VM_EXIT_LOAD_IA32_EFER
,
1717 guest_val
, host_val
);
1721 case MSR_CORE_PERF_GLOBAL_CTRL
:
1722 if (cpu_has_load_perf_global_ctrl
) {
1723 add_atomic_switch_msr_special(vmx
,
1724 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1725 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1726 GUEST_IA32_PERF_GLOBAL_CTRL
,
1727 HOST_IA32_PERF_GLOBAL_CTRL
,
1728 guest_val
, host_val
);
1734 for (i
= 0; i
< m
->nr
; ++i
)
1735 if (m
->guest
[i
].index
== msr
)
1738 if (i
== NR_AUTOLOAD_MSRS
) {
1739 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1740 "Can't add msr %x\n", msr
);
1742 } else if (i
== m
->nr
) {
1744 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1745 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1748 m
->guest
[i
].index
= msr
;
1749 m
->guest
[i
].value
= guest_val
;
1750 m
->host
[i
].index
= msr
;
1751 m
->host
[i
].value
= host_val
;
1754 static void reload_tss(void)
1757 * VT restores TR but not its size. Useless.
1759 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1760 struct desc_struct
*descs
;
1762 descs
= (void *)gdt
->address
;
1763 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1767 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1772 guest_efer
= vmx
->vcpu
.arch
.efer
;
1775 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1778 ignore_bits
= EFER_NX
| EFER_SCE
;
1779 #ifdef CONFIG_X86_64
1780 ignore_bits
|= EFER_LMA
| EFER_LME
;
1781 /* SCE is meaningful only in long mode on Intel */
1782 if (guest_efer
& EFER_LMA
)
1783 ignore_bits
&= ~(u64
)EFER_SCE
;
1785 guest_efer
&= ~ignore_bits
;
1786 guest_efer
|= host_efer
& ignore_bits
;
1787 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1788 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1790 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1793 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1794 * On CPUs that support "load IA32_EFER", always switch EFER
1795 * atomically, since it's faster than switching it manually.
1797 if (cpu_has_load_ia32_efer
||
1798 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1799 guest_efer
= vmx
->vcpu
.arch
.efer
;
1800 if (!(guest_efer
& EFER_LMA
))
1801 guest_efer
&= ~EFER_LME
;
1802 if (guest_efer
!= host_efer
)
1803 add_atomic_switch_msr(vmx
, MSR_EFER
,
1804 guest_efer
, host_efer
);
1811 static unsigned long segment_base(u16 selector
)
1813 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1814 struct desc_struct
*d
;
1815 unsigned long table_base
;
1818 if (!(selector
& ~3))
1821 table_base
= gdt
->address
;
1823 if (selector
& 4) { /* from ldt */
1824 u16 ldt_selector
= kvm_read_ldt();
1826 if (!(ldt_selector
& ~3))
1829 table_base
= segment_base(ldt_selector
);
1831 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1832 v
= get_desc_base(d
);
1833 #ifdef CONFIG_X86_64
1834 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1835 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1840 static inline unsigned long kvm_read_tr_base(void)
1843 asm("str %0" : "=g"(tr
));
1844 return segment_base(tr
);
1847 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1852 if (vmx
->host_state
.loaded
)
1855 vmx
->host_state
.loaded
= 1;
1857 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1858 * allow segment selectors with cpl > 0 or ti == 1.
1860 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1861 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1862 savesegment(fs
, vmx
->host_state
.fs_sel
);
1863 if (!(vmx
->host_state
.fs_sel
& 7)) {
1864 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1865 vmx
->host_state
.fs_reload_needed
= 0;
1867 vmcs_write16(HOST_FS_SELECTOR
, 0);
1868 vmx
->host_state
.fs_reload_needed
= 1;
1870 savesegment(gs
, vmx
->host_state
.gs_sel
);
1871 if (!(vmx
->host_state
.gs_sel
& 7))
1872 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1874 vmcs_write16(HOST_GS_SELECTOR
, 0);
1875 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1878 #ifdef CONFIG_X86_64
1879 savesegment(ds
, vmx
->host_state
.ds_sel
);
1880 savesegment(es
, vmx
->host_state
.es_sel
);
1883 #ifdef CONFIG_X86_64
1884 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1885 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1887 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1888 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1891 #ifdef CONFIG_X86_64
1892 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1893 if (is_long_mode(&vmx
->vcpu
))
1894 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1896 if (boot_cpu_has(X86_FEATURE_MPX
))
1897 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1898 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1899 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1900 vmx
->guest_msrs
[i
].data
,
1901 vmx
->guest_msrs
[i
].mask
);
1904 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1906 if (!vmx
->host_state
.loaded
)
1909 ++vmx
->vcpu
.stat
.host_state_reload
;
1910 vmx
->host_state
.loaded
= 0;
1911 #ifdef CONFIG_X86_64
1912 if (is_long_mode(&vmx
->vcpu
))
1913 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1915 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1916 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1917 #ifdef CONFIG_X86_64
1918 load_gs_index(vmx
->host_state
.gs_sel
);
1920 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1923 if (vmx
->host_state
.fs_reload_needed
)
1924 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1925 #ifdef CONFIG_X86_64
1926 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1927 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1928 loadsegment(es
, vmx
->host_state
.es_sel
);
1932 #ifdef CONFIG_X86_64
1933 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1935 if (vmx
->host_state
.msr_host_bndcfgs
)
1936 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1938 * If the FPU is not active (through the host task or
1939 * the guest vcpu), then restore the cr0.TS bit.
1941 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
1943 load_gdt(this_cpu_ptr(&host_gdt
));
1946 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1949 __vmx_load_host_state(vmx
);
1953 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
1955 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
1956 struct pi_desc old
, new;
1959 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
1960 !irq_remapping_cap(IRQ_POSTING_CAP
))
1964 old
.control
= new.control
= pi_desc
->control
;
1967 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1968 * are two possible cases:
1969 * 1. After running 'pre_block', context switch
1970 * happened. For this case, 'sn' was set in
1971 * vmx_vcpu_put(), so we need to clear it here.
1972 * 2. After running 'pre_block', we were blocked,
1973 * and woken up by some other guy. For this case,
1974 * we don't need to do anything, 'pi_post_block'
1975 * will do everything for us. However, we cannot
1976 * check whether it is case #1 or case #2 here
1977 * (maybe, not needed), so we also clear sn here,
1978 * I think it is not a big deal.
1980 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
1981 if (vcpu
->cpu
!= cpu
) {
1982 dest
= cpu_physical_id(cpu
);
1984 if (x2apic_enabled())
1987 new.ndst
= (dest
<< 8) & 0xFF00;
1990 /* set 'NV' to 'notification vector' */
1991 new.nv
= POSTED_INTR_VECTOR
;
1994 /* Allow posting non-urgent interrupts */
1996 } while (cmpxchg(&pi_desc
->control
, old
.control
,
1997 new.control
) != old
.control
);
2000 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2001 * vcpu mutex is already taken.
2003 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2006 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2009 kvm_cpu_vmxon(phys_addr
);
2010 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2011 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2013 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2014 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2015 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2018 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2019 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2020 unsigned long sysenter_esp
;
2022 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2023 local_irq_disable();
2024 crash_disable_local_vmclear(cpu
);
2027 * Read loaded_vmcs->cpu should be before fetching
2028 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2029 * See the comments in __loaded_vmcs_clear().
2033 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2034 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2035 crash_enable_local_vmclear(cpu
);
2039 * Linux uses per-cpu TSS and GDT, so set these when switching
2042 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2043 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2045 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2046 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2047 vmx
->loaded_vmcs
->cpu
= cpu
;
2050 vmx_vcpu_pi_load(vcpu
, cpu
);
2053 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2055 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2057 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2058 !irq_remapping_cap(IRQ_POSTING_CAP
))
2061 /* Set SN when the vCPU is preempted */
2062 if (vcpu
->preempted
)
2066 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2068 vmx_vcpu_pi_put(vcpu
);
2070 __vmx_load_host_state(to_vmx(vcpu
));
2071 if (!vmm_exclusive
) {
2072 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2078 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2082 if (vcpu
->fpu_active
)
2084 vcpu
->fpu_active
= 1;
2085 cr0
= vmcs_readl(GUEST_CR0
);
2086 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2087 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2088 vmcs_writel(GUEST_CR0
, cr0
);
2089 update_exception_bitmap(vcpu
);
2090 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2091 if (is_guest_mode(vcpu
))
2092 vcpu
->arch
.cr0_guest_owned_bits
&=
2093 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2094 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2097 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2100 * Return the cr0 value that a nested guest would read. This is a combination
2101 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2102 * its hypervisor (cr0_read_shadow).
2104 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2106 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2107 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2109 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2111 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2112 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2115 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2117 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2118 * set this *before* calling this function.
2120 vmx_decache_cr0_guest_bits(vcpu
);
2121 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2122 update_exception_bitmap(vcpu
);
2123 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2124 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2125 if (is_guest_mode(vcpu
)) {
2127 * L1's specified read shadow might not contain the TS bit,
2128 * so now that we turned on shadowing of this bit, we need to
2129 * set this bit of the shadow. Like in nested_vmx_run we need
2130 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2131 * up-to-date here because we just decached cr0.TS (and we'll
2132 * only update vmcs12->guest_cr0 on nested exit).
2134 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2135 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2136 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2137 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2139 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2142 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2144 unsigned long rflags
, save_rflags
;
2146 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2147 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2148 rflags
= vmcs_readl(GUEST_RFLAGS
);
2149 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2150 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2151 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2152 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2154 to_vmx(vcpu
)->rflags
= rflags
;
2156 return to_vmx(vcpu
)->rflags
;
2159 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2161 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2162 to_vmx(vcpu
)->rflags
= rflags
;
2163 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2164 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2165 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2167 vmcs_writel(GUEST_RFLAGS
, rflags
);
2170 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2172 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2175 if (interruptibility
& GUEST_INTR_STATE_STI
)
2176 ret
|= KVM_X86_SHADOW_INT_STI
;
2177 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2178 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2183 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2185 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2186 u32 interruptibility
= interruptibility_old
;
2188 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2190 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2191 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2192 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2193 interruptibility
|= GUEST_INTR_STATE_STI
;
2195 if ((interruptibility
!= interruptibility_old
))
2196 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2199 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2203 rip
= kvm_rip_read(vcpu
);
2204 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2205 kvm_rip_write(vcpu
, rip
);
2207 /* skipping an emulated instruction also counts */
2208 vmx_set_interrupt_shadow(vcpu
, 0);
2212 * KVM wants to inject page-faults which it got to the guest. This function
2213 * checks whether in a nested guest, we need to inject them to L1 or L2.
2215 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2217 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2219 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2222 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2223 vmcs_read32(VM_EXIT_INTR_INFO
),
2224 vmcs_readl(EXIT_QUALIFICATION
));
2228 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2229 bool has_error_code
, u32 error_code
,
2232 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2233 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2235 if (!reinject
&& is_guest_mode(vcpu
) &&
2236 nested_vmx_check_exception(vcpu
, nr
))
2239 if (has_error_code
) {
2240 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2241 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2244 if (vmx
->rmode
.vm86_active
) {
2246 if (kvm_exception_is_soft(nr
))
2247 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2248 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2249 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2253 if (kvm_exception_is_soft(nr
)) {
2254 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2255 vmx
->vcpu
.arch
.event_exit_inst_len
);
2256 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2258 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2260 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2263 static bool vmx_rdtscp_supported(void)
2265 return cpu_has_vmx_rdtscp();
2268 static bool vmx_invpcid_supported(void)
2270 return cpu_has_vmx_invpcid() && enable_ept
;
2274 * Swap MSR entry in host/guest MSR entry array.
2276 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2278 struct shared_msr_entry tmp
;
2280 tmp
= vmx
->guest_msrs
[to
];
2281 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2282 vmx
->guest_msrs
[from
] = tmp
;
2285 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2287 unsigned long *msr_bitmap
;
2289 if (is_guest_mode(vcpu
))
2290 msr_bitmap
= vmx_msr_bitmap_nested
;
2291 else if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
) {
2292 if (is_long_mode(vcpu
))
2293 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2295 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2297 if (is_long_mode(vcpu
))
2298 msr_bitmap
= vmx_msr_bitmap_longmode
;
2300 msr_bitmap
= vmx_msr_bitmap_legacy
;
2303 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2307 * Set up the vmcs to automatically save and restore system
2308 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2309 * mode, as fiddling with msrs is very expensive.
2311 static void setup_msrs(struct vcpu_vmx
*vmx
)
2313 int save_nmsrs
, index
;
2316 #ifdef CONFIG_X86_64
2317 if (is_long_mode(&vmx
->vcpu
)) {
2318 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2320 move_msr_up(vmx
, index
, save_nmsrs
++);
2321 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2323 move_msr_up(vmx
, index
, save_nmsrs
++);
2324 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2326 move_msr_up(vmx
, index
, save_nmsrs
++);
2327 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2328 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2329 move_msr_up(vmx
, index
, save_nmsrs
++);
2331 * MSR_STAR is only needed on long mode guests, and only
2332 * if efer.sce is enabled.
2334 index
= __find_msr_index(vmx
, MSR_STAR
);
2335 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2336 move_msr_up(vmx
, index
, save_nmsrs
++);
2339 index
= __find_msr_index(vmx
, MSR_EFER
);
2340 if (index
>= 0 && update_transition_efer(vmx
, index
))
2341 move_msr_up(vmx
, index
, save_nmsrs
++);
2343 vmx
->save_nmsrs
= save_nmsrs
;
2345 if (cpu_has_vmx_msr_bitmap())
2346 vmx_set_msr_bitmap(&vmx
->vcpu
);
2350 * reads and returns guest's timestamp counter "register"
2351 * guest_tsc = host_tsc + tsc_offset -- 21.3
2353 static u64
guest_read_tsc(void)
2355 u64 host_tsc
, tsc_offset
;
2358 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2359 return host_tsc
+ tsc_offset
;
2363 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2364 * counter, even if a nested guest (L2) is currently running.
2366 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2370 tsc_offset
= is_guest_mode(vcpu
) ?
2371 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2372 vmcs_read64(TSC_OFFSET
);
2373 return host_tsc
+ tsc_offset
;
2377 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2378 * software catchup for faster rates on slower CPUs.
2380 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2385 if (user_tsc_khz
> tsc_khz
) {
2386 vcpu
->arch
.tsc_catchup
= 1;
2387 vcpu
->arch
.tsc_always_catchup
= 1;
2389 WARN(1, "user requested TSC rate below hardware speed\n");
2392 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2394 return vmcs_read64(TSC_OFFSET
);
2398 * writes 'offset' into guest's timestamp counter offset register
2400 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2402 if (is_guest_mode(vcpu
)) {
2404 * We're here if L1 chose not to trap WRMSR to TSC. According
2405 * to the spec, this should set L1's TSC; The offset that L1
2406 * set for L2 remains unchanged, and still needs to be added
2407 * to the newly set TSC to get L2's TSC.
2409 struct vmcs12
*vmcs12
;
2410 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2411 /* recalculate vmcs02.TSC_OFFSET: */
2412 vmcs12
= get_vmcs12(vcpu
);
2413 vmcs_write64(TSC_OFFSET
, offset
+
2414 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2415 vmcs12
->tsc_offset
: 0));
2417 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2418 vmcs_read64(TSC_OFFSET
), offset
);
2419 vmcs_write64(TSC_OFFSET
, offset
);
2423 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2425 u64 offset
= vmcs_read64(TSC_OFFSET
);
2427 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2428 if (is_guest_mode(vcpu
)) {
2429 /* Even when running L2, the adjustment needs to apply to L1 */
2430 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2432 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2433 offset
+ adjustment
);
2436 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2438 return target_tsc
- rdtsc();
2441 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2443 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2444 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2448 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2449 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2450 * all guests if the "nested" module option is off, and can also be disabled
2451 * for a single guest by disabling its VMX cpuid bit.
2453 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2455 return nested
&& guest_cpuid_has_vmx(vcpu
);
2459 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2460 * returned for the various VMX controls MSRs when nested VMX is enabled.
2461 * The same values should also be used to verify that vmcs12 control fields are
2462 * valid during nested entry from L1 to L2.
2463 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2464 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2465 * bit in the high half is on if the corresponding bit in the control field
2466 * may be on. See also vmx_control_verify().
2468 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2471 * Note that as a general rule, the high half of the MSRs (bits in
2472 * the control fields which may be 1) should be initialized by the
2473 * intersection of the underlying hardware's MSR (i.e., features which
2474 * can be supported) and the list of features we want to expose -
2475 * because they are known to be properly supported in our code.
2476 * Also, usually, the low half of the MSRs (bits which must be 1) can
2477 * be set to 0, meaning that L1 may turn off any of these bits. The
2478 * reason is that if one of these bits is necessary, it will appear
2479 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2480 * fields of vmcs01 and vmcs02, will turn these bits off - and
2481 * nested_vmx_exit_handled() will not pass related exits to L1.
2482 * These rules have exceptions below.
2485 /* pin-based controls */
2486 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2487 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2488 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2489 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2490 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2491 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2492 PIN_BASED_EXT_INTR_MASK
|
2493 PIN_BASED_NMI_EXITING
|
2494 PIN_BASED_VIRTUAL_NMIS
;
2495 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2496 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2497 PIN_BASED_VMX_PREEMPTION_TIMER
;
2498 if (vmx_cpu_uses_apicv(&vmx
->vcpu
))
2499 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2500 PIN_BASED_POSTED_INTR
;
2503 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2504 vmx
->nested
.nested_vmx_exit_ctls_low
,
2505 vmx
->nested
.nested_vmx_exit_ctls_high
);
2506 vmx
->nested
.nested_vmx_exit_ctls_low
=
2507 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2509 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2510 #ifdef CONFIG_X86_64
2511 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2513 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2514 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2515 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2516 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2517 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2519 if (vmx_mpx_supported())
2520 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2522 /* We support free control of debug control saving. */
2523 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2524 vmx
->nested
.nested_vmx_exit_ctls_low
&
2525 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2527 /* entry controls */
2528 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2529 vmx
->nested
.nested_vmx_entry_ctls_low
,
2530 vmx
->nested
.nested_vmx_entry_ctls_high
);
2531 vmx
->nested
.nested_vmx_entry_ctls_low
=
2532 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2533 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2534 #ifdef CONFIG_X86_64
2535 VM_ENTRY_IA32E_MODE
|
2537 VM_ENTRY_LOAD_IA32_PAT
;
2538 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2539 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2540 if (vmx_mpx_supported())
2541 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2543 /* We support free control of debug control loading. */
2544 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2545 vmx
->nested
.nested_vmx_entry_ctls_low
&
2546 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2548 /* cpu-based controls */
2549 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2550 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2551 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2552 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2553 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2554 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2555 CPU_BASED_VIRTUAL_INTR_PENDING
|
2556 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2557 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2558 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2559 CPU_BASED_CR3_STORE_EXITING
|
2560 #ifdef CONFIG_X86_64
2561 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2563 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2564 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2565 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2566 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2567 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2569 * We can allow some features even when not supported by the
2570 * hardware. For example, L1 can specify an MSR bitmap - and we
2571 * can use it to avoid exits to L1 - even when L0 runs L2
2572 * without MSR bitmaps.
2574 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2575 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2576 CPU_BASED_USE_MSR_BITMAPS
;
2578 /* We support free control of CR3 access interception. */
2579 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2580 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2581 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2583 /* secondary cpu-based controls */
2584 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2585 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2586 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2587 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2588 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2589 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2590 SECONDARY_EXEC_RDTSCP
|
2591 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2592 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2593 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2594 SECONDARY_EXEC_WBINVD_EXITING
|
2595 SECONDARY_EXEC_XSAVES
|
2596 SECONDARY_EXEC_PCOMMIT
;
2599 /* nested EPT: emulate EPT also to L1 */
2600 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2601 SECONDARY_EXEC_ENABLE_EPT
;
2602 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2603 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2605 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2607 * For nested guests, we don't do anything specific
2608 * for single context invalidation. Hence, only advertise
2609 * support for global context invalidation.
2611 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2613 vmx
->nested
.nested_vmx_ept_caps
= 0;
2615 if (enable_unrestricted_guest
)
2616 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2617 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2619 /* miscellaneous data */
2620 rdmsr(MSR_IA32_VMX_MISC
,
2621 vmx
->nested
.nested_vmx_misc_low
,
2622 vmx
->nested
.nested_vmx_misc_high
);
2623 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2624 vmx
->nested
.nested_vmx_misc_low
|=
2625 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2626 VMX_MISC_ACTIVITY_HLT
;
2627 vmx
->nested
.nested_vmx_misc_high
= 0;
2630 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2633 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2635 return ((control
& high
) | low
) == control
;
2638 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2640 return low
| ((u64
)high
<< 32);
2643 /* Returns 0 on success, non-0 otherwise. */
2644 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2646 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2648 switch (msr_index
) {
2649 case MSR_IA32_VMX_BASIC
:
2651 * This MSR reports some information about VMX support. We
2652 * should return information about the VMX we emulate for the
2653 * guest, and the VMCS structure we give it - not about the
2654 * VMX support of the underlying hardware.
2656 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2657 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2658 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2660 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2661 case MSR_IA32_VMX_PINBASED_CTLS
:
2662 *pdata
= vmx_control_msr(
2663 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2664 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2666 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2667 *pdata
= vmx_control_msr(
2668 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2669 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2671 case MSR_IA32_VMX_PROCBASED_CTLS
:
2672 *pdata
= vmx_control_msr(
2673 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2674 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2676 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2677 *pdata
= vmx_control_msr(
2678 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2679 vmx
->nested
.nested_vmx_exit_ctls_high
);
2681 case MSR_IA32_VMX_EXIT_CTLS
:
2682 *pdata
= vmx_control_msr(
2683 vmx
->nested
.nested_vmx_exit_ctls_low
,
2684 vmx
->nested
.nested_vmx_exit_ctls_high
);
2686 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2687 *pdata
= vmx_control_msr(
2688 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2689 vmx
->nested
.nested_vmx_entry_ctls_high
);
2691 case MSR_IA32_VMX_ENTRY_CTLS
:
2692 *pdata
= vmx_control_msr(
2693 vmx
->nested
.nested_vmx_entry_ctls_low
,
2694 vmx
->nested
.nested_vmx_entry_ctls_high
);
2696 case MSR_IA32_VMX_MISC
:
2697 *pdata
= vmx_control_msr(
2698 vmx
->nested
.nested_vmx_misc_low
,
2699 vmx
->nested
.nested_vmx_misc_high
);
2702 * These MSRs specify bits which the guest must keep fixed (on or off)
2703 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2704 * We picked the standard core2 setting.
2706 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2707 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2708 case MSR_IA32_VMX_CR0_FIXED0
:
2709 *pdata
= VMXON_CR0_ALWAYSON
;
2711 case MSR_IA32_VMX_CR0_FIXED1
:
2714 case MSR_IA32_VMX_CR4_FIXED0
:
2715 *pdata
= VMXON_CR4_ALWAYSON
;
2717 case MSR_IA32_VMX_CR4_FIXED1
:
2720 case MSR_IA32_VMX_VMCS_ENUM
:
2721 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2723 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2724 *pdata
= vmx_control_msr(
2725 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2726 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2728 case MSR_IA32_VMX_EPT_VPID_CAP
:
2729 /* Currently, no nested vpid support */
2730 *pdata
= vmx
->nested
.nested_vmx_ept_caps
;
2740 * Reads an msr value (of 'msr_index') into 'pdata'.
2741 * Returns 0 on success, non-0 otherwise.
2742 * Assumes vcpu_load() was already called.
2744 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2746 struct shared_msr_entry
*msr
;
2748 switch (msr_info
->index
) {
2749 #ifdef CONFIG_X86_64
2751 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2754 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2756 case MSR_KERNEL_GS_BASE
:
2757 vmx_load_host_state(to_vmx(vcpu
));
2758 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2762 return kvm_get_msr_common(vcpu
, msr_info
);
2764 msr_info
->data
= guest_read_tsc();
2766 case MSR_IA32_SYSENTER_CS
:
2767 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2769 case MSR_IA32_SYSENTER_EIP
:
2770 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2772 case MSR_IA32_SYSENTER_ESP
:
2773 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2775 case MSR_IA32_BNDCFGS
:
2776 if (!vmx_mpx_supported())
2778 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2780 case MSR_IA32_FEATURE_CONTROL
:
2781 if (!nested_vmx_allowed(vcpu
))
2783 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2785 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2786 if (!nested_vmx_allowed(vcpu
))
2788 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2790 if (!vmx_xsaves_supported())
2792 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2795 if (!guest_cpuid_has_rdtscp(vcpu
))
2797 /* Otherwise falls through */
2799 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2801 msr_info
->data
= msr
->data
;
2804 return kvm_get_msr_common(vcpu
, msr_info
);
2810 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2813 * Writes msr value into into the appropriate "register".
2814 * Returns 0 on success, non-0 otherwise.
2815 * Assumes vcpu_load() was already called.
2817 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2819 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2820 struct shared_msr_entry
*msr
;
2822 u32 msr_index
= msr_info
->index
;
2823 u64 data
= msr_info
->data
;
2825 switch (msr_index
) {
2827 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2829 #ifdef CONFIG_X86_64
2831 vmx_segment_cache_clear(vmx
);
2832 vmcs_writel(GUEST_FS_BASE
, data
);
2835 vmx_segment_cache_clear(vmx
);
2836 vmcs_writel(GUEST_GS_BASE
, data
);
2838 case MSR_KERNEL_GS_BASE
:
2839 vmx_load_host_state(vmx
);
2840 vmx
->msr_guest_kernel_gs_base
= data
;
2843 case MSR_IA32_SYSENTER_CS
:
2844 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2846 case MSR_IA32_SYSENTER_EIP
:
2847 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2849 case MSR_IA32_SYSENTER_ESP
:
2850 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2852 case MSR_IA32_BNDCFGS
:
2853 if (!vmx_mpx_supported())
2855 vmcs_write64(GUEST_BNDCFGS
, data
);
2858 kvm_write_tsc(vcpu
, msr_info
);
2860 case MSR_IA32_CR_PAT
:
2861 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2862 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2864 vmcs_write64(GUEST_IA32_PAT
, data
);
2865 vcpu
->arch
.pat
= data
;
2868 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2870 case MSR_IA32_TSC_ADJUST
:
2871 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2873 case MSR_IA32_FEATURE_CONTROL
:
2874 if (!nested_vmx_allowed(vcpu
) ||
2875 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2876 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2878 vmx
->nested
.msr_ia32_feature_control
= data
;
2879 if (msr_info
->host_initiated
&& data
== 0)
2880 vmx_leave_nested(vcpu
);
2882 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2883 return 1; /* they are read-only */
2885 if (!vmx_xsaves_supported())
2888 * The only supported bit as of Skylake is bit 8, but
2889 * it is not supported on KVM.
2893 vcpu
->arch
.ia32_xss
= data
;
2894 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2895 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2896 vcpu
->arch
.ia32_xss
, host_xss
);
2898 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2901 if (!guest_cpuid_has_rdtscp(vcpu
))
2903 /* Check reserved bit, higher 32 bits should be zero */
2904 if ((data
>> 32) != 0)
2906 /* Otherwise falls through */
2908 msr
= find_msr_entry(vmx
, msr_index
);
2910 u64 old_msr_data
= msr
->data
;
2912 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2914 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2918 msr
->data
= old_msr_data
;
2922 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2928 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2930 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2933 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2936 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2938 case VCPU_EXREG_PDPTR
:
2940 ept_save_pdptrs(vcpu
);
2947 static __init
int cpu_has_kvm_support(void)
2949 return cpu_has_vmx();
2952 static __init
int vmx_disabled_by_bios(void)
2956 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2957 if (msr
& FEATURE_CONTROL_LOCKED
) {
2958 /* launched w/ TXT and VMX disabled */
2959 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2962 /* launched w/o TXT and VMX only enabled w/ TXT */
2963 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2964 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2965 && !tboot_enabled()) {
2966 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2967 "activate TXT before enabling KVM\n");
2970 /* launched w/o TXT and VMX disabled */
2971 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2972 && !tboot_enabled())
2979 static void kvm_cpu_vmxon(u64 addr
)
2981 asm volatile (ASM_VMX_VMXON_RAX
2982 : : "a"(&addr
), "m"(addr
)
2986 static int hardware_enable(void)
2988 int cpu
= raw_smp_processor_id();
2989 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2992 if (cr4_read_shadow() & X86_CR4_VMXE
)
2995 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2996 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
2997 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3000 * Now we can enable the vmclear operation in kdump
3001 * since the loaded_vmcss_on_cpu list on this cpu
3002 * has been initialized.
3004 * Though the cpu is not in VMX operation now, there
3005 * is no problem to enable the vmclear operation
3006 * for the loaded_vmcss_on_cpu list is empty!
3008 crash_enable_local_vmclear(cpu
);
3010 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3012 test_bits
= FEATURE_CONTROL_LOCKED
;
3013 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3014 if (tboot_enabled())
3015 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3017 if ((old
& test_bits
) != test_bits
) {
3018 /* enable and lock */
3019 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3021 cr4_set_bits(X86_CR4_VMXE
);
3023 if (vmm_exclusive
) {
3024 kvm_cpu_vmxon(phys_addr
);
3028 native_store_gdt(this_cpu_ptr(&host_gdt
));
3033 static void vmclear_local_loaded_vmcss(void)
3035 int cpu
= raw_smp_processor_id();
3036 struct loaded_vmcs
*v
, *n
;
3038 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3039 loaded_vmcss_on_cpu_link
)
3040 __loaded_vmcs_clear(v
);
3044 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3047 static void kvm_cpu_vmxoff(void)
3049 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3052 static void hardware_disable(void)
3054 if (vmm_exclusive
) {
3055 vmclear_local_loaded_vmcss();
3058 cr4_clear_bits(X86_CR4_VMXE
);
3061 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3062 u32 msr
, u32
*result
)
3064 u32 vmx_msr_low
, vmx_msr_high
;
3065 u32 ctl
= ctl_min
| ctl_opt
;
3067 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3069 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3070 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3072 /* Ensure minimum (required) set of control bits are supported. */
3080 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3082 u32 vmx_msr_low
, vmx_msr_high
;
3084 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3085 return vmx_msr_high
& ctl
;
3088 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3090 u32 vmx_msr_low
, vmx_msr_high
;
3091 u32 min
, opt
, min2
, opt2
;
3092 u32 _pin_based_exec_control
= 0;
3093 u32 _cpu_based_exec_control
= 0;
3094 u32 _cpu_based_2nd_exec_control
= 0;
3095 u32 _vmexit_control
= 0;
3096 u32 _vmentry_control
= 0;
3098 min
= CPU_BASED_HLT_EXITING
|
3099 #ifdef CONFIG_X86_64
3100 CPU_BASED_CR8_LOAD_EXITING
|
3101 CPU_BASED_CR8_STORE_EXITING
|
3103 CPU_BASED_CR3_LOAD_EXITING
|
3104 CPU_BASED_CR3_STORE_EXITING
|
3105 CPU_BASED_USE_IO_BITMAPS
|
3106 CPU_BASED_MOV_DR_EXITING
|
3107 CPU_BASED_USE_TSC_OFFSETING
|
3108 CPU_BASED_MWAIT_EXITING
|
3109 CPU_BASED_MONITOR_EXITING
|
3110 CPU_BASED_INVLPG_EXITING
|
3111 CPU_BASED_RDPMC_EXITING
;
3113 opt
= CPU_BASED_TPR_SHADOW
|
3114 CPU_BASED_USE_MSR_BITMAPS
|
3115 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3116 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3117 &_cpu_based_exec_control
) < 0)
3119 #ifdef CONFIG_X86_64
3120 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3121 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3122 ~CPU_BASED_CR8_STORE_EXITING
;
3124 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3126 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3127 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3128 SECONDARY_EXEC_WBINVD_EXITING
|
3129 SECONDARY_EXEC_ENABLE_VPID
|
3130 SECONDARY_EXEC_ENABLE_EPT
|
3131 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3132 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3133 SECONDARY_EXEC_RDTSCP
|
3134 SECONDARY_EXEC_ENABLE_INVPCID
|
3135 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3136 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3137 SECONDARY_EXEC_SHADOW_VMCS
|
3138 SECONDARY_EXEC_XSAVES
|
3139 SECONDARY_EXEC_ENABLE_PML
|
3140 SECONDARY_EXEC_PCOMMIT
;
3141 if (adjust_vmx_controls(min2
, opt2
,
3142 MSR_IA32_VMX_PROCBASED_CTLS2
,
3143 &_cpu_based_2nd_exec_control
) < 0)
3146 #ifndef CONFIG_X86_64
3147 if (!(_cpu_based_2nd_exec_control
&
3148 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3149 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3152 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3153 _cpu_based_2nd_exec_control
&= ~(
3154 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3155 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3156 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3158 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3159 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3161 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3162 CPU_BASED_CR3_STORE_EXITING
|
3163 CPU_BASED_INVLPG_EXITING
);
3164 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3165 vmx_capability
.ept
, vmx_capability
.vpid
);
3168 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3169 #ifdef CONFIG_X86_64
3170 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3172 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3173 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3174 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3175 &_vmexit_control
) < 0)
3178 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3179 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3180 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3181 &_pin_based_exec_control
) < 0)
3184 if (!(_cpu_based_2nd_exec_control
&
3185 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3186 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3187 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3189 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3190 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3191 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3192 &_vmentry_control
) < 0)
3195 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3197 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3198 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3201 #ifdef CONFIG_X86_64
3202 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3203 if (vmx_msr_high
& (1u<<16))
3207 /* Require Write-Back (WB) memory type for VMCS accesses. */
3208 if (((vmx_msr_high
>> 18) & 15) != 6)
3211 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3212 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3213 vmcs_conf
->revision_id
= vmx_msr_low
;
3215 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3216 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3217 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3218 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3219 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3221 cpu_has_load_ia32_efer
=
3222 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3223 VM_ENTRY_LOAD_IA32_EFER
)
3224 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3225 VM_EXIT_LOAD_IA32_EFER
);
3227 cpu_has_load_perf_global_ctrl
=
3228 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3229 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3230 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3231 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3234 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3235 * but due to arrata below it can't be used. Workaround is to use
3236 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3238 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3243 * BC86,AAY89,BD102 (model 44)
3247 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3248 switch (boot_cpu_data
.x86_model
) {
3254 cpu_has_load_perf_global_ctrl
= false;
3255 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3256 "does not work properly. Using workaround\n");
3264 rdmsrl(MSR_IA32_XSS
, host_xss
);
3269 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3271 int node
= cpu_to_node(cpu
);
3275 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3278 vmcs
= page_address(pages
);
3279 memset(vmcs
, 0, vmcs_config
.size
);
3280 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3284 static struct vmcs
*alloc_vmcs(void)
3286 return alloc_vmcs_cpu(raw_smp_processor_id());
3289 static void free_vmcs(struct vmcs
*vmcs
)
3291 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3295 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3297 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3299 if (!loaded_vmcs
->vmcs
)
3301 loaded_vmcs_clear(loaded_vmcs
);
3302 free_vmcs(loaded_vmcs
->vmcs
);
3303 loaded_vmcs
->vmcs
= NULL
;
3306 static void free_kvm_area(void)
3310 for_each_possible_cpu(cpu
) {
3311 free_vmcs(per_cpu(vmxarea
, cpu
));
3312 per_cpu(vmxarea
, cpu
) = NULL
;
3316 static void init_vmcs_shadow_fields(void)
3320 /* No checks for read only fields yet */
3322 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3323 switch (shadow_read_write_fields
[i
]) {
3325 if (!vmx_mpx_supported())
3333 shadow_read_write_fields
[j
] =
3334 shadow_read_write_fields
[i
];
3337 max_shadow_read_write_fields
= j
;
3339 /* shadowed fields guest access without vmexit */
3340 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3341 clear_bit(shadow_read_write_fields
[i
],
3342 vmx_vmwrite_bitmap
);
3343 clear_bit(shadow_read_write_fields
[i
],
3346 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3347 clear_bit(shadow_read_only_fields
[i
],
3351 static __init
int alloc_kvm_area(void)
3355 for_each_possible_cpu(cpu
) {
3358 vmcs
= alloc_vmcs_cpu(cpu
);
3364 per_cpu(vmxarea
, cpu
) = vmcs
;
3369 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3371 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3374 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3375 struct kvm_segment
*save
)
3377 if (!emulate_invalid_guest_state
) {
3379 * CS and SS RPL should be equal during guest entry according
3380 * to VMX spec, but in reality it is not always so. Since vcpu
3381 * is in the middle of the transition from real mode to
3382 * protected mode it is safe to assume that RPL 0 is a good
3385 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3386 save
->selector
&= ~SEGMENT_RPL_MASK
;
3387 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3390 vmx_set_segment(vcpu
, save
, seg
);
3393 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3395 unsigned long flags
;
3396 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3399 * Update real mode segment cache. It may be not up-to-date if sement
3400 * register was written while vcpu was in a guest mode.
3402 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3403 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3404 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3405 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3406 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3407 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3409 vmx
->rmode
.vm86_active
= 0;
3411 vmx_segment_cache_clear(vmx
);
3413 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3415 flags
= vmcs_readl(GUEST_RFLAGS
);
3416 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3417 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3418 vmcs_writel(GUEST_RFLAGS
, flags
);
3420 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3421 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3423 update_exception_bitmap(vcpu
);
3425 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3426 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3427 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3428 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3429 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3430 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3433 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3435 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3436 struct kvm_segment var
= *save
;
3439 if (seg
== VCPU_SREG_CS
)
3442 if (!emulate_invalid_guest_state
) {
3443 var
.selector
= var
.base
>> 4;
3444 var
.base
= var
.base
& 0xffff0;
3454 if (save
->base
& 0xf)
3455 printk_once(KERN_WARNING
"kvm: segment base is not "
3456 "paragraph aligned when entering "
3457 "protected mode (seg=%d)", seg
);
3460 vmcs_write16(sf
->selector
, var
.selector
);
3461 vmcs_write32(sf
->base
, var
.base
);
3462 vmcs_write32(sf
->limit
, var
.limit
);
3463 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3466 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3468 unsigned long flags
;
3469 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3471 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3472 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3473 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3474 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3475 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3476 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3477 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3479 vmx
->rmode
.vm86_active
= 1;
3482 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3483 * vcpu. Warn the user that an update is overdue.
3485 if (!vcpu
->kvm
->arch
.tss_addr
)
3486 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3487 "called before entering vcpu\n");
3489 vmx_segment_cache_clear(vmx
);
3491 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3492 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3493 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3495 flags
= vmcs_readl(GUEST_RFLAGS
);
3496 vmx
->rmode
.save_rflags
= flags
;
3498 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3500 vmcs_writel(GUEST_RFLAGS
, flags
);
3501 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3502 update_exception_bitmap(vcpu
);
3504 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3505 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3506 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3507 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3508 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3509 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3511 kvm_mmu_reset_context(vcpu
);
3514 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3516 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3517 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3523 * Force kernel_gs_base reloading before EFER changes, as control
3524 * of this msr depends on is_long_mode().
3526 vmx_load_host_state(to_vmx(vcpu
));
3527 vcpu
->arch
.efer
= efer
;
3528 if (efer
& EFER_LMA
) {
3529 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3532 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3534 msr
->data
= efer
& ~EFER_LME
;
3539 #ifdef CONFIG_X86_64
3541 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3545 vmx_segment_cache_clear(to_vmx(vcpu
));
3547 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3548 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3549 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3551 vmcs_write32(GUEST_TR_AR_BYTES
,
3552 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3553 | VMX_AR_TYPE_BUSY_64_TSS
);
3555 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3558 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3560 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3561 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3566 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3568 vpid_sync_context(vpid
);
3570 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3572 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3576 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3578 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3581 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3583 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3585 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3586 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3589 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3591 if (enable_ept
&& is_paging(vcpu
))
3592 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3593 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3596 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3598 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3600 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3601 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3604 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3606 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3608 if (!test_bit(VCPU_EXREG_PDPTR
,
3609 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3612 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3613 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3614 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3615 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3616 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3620 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3622 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3624 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3625 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3626 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3627 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3628 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3631 __set_bit(VCPU_EXREG_PDPTR
,
3632 (unsigned long *)&vcpu
->arch
.regs_avail
);
3633 __set_bit(VCPU_EXREG_PDPTR
,
3634 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3637 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3639 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3641 struct kvm_vcpu
*vcpu
)
3643 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3644 vmx_decache_cr3(vcpu
);
3645 if (!(cr0
& X86_CR0_PG
)) {
3646 /* From paging/starting to nonpaging */
3647 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3648 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3649 (CPU_BASED_CR3_LOAD_EXITING
|
3650 CPU_BASED_CR3_STORE_EXITING
));
3651 vcpu
->arch
.cr0
= cr0
;
3652 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3653 } else if (!is_paging(vcpu
)) {
3654 /* From nonpaging to paging */
3655 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3656 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3657 ~(CPU_BASED_CR3_LOAD_EXITING
|
3658 CPU_BASED_CR3_STORE_EXITING
));
3659 vcpu
->arch
.cr0
= cr0
;
3660 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3663 if (!(cr0
& X86_CR0_WP
))
3664 *hw_cr0
&= ~X86_CR0_WP
;
3667 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3669 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3670 unsigned long hw_cr0
;
3672 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3673 if (enable_unrestricted_guest
)
3674 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3676 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3678 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3681 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3685 #ifdef CONFIG_X86_64
3686 if (vcpu
->arch
.efer
& EFER_LME
) {
3687 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3689 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3695 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3697 if (!vcpu
->fpu_active
)
3698 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3700 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3701 vmcs_writel(GUEST_CR0
, hw_cr0
);
3702 vcpu
->arch
.cr0
= cr0
;
3704 /* depends on vcpu->arch.cr0 to be set to a new value */
3705 vmx
->emulation_required
= emulation_required(vcpu
);
3708 static u64
construct_eptp(unsigned long root_hpa
)
3712 /* TODO write the value reading from MSR */
3713 eptp
= VMX_EPT_DEFAULT_MT
|
3714 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3715 if (enable_ept_ad_bits
)
3716 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3717 eptp
|= (root_hpa
& PAGE_MASK
);
3722 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3724 unsigned long guest_cr3
;
3729 eptp
= construct_eptp(cr3
);
3730 vmcs_write64(EPT_POINTER
, eptp
);
3731 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3732 guest_cr3
= kvm_read_cr3(vcpu
);
3734 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3735 ept_load_pdptrs(vcpu
);
3738 vmx_flush_tlb(vcpu
);
3739 vmcs_writel(GUEST_CR3
, guest_cr3
);
3742 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3745 * Pass through host's Machine Check Enable value to hw_cr4, which
3746 * is in force while we are in guest mode. Do not let guests control
3747 * this bit, even if host CR4.MCE == 0.
3749 unsigned long hw_cr4
=
3750 (cr4_read_shadow() & X86_CR4_MCE
) |
3751 (cr4
& ~X86_CR4_MCE
) |
3752 (to_vmx(vcpu
)->rmode
.vm86_active
?
3753 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3755 if (cr4
& X86_CR4_VMXE
) {
3757 * To use VMXON (and later other VMX instructions), a guest
3758 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3759 * So basically the check on whether to allow nested VMX
3762 if (!nested_vmx_allowed(vcpu
))
3765 if (to_vmx(vcpu
)->nested
.vmxon
&&
3766 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3769 vcpu
->arch
.cr4
= cr4
;
3771 if (!is_paging(vcpu
)) {
3772 hw_cr4
&= ~X86_CR4_PAE
;
3773 hw_cr4
|= X86_CR4_PSE
;
3775 * SMEP/SMAP is disabled if CPU is in non-paging mode
3776 * in hardware. However KVM always uses paging mode to
3777 * emulate guest non-paging mode with TDP.
3778 * To emulate this behavior, SMEP/SMAP needs to be
3779 * manually disabled when guest switches to non-paging
3782 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3783 } else if (!(cr4
& X86_CR4_PAE
)) {
3784 hw_cr4
&= ~X86_CR4_PAE
;
3788 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3789 vmcs_writel(GUEST_CR4
, hw_cr4
);
3793 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3794 struct kvm_segment
*var
, int seg
)
3796 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3799 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3800 *var
= vmx
->rmode
.segs
[seg
];
3801 if (seg
== VCPU_SREG_TR
3802 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3804 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3805 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3808 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3809 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3810 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3811 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3812 var
->unusable
= (ar
>> 16) & 1;
3813 var
->type
= ar
& 15;
3814 var
->s
= (ar
>> 4) & 1;
3815 var
->dpl
= (ar
>> 5) & 3;
3817 * Some userspaces do not preserve unusable property. Since usable
3818 * segment has to be present according to VMX spec we can use present
3819 * property to amend userspace bug by making unusable segment always
3820 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3821 * segment as unusable.
3823 var
->present
= !var
->unusable
;
3824 var
->avl
= (ar
>> 12) & 1;
3825 var
->l
= (ar
>> 13) & 1;
3826 var
->db
= (ar
>> 14) & 1;
3827 var
->g
= (ar
>> 15) & 1;
3830 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3832 struct kvm_segment s
;
3834 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3835 vmx_get_segment(vcpu
, &s
, seg
);
3838 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3841 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3843 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3845 if (unlikely(vmx
->rmode
.vm86_active
))
3848 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3849 return VMX_AR_DPL(ar
);
3853 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3857 if (var
->unusable
|| !var
->present
)
3860 ar
= var
->type
& 15;
3861 ar
|= (var
->s
& 1) << 4;
3862 ar
|= (var
->dpl
& 3) << 5;
3863 ar
|= (var
->present
& 1) << 7;
3864 ar
|= (var
->avl
& 1) << 12;
3865 ar
|= (var
->l
& 1) << 13;
3866 ar
|= (var
->db
& 1) << 14;
3867 ar
|= (var
->g
& 1) << 15;
3873 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3874 struct kvm_segment
*var
, int seg
)
3876 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3877 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3879 vmx_segment_cache_clear(vmx
);
3881 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3882 vmx
->rmode
.segs
[seg
] = *var
;
3883 if (seg
== VCPU_SREG_TR
)
3884 vmcs_write16(sf
->selector
, var
->selector
);
3886 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3890 vmcs_writel(sf
->base
, var
->base
);
3891 vmcs_write32(sf
->limit
, var
->limit
);
3892 vmcs_write16(sf
->selector
, var
->selector
);
3895 * Fix the "Accessed" bit in AR field of segment registers for older
3897 * IA32 arch specifies that at the time of processor reset the
3898 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3899 * is setting it to 0 in the userland code. This causes invalid guest
3900 * state vmexit when "unrestricted guest" mode is turned on.
3901 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3902 * tree. Newer qemu binaries with that qemu fix would not need this
3905 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3906 var
->type
|= 0x1; /* Accessed */
3908 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3911 vmx
->emulation_required
= emulation_required(vcpu
);
3914 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3916 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3918 *db
= (ar
>> 14) & 1;
3919 *l
= (ar
>> 13) & 1;
3922 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3924 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3925 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3928 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3930 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3931 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3934 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3936 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3937 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3940 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3942 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3943 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3946 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3948 struct kvm_segment var
;
3951 vmx_get_segment(vcpu
, &var
, seg
);
3953 if (seg
== VCPU_SREG_CS
)
3955 ar
= vmx_segment_access_rights(&var
);
3957 if (var
.base
!= (var
.selector
<< 4))
3959 if (var
.limit
!= 0xffff)
3967 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3969 struct kvm_segment cs
;
3970 unsigned int cs_rpl
;
3972 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3973 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3977 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
3981 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
3982 if (cs
.dpl
> cs_rpl
)
3985 if (cs
.dpl
!= cs_rpl
)
3991 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3995 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3997 struct kvm_segment ss
;
3998 unsigned int ss_rpl
;
4000 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4001 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4005 if (ss
.type
!= 3 && ss
.type
!= 7)
4009 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4017 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4019 struct kvm_segment var
;
4022 vmx_get_segment(vcpu
, &var
, seg
);
4023 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4031 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4032 if (var
.dpl
< rpl
) /* DPL < RPL */
4036 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4042 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4044 struct kvm_segment tr
;
4046 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4050 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4052 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4060 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4062 struct kvm_segment ldtr
;
4064 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4068 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4078 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4080 struct kvm_segment cs
, ss
;
4082 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4083 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4085 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4086 (ss
.selector
& SEGMENT_RPL_MASK
));
4090 * Check if guest state is valid. Returns true if valid, false if
4092 * We assume that registers are always usable
4094 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4096 if (enable_unrestricted_guest
)
4099 /* real mode guest state checks */
4100 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4101 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4103 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4105 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4107 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4109 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4111 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4114 /* protected mode guest state checks */
4115 if (!cs_ss_rpl_check(vcpu
))
4117 if (!code_segment_valid(vcpu
))
4119 if (!stack_segment_valid(vcpu
))
4121 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4123 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4125 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4127 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4129 if (!tr_valid(vcpu
))
4131 if (!ldtr_valid(vcpu
))
4135 * - Add checks on RIP
4136 * - Add checks on RFLAGS
4142 static int init_rmode_tss(struct kvm
*kvm
)
4148 idx
= srcu_read_lock(&kvm
->srcu
);
4149 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4150 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4153 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4154 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4155 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4158 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4161 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4165 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4166 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4169 srcu_read_unlock(&kvm
->srcu
, idx
);
4173 static int init_rmode_identity_map(struct kvm
*kvm
)
4176 pfn_t identity_map_pfn
;
4182 /* Protect kvm->arch.ept_identity_pagetable_done. */
4183 mutex_lock(&kvm
->slots_lock
);
4185 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4188 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4190 r
= alloc_identity_pagetable(kvm
);
4194 idx
= srcu_read_lock(&kvm
->srcu
);
4195 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4198 /* Set up identity-mapping pagetable for EPT in real mode */
4199 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4200 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4201 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4202 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4203 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4207 kvm
->arch
.ept_identity_pagetable_done
= true;
4210 srcu_read_unlock(&kvm
->srcu
, idx
);
4213 mutex_unlock(&kvm
->slots_lock
);
4217 static void seg_setup(int seg
)
4219 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4222 vmcs_write16(sf
->selector
, 0);
4223 vmcs_writel(sf
->base
, 0);
4224 vmcs_write32(sf
->limit
, 0xffff);
4226 if (seg
== VCPU_SREG_CS
)
4227 ar
|= 0x08; /* code segment */
4229 vmcs_write32(sf
->ar_bytes
, ar
);
4232 static int alloc_apic_access_page(struct kvm
*kvm
)
4237 mutex_lock(&kvm
->slots_lock
);
4238 if (kvm
->arch
.apic_access_page_done
)
4240 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4241 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4245 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4246 if (is_error_page(page
)) {
4252 * Do not pin the page in memory, so that memory hot-unplug
4253 * is able to migrate it.
4256 kvm
->arch
.apic_access_page_done
= true;
4258 mutex_unlock(&kvm
->slots_lock
);
4262 static int alloc_identity_pagetable(struct kvm
*kvm
)
4264 /* Called with kvm->slots_lock held. */
4268 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4270 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4271 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4276 static int allocate_vpid(void)
4282 spin_lock(&vmx_vpid_lock
);
4283 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4284 if (vpid
< VMX_NR_VPIDS
)
4285 __set_bit(vpid
, vmx_vpid_bitmap
);
4288 spin_unlock(&vmx_vpid_lock
);
4292 static void free_vpid(int vpid
)
4294 if (!enable_vpid
|| vpid
== 0)
4296 spin_lock(&vmx_vpid_lock
);
4297 __clear_bit(vpid
, vmx_vpid_bitmap
);
4298 spin_unlock(&vmx_vpid_lock
);
4301 #define MSR_TYPE_R 1
4302 #define MSR_TYPE_W 2
4303 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4306 int f
= sizeof(unsigned long);
4308 if (!cpu_has_vmx_msr_bitmap())
4312 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4313 * have the write-low and read-high bitmap offsets the wrong way round.
4314 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4316 if (msr
<= 0x1fff) {
4317 if (type
& MSR_TYPE_R
)
4319 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4321 if (type
& MSR_TYPE_W
)
4323 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4325 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4327 if (type
& MSR_TYPE_R
)
4329 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4331 if (type
& MSR_TYPE_W
)
4333 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4338 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4341 int f
= sizeof(unsigned long);
4343 if (!cpu_has_vmx_msr_bitmap())
4347 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4348 * have the write-low and read-high bitmap offsets the wrong way round.
4349 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4351 if (msr
<= 0x1fff) {
4352 if (type
& MSR_TYPE_R
)
4354 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4356 if (type
& MSR_TYPE_W
)
4358 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4360 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4362 if (type
& MSR_TYPE_R
)
4364 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4366 if (type
& MSR_TYPE_W
)
4368 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4374 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4375 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4377 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4378 unsigned long *msr_bitmap_nested
,
4381 int f
= sizeof(unsigned long);
4383 if (!cpu_has_vmx_msr_bitmap()) {
4389 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4390 * have the write-low and read-high bitmap offsets the wrong way round.
4391 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4393 if (msr
<= 0x1fff) {
4394 if (type
& MSR_TYPE_R
&&
4395 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4397 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4399 if (type
& MSR_TYPE_W
&&
4400 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4402 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4404 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4406 if (type
& MSR_TYPE_R
&&
4407 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4409 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4411 if (type
& MSR_TYPE_W
&&
4412 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4414 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4419 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4422 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4423 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4424 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4425 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4428 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4430 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4432 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4436 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4438 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4440 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4444 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4446 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4448 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4452 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
)
4454 return enable_apicv
&& lapic_in_kernel(vcpu
);
4457 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4459 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4464 if (vmx
->nested
.pi_desc
&&
4465 vmx
->nested
.pi_pending
) {
4466 vmx
->nested
.pi_pending
= false;
4467 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4470 max_irr
= find_last_bit(
4471 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4476 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4481 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4482 kunmap(vmx
->nested
.virtual_apic_page
);
4484 status
= vmcs_read16(GUEST_INTR_STATUS
);
4485 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4487 status
|= (u8
)max_irr
;
4488 vmcs_write16(GUEST_INTR_STATUS
, status
);
4494 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4497 if (vcpu
->mode
== IN_GUEST_MODE
) {
4498 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4501 * Currently, we don't support urgent interrupt,
4502 * all interrupts are recognized as non-urgent
4503 * interrupt, so we cannot post interrupts when
4506 * If the vcpu is in guest mode, it means it is
4507 * running instead of being scheduled out and
4508 * waiting in the run queue, and that's the only
4509 * case when 'SN' is set currently, warning if
4512 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4514 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4515 POSTED_INTR_VECTOR
);
4522 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4525 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4527 if (is_guest_mode(vcpu
) &&
4528 vector
== vmx
->nested
.posted_intr_nv
) {
4529 /* the PIR and ON have been set by L1. */
4530 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4532 * If a posted intr is not recognized by hardware,
4533 * we will accomplish it in the next vmentry.
4535 vmx
->nested
.pi_pending
= true;
4536 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4542 * Send interrupt to vcpu via posted interrupt way.
4543 * 1. If target vcpu is running(non-root mode), send posted interrupt
4544 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4545 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4546 * interrupt from PIR in next vmentry.
4548 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4550 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4553 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4557 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4560 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4561 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4562 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4563 kvm_vcpu_kick(vcpu
);
4566 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4568 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4570 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4573 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4576 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4582 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4583 * will not change in the lifetime of the guest.
4584 * Note that host-state that does change is set elsewhere. E.g., host-state
4585 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4587 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4594 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4595 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4597 /* Save the most likely value for this task's CR4 in the VMCS. */
4598 cr4
= cr4_read_shadow();
4599 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4600 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4602 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4603 #ifdef CONFIG_X86_64
4605 * Load null selectors, so we can avoid reloading them in
4606 * __vmx_load_host_state(), in case userspace uses the null selectors
4607 * too (the expected case).
4609 vmcs_write16(HOST_DS_SELECTOR
, 0);
4610 vmcs_write16(HOST_ES_SELECTOR
, 0);
4612 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4613 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4615 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4616 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4618 native_store_idt(&dt
);
4619 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4620 vmx
->host_idt_base
= dt
.address
;
4622 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4624 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4625 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4626 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4627 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4629 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4630 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4631 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4635 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4637 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4639 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4640 if (is_guest_mode(&vmx
->vcpu
))
4641 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4642 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4643 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4646 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4648 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4650 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4651 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4652 return pin_based_exec_ctrl
;
4655 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4657 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4659 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4660 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4662 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4663 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4664 #ifdef CONFIG_X86_64
4665 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4666 CPU_BASED_CR8_LOAD_EXITING
;
4670 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4671 CPU_BASED_CR3_LOAD_EXITING
|
4672 CPU_BASED_INVLPG_EXITING
;
4673 return exec_control
;
4676 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4678 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4679 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4680 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4682 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4684 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4685 enable_unrestricted_guest
= 0;
4686 /* Enable INVPCID for non-ept guests may cause performance regression. */
4687 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4689 if (!enable_unrestricted_guest
)
4690 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4692 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4693 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4694 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4695 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4696 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4697 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4699 We can NOT enable shadow_vmcs here because we don't have yet
4702 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4703 /* PML is enabled/disabled in creating/destorying vcpu */
4704 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4706 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4707 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4709 return exec_control
;
4712 static void ept_set_mmio_spte_mask(void)
4715 * EPT Misconfigurations can be generated if the value of bits 2:0
4716 * of an EPT paging-structure entry is 110b (write/execute).
4717 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4720 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4723 #define VMX_XSS_EXIT_BITMAP 0
4725 * Sets up the vmcs for emulated real mode.
4727 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4729 #ifdef CONFIG_X86_64
4735 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4736 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4738 if (enable_shadow_vmcs
) {
4739 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4740 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4742 if (cpu_has_vmx_msr_bitmap())
4743 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4745 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4748 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4750 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4752 if (cpu_has_secondary_exec_ctrls())
4753 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4754 vmx_secondary_exec_control(vmx
));
4756 if (vmx_cpu_uses_apicv(&vmx
->vcpu
)) {
4757 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4758 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4759 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4760 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4762 vmcs_write16(GUEST_INTR_STATUS
, 0);
4764 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4765 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4769 vmcs_write32(PLE_GAP
, ple_gap
);
4770 vmx
->ple_window
= ple_window
;
4771 vmx
->ple_window_dirty
= true;
4774 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4775 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4776 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4778 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4779 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4780 vmx_set_constant_host_state(vmx
);
4781 #ifdef CONFIG_X86_64
4782 rdmsrl(MSR_FS_BASE
, a
);
4783 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4784 rdmsrl(MSR_GS_BASE
, a
);
4785 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4787 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4788 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4791 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4792 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4793 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4794 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4795 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4797 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4798 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4800 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4801 u32 index
= vmx_msr_index
[i
];
4802 u32 data_low
, data_high
;
4805 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4807 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4809 vmx
->guest_msrs
[j
].index
= i
;
4810 vmx
->guest_msrs
[j
].data
= 0;
4811 vmx
->guest_msrs
[j
].mask
= -1ull;
4816 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4818 /* 22.2.1, 20.8.1 */
4819 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4821 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4822 set_cr4_guest_host_mask(vmx
);
4824 if (vmx_xsaves_supported())
4825 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4830 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4832 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4833 struct msr_data apic_base_msr
;
4836 vmx
->rmode
.vm86_active
= 0;
4838 vmx
->soft_vnmi_blocked
= 0;
4840 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4841 kvm_set_cr8(vcpu
, 0);
4844 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4845 MSR_IA32_APICBASE_ENABLE
;
4846 if (kvm_vcpu_is_reset_bsp(vcpu
))
4847 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4848 apic_base_msr
.host_initiated
= true;
4849 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4852 vmx_segment_cache_clear(vmx
);
4854 seg_setup(VCPU_SREG_CS
);
4855 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4856 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4858 seg_setup(VCPU_SREG_DS
);
4859 seg_setup(VCPU_SREG_ES
);
4860 seg_setup(VCPU_SREG_FS
);
4861 seg_setup(VCPU_SREG_GS
);
4862 seg_setup(VCPU_SREG_SS
);
4864 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4865 vmcs_writel(GUEST_TR_BASE
, 0);
4866 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4867 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4869 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4870 vmcs_writel(GUEST_LDTR_BASE
, 0);
4871 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4872 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4875 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4876 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4877 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4878 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4881 vmcs_writel(GUEST_RFLAGS
, 0x02);
4882 kvm_rip_write(vcpu
, 0xfff0);
4884 vmcs_writel(GUEST_GDTR_BASE
, 0);
4885 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4887 vmcs_writel(GUEST_IDTR_BASE
, 0);
4888 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4890 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4891 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4892 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4896 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4898 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4899 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4900 if (cpu_need_tpr_shadow(vcpu
))
4901 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4902 __pa(vcpu
->arch
.apic
->regs
));
4903 vmcs_write32(TPR_THRESHOLD
, 0);
4906 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4908 if (vmx_cpu_uses_apicv(vcpu
))
4909 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4912 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4914 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4915 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
4916 vmx
->vcpu
.arch
.cr0
= cr0
;
4917 vmx_set_cr4(vcpu
, 0);
4919 vmx_set_efer(vcpu
, 0);
4920 vmx_fpu_activate(vcpu
);
4921 update_exception_bitmap(vcpu
);
4923 vpid_sync_context(vmx
->vpid
);
4927 * In nested virtualization, check if L1 asked to exit on external interrupts.
4928 * For most existing hypervisors, this will always return true.
4930 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4932 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4933 PIN_BASED_EXT_INTR_MASK
;
4937 * In nested virtualization, check if L1 has set
4938 * VM_EXIT_ACK_INTR_ON_EXIT
4940 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4942 return get_vmcs12(vcpu
)->vm_exit_controls
&
4943 VM_EXIT_ACK_INTR_ON_EXIT
;
4946 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4948 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4949 PIN_BASED_NMI_EXITING
;
4952 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4954 u32 cpu_based_vm_exec_control
;
4956 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4957 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4958 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4961 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4963 u32 cpu_based_vm_exec_control
;
4965 if (!cpu_has_virtual_nmis() ||
4966 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4967 enable_irq_window(vcpu
);
4971 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4972 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4973 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4976 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4978 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4980 int irq
= vcpu
->arch
.interrupt
.nr
;
4982 trace_kvm_inj_virq(irq
);
4984 ++vcpu
->stat
.irq_injections
;
4985 if (vmx
->rmode
.vm86_active
) {
4987 if (vcpu
->arch
.interrupt
.soft
)
4988 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4989 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4990 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4993 intr
= irq
| INTR_INFO_VALID_MASK
;
4994 if (vcpu
->arch
.interrupt
.soft
) {
4995 intr
|= INTR_TYPE_SOFT_INTR
;
4996 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4997 vmx
->vcpu
.arch
.event_exit_inst_len
);
4999 intr
|= INTR_TYPE_EXT_INTR
;
5000 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5003 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5007 if (is_guest_mode(vcpu
))
5010 if (!cpu_has_virtual_nmis()) {
5012 * Tracking the NMI-blocked state in software is built upon
5013 * finding the next open IRQ window. This, in turn, depends on
5014 * well-behaving guests: They have to keep IRQs disabled at
5015 * least as long as the NMI handler runs. Otherwise we may
5016 * cause NMI nesting, maybe breaking the guest. But as this is
5017 * highly unlikely, we can live with the residual risk.
5019 vmx
->soft_vnmi_blocked
= 1;
5020 vmx
->vnmi_blocked_time
= 0;
5023 ++vcpu
->stat
.nmi_injections
;
5024 vmx
->nmi_known_unmasked
= false;
5025 if (vmx
->rmode
.vm86_active
) {
5026 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5027 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5030 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5031 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5034 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5036 if (!cpu_has_virtual_nmis())
5037 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5038 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5040 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5043 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5045 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5047 if (!cpu_has_virtual_nmis()) {
5048 if (vmx
->soft_vnmi_blocked
!= masked
) {
5049 vmx
->soft_vnmi_blocked
= masked
;
5050 vmx
->vnmi_blocked_time
= 0;
5053 vmx
->nmi_known_unmasked
= !masked
;
5055 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5056 GUEST_INTR_STATE_NMI
);
5058 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5059 GUEST_INTR_STATE_NMI
);
5063 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5065 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5068 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5071 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5072 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5073 | GUEST_INTR_STATE_NMI
));
5076 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5078 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5079 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5080 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5081 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5084 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5088 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5092 kvm
->arch
.tss_addr
= addr
;
5093 return init_rmode_tss(kvm
);
5096 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5101 * Update instruction length as we may reinject the exception
5102 * from user space while in guest debugging mode.
5104 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5105 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5106 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5110 if (vcpu
->guest_debug
&
5111 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5128 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5129 int vec
, u32 err_code
)
5132 * Instruction with address size override prefix opcode 0x67
5133 * Cause the #SS fault with 0 error code in VM86 mode.
5135 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5136 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5137 if (vcpu
->arch
.halt_request
) {
5138 vcpu
->arch
.halt_request
= 0;
5139 return kvm_vcpu_halt(vcpu
);
5147 * Forward all other exceptions that are valid in real mode.
5148 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5149 * the required debugging infrastructure rework.
5151 kvm_queue_exception(vcpu
, vec
);
5156 * Trigger machine check on the host. We assume all the MSRs are already set up
5157 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5158 * We pass a fake environment to the machine check handler because we want
5159 * the guest to be always treated like user space, no matter what context
5160 * it used internally.
5162 static void kvm_machine_check(void)
5164 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5165 struct pt_regs regs
= {
5166 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5167 .flags
= X86_EFLAGS_IF
,
5170 do_machine_check(®s
, 0);
5174 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5176 /* already handled by vcpu_run */
5180 static int handle_exception(struct kvm_vcpu
*vcpu
)
5182 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5183 struct kvm_run
*kvm_run
= vcpu
->run
;
5184 u32 intr_info
, ex_no
, error_code
;
5185 unsigned long cr2
, rip
, dr6
;
5187 enum emulation_result er
;
5189 vect_info
= vmx
->idt_vectoring_info
;
5190 intr_info
= vmx
->exit_intr_info
;
5192 if (is_machine_check(intr_info
))
5193 return handle_machine_check(vcpu
);
5195 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5196 return 1; /* already handled by vmx_vcpu_run() */
5198 if (is_no_device(intr_info
)) {
5199 vmx_fpu_activate(vcpu
);
5203 if (is_invalid_opcode(intr_info
)) {
5204 if (is_guest_mode(vcpu
)) {
5205 kvm_queue_exception(vcpu
, UD_VECTOR
);
5208 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5209 if (er
!= EMULATE_DONE
)
5210 kvm_queue_exception(vcpu
, UD_VECTOR
);
5215 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5216 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5219 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5220 * MMIO, it is better to report an internal error.
5221 * See the comments in vmx_handle_exit.
5223 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5224 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5225 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5226 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5227 vcpu
->run
->internal
.ndata
= 3;
5228 vcpu
->run
->internal
.data
[0] = vect_info
;
5229 vcpu
->run
->internal
.data
[1] = intr_info
;
5230 vcpu
->run
->internal
.data
[2] = error_code
;
5234 if (is_page_fault(intr_info
)) {
5235 /* EPT won't cause page fault directly */
5237 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5238 trace_kvm_page_fault(cr2
, error_code
);
5240 if (kvm_event_needs_reinjection(vcpu
))
5241 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5242 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5245 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5247 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5248 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5252 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5253 if (!(vcpu
->guest_debug
&
5254 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5255 vcpu
->arch
.dr6
&= ~15;
5256 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5257 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5258 skip_emulated_instruction(vcpu
);
5260 kvm_queue_exception(vcpu
, DB_VECTOR
);
5263 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5264 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5268 * Update instruction length as we may reinject #BP from
5269 * user space while in guest debugging mode. Reading it for
5270 * #DB as well causes no harm, it is not used in that case.
5272 vmx
->vcpu
.arch
.event_exit_inst_len
=
5273 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5274 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5275 rip
= kvm_rip_read(vcpu
);
5276 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5277 kvm_run
->debug
.arch
.exception
= ex_no
;
5280 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5281 kvm_run
->ex
.exception
= ex_no
;
5282 kvm_run
->ex
.error_code
= error_code
;
5288 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5290 ++vcpu
->stat
.irq_exits
;
5294 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5296 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5300 static int handle_io(struct kvm_vcpu
*vcpu
)
5302 unsigned long exit_qualification
;
5303 int size
, in
, string
;
5306 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5307 string
= (exit_qualification
& 16) != 0;
5308 in
= (exit_qualification
& 8) != 0;
5310 ++vcpu
->stat
.io_exits
;
5313 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5315 port
= exit_qualification
>> 16;
5316 size
= (exit_qualification
& 7) + 1;
5317 skip_emulated_instruction(vcpu
);
5319 return kvm_fast_pio_out(vcpu
, size
, port
);
5323 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5326 * Patch in the VMCALL instruction:
5328 hypercall
[0] = 0x0f;
5329 hypercall
[1] = 0x01;
5330 hypercall
[2] = 0xc1;
5333 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5335 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5336 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5338 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5339 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5340 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5341 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5342 return (val
& always_on
) == always_on
;
5345 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5346 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5348 if (is_guest_mode(vcpu
)) {
5349 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5350 unsigned long orig_val
= val
;
5353 * We get here when L2 changed cr0 in a way that did not change
5354 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5355 * but did change L0 shadowed bits. So we first calculate the
5356 * effective cr0 value that L1 would like to write into the
5357 * hardware. It consists of the L2-owned bits from the new
5358 * value combined with the L1-owned bits from L1's guest_cr0.
5360 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5361 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5363 if (!nested_cr0_valid(vcpu
, val
))
5366 if (kvm_set_cr0(vcpu
, val
))
5368 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5371 if (to_vmx(vcpu
)->nested
.vmxon
&&
5372 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5374 return kvm_set_cr0(vcpu
, val
);
5378 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5380 if (is_guest_mode(vcpu
)) {
5381 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5382 unsigned long orig_val
= val
;
5384 /* analogously to handle_set_cr0 */
5385 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5386 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5387 if (kvm_set_cr4(vcpu
, val
))
5389 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5392 return kvm_set_cr4(vcpu
, val
);
5395 /* called to set cr0 as approriate for clts instruction exit. */
5396 static void handle_clts(struct kvm_vcpu
*vcpu
)
5398 if (is_guest_mode(vcpu
)) {
5400 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5401 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5402 * just pretend it's off (also in arch.cr0 for fpu_activate).
5404 vmcs_writel(CR0_READ_SHADOW
,
5405 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5406 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5408 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5411 static int handle_cr(struct kvm_vcpu
*vcpu
)
5413 unsigned long exit_qualification
, val
;
5418 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5419 cr
= exit_qualification
& 15;
5420 reg
= (exit_qualification
>> 8) & 15;
5421 switch ((exit_qualification
>> 4) & 3) {
5422 case 0: /* mov to cr */
5423 val
= kvm_register_readl(vcpu
, reg
);
5424 trace_kvm_cr_write(cr
, val
);
5427 err
= handle_set_cr0(vcpu
, val
);
5428 kvm_complete_insn_gp(vcpu
, err
);
5431 err
= kvm_set_cr3(vcpu
, val
);
5432 kvm_complete_insn_gp(vcpu
, err
);
5435 err
= handle_set_cr4(vcpu
, val
);
5436 kvm_complete_insn_gp(vcpu
, err
);
5439 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5441 err
= kvm_set_cr8(vcpu
, cr8
);
5442 kvm_complete_insn_gp(vcpu
, err
);
5443 if (lapic_in_kernel(vcpu
))
5445 if (cr8_prev
<= cr8
)
5447 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5454 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5455 skip_emulated_instruction(vcpu
);
5456 vmx_fpu_activate(vcpu
);
5458 case 1: /*mov from cr*/
5461 val
= kvm_read_cr3(vcpu
);
5462 kvm_register_write(vcpu
, reg
, val
);
5463 trace_kvm_cr_read(cr
, val
);
5464 skip_emulated_instruction(vcpu
);
5467 val
= kvm_get_cr8(vcpu
);
5468 kvm_register_write(vcpu
, reg
, val
);
5469 trace_kvm_cr_read(cr
, val
);
5470 skip_emulated_instruction(vcpu
);
5475 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5476 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5477 kvm_lmsw(vcpu
, val
);
5479 skip_emulated_instruction(vcpu
);
5484 vcpu
->run
->exit_reason
= 0;
5485 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5486 (int)(exit_qualification
>> 4) & 3, cr
);
5490 static int handle_dr(struct kvm_vcpu
*vcpu
)
5492 unsigned long exit_qualification
;
5495 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5496 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5498 /* First, if DR does not exist, trigger UD */
5499 if (!kvm_require_dr(vcpu
, dr
))
5502 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5503 if (!kvm_require_cpl(vcpu
, 0))
5505 dr7
= vmcs_readl(GUEST_DR7
);
5508 * As the vm-exit takes precedence over the debug trap, we
5509 * need to emulate the latter, either for the host or the
5510 * guest debugging itself.
5512 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5513 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5514 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5515 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5516 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5517 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5520 vcpu
->arch
.dr6
&= ~15;
5521 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5522 kvm_queue_exception(vcpu
, DB_VECTOR
);
5527 if (vcpu
->guest_debug
== 0) {
5528 u32 cpu_based_vm_exec_control
;
5530 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5531 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5532 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5535 * No more DR vmexits; force a reload of the debug registers
5536 * and reenter on this instruction. The next vmexit will
5537 * retrieve the full state of the debug registers.
5539 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5543 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5544 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5547 if (kvm_get_dr(vcpu
, dr
, &val
))
5549 kvm_register_write(vcpu
, reg
, val
);
5551 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5554 skip_emulated_instruction(vcpu
);
5558 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5560 return vcpu
->arch
.dr6
;
5563 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5567 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5569 u32 cpu_based_vm_exec_control
;
5571 get_debugreg(vcpu
->arch
.db
[0], 0);
5572 get_debugreg(vcpu
->arch
.db
[1], 1);
5573 get_debugreg(vcpu
->arch
.db
[2], 2);
5574 get_debugreg(vcpu
->arch
.db
[3], 3);
5575 get_debugreg(vcpu
->arch
.dr6
, 6);
5576 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5578 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5580 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5581 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5582 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5585 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5587 vmcs_writel(GUEST_DR7
, val
);
5590 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5592 kvm_emulate_cpuid(vcpu
);
5596 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5598 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5599 struct msr_data msr_info
;
5601 msr_info
.index
= ecx
;
5602 msr_info
.host_initiated
= false;
5603 if (vmx_get_msr(vcpu
, &msr_info
)) {
5604 trace_kvm_msr_read_ex(ecx
);
5605 kvm_inject_gp(vcpu
, 0);
5609 trace_kvm_msr_read(ecx
, msr_info
.data
);
5611 /* FIXME: handling of bits 32:63 of rax, rdx */
5612 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5613 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5614 skip_emulated_instruction(vcpu
);
5618 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5620 struct msr_data msr
;
5621 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5622 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5623 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5627 msr
.host_initiated
= false;
5628 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5629 trace_kvm_msr_write_ex(ecx
, data
);
5630 kvm_inject_gp(vcpu
, 0);
5634 trace_kvm_msr_write(ecx
, data
);
5635 skip_emulated_instruction(vcpu
);
5639 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5641 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5645 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5647 u32 cpu_based_vm_exec_control
;
5649 /* clear pending irq */
5650 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5651 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5652 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5654 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5656 ++vcpu
->stat
.irq_window_exits
;
5660 static int handle_halt(struct kvm_vcpu
*vcpu
)
5662 return kvm_emulate_halt(vcpu
);
5665 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5667 kvm_emulate_hypercall(vcpu
);
5671 static int handle_invd(struct kvm_vcpu
*vcpu
)
5673 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5676 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5678 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5680 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5681 skip_emulated_instruction(vcpu
);
5685 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5689 err
= kvm_rdpmc(vcpu
);
5690 kvm_complete_insn_gp(vcpu
, err
);
5695 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5697 kvm_emulate_wbinvd(vcpu
);
5701 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5703 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5704 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5706 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5707 skip_emulated_instruction(vcpu
);
5711 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5713 skip_emulated_instruction(vcpu
);
5714 WARN(1, "this should never happen\n");
5718 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5720 skip_emulated_instruction(vcpu
);
5721 WARN(1, "this should never happen\n");
5725 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5727 if (likely(fasteoi
)) {
5728 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5729 int access_type
, offset
;
5731 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5732 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5734 * Sane guest uses MOV to write EOI, with written value
5735 * not cared. So make a short-circuit here by avoiding
5736 * heavy instruction emulation.
5738 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5739 (offset
== APIC_EOI
)) {
5740 kvm_lapic_set_eoi(vcpu
);
5741 skip_emulated_instruction(vcpu
);
5745 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5748 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5750 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5751 int vector
= exit_qualification
& 0xff;
5753 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5754 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5758 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5760 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5761 u32 offset
= exit_qualification
& 0xfff;
5763 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5764 kvm_apic_write_nodecode(vcpu
, offset
);
5768 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5770 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5771 unsigned long exit_qualification
;
5772 bool has_error_code
= false;
5775 int reason
, type
, idt_v
, idt_index
;
5777 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5778 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5779 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5781 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5783 reason
= (u32
)exit_qualification
>> 30;
5784 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5786 case INTR_TYPE_NMI_INTR
:
5787 vcpu
->arch
.nmi_injected
= false;
5788 vmx_set_nmi_mask(vcpu
, true);
5790 case INTR_TYPE_EXT_INTR
:
5791 case INTR_TYPE_SOFT_INTR
:
5792 kvm_clear_interrupt_queue(vcpu
);
5794 case INTR_TYPE_HARD_EXCEPTION
:
5795 if (vmx
->idt_vectoring_info
&
5796 VECTORING_INFO_DELIVER_CODE_MASK
) {
5797 has_error_code
= true;
5799 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5802 case INTR_TYPE_SOFT_EXCEPTION
:
5803 kvm_clear_exception_queue(vcpu
);
5809 tss_selector
= exit_qualification
;
5811 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5812 type
!= INTR_TYPE_EXT_INTR
&&
5813 type
!= INTR_TYPE_NMI_INTR
))
5814 skip_emulated_instruction(vcpu
);
5816 if (kvm_task_switch(vcpu
, tss_selector
,
5817 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5818 has_error_code
, error_code
) == EMULATE_FAIL
) {
5819 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5820 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5821 vcpu
->run
->internal
.ndata
= 0;
5826 * TODO: What about debug traps on tss switch?
5827 * Are we supposed to inject them and update dr6?
5833 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5835 unsigned long exit_qualification
;
5840 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5842 gla_validity
= (exit_qualification
>> 7) & 0x3;
5843 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5844 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5845 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5846 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5847 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5848 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5849 (long unsigned int)exit_qualification
);
5850 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5851 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5856 * EPT violation happened while executing iret from NMI,
5857 * "blocked by NMI" bit has to be set before next VM entry.
5858 * There are errata that may cause this bit to not be set:
5861 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5862 cpu_has_virtual_nmis() &&
5863 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5864 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5866 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5867 trace_kvm_page_fault(gpa
, exit_qualification
);
5869 /* It is a write fault? */
5870 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5871 /* It is a fetch fault? */
5872 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5873 /* ept page table is present? */
5874 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5876 vcpu
->arch
.exit_qualification
= exit_qualification
;
5878 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5881 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5886 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5887 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5888 skip_emulated_instruction(vcpu
);
5889 trace_kvm_fast_mmio(gpa
);
5893 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5894 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5895 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5898 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5899 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5901 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5904 /* It is the real ept misconfig */
5907 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5908 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5913 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5915 u32 cpu_based_vm_exec_control
;
5917 /* clear pending NMI */
5918 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5919 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5920 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5921 ++vcpu
->stat
.nmi_window_exits
;
5922 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5927 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5929 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5930 enum emulation_result err
= EMULATE_DONE
;
5933 bool intr_window_requested
;
5934 unsigned count
= 130;
5936 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5937 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5939 while (vmx
->emulation_required
&& count
-- != 0) {
5940 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5941 return handle_interrupt_window(&vmx
->vcpu
);
5943 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5946 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5948 if (err
== EMULATE_USER_EXIT
) {
5949 ++vcpu
->stat
.mmio_exits
;
5954 if (err
!= EMULATE_DONE
) {
5955 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5956 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5957 vcpu
->run
->internal
.ndata
= 0;
5961 if (vcpu
->arch
.halt_request
) {
5962 vcpu
->arch
.halt_request
= 0;
5963 ret
= kvm_vcpu_halt(vcpu
);
5967 if (signal_pending(current
))
5977 static int __grow_ple_window(int val
)
5979 if (ple_window_grow
< 1)
5982 val
= min(val
, ple_window_actual_max
);
5984 if (ple_window_grow
< ple_window
)
5985 val
*= ple_window_grow
;
5987 val
+= ple_window_grow
;
5992 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5997 if (modifier
< ple_window
)
6002 return max(val
, minimum
);
6005 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6007 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6008 int old
= vmx
->ple_window
;
6010 vmx
->ple_window
= __grow_ple_window(old
);
6012 if (vmx
->ple_window
!= old
)
6013 vmx
->ple_window_dirty
= true;
6015 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6018 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6020 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6021 int old
= vmx
->ple_window
;
6023 vmx
->ple_window
= __shrink_ple_window(old
,
6024 ple_window_shrink
, ple_window
);
6026 if (vmx
->ple_window
!= old
)
6027 vmx
->ple_window_dirty
= true;
6029 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6033 * ple_window_actual_max is computed to be one grow_ple_window() below
6034 * ple_window_max. (See __grow_ple_window for the reason.)
6035 * This prevents overflows, because ple_window_max is int.
6036 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6038 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6040 static void update_ple_window_actual_max(void)
6042 ple_window_actual_max
=
6043 __shrink_ple_window(max(ple_window_max
, ple_window
),
6044 ple_window_grow
, INT_MIN
);
6048 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6050 static void wakeup_handler(void)
6052 struct kvm_vcpu
*vcpu
;
6053 int cpu
= smp_processor_id();
6055 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6056 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6057 blocked_vcpu_list
) {
6058 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6060 if (pi_test_on(pi_desc
) == 1)
6061 kvm_vcpu_kick(vcpu
);
6063 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6066 static __init
int hardware_setup(void)
6068 int r
= -ENOMEM
, i
, msr
;
6070 rdmsrl_safe(MSR_EFER
, &host_efer
);
6072 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6073 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6075 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6076 if (!vmx_io_bitmap_a
)
6079 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6080 if (!vmx_io_bitmap_b
)
6083 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6084 if (!vmx_msr_bitmap_legacy
)
6087 vmx_msr_bitmap_legacy_x2apic
=
6088 (unsigned long *)__get_free_page(GFP_KERNEL
);
6089 if (!vmx_msr_bitmap_legacy_x2apic
)
6092 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6093 if (!vmx_msr_bitmap_longmode
)
6096 vmx_msr_bitmap_longmode_x2apic
=
6097 (unsigned long *)__get_free_page(GFP_KERNEL
);
6098 if (!vmx_msr_bitmap_longmode_x2apic
)
6102 vmx_msr_bitmap_nested
=
6103 (unsigned long *)__get_free_page(GFP_KERNEL
);
6104 if (!vmx_msr_bitmap_nested
)
6108 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6109 if (!vmx_vmread_bitmap
)
6112 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6113 if (!vmx_vmwrite_bitmap
)
6116 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6117 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6120 * Allow direct access to the PC debug port (it is often used for I/O
6121 * delays, but the vmexits simply slow things down).
6123 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6124 clear_bit(0x80, vmx_io_bitmap_a
);
6126 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6128 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6129 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6131 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6133 if (setup_vmcs_config(&vmcs_config
) < 0) {
6138 if (boot_cpu_has(X86_FEATURE_NX
))
6139 kvm_enable_efer_bits(EFER_NX
);
6141 if (!cpu_has_vmx_vpid())
6143 if (!cpu_has_vmx_shadow_vmcs())
6144 enable_shadow_vmcs
= 0;
6145 if (enable_shadow_vmcs
)
6146 init_vmcs_shadow_fields();
6148 if (!cpu_has_vmx_ept() ||
6149 !cpu_has_vmx_ept_4levels()) {
6151 enable_unrestricted_guest
= 0;
6152 enable_ept_ad_bits
= 0;
6155 if (!cpu_has_vmx_ept_ad_bits())
6156 enable_ept_ad_bits
= 0;
6158 if (!cpu_has_vmx_unrestricted_guest())
6159 enable_unrestricted_guest
= 0;
6161 if (!cpu_has_vmx_flexpriority())
6162 flexpriority_enabled
= 0;
6165 * set_apic_access_page_addr() is used to reload apic access
6166 * page upon invalidation. No need to do anything if not
6167 * using the APIC_ACCESS_ADDR VMCS field.
6169 if (!flexpriority_enabled
)
6170 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6172 if (!cpu_has_vmx_tpr_shadow())
6173 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6175 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6176 kvm_disable_largepages();
6178 if (!cpu_has_vmx_ple())
6181 if (!cpu_has_vmx_apicv())
6185 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6187 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6188 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6189 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6190 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6193 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6194 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6195 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6196 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6197 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6198 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6199 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6201 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6202 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6203 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6204 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6206 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6209 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6210 vmx_disable_intercept_msr_read_x2apic(msr
);
6212 /* According SDM, in x2apic mode, the whole id reg is used.
6213 * But in KVM, it only use the highest eight bits. Need to
6215 vmx_enable_intercept_msr_read_x2apic(0x802);
6217 vmx_enable_intercept_msr_read_x2apic(0x839);
6219 vmx_disable_intercept_msr_write_x2apic(0x808);
6221 vmx_disable_intercept_msr_write_x2apic(0x80b);
6223 vmx_disable_intercept_msr_write_x2apic(0x83f);
6227 kvm_mmu_set_mask_ptes(0ull,
6228 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6229 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6230 0ull, VMX_EPT_EXECUTABLE_MASK
);
6231 ept_set_mmio_spte_mask();
6236 update_ple_window_actual_max();
6239 * Only enable PML when hardware supports PML feature, and both EPT
6240 * and EPT A/D bit features are enabled -- PML depends on them to work.
6242 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6246 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6247 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6248 kvm_x86_ops
->flush_log_dirty
= NULL
;
6249 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6252 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6254 return alloc_kvm_area();
6257 free_page((unsigned long)vmx_vmwrite_bitmap
);
6259 free_page((unsigned long)vmx_vmread_bitmap
);
6262 free_page((unsigned long)vmx_msr_bitmap_nested
);
6264 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6266 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6268 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6270 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6272 free_page((unsigned long)vmx_io_bitmap_b
);
6274 free_page((unsigned long)vmx_io_bitmap_a
);
6279 static __exit
void hardware_unsetup(void)
6281 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6282 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6283 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6284 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6285 free_page((unsigned long)vmx_io_bitmap_b
);
6286 free_page((unsigned long)vmx_io_bitmap_a
);
6287 free_page((unsigned long)vmx_vmwrite_bitmap
);
6288 free_page((unsigned long)vmx_vmread_bitmap
);
6290 free_page((unsigned long)vmx_msr_bitmap_nested
);
6296 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6297 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6299 static int handle_pause(struct kvm_vcpu
*vcpu
)
6302 grow_ple_window(vcpu
);
6304 skip_emulated_instruction(vcpu
);
6305 kvm_vcpu_on_spin(vcpu
);
6310 static int handle_nop(struct kvm_vcpu
*vcpu
)
6312 skip_emulated_instruction(vcpu
);
6316 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6318 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6319 return handle_nop(vcpu
);
6322 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6327 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6329 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6330 return handle_nop(vcpu
);
6334 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6335 * We could reuse a single VMCS for all the L2 guests, but we also want the
6336 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6337 * allows keeping them loaded on the processor, and in the future will allow
6338 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6339 * every entry if they never change.
6340 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6341 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6343 * The following functions allocate and free a vmcs02 in this pool.
6346 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6347 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6349 struct vmcs02_list
*item
;
6350 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6351 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6352 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6353 return &item
->vmcs02
;
6356 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6357 /* Recycle the least recently used VMCS. */
6358 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6359 struct vmcs02_list
, list
);
6360 item
->vmptr
= vmx
->nested
.current_vmptr
;
6361 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6362 return &item
->vmcs02
;
6365 /* Create a new VMCS */
6366 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6369 item
->vmcs02
.vmcs
= alloc_vmcs();
6370 if (!item
->vmcs02
.vmcs
) {
6374 loaded_vmcs_init(&item
->vmcs02
);
6375 item
->vmptr
= vmx
->nested
.current_vmptr
;
6376 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6377 vmx
->nested
.vmcs02_num
++;
6378 return &item
->vmcs02
;
6381 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6382 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6384 struct vmcs02_list
*item
;
6385 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6386 if (item
->vmptr
== vmptr
) {
6387 free_loaded_vmcs(&item
->vmcs02
);
6388 list_del(&item
->list
);
6390 vmx
->nested
.vmcs02_num
--;
6396 * Free all VMCSs saved for this vcpu, except the one pointed by
6397 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6398 * must be &vmx->vmcs01.
6400 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6402 struct vmcs02_list
*item
, *n
;
6404 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6405 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6407 * Something will leak if the above WARN triggers. Better than
6410 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6413 free_loaded_vmcs(&item
->vmcs02
);
6414 list_del(&item
->list
);
6416 vmx
->nested
.vmcs02_num
--;
6421 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6422 * set the success or error code of an emulated VMX instruction, as specified
6423 * by Vol 2B, VMX Instruction Reference, "Conventions".
6425 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6427 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6428 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6429 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6432 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6434 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6435 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6436 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6440 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6441 u32 vm_instruction_error
)
6443 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6445 * failValid writes the error number to the current VMCS, which
6446 * can't be done there isn't a current VMCS.
6448 nested_vmx_failInvalid(vcpu
);
6451 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6452 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6453 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6455 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6457 * We don't need to force a shadow sync because
6458 * VM_INSTRUCTION_ERROR is not shadowed
6462 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6464 /* TODO: not to reset guest simply here. */
6465 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6466 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6469 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6471 struct vcpu_vmx
*vmx
=
6472 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6474 vmx
->nested
.preemption_timer_expired
= true;
6475 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6476 kvm_vcpu_kick(&vmx
->vcpu
);
6478 return HRTIMER_NORESTART
;
6482 * Decode the memory-address operand of a vmx instruction, as recorded on an
6483 * exit caused by such an instruction (run by a guest hypervisor).
6484 * On success, returns 0. When the operand is invalid, returns 1 and throws
6487 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6488 unsigned long exit_qualification
,
6489 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6493 struct kvm_segment s
;
6496 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6497 * Execution", on an exit, vmx_instruction_info holds most of the
6498 * addressing components of the operand. Only the displacement part
6499 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6500 * For how an actual address is calculated from all these components,
6501 * refer to Vol. 1, "Operand Addressing".
6503 int scaling
= vmx_instruction_info
& 3;
6504 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6505 bool is_reg
= vmx_instruction_info
& (1u << 10);
6506 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6507 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6508 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6509 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6510 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6513 kvm_queue_exception(vcpu
, UD_VECTOR
);
6517 /* Addr = segment_base + offset */
6518 /* offset = base + [index * scale] + displacement */
6519 off
= exit_qualification
; /* holds the displacement */
6521 off
+= kvm_register_read(vcpu
, base_reg
);
6523 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6524 vmx_get_segment(vcpu
, &s
, seg_reg
);
6525 *ret
= s
.base
+ off
;
6527 if (addr_size
== 1) /* 32 bit */
6530 /* Checks for #GP/#SS exceptions. */
6532 if (is_protmode(vcpu
)) {
6533 /* Protected mode: apply checks for segment validity in the
6535 * - segment type check (#GP(0) may be thrown)
6536 * - usability check (#GP(0)/#SS(0))
6537 * - limit check (#GP(0)/#SS(0))
6540 /* #GP(0) if the destination operand is located in a
6541 * read-only data segment or any code segment.
6543 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6545 /* #GP(0) if the source operand is located in an
6546 * execute-only code segment
6548 exn
= ((s
.type
& 0xa) == 8);
6551 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6554 if (is_long_mode(vcpu
)) {
6555 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6556 * non-canonical form. This is an only check for long mode.
6558 exn
= is_noncanonical_address(*ret
);
6559 } else if (is_protmode(vcpu
)) {
6560 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6562 exn
= (s
.unusable
!= 0);
6563 /* Protected mode: #GP(0)/#SS(0) if the memory
6564 * operand is outside the segment limit.
6566 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6569 kvm_queue_exception_e(vcpu
,
6570 seg_reg
== VCPU_SREG_SS
?
6571 SS_VECTOR
: GP_VECTOR
,
6580 * This function performs the various checks including
6581 * - if it's 4KB aligned
6582 * - No bits beyond the physical address width are set
6583 * - Returns 0 on success or else 1
6584 * (Intel SDM Section 30.3)
6586 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6591 struct x86_exception e
;
6593 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6594 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6596 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6597 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6600 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6601 sizeof(vmptr
), &e
)) {
6602 kvm_inject_page_fault(vcpu
, &e
);
6606 switch (exit_reason
) {
6607 case EXIT_REASON_VMON
:
6610 * The first 4 bytes of VMXON region contain the supported
6611 * VMCS revision identifier
6613 * Note - IA32_VMX_BASIC[48] will never be 1
6614 * for the nested case;
6615 * which replaces physical address width with 32
6618 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6619 nested_vmx_failInvalid(vcpu
);
6620 skip_emulated_instruction(vcpu
);
6624 page
= nested_get_page(vcpu
, vmptr
);
6626 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6627 nested_vmx_failInvalid(vcpu
);
6629 skip_emulated_instruction(vcpu
);
6633 vmx
->nested
.vmxon_ptr
= vmptr
;
6635 case EXIT_REASON_VMCLEAR
:
6636 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6637 nested_vmx_failValid(vcpu
,
6638 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6639 skip_emulated_instruction(vcpu
);
6643 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6644 nested_vmx_failValid(vcpu
,
6645 VMXERR_VMCLEAR_VMXON_POINTER
);
6646 skip_emulated_instruction(vcpu
);
6650 case EXIT_REASON_VMPTRLD
:
6651 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6652 nested_vmx_failValid(vcpu
,
6653 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6654 skip_emulated_instruction(vcpu
);
6658 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6659 nested_vmx_failValid(vcpu
,
6660 VMXERR_VMCLEAR_VMXON_POINTER
);
6661 skip_emulated_instruction(vcpu
);
6666 return 1; /* shouldn't happen */
6675 * Emulate the VMXON instruction.
6676 * Currently, we just remember that VMX is active, and do not save or even
6677 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6678 * do not currently need to store anything in that guest-allocated memory
6679 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6680 * argument is different from the VMXON pointer (which the spec says they do).
6682 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6684 struct kvm_segment cs
;
6685 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6686 struct vmcs
*shadow_vmcs
;
6687 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6688 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6690 /* The Intel VMX Instruction Reference lists a bunch of bits that
6691 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6692 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6693 * Otherwise, we should fail with #UD. We test these now:
6695 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6696 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6697 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6698 kvm_queue_exception(vcpu
, UD_VECTOR
);
6702 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6703 if (is_long_mode(vcpu
) && !cs
.l
) {
6704 kvm_queue_exception(vcpu
, UD_VECTOR
);
6708 if (vmx_get_cpl(vcpu
)) {
6709 kvm_inject_gp(vcpu
, 0);
6713 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6716 if (vmx
->nested
.vmxon
) {
6717 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6718 skip_emulated_instruction(vcpu
);
6722 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6723 != VMXON_NEEDED_FEATURES
) {
6724 kvm_inject_gp(vcpu
, 0);
6728 if (enable_shadow_vmcs
) {
6729 shadow_vmcs
= alloc_vmcs();
6732 /* mark vmcs as shadow */
6733 shadow_vmcs
->revision_id
|= (1u << 31);
6734 /* init shadow vmcs */
6735 vmcs_clear(shadow_vmcs
);
6736 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6739 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6740 vmx
->nested
.vmcs02_num
= 0;
6742 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6744 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6746 vmx
->nested
.vmxon
= true;
6748 skip_emulated_instruction(vcpu
);
6749 nested_vmx_succeed(vcpu
);
6754 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6755 * for running VMX instructions (except VMXON, whose prerequisites are
6756 * slightly different). It also specifies what exception to inject otherwise.
6758 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6760 struct kvm_segment cs
;
6761 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6763 if (!vmx
->nested
.vmxon
) {
6764 kvm_queue_exception(vcpu
, UD_VECTOR
);
6768 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6769 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6770 (is_long_mode(vcpu
) && !cs
.l
)) {
6771 kvm_queue_exception(vcpu
, UD_VECTOR
);
6775 if (vmx_get_cpl(vcpu
)) {
6776 kvm_inject_gp(vcpu
, 0);
6783 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6785 if (vmx
->nested
.current_vmptr
== -1ull)
6788 /* current_vmptr and current_vmcs12 are always set/reset together */
6789 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6792 if (enable_shadow_vmcs
) {
6793 /* copy to memory all shadowed fields in case
6794 they were modified */
6795 copy_shadow_to_vmcs12(vmx
);
6796 vmx
->nested
.sync_shadow_vmcs
= false;
6797 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6798 SECONDARY_EXEC_SHADOW_VMCS
);
6799 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6801 vmx
->nested
.posted_intr_nv
= -1;
6802 kunmap(vmx
->nested
.current_vmcs12_page
);
6803 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6804 vmx
->nested
.current_vmptr
= -1ull;
6805 vmx
->nested
.current_vmcs12
= NULL
;
6809 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6810 * just stops using VMX.
6812 static void free_nested(struct vcpu_vmx
*vmx
)
6814 if (!vmx
->nested
.vmxon
)
6817 vmx
->nested
.vmxon
= false;
6818 nested_release_vmcs12(vmx
);
6819 if (enable_shadow_vmcs
)
6820 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6821 /* Unpin physical memory we referred to in current vmcs02 */
6822 if (vmx
->nested
.apic_access_page
) {
6823 nested_release_page(vmx
->nested
.apic_access_page
);
6824 vmx
->nested
.apic_access_page
= NULL
;
6826 if (vmx
->nested
.virtual_apic_page
) {
6827 nested_release_page(vmx
->nested
.virtual_apic_page
);
6828 vmx
->nested
.virtual_apic_page
= NULL
;
6830 if (vmx
->nested
.pi_desc_page
) {
6831 kunmap(vmx
->nested
.pi_desc_page
);
6832 nested_release_page(vmx
->nested
.pi_desc_page
);
6833 vmx
->nested
.pi_desc_page
= NULL
;
6834 vmx
->nested
.pi_desc
= NULL
;
6837 nested_free_all_saved_vmcss(vmx
);
6840 /* Emulate the VMXOFF instruction */
6841 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6843 if (!nested_vmx_check_permission(vcpu
))
6845 free_nested(to_vmx(vcpu
));
6846 skip_emulated_instruction(vcpu
);
6847 nested_vmx_succeed(vcpu
);
6851 /* Emulate the VMCLEAR instruction */
6852 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6854 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6856 struct vmcs12
*vmcs12
;
6859 if (!nested_vmx_check_permission(vcpu
))
6862 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6865 if (vmptr
== vmx
->nested
.current_vmptr
)
6866 nested_release_vmcs12(vmx
);
6868 page
= nested_get_page(vcpu
, vmptr
);
6871 * For accurate processor emulation, VMCLEAR beyond available
6872 * physical memory should do nothing at all. However, it is
6873 * possible that a nested vmx bug, not a guest hypervisor bug,
6874 * resulted in this case, so let's shut down before doing any
6877 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6880 vmcs12
= kmap(page
);
6881 vmcs12
->launch_state
= 0;
6883 nested_release_page(page
);
6885 nested_free_vmcs02(vmx
, vmptr
);
6887 skip_emulated_instruction(vcpu
);
6888 nested_vmx_succeed(vcpu
);
6892 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6894 /* Emulate the VMLAUNCH instruction */
6895 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6897 return nested_vmx_run(vcpu
, true);
6900 /* Emulate the VMRESUME instruction */
6901 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6904 return nested_vmx_run(vcpu
, false);
6907 enum vmcs_field_type
{
6908 VMCS_FIELD_TYPE_U16
= 0,
6909 VMCS_FIELD_TYPE_U64
= 1,
6910 VMCS_FIELD_TYPE_U32
= 2,
6911 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6914 static inline int vmcs_field_type(unsigned long field
)
6916 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6917 return VMCS_FIELD_TYPE_U32
;
6918 return (field
>> 13) & 0x3 ;
6921 static inline int vmcs_field_readonly(unsigned long field
)
6923 return (((field
>> 10) & 0x3) == 1);
6927 * Read a vmcs12 field. Since these can have varying lengths and we return
6928 * one type, we chose the biggest type (u64) and zero-extend the return value
6929 * to that size. Note that the caller, handle_vmread, might need to use only
6930 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6931 * 64-bit fields are to be returned).
6933 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6934 unsigned long field
, u64
*ret
)
6936 short offset
= vmcs_field_to_offset(field
);
6942 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6944 switch (vmcs_field_type(field
)) {
6945 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6946 *ret
= *((natural_width
*)p
);
6948 case VMCS_FIELD_TYPE_U16
:
6951 case VMCS_FIELD_TYPE_U32
:
6954 case VMCS_FIELD_TYPE_U64
:
6964 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6965 unsigned long field
, u64 field_value
){
6966 short offset
= vmcs_field_to_offset(field
);
6967 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6971 switch (vmcs_field_type(field
)) {
6972 case VMCS_FIELD_TYPE_U16
:
6973 *(u16
*)p
= field_value
;
6975 case VMCS_FIELD_TYPE_U32
:
6976 *(u32
*)p
= field_value
;
6978 case VMCS_FIELD_TYPE_U64
:
6979 *(u64
*)p
= field_value
;
6981 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6982 *(natural_width
*)p
= field_value
;
6991 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6994 unsigned long field
;
6996 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6997 const unsigned long *fields
= shadow_read_write_fields
;
6998 const int num_fields
= max_shadow_read_write_fields
;
7002 vmcs_load(shadow_vmcs
);
7004 for (i
= 0; i
< num_fields
; i
++) {
7006 switch (vmcs_field_type(field
)) {
7007 case VMCS_FIELD_TYPE_U16
:
7008 field_value
= vmcs_read16(field
);
7010 case VMCS_FIELD_TYPE_U32
:
7011 field_value
= vmcs_read32(field
);
7013 case VMCS_FIELD_TYPE_U64
:
7014 field_value
= vmcs_read64(field
);
7016 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7017 field_value
= vmcs_readl(field
);
7023 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7026 vmcs_clear(shadow_vmcs
);
7027 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7032 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7034 const unsigned long *fields
[] = {
7035 shadow_read_write_fields
,
7036 shadow_read_only_fields
7038 const int max_fields
[] = {
7039 max_shadow_read_write_fields
,
7040 max_shadow_read_only_fields
7043 unsigned long field
;
7044 u64 field_value
= 0;
7045 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7047 vmcs_load(shadow_vmcs
);
7049 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7050 for (i
= 0; i
< max_fields
[q
]; i
++) {
7051 field
= fields
[q
][i
];
7052 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7054 switch (vmcs_field_type(field
)) {
7055 case VMCS_FIELD_TYPE_U16
:
7056 vmcs_write16(field
, (u16
)field_value
);
7058 case VMCS_FIELD_TYPE_U32
:
7059 vmcs_write32(field
, (u32
)field_value
);
7061 case VMCS_FIELD_TYPE_U64
:
7062 vmcs_write64(field
, (u64
)field_value
);
7064 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7065 vmcs_writel(field
, (long)field_value
);
7074 vmcs_clear(shadow_vmcs
);
7075 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7079 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7080 * used before) all generate the same failure when it is missing.
7082 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7085 if (vmx
->nested
.current_vmptr
== -1ull) {
7086 nested_vmx_failInvalid(vcpu
);
7087 skip_emulated_instruction(vcpu
);
7093 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7095 unsigned long field
;
7097 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7098 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7101 if (!nested_vmx_check_permission(vcpu
) ||
7102 !nested_vmx_check_vmcs12(vcpu
))
7105 /* Decode instruction info and find the field to read */
7106 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7107 /* Read the field, zero-extended to a u64 field_value */
7108 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7109 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7110 skip_emulated_instruction(vcpu
);
7114 * Now copy part of this value to register or memory, as requested.
7115 * Note that the number of bits actually copied is 32 or 64 depending
7116 * on the guest's mode (32 or 64 bit), not on the given field's length.
7118 if (vmx_instruction_info
& (1u << 10)) {
7119 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7122 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7123 vmx_instruction_info
, true, &gva
))
7125 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7126 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7127 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7130 nested_vmx_succeed(vcpu
);
7131 skip_emulated_instruction(vcpu
);
7136 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7138 unsigned long field
;
7140 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7141 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7142 /* The value to write might be 32 or 64 bits, depending on L1's long
7143 * mode, and eventually we need to write that into a field of several
7144 * possible lengths. The code below first zero-extends the value to 64
7145 * bit (field_value), and then copies only the approriate number of
7146 * bits into the vmcs12 field.
7148 u64 field_value
= 0;
7149 struct x86_exception e
;
7151 if (!nested_vmx_check_permission(vcpu
) ||
7152 !nested_vmx_check_vmcs12(vcpu
))
7155 if (vmx_instruction_info
& (1u << 10))
7156 field_value
= kvm_register_readl(vcpu
,
7157 (((vmx_instruction_info
) >> 3) & 0xf));
7159 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7160 vmx_instruction_info
, false, &gva
))
7162 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7163 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7164 kvm_inject_page_fault(vcpu
, &e
);
7170 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7171 if (vmcs_field_readonly(field
)) {
7172 nested_vmx_failValid(vcpu
,
7173 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7174 skip_emulated_instruction(vcpu
);
7178 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7179 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7180 skip_emulated_instruction(vcpu
);
7184 nested_vmx_succeed(vcpu
);
7185 skip_emulated_instruction(vcpu
);
7189 /* Emulate the VMPTRLD instruction */
7190 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7192 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7195 if (!nested_vmx_check_permission(vcpu
))
7198 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7201 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7202 struct vmcs12
*new_vmcs12
;
7204 page
= nested_get_page(vcpu
, vmptr
);
7206 nested_vmx_failInvalid(vcpu
);
7207 skip_emulated_instruction(vcpu
);
7210 new_vmcs12
= kmap(page
);
7211 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7213 nested_release_page_clean(page
);
7214 nested_vmx_failValid(vcpu
,
7215 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7216 skip_emulated_instruction(vcpu
);
7220 nested_release_vmcs12(vmx
);
7221 vmx
->nested
.current_vmptr
= vmptr
;
7222 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7223 vmx
->nested
.current_vmcs12_page
= page
;
7224 if (enable_shadow_vmcs
) {
7225 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7226 SECONDARY_EXEC_SHADOW_VMCS
);
7227 vmcs_write64(VMCS_LINK_POINTER
,
7228 __pa(vmx
->nested
.current_shadow_vmcs
));
7229 vmx
->nested
.sync_shadow_vmcs
= true;
7233 nested_vmx_succeed(vcpu
);
7234 skip_emulated_instruction(vcpu
);
7238 /* Emulate the VMPTRST instruction */
7239 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7241 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7242 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7244 struct x86_exception e
;
7246 if (!nested_vmx_check_permission(vcpu
))
7249 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7250 vmx_instruction_info
, true, &vmcs_gva
))
7252 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7253 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7254 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7256 kvm_inject_page_fault(vcpu
, &e
);
7259 nested_vmx_succeed(vcpu
);
7260 skip_emulated_instruction(vcpu
);
7264 /* Emulate the INVEPT instruction */
7265 static int handle_invept(struct kvm_vcpu
*vcpu
)
7267 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7268 u32 vmx_instruction_info
, types
;
7271 struct x86_exception e
;
7276 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7277 SECONDARY_EXEC_ENABLE_EPT
) ||
7278 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7279 kvm_queue_exception(vcpu
, UD_VECTOR
);
7283 if (!nested_vmx_check_permission(vcpu
))
7286 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7287 kvm_queue_exception(vcpu
, UD_VECTOR
);
7291 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7292 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7294 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7296 if (!(types
& (1UL << type
))) {
7297 nested_vmx_failValid(vcpu
,
7298 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7302 /* According to the Intel VMX instruction reference, the memory
7303 * operand is read even if it isn't needed (e.g., for type==global)
7305 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7306 vmx_instruction_info
, false, &gva
))
7308 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7309 sizeof(operand
), &e
)) {
7310 kvm_inject_page_fault(vcpu
, &e
);
7315 case VMX_EPT_EXTENT_GLOBAL
:
7316 kvm_mmu_sync_roots(vcpu
);
7317 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7318 nested_vmx_succeed(vcpu
);
7321 /* Trap single context invalidation invept calls */
7326 skip_emulated_instruction(vcpu
);
7330 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7332 kvm_queue_exception(vcpu
, UD_VECTOR
);
7336 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7338 unsigned long exit_qualification
;
7340 trace_kvm_pml_full(vcpu
->vcpu_id
);
7342 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7345 * PML buffer FULL happened while executing iret from NMI,
7346 * "blocked by NMI" bit has to be set before next VM entry.
7348 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7349 cpu_has_virtual_nmis() &&
7350 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7351 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7352 GUEST_INTR_STATE_NMI
);
7355 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7356 * here.., and there's no userspace involvement needed for PML.
7361 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7363 /* we never catch pcommit instruct for L1 guest. */
7369 * The exit handlers return 1 if the exit was handled fully and guest execution
7370 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7371 * to be done to userspace and return 0.
7373 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7374 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7375 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7376 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7377 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7378 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7379 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7380 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7381 [EXIT_REASON_CPUID
] = handle_cpuid
,
7382 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7383 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7384 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7385 [EXIT_REASON_HLT
] = handle_halt
,
7386 [EXIT_REASON_INVD
] = handle_invd
,
7387 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7388 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7389 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7390 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7391 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7392 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7393 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7394 [EXIT_REASON_VMREAD
] = handle_vmread
,
7395 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7396 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7397 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7398 [EXIT_REASON_VMON
] = handle_vmon
,
7399 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7400 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7401 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7402 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7403 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7404 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7405 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7406 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7407 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7408 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7409 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7410 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7411 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7412 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7413 [EXIT_REASON_INVEPT
] = handle_invept
,
7414 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7415 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7416 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7417 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7418 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7421 static const int kvm_vmx_max_exit_handlers
=
7422 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7424 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7425 struct vmcs12
*vmcs12
)
7427 unsigned long exit_qualification
;
7428 gpa_t bitmap
, last_bitmap
;
7433 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7434 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7436 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7438 port
= exit_qualification
>> 16;
7439 size
= (exit_qualification
& 7) + 1;
7441 last_bitmap
= (gpa_t
)-1;
7446 bitmap
= vmcs12
->io_bitmap_a
;
7447 else if (port
< 0x10000)
7448 bitmap
= vmcs12
->io_bitmap_b
;
7451 bitmap
+= (port
& 0x7fff) / 8;
7453 if (last_bitmap
!= bitmap
)
7454 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7456 if (b
& (1 << (port
& 7)))
7461 last_bitmap
= bitmap
;
7468 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7469 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7470 * disinterest in the current event (read or write a specific MSR) by using an
7471 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7473 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7474 struct vmcs12
*vmcs12
, u32 exit_reason
)
7476 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7479 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7483 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7484 * for the four combinations of read/write and low/high MSR numbers.
7485 * First we need to figure out which of the four to use:
7487 bitmap
= vmcs12
->msr_bitmap
;
7488 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7490 if (msr_index
>= 0xc0000000) {
7491 msr_index
-= 0xc0000000;
7495 /* Then read the msr_index'th bit from this bitmap: */
7496 if (msr_index
< 1024*8) {
7498 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7500 return 1 & (b
>> (msr_index
& 7));
7502 return true; /* let L1 handle the wrong parameter */
7506 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7507 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7508 * intercept (via guest_host_mask etc.) the current event.
7510 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7511 struct vmcs12
*vmcs12
)
7513 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7514 int cr
= exit_qualification
& 15;
7515 int reg
= (exit_qualification
>> 8) & 15;
7516 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7518 switch ((exit_qualification
>> 4) & 3) {
7519 case 0: /* mov to cr */
7522 if (vmcs12
->cr0_guest_host_mask
&
7523 (val
^ vmcs12
->cr0_read_shadow
))
7527 if ((vmcs12
->cr3_target_count
>= 1 &&
7528 vmcs12
->cr3_target_value0
== val
) ||
7529 (vmcs12
->cr3_target_count
>= 2 &&
7530 vmcs12
->cr3_target_value1
== val
) ||
7531 (vmcs12
->cr3_target_count
>= 3 &&
7532 vmcs12
->cr3_target_value2
== val
) ||
7533 (vmcs12
->cr3_target_count
>= 4 &&
7534 vmcs12
->cr3_target_value3
== val
))
7536 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7540 if (vmcs12
->cr4_guest_host_mask
&
7541 (vmcs12
->cr4_read_shadow
^ val
))
7545 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7551 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7552 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7555 case 1: /* mov from cr */
7558 if (vmcs12
->cpu_based_vm_exec_control
&
7559 CPU_BASED_CR3_STORE_EXITING
)
7563 if (vmcs12
->cpu_based_vm_exec_control
&
7564 CPU_BASED_CR8_STORE_EXITING
)
7571 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7572 * cr0. Other attempted changes are ignored, with no exit.
7574 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7575 (val
^ vmcs12
->cr0_read_shadow
))
7577 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7578 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7587 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7588 * should handle it ourselves in L0 (and then continue L2). Only call this
7589 * when in is_guest_mode (L2).
7591 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7593 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7594 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7595 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7596 u32 exit_reason
= vmx
->exit_reason
;
7598 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7599 vmcs_readl(EXIT_QUALIFICATION
),
7600 vmx
->idt_vectoring_info
,
7602 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7605 if (vmx
->nested
.nested_run_pending
)
7608 if (unlikely(vmx
->fail
)) {
7609 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7610 vmcs_read32(VM_INSTRUCTION_ERROR
));
7614 switch (exit_reason
) {
7615 case EXIT_REASON_EXCEPTION_NMI
:
7616 if (!is_exception(intr_info
))
7618 else if (is_page_fault(intr_info
))
7620 else if (is_no_device(intr_info
) &&
7621 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7623 return vmcs12
->exception_bitmap
&
7624 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7625 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7627 case EXIT_REASON_TRIPLE_FAULT
:
7629 case EXIT_REASON_PENDING_INTERRUPT
:
7630 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7631 case EXIT_REASON_NMI_WINDOW
:
7632 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7633 case EXIT_REASON_TASK_SWITCH
:
7635 case EXIT_REASON_CPUID
:
7636 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7639 case EXIT_REASON_HLT
:
7640 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7641 case EXIT_REASON_INVD
:
7643 case EXIT_REASON_INVLPG
:
7644 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7645 case EXIT_REASON_RDPMC
:
7646 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7647 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7648 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7649 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7650 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7651 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7652 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7653 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7654 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7656 * VMX instructions trap unconditionally. This allows L1 to
7657 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7660 case EXIT_REASON_CR_ACCESS
:
7661 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7662 case EXIT_REASON_DR_ACCESS
:
7663 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7664 case EXIT_REASON_IO_INSTRUCTION
:
7665 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7666 case EXIT_REASON_MSR_READ
:
7667 case EXIT_REASON_MSR_WRITE
:
7668 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7669 case EXIT_REASON_INVALID_STATE
:
7671 case EXIT_REASON_MWAIT_INSTRUCTION
:
7672 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7673 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7674 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7675 case EXIT_REASON_MONITOR_INSTRUCTION
:
7676 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7677 case EXIT_REASON_PAUSE_INSTRUCTION
:
7678 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7679 nested_cpu_has2(vmcs12
,
7680 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7681 case EXIT_REASON_MCE_DURING_VMENTRY
:
7683 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7684 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7685 case EXIT_REASON_APIC_ACCESS
:
7686 return nested_cpu_has2(vmcs12
,
7687 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7688 case EXIT_REASON_APIC_WRITE
:
7689 case EXIT_REASON_EOI_INDUCED
:
7690 /* apic_write and eoi_induced should exit unconditionally. */
7692 case EXIT_REASON_EPT_VIOLATION
:
7694 * L0 always deals with the EPT violation. If nested EPT is
7695 * used, and the nested mmu code discovers that the address is
7696 * missing in the guest EPT table (EPT12), the EPT violation
7697 * will be injected with nested_ept_inject_page_fault()
7700 case EXIT_REASON_EPT_MISCONFIG
:
7702 * L2 never uses directly L1's EPT, but rather L0's own EPT
7703 * table (shadow on EPT) or a merged EPT table that L0 built
7704 * (EPT on EPT). So any problems with the structure of the
7705 * table is L0's fault.
7708 case EXIT_REASON_WBINVD
:
7709 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7710 case EXIT_REASON_XSETBV
:
7712 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7714 * This should never happen, since it is not possible to
7715 * set XSS to a non-zero value---neither in L1 nor in L2.
7716 * If if it were, XSS would have to be checked against
7717 * the XSS exit bitmap in vmcs12.
7719 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7720 case EXIT_REASON_PCOMMIT
:
7721 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
7727 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7729 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7730 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7733 static int vmx_enable_pml(struct vcpu_vmx
*vmx
)
7735 struct page
*pml_pg
;
7737 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7741 vmx
->pml_pg
= pml_pg
;
7743 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7744 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7746 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_ENABLE_PML
);
7751 static void vmx_disable_pml(struct vcpu_vmx
*vmx
)
7753 ASSERT(vmx
->pml_pg
);
7754 __free_page(vmx
->pml_pg
);
7757 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_ENABLE_PML
);
7760 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7766 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7768 /* Do nothing if PML buffer is empty */
7769 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7772 /* PML index always points to next available PML buffer entity */
7773 if (pml_idx
>= PML_ENTITY_NUM
)
7778 pml_buf
= page_address(vmx
->pml_pg
);
7779 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7782 gpa
= pml_buf
[pml_idx
];
7783 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7784 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7787 /* reset PML index */
7788 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7792 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7793 * Called before reporting dirty_bitmap to userspace.
7795 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7798 struct kvm_vcpu
*vcpu
;
7800 * We only need to kick vcpu out of guest mode here, as PML buffer
7801 * is flushed at beginning of all VMEXITs, and it's obvious that only
7802 * vcpus running in guest are possible to have unflushed GPAs in PML
7805 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7806 kvm_vcpu_kick(vcpu
);
7809 static void vmx_dump_sel(char *name
, uint32_t sel
)
7811 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7812 name
, vmcs_read32(sel
),
7813 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
7814 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
7815 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
7818 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
7820 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7821 name
, vmcs_read32(limit
),
7822 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
7825 static void dump_vmcs(void)
7827 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
7828 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
7829 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7830 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
7831 u32 secondary_exec_control
= 0;
7832 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
7833 u64 efer
= vmcs_readl(GUEST_IA32_EFER
);
7836 if (cpu_has_secondary_exec_ctrls())
7837 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7839 pr_err("*** Guest State ***\n");
7840 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7841 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
7842 vmcs_readl(CR0_GUEST_HOST_MASK
));
7843 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7844 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
7845 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
7846 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
7847 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
7849 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7850 vmcs_readl(GUEST_PDPTR0
), vmcs_readl(GUEST_PDPTR1
));
7851 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7852 vmcs_readl(GUEST_PDPTR2
), vmcs_readl(GUEST_PDPTR3
));
7854 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7855 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
7856 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7857 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
7858 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7859 vmcs_readl(GUEST_SYSENTER_ESP
),
7860 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
7861 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
7862 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
7863 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
7864 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
7865 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
7866 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
7867 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
7868 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
7869 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
7870 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
7871 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
7872 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
7873 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7874 efer
, vmcs_readl(GUEST_IA32_PAT
));
7875 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7876 vmcs_readl(GUEST_IA32_DEBUGCTL
),
7877 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
7878 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
7879 pr_err("PerfGlobCtl = 0x%016lx\n",
7880 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL
));
7881 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
7882 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS
));
7883 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7884 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
7885 vmcs_read32(GUEST_ACTIVITY_STATE
));
7886 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
7887 pr_err("InterruptStatus = %04x\n",
7888 vmcs_read16(GUEST_INTR_STATUS
));
7890 pr_err("*** Host State ***\n");
7891 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7892 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
7893 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7894 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
7895 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
7896 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
7897 vmcs_read16(HOST_TR_SELECTOR
));
7898 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7899 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
7900 vmcs_readl(HOST_TR_BASE
));
7901 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7902 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
7903 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7904 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
7905 vmcs_readl(HOST_CR4
));
7906 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7907 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
7908 vmcs_read32(HOST_IA32_SYSENTER_CS
),
7909 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
7910 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
7911 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7912 vmcs_readl(HOST_IA32_EFER
), vmcs_readl(HOST_IA32_PAT
));
7913 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7914 pr_err("PerfGlobCtl = 0x%016lx\n",
7915 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL
));
7917 pr_err("*** Control State ***\n");
7918 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7919 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
7920 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
7921 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7922 vmcs_read32(EXCEPTION_BITMAP
),
7923 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
7924 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
7925 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7926 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7927 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
7928 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
7929 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7930 vmcs_read32(VM_EXIT_INTR_INFO
),
7931 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7932 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
7933 pr_err(" reason=%08x qualification=%016lx\n",
7934 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
7935 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7936 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
7937 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
7938 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET
));
7939 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
7940 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
7941 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
7942 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
7943 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
7944 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER
));
7945 n
= vmcs_read32(CR3_TARGET_COUNT
);
7946 for (i
= 0; i
+ 1 < n
; i
+= 4)
7947 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7948 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
7949 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
7951 pr_err("CR3 target%u=%016lx\n",
7952 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
7953 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
7954 pr_err("PLE Gap=%08x Window=%08x\n",
7955 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
7956 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
7957 pr_err("Virtual processor ID = 0x%04x\n",
7958 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
7962 * The guest has exited. See if we can fix it or if we need userspace
7965 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7967 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7968 u32 exit_reason
= vmx
->exit_reason
;
7969 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7972 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7973 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7974 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7975 * mode as if vcpus is in root mode, the PML buffer must has been
7979 vmx_flush_pml_buffer(vcpu
);
7981 /* If guest state is invalid, start emulating */
7982 if (vmx
->emulation_required
)
7983 return handle_invalid_guest_state(vcpu
);
7985 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7986 nested_vmx_vmexit(vcpu
, exit_reason
,
7987 vmcs_read32(VM_EXIT_INTR_INFO
),
7988 vmcs_readl(EXIT_QUALIFICATION
));
7992 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7994 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7995 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8000 if (unlikely(vmx
->fail
)) {
8001 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8002 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8003 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8009 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8010 * delivery event since it indicates guest is accessing MMIO.
8011 * The vm-exit can be triggered again after return to guest that
8012 * will cause infinite loop.
8014 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8015 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8016 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8017 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8018 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8019 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8020 vcpu
->run
->internal
.ndata
= 2;
8021 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8022 vcpu
->run
->internal
.data
[1] = exit_reason
;
8026 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8027 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8028 get_vmcs12(vcpu
))))) {
8029 if (vmx_interrupt_allowed(vcpu
)) {
8030 vmx
->soft_vnmi_blocked
= 0;
8031 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8032 vcpu
->arch
.nmi_pending
) {
8034 * This CPU don't support us in finding the end of an
8035 * NMI-blocked window if the guest runs with IRQs
8036 * disabled. So we pull the trigger after 1 s of
8037 * futile waiting, but inform the user about this.
8039 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8040 "state on VCPU %d after 1 s timeout\n",
8041 __func__
, vcpu
->vcpu_id
);
8042 vmx
->soft_vnmi_blocked
= 0;
8046 if (exit_reason
< kvm_vmx_max_exit_handlers
8047 && kvm_vmx_exit_handlers
[exit_reason
])
8048 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8050 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8051 kvm_queue_exception(vcpu
, UD_VECTOR
);
8056 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8058 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8060 if (is_guest_mode(vcpu
) &&
8061 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8064 if (irr
== -1 || tpr
< irr
) {
8065 vmcs_write32(TPR_THRESHOLD
, 0);
8069 vmcs_write32(TPR_THRESHOLD
, irr
);
8072 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8074 u32 sec_exec_control
;
8077 * There is not point to enable virtualize x2apic without enable
8080 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8081 !vmx_cpu_uses_apicv(vcpu
))
8084 if (!cpu_need_tpr_shadow(vcpu
))
8087 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8090 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8091 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8093 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8094 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8096 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8098 vmx_set_msr_bitmap(vcpu
);
8101 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8103 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8106 * Currently we do not handle the nested case where L2 has an
8107 * APIC access page of its own; that page is still pinned.
8108 * Hence, we skip the case where the VCPU is in guest mode _and_
8109 * L1 prepared an APIC access page for L2.
8111 * For the case where L1 and L2 share the same APIC access page
8112 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8113 * in the vmcs12), this function will only update either the vmcs01
8114 * or the vmcs02. If the former, the vmcs02 will be updated by
8115 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8116 * the next L2->L1 exit.
8118 if (!is_guest_mode(vcpu
) ||
8119 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8120 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8121 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8124 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
8132 status
= vmcs_read16(GUEST_INTR_STATUS
);
8137 vmcs_write16(GUEST_INTR_STATUS
, status
);
8141 static void vmx_set_rvi(int vector
)
8149 status
= vmcs_read16(GUEST_INTR_STATUS
);
8150 old
= (u8
)status
& 0xff;
8151 if ((u8
)vector
!= old
) {
8153 status
|= (u8
)vector
;
8154 vmcs_write16(GUEST_INTR_STATUS
, status
);
8158 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8160 if (!is_guest_mode(vcpu
)) {
8161 vmx_set_rvi(max_irr
);
8169 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8172 if (nested_exit_on_intr(vcpu
))
8176 * Else, fall back to pre-APICv interrupt injection since L2
8177 * is run without virtual interrupt delivery.
8179 if (!kvm_event_needs_reinjection(vcpu
) &&
8180 vmx_interrupt_allowed(vcpu
)) {
8181 kvm_queue_interrupt(vcpu
, max_irr
, false);
8182 vmx_inject_irq(vcpu
);
8186 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
)
8188 u64
*eoi_exit_bitmap
= vcpu
->arch
.eoi_exit_bitmap
;
8189 if (!vmx_cpu_uses_apicv(vcpu
))
8192 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8193 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8194 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8195 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8198 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8202 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8203 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8206 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8207 exit_intr_info
= vmx
->exit_intr_info
;
8209 /* Handle machine checks before interrupts are enabled */
8210 if (is_machine_check(exit_intr_info
))
8211 kvm_machine_check();
8213 /* We need to handle NMIs before interrupts are enabled */
8214 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8215 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8216 kvm_before_handle_nmi(&vmx
->vcpu
);
8218 kvm_after_handle_nmi(&vmx
->vcpu
);
8222 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8224 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8227 * If external interrupt exists, IF bit is set in rflags/eflags on the
8228 * interrupt stack frame, and interrupt will be enabled on a return
8229 * from interrupt handler.
8231 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8232 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8233 unsigned int vector
;
8234 unsigned long entry
;
8236 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8237 #ifdef CONFIG_X86_64
8241 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8242 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8243 entry
= gate_offset(*desc
);
8245 #ifdef CONFIG_X86_64
8246 "mov %%" _ASM_SP
", %[sp]\n\t"
8247 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8252 "orl $0x200, (%%" _ASM_SP
")\n\t"
8253 __ASM_SIZE(push
) " $%c[cs]\n\t"
8254 "call *%[entry]\n\t"
8256 #ifdef CONFIG_X86_64
8261 [ss
]"i"(__KERNEL_DS
),
8262 [cs
]"i"(__KERNEL_CS
)
8268 static bool vmx_has_high_real_mode_segbase(void)
8270 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8273 static bool vmx_mpx_supported(void)
8275 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8276 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8279 static bool vmx_xsaves_supported(void)
8281 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8282 SECONDARY_EXEC_XSAVES
;
8285 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8290 bool idtv_info_valid
;
8292 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8294 if (cpu_has_virtual_nmis()) {
8295 if (vmx
->nmi_known_unmasked
)
8298 * Can't use vmx->exit_intr_info since we're not sure what
8299 * the exit reason is.
8301 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8302 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8303 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8305 * SDM 3: 27.7.1.2 (September 2008)
8306 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8307 * a guest IRET fault.
8308 * SDM 3: 23.2.2 (September 2008)
8309 * Bit 12 is undefined in any of the following cases:
8310 * If the VM exit sets the valid bit in the IDT-vectoring
8311 * information field.
8312 * If the VM exit is due to a double fault.
8314 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8315 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8316 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8317 GUEST_INTR_STATE_NMI
);
8319 vmx
->nmi_known_unmasked
=
8320 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8321 & GUEST_INTR_STATE_NMI
);
8322 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8323 vmx
->vnmi_blocked_time
+=
8324 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8327 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8328 u32 idt_vectoring_info
,
8329 int instr_len_field
,
8330 int error_code_field
)
8334 bool idtv_info_valid
;
8336 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8338 vcpu
->arch
.nmi_injected
= false;
8339 kvm_clear_exception_queue(vcpu
);
8340 kvm_clear_interrupt_queue(vcpu
);
8342 if (!idtv_info_valid
)
8345 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8347 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8348 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8351 case INTR_TYPE_NMI_INTR
:
8352 vcpu
->arch
.nmi_injected
= true;
8354 * SDM 3: 27.7.1.2 (September 2008)
8355 * Clear bit "block by NMI" before VM entry if a NMI
8358 vmx_set_nmi_mask(vcpu
, false);
8360 case INTR_TYPE_SOFT_EXCEPTION
:
8361 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8363 case INTR_TYPE_HARD_EXCEPTION
:
8364 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8365 u32 err
= vmcs_read32(error_code_field
);
8366 kvm_requeue_exception_e(vcpu
, vector
, err
);
8368 kvm_requeue_exception(vcpu
, vector
);
8370 case INTR_TYPE_SOFT_INTR
:
8371 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8373 case INTR_TYPE_EXT_INTR
:
8374 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8381 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8383 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8384 VM_EXIT_INSTRUCTION_LEN
,
8385 IDT_VECTORING_ERROR_CODE
);
8388 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8390 __vmx_complete_interrupts(vcpu
,
8391 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8392 VM_ENTRY_INSTRUCTION_LEN
,
8393 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8395 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8398 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8401 struct perf_guest_switch_msr
*msrs
;
8403 msrs
= perf_guest_get_msrs(&nr_msrs
);
8408 for (i
= 0; i
< nr_msrs
; i
++)
8409 if (msrs
[i
].host
== msrs
[i
].guest
)
8410 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8412 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8416 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8418 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8419 unsigned long debugctlmsr
, cr4
;
8421 /* Record the guest's net vcpu time for enforced NMI injections. */
8422 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8423 vmx
->entry_time
= ktime_get();
8425 /* Don't enter VMX if guest state is invalid, let the exit handler
8426 start emulation until we arrive back to a valid state */
8427 if (vmx
->emulation_required
)
8430 if (vmx
->ple_window_dirty
) {
8431 vmx
->ple_window_dirty
= false;
8432 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8435 if (vmx
->nested
.sync_shadow_vmcs
) {
8436 copy_vmcs12_to_shadow(vmx
);
8437 vmx
->nested
.sync_shadow_vmcs
= false;
8440 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8441 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8442 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8443 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8445 cr4
= cr4_read_shadow();
8446 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8447 vmcs_writel(HOST_CR4
, cr4
);
8448 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8451 /* When single-stepping over STI and MOV SS, we must clear the
8452 * corresponding interruptibility bits in the guest state. Otherwise
8453 * vmentry fails as it then expects bit 14 (BS) in pending debug
8454 * exceptions being set, but that's not correct for the guest debugging
8456 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8457 vmx_set_interrupt_shadow(vcpu
, 0);
8459 atomic_switch_perf_msrs(vmx
);
8460 debugctlmsr
= get_debugctlmsr();
8462 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8464 /* Store host registers */
8465 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8466 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8467 "push %%" _ASM_CX
" \n\t"
8468 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8470 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8471 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8473 /* Reload cr2 if changed */
8474 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8475 "mov %%cr2, %%" _ASM_DX
" \n\t"
8476 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8478 "mov %%" _ASM_AX
", %%cr2 \n\t"
8480 /* Check if vmlaunch of vmresume is needed */
8481 "cmpl $0, %c[launched](%0) \n\t"
8482 /* Load guest registers. Don't clobber flags. */
8483 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8484 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8485 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8486 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8487 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8488 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8489 #ifdef CONFIG_X86_64
8490 "mov %c[r8](%0), %%r8 \n\t"
8491 "mov %c[r9](%0), %%r9 \n\t"
8492 "mov %c[r10](%0), %%r10 \n\t"
8493 "mov %c[r11](%0), %%r11 \n\t"
8494 "mov %c[r12](%0), %%r12 \n\t"
8495 "mov %c[r13](%0), %%r13 \n\t"
8496 "mov %c[r14](%0), %%r14 \n\t"
8497 "mov %c[r15](%0), %%r15 \n\t"
8499 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8501 /* Enter guest mode */
8503 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8505 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8507 /* Save guest registers, load host registers, keep flags */
8508 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8510 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8511 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8512 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8513 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8514 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8515 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8516 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8517 #ifdef CONFIG_X86_64
8518 "mov %%r8, %c[r8](%0) \n\t"
8519 "mov %%r9, %c[r9](%0) \n\t"
8520 "mov %%r10, %c[r10](%0) \n\t"
8521 "mov %%r11, %c[r11](%0) \n\t"
8522 "mov %%r12, %c[r12](%0) \n\t"
8523 "mov %%r13, %c[r13](%0) \n\t"
8524 "mov %%r14, %c[r14](%0) \n\t"
8525 "mov %%r15, %c[r15](%0) \n\t"
8527 "mov %%cr2, %%" _ASM_AX
" \n\t"
8528 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8530 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8531 "setbe %c[fail](%0) \n\t"
8532 ".pushsection .rodata \n\t"
8533 ".global vmx_return \n\t"
8534 "vmx_return: " _ASM_PTR
" 2b \n\t"
8536 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8537 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8538 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8539 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8540 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8541 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8542 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8543 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8544 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8545 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8546 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8547 #ifdef CONFIG_X86_64
8548 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8549 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8550 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8551 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8552 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8553 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8554 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8555 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8557 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8558 [wordsize
]"i"(sizeof(ulong
))
8560 #ifdef CONFIG_X86_64
8561 , "rax", "rbx", "rdi", "rsi"
8562 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8564 , "eax", "ebx", "edi", "esi"
8568 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8570 update_debugctlmsr(debugctlmsr
);
8572 #ifndef CONFIG_X86_64
8574 * The sysexit path does not restore ds/es, so we must set them to
8575 * a reasonable value ourselves.
8577 * We can't defer this to vmx_load_host_state() since that function
8578 * may be executed in interrupt context, which saves and restore segments
8579 * around it, nullifying its effect.
8581 loadsegment(ds
, __USER_DS
);
8582 loadsegment(es
, __USER_DS
);
8585 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8586 | (1 << VCPU_EXREG_RFLAGS
)
8587 | (1 << VCPU_EXREG_PDPTR
)
8588 | (1 << VCPU_EXREG_SEGMENTS
)
8589 | (1 << VCPU_EXREG_CR3
));
8590 vcpu
->arch
.regs_dirty
= 0;
8592 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8594 vmx
->loaded_vmcs
->launched
= 1;
8596 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8597 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
8600 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8601 * we did not inject a still-pending event to L1 now because of
8602 * nested_run_pending, we need to re-enable this bit.
8604 if (vmx
->nested
.nested_run_pending
)
8605 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8607 vmx
->nested
.nested_run_pending
= 0;
8609 vmx_complete_atomic_exit(vmx
);
8610 vmx_recover_nmi_blocking(vmx
);
8611 vmx_complete_interrupts(vmx
);
8614 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8616 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8619 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8623 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8625 vmx_vcpu_load(vcpu
, cpu
);
8630 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8632 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8635 vmx_disable_pml(vmx
);
8636 free_vpid(vmx
->vpid
);
8637 leave_guest_mode(vcpu
);
8638 vmx_load_vmcs01(vcpu
);
8640 free_loaded_vmcs(vmx
->loaded_vmcs
);
8641 kfree(vmx
->guest_msrs
);
8642 kvm_vcpu_uninit(vcpu
);
8643 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8646 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8649 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8653 return ERR_PTR(-ENOMEM
);
8655 vmx
->vpid
= allocate_vpid();
8657 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8661 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8662 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8666 if (!vmx
->guest_msrs
) {
8670 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8671 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8672 if (!vmx
->loaded_vmcs
->vmcs
)
8675 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8676 loaded_vmcs_init(vmx
->loaded_vmcs
);
8681 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8682 vmx
->vcpu
.cpu
= cpu
;
8683 err
= vmx_vcpu_setup(vmx
);
8684 vmx_vcpu_put(&vmx
->vcpu
);
8688 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8689 err
= alloc_apic_access_page(kvm
);
8695 if (!kvm
->arch
.ept_identity_map_addr
)
8696 kvm
->arch
.ept_identity_map_addr
=
8697 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8698 err
= init_rmode_identity_map(kvm
);
8704 nested_vmx_setup_ctls_msrs(vmx
);
8706 vmx
->nested
.posted_intr_nv
= -1;
8707 vmx
->nested
.current_vmptr
= -1ull;
8708 vmx
->nested
.current_vmcs12
= NULL
;
8711 * If PML is turned on, failure on enabling PML just results in failure
8712 * of creating the vcpu, therefore we can simplify PML logic (by
8713 * avoiding dealing with cases, such as enabling PML partially on vcpus
8714 * for the guest, etc.
8717 err
= vmx_enable_pml(vmx
);
8725 free_loaded_vmcs(vmx
->loaded_vmcs
);
8727 kfree(vmx
->guest_msrs
);
8729 kvm_vcpu_uninit(&vmx
->vcpu
);
8731 free_vpid(vmx
->vpid
);
8732 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8733 return ERR_PTR(err
);
8736 static void __init
vmx_check_processor_compat(void *rtn
)
8738 struct vmcs_config vmcs_conf
;
8741 if (setup_vmcs_config(&vmcs_conf
) < 0)
8743 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8744 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8745 smp_processor_id());
8750 static int get_ept_level(void)
8752 return VMX_EPT_DEFAULT_GAW
+ 1;
8755 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8760 /* For VT-d and EPT combination
8761 * 1. MMIO: always map as UC
8763 * a. VT-d without snooping control feature: can't guarantee the
8764 * result, try to trust guest.
8765 * b. VT-d with snooping control feature: snooping control feature of
8766 * VT-d engine can guarantee the cache correctness. Just set it
8767 * to WB to keep consistent with host. So the same as item 3.
8768 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8769 * consistent with host MTRR
8772 cache
= MTRR_TYPE_UNCACHABLE
;
8776 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8777 ipat
= VMX_EPT_IPAT_BIT
;
8778 cache
= MTRR_TYPE_WRBACK
;
8782 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8783 ipat
= VMX_EPT_IPAT_BIT
;
8784 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
8785 cache
= MTRR_TYPE_WRBACK
;
8787 cache
= MTRR_TYPE_UNCACHABLE
;
8791 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
8794 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
8797 static int vmx_get_lpage_level(void)
8799 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8800 return PT_DIRECTORY_LEVEL
;
8802 /* For shadow and EPT supported 1GB page */
8803 return PT_PDPE_LEVEL
;
8806 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
8809 * These bits in the secondary execution controls field
8810 * are dynamic, the others are mostly based on the hypervisor
8811 * architecture and the guest's CPUID. Do not touch the
8815 SECONDARY_EXEC_SHADOW_VMCS
|
8816 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
8817 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8819 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8821 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8822 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
8825 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8827 struct kvm_cpuid_entry2
*best
;
8828 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8829 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
8831 if (vmx_rdtscp_supported()) {
8832 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
8833 if (!rdtscp_enabled
)
8834 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
8838 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8839 SECONDARY_EXEC_RDTSCP
;
8841 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8842 ~SECONDARY_EXEC_RDTSCP
;
8846 /* Exposing INVPCID only when PCID is exposed */
8847 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8848 if (vmx_invpcid_supported() &&
8849 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
8850 !guest_cpuid_has_pcid(vcpu
))) {
8851 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8854 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8857 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
8859 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
8860 if (guest_cpuid_has_pcommit(vcpu
))
8861 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8862 SECONDARY_EXEC_PCOMMIT
;
8864 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8865 ~SECONDARY_EXEC_PCOMMIT
;
8869 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8871 if (func
== 1 && nested
)
8872 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8875 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8876 struct x86_exception
*fault
)
8878 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8881 if (fault
->error_code
& PFERR_RSVD_MASK
)
8882 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8884 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8885 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8886 vmcs12
->guest_physical_address
= fault
->address
;
8889 /* Callbacks for nested_ept_init_mmu_context: */
8891 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8893 /* return the page table to be shadowed - in our case, EPT12 */
8894 return get_vmcs12(vcpu
)->ept_pointer
;
8897 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8899 WARN_ON(mmu_is_nested(vcpu
));
8900 kvm_init_shadow_ept_mmu(vcpu
,
8901 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
8902 VMX_EPT_EXECUTE_ONLY_BIT
);
8903 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8904 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8905 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8907 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8910 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8912 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
8918 bool inequality
, bit
;
8920 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
8922 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
8923 vmcs12
->page_fault_error_code_match
;
8924 return inequality
^ bit
;
8927 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
8928 struct x86_exception
*fault
)
8930 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8932 WARN_ON(!is_guest_mode(vcpu
));
8934 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
8935 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
8936 vmcs_read32(VM_EXIT_INTR_INFO
),
8937 vmcs_readl(EXIT_QUALIFICATION
));
8939 kvm_inject_page_fault(vcpu
, fault
);
8942 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
8943 struct vmcs12
*vmcs12
)
8945 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8946 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8948 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8949 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
8950 vmcs12
->apic_access_addr
>> maxphyaddr
)
8954 * Translate L1 physical address to host physical
8955 * address for vmcs02. Keep the page pinned, so this
8956 * physical address remains valid. We keep a reference
8957 * to it so we can release it later.
8959 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8960 nested_release_page(vmx
->nested
.apic_access_page
);
8961 vmx
->nested
.apic_access_page
=
8962 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8965 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8966 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
8967 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
8970 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8971 nested_release_page(vmx
->nested
.virtual_apic_page
);
8972 vmx
->nested
.virtual_apic_page
=
8973 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8976 * Failing the vm entry is _not_ what the processor does
8977 * but it's basically the only possibility we have.
8978 * We could still enter the guest if CR8 load exits are
8979 * enabled, CR8 store exits are enabled, and virtualize APIC
8980 * access is disabled; in this case the processor would never
8981 * use the TPR shadow and we could simply clear the bit from
8982 * the execution control. But such a configuration is useless,
8983 * so let's keep the code simple.
8985 if (!vmx
->nested
.virtual_apic_page
)
8989 if (nested_cpu_has_posted_intr(vmcs12
)) {
8990 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
8991 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
8994 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
8995 kunmap(vmx
->nested
.pi_desc_page
);
8996 nested_release_page(vmx
->nested
.pi_desc_page
);
8998 vmx
->nested
.pi_desc_page
=
8999 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9000 if (!vmx
->nested
.pi_desc_page
)
9003 vmx
->nested
.pi_desc
=
9004 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9005 if (!vmx
->nested
.pi_desc
) {
9006 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9009 vmx
->nested
.pi_desc
=
9010 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9011 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9018 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9020 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9021 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9023 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9026 /* Make sure short timeouts reliably trigger an immediate vmexit.
9027 * hrtimer_start does not guarantee this. */
9028 if (preemption_timeout
<= 1) {
9029 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9033 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9034 preemption_timeout
*= 1000000;
9035 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9036 hrtimer_start(&vmx
->nested
.preemption_timer
,
9037 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9040 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9041 struct vmcs12
*vmcs12
)
9046 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9049 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9053 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9055 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9056 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9063 * Merge L0's and L1's MSR bitmap, return false to indicate that
9064 * we do not use the hardware.
9066 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9067 struct vmcs12
*vmcs12
)
9071 unsigned long *msr_bitmap
;
9073 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9076 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9081 msr_bitmap
= (unsigned long *)kmap(page
);
9083 nested_release_page_clean(page
);
9088 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9089 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9090 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9091 nested_vmx_disable_intercept_for_msr(
9093 vmx_msr_bitmap_nested
,
9095 /* TPR is allowed */
9096 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9097 vmx_msr_bitmap_nested
,
9098 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9099 MSR_TYPE_R
| MSR_TYPE_W
);
9100 if (nested_cpu_has_vid(vmcs12
)) {
9101 /* EOI and self-IPI are allowed */
9102 nested_vmx_disable_intercept_for_msr(
9104 vmx_msr_bitmap_nested
,
9105 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9107 nested_vmx_disable_intercept_for_msr(
9109 vmx_msr_bitmap_nested
,
9110 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9115 * Enable reading intercept of all the x2apic
9116 * MSRs. We should not rely on vmcs12 to do any
9117 * optimizations here, it may have been modified
9120 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9121 __vmx_enable_intercept_for_msr(
9122 vmx_msr_bitmap_nested
,
9126 __vmx_enable_intercept_for_msr(
9127 vmx_msr_bitmap_nested
,
9128 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9130 __vmx_enable_intercept_for_msr(
9131 vmx_msr_bitmap_nested
,
9132 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9134 __vmx_enable_intercept_for_msr(
9135 vmx_msr_bitmap_nested
,
9136 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9140 nested_release_page_clean(page
);
9145 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9146 struct vmcs12
*vmcs12
)
9148 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9149 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9150 !nested_cpu_has_vid(vmcs12
) &&
9151 !nested_cpu_has_posted_intr(vmcs12
))
9155 * If virtualize x2apic mode is enabled,
9156 * virtualize apic access must be disabled.
9158 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9159 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9163 * If virtual interrupt delivery is enabled,
9164 * we must exit on external interrupts.
9166 if (nested_cpu_has_vid(vmcs12
) &&
9167 !nested_exit_on_intr(vcpu
))
9171 * bits 15:8 should be zero in posted_intr_nv,
9172 * the descriptor address has been already checked
9173 * in nested_get_vmcs12_pages.
9175 if (nested_cpu_has_posted_intr(vmcs12
) &&
9176 (!nested_cpu_has_vid(vmcs12
) ||
9177 !nested_exit_intr_ack_set(vcpu
) ||
9178 vmcs12
->posted_intr_nv
& 0xff00))
9181 /* tpr shadow is needed by all apicv features. */
9182 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9188 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9189 unsigned long count_field
,
9190 unsigned long addr_field
)
9195 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9196 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9202 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9203 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9204 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9205 pr_warn_ratelimited(
9206 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9207 addr_field
, maxphyaddr
, count
, addr
);
9213 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9214 struct vmcs12
*vmcs12
)
9216 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9217 vmcs12
->vm_exit_msr_store_count
== 0 &&
9218 vmcs12
->vm_entry_msr_load_count
== 0)
9219 return 0; /* Fast path */
9220 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9221 VM_EXIT_MSR_LOAD_ADDR
) ||
9222 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9223 VM_EXIT_MSR_STORE_ADDR
) ||
9224 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9225 VM_ENTRY_MSR_LOAD_ADDR
))
9230 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9231 struct vmx_msr_entry
*e
)
9233 /* x2APIC MSR accesses are not allowed */
9234 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9236 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9237 e
->index
== MSR_IA32_UCODE_REV
)
9239 if (e
->reserved
!= 0)
9244 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9245 struct vmx_msr_entry
*e
)
9247 if (e
->index
== MSR_FS_BASE
||
9248 e
->index
== MSR_GS_BASE
||
9249 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9250 nested_vmx_msr_check_common(vcpu
, e
))
9255 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9256 struct vmx_msr_entry
*e
)
9258 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9259 nested_vmx_msr_check_common(vcpu
, e
))
9265 * Load guest's/host's msr at nested entry/exit.
9266 * return 0 for success, entry index for failure.
9268 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9271 struct vmx_msr_entry e
;
9272 struct msr_data msr
;
9274 msr
.host_initiated
= false;
9275 for (i
= 0; i
< count
; i
++) {
9276 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9278 pr_warn_ratelimited(
9279 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9280 __func__
, i
, gpa
+ i
* sizeof(e
));
9283 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9284 pr_warn_ratelimited(
9285 "%s check failed (%u, 0x%x, 0x%x)\n",
9286 __func__
, i
, e
.index
, e
.reserved
);
9289 msr
.index
= e
.index
;
9291 if (kvm_set_msr(vcpu
, &msr
)) {
9292 pr_warn_ratelimited(
9293 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9294 __func__
, i
, e
.index
, e
.value
);
9303 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9306 struct vmx_msr_entry e
;
9308 for (i
= 0; i
< count
; i
++) {
9309 struct msr_data msr_info
;
9310 if (kvm_vcpu_read_guest(vcpu
,
9311 gpa
+ i
* sizeof(e
),
9312 &e
, 2 * sizeof(u32
))) {
9313 pr_warn_ratelimited(
9314 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9315 __func__
, i
, gpa
+ i
* sizeof(e
));
9318 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9319 pr_warn_ratelimited(
9320 "%s check failed (%u, 0x%x, 0x%x)\n",
9321 __func__
, i
, e
.index
, e
.reserved
);
9324 msr_info
.host_initiated
= false;
9325 msr_info
.index
= e
.index
;
9326 if (kvm_get_msr(vcpu
, &msr_info
)) {
9327 pr_warn_ratelimited(
9328 "%s cannot read MSR (%u, 0x%x)\n",
9329 __func__
, i
, e
.index
);
9332 if (kvm_vcpu_write_guest(vcpu
,
9333 gpa
+ i
* sizeof(e
) +
9334 offsetof(struct vmx_msr_entry
, value
),
9335 &msr_info
.data
, sizeof(msr_info
.data
))) {
9336 pr_warn_ratelimited(
9337 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9338 __func__
, i
, e
.index
, msr_info
.data
);
9346 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9347 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9348 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9349 * guest in a way that will both be appropriate to L1's requests, and our
9350 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9351 * function also has additional necessary side-effects, like setting various
9352 * vcpu->arch fields.
9354 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9356 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9359 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9360 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9361 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9362 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9363 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9364 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9365 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9366 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9367 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9368 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9369 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9370 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9371 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9372 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9373 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9374 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9375 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9376 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9377 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9378 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9379 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9380 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9381 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9382 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9383 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9384 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9385 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9386 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9387 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9388 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9389 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9390 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9391 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9392 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9393 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9394 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9396 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9397 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9398 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9400 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9401 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9404 vmcs12
->vm_entry_intr_info_field
);
9405 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9406 vmcs12
->vm_entry_exception_error_code
);
9407 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9408 vmcs12
->vm_entry_instruction_len
);
9409 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9410 vmcs12
->guest_interruptibility_info
);
9411 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9412 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9413 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9414 vmcs12
->guest_pending_dbg_exceptions
);
9415 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9416 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9418 if (nested_cpu_has_xsaves(vmcs12
))
9419 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9420 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9422 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9423 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9424 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9426 if (nested_cpu_has_posted_intr(vmcs12
)) {
9428 * Note that we use L0's vector here and in
9429 * vmx_deliver_nested_posted_interrupt.
9431 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9432 vmx
->nested
.pi_pending
= false;
9433 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9434 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9435 page_to_phys(vmx
->nested
.pi_desc_page
) +
9436 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9439 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9441 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9443 vmx
->nested
.preemption_timer_expired
= false;
9444 if (nested_cpu_has_preemption_timer(vmcs12
))
9445 vmx_start_preemption_timer(vcpu
);
9448 * Whether page-faults are trapped is determined by a combination of
9449 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9450 * If enable_ept, L0 doesn't care about page faults and we should
9451 * set all of these to L1's desires. However, if !enable_ept, L0 does
9452 * care about (at least some) page faults, and because it is not easy
9453 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9454 * to exit on each and every L2 page fault. This is done by setting
9455 * MASK=MATCH=0 and (see below) EB.PF=1.
9456 * Note that below we don't need special code to set EB.PF beyond the
9457 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9458 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9459 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9461 * A problem with this approach (when !enable_ept) is that L1 may be
9462 * injected with more page faults than it asked for. This could have
9463 * caused problems, but in practice existing hypervisors don't care.
9464 * To fix this, we will need to emulate the PFEC checking (on the L1
9465 * page tables), using walk_addr(), when injecting PFs to L1.
9467 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9468 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9469 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9470 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9472 if (cpu_has_secondary_exec_ctrls()) {
9473 exec_control
= vmx_secondary_exec_control(vmx
);
9475 /* Take the following fields only from vmcs12 */
9476 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9477 SECONDARY_EXEC_RDTSCP
|
9478 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9479 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9480 SECONDARY_EXEC_PCOMMIT
);
9481 if (nested_cpu_has(vmcs12
,
9482 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9483 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9485 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9487 * If translation failed, no matter: This feature asks
9488 * to exit when accessing the given address, and if it
9489 * can never be accessed, this feature won't do
9492 if (!vmx
->nested
.apic_access_page
)
9494 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9496 vmcs_write64(APIC_ACCESS_ADDR
,
9497 page_to_phys(vmx
->nested
.apic_access_page
));
9498 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9499 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9501 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9502 kvm_vcpu_reload_apic_access_page(vcpu
);
9505 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9506 vmcs_write64(EOI_EXIT_BITMAP0
,
9507 vmcs12
->eoi_exit_bitmap0
);
9508 vmcs_write64(EOI_EXIT_BITMAP1
,
9509 vmcs12
->eoi_exit_bitmap1
);
9510 vmcs_write64(EOI_EXIT_BITMAP2
,
9511 vmcs12
->eoi_exit_bitmap2
);
9512 vmcs_write64(EOI_EXIT_BITMAP3
,
9513 vmcs12
->eoi_exit_bitmap3
);
9514 vmcs_write16(GUEST_INTR_STATUS
,
9515 vmcs12
->guest_intr_status
);
9518 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9523 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9524 * Some constant fields are set here by vmx_set_constant_host_state().
9525 * Other fields are different per CPU, and will be set later when
9526 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9528 vmx_set_constant_host_state(vmx
);
9531 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9532 * entry, but only if the current (host) sp changed from the value
9533 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9534 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9535 * here we just force the write to happen on entry.
9539 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9540 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9541 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9542 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9543 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9545 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9546 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9547 page_to_phys(vmx
->nested
.virtual_apic_page
));
9548 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9551 if (cpu_has_vmx_msr_bitmap() &&
9552 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9553 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9554 /* MSR_BITMAP will be set by following vmx_set_efer. */
9556 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9559 * Merging of IO bitmap not currently supported.
9560 * Rather, exit every time.
9562 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9563 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9565 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9567 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9568 * bitwise-or of what L1 wants to trap for L2, and what we want to
9569 * trap. Note that CR0.TS also needs updating - we do this later.
9571 update_exception_bitmap(vcpu
);
9572 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9573 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9575 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9576 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9577 * bits are further modified by vmx_set_efer() below.
9579 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9581 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9582 * emulated by vmx_set_efer(), below.
9584 vm_entry_controls_init(vmx
,
9585 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9586 ~VM_ENTRY_IA32E_MODE
) |
9587 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9589 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9590 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9591 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9592 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9593 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9596 set_cr4_guest_host_mask(vmx
);
9598 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9599 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9601 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9602 vmcs_write64(TSC_OFFSET
,
9603 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9605 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9609 * Trivially support vpid by letting L2s share their parent
9610 * L1's vpid. TODO: move to a more elaborate solution, giving
9611 * each L2 its own vpid and exposing the vpid feature to L1.
9613 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9614 vmx_flush_tlb(vcpu
);
9617 if (nested_cpu_has_ept(vmcs12
)) {
9618 kvm_mmu_unload(vcpu
);
9619 nested_ept_init_mmu_context(vcpu
);
9622 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9623 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9624 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9625 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9627 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9628 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9629 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9632 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9633 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9634 * The CR0_READ_SHADOW is what L2 should have expected to read given
9635 * the specifications by L1; It's not enough to take
9636 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9637 * have more bits than L1 expected.
9639 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9640 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9642 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9643 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9645 /* shadow page tables on either EPT or shadow page tables */
9646 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9647 kvm_mmu_reset_context(vcpu
);
9650 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9653 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9656 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9657 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9658 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9659 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9662 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9663 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9667 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9668 * for running an L2 nested guest.
9670 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9672 struct vmcs12
*vmcs12
;
9673 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9675 struct loaded_vmcs
*vmcs02
;
9679 if (!nested_vmx_check_permission(vcpu
) ||
9680 !nested_vmx_check_vmcs12(vcpu
))
9683 skip_emulated_instruction(vcpu
);
9684 vmcs12
= get_vmcs12(vcpu
);
9686 if (enable_shadow_vmcs
)
9687 copy_shadow_to_vmcs12(vmx
);
9690 * The nested entry process starts with enforcing various prerequisites
9691 * on vmcs12 as required by the Intel SDM, and act appropriately when
9692 * they fail: As the SDM explains, some conditions should cause the
9693 * instruction to fail, while others will cause the instruction to seem
9694 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9695 * To speed up the normal (success) code path, we should avoid checking
9696 * for misconfigurations which will anyway be caught by the processor
9697 * when using the merged vmcs02.
9699 if (vmcs12
->launch_state
== launch
) {
9700 nested_vmx_failValid(vcpu
,
9701 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9702 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9706 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9707 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9708 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9712 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9713 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9717 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9718 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9722 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9723 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9727 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9728 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9732 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9733 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9734 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9735 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9736 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9737 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9738 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9739 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9740 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9741 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9742 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9743 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9744 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9745 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9746 vmx
->nested
.nested_vmx_entry_ctls_high
))
9748 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9752 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9753 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9754 nested_vmx_failValid(vcpu
,
9755 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9759 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9760 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9761 nested_vmx_entry_failure(vcpu
, vmcs12
,
9762 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9765 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9766 nested_vmx_entry_failure(vcpu
, vmcs12
,
9767 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9772 * If the load IA32_EFER VM-entry control is 1, the following checks
9773 * are performed on the field for the IA32_EFER MSR:
9774 * - Bits reserved in the IA32_EFER MSR must be 0.
9775 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9776 * the IA-32e mode guest VM-exit control. It must also be identical
9777 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9780 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9781 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9782 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9783 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9784 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9785 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9786 nested_vmx_entry_failure(vcpu
, vmcs12
,
9787 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9793 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9794 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9795 * the values of the LMA and LME bits in the field must each be that of
9796 * the host address-space size VM-exit control.
9798 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9799 ia32e
= (vmcs12
->vm_exit_controls
&
9800 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9801 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9802 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9803 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9804 nested_vmx_entry_failure(vcpu
, vmcs12
,
9805 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9811 * We're finally done with prerequisite checking, and can start with
9815 vmcs02
= nested_get_current_vmcs02(vmx
);
9819 enter_guest_mode(vcpu
);
9821 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9823 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9824 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9827 vmx
->loaded_vmcs
= vmcs02
;
9829 vmx_vcpu_load(vcpu
, cpu
);
9833 vmx_segment_cache_clear(vmx
);
9835 prepare_vmcs02(vcpu
, vmcs12
);
9837 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9838 vmcs12
->vm_entry_msr_load_addr
,
9839 vmcs12
->vm_entry_msr_load_count
);
9840 if (msr_entry_idx
) {
9841 leave_guest_mode(vcpu
);
9842 vmx_load_vmcs01(vcpu
);
9843 nested_vmx_entry_failure(vcpu
, vmcs12
,
9844 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9848 vmcs12
->launch_state
= 1;
9850 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9851 return kvm_vcpu_halt(vcpu
);
9853 vmx
->nested
.nested_run_pending
= 1;
9856 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9857 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9858 * returned as far as L1 is concerned. It will only return (and set
9859 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9865 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9866 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9867 * This function returns the new value we should put in vmcs12.guest_cr0.
9868 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9869 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9870 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9871 * didn't trap the bit, because if L1 did, so would L0).
9872 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9873 * been modified by L2, and L1 knows it. So just leave the old value of
9874 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9875 * isn't relevant, because if L0 traps this bit it can set it to anything.
9876 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9877 * changed these bits, and therefore they need to be updated, but L0
9878 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9879 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9881 static inline unsigned long
9882 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9885 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9886 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
9887 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
9888 vcpu
->arch
.cr0_guest_owned_bits
));
9891 static inline unsigned long
9892 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9895 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
9896 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
9897 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
9898 vcpu
->arch
.cr4_guest_owned_bits
));
9901 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
9902 struct vmcs12
*vmcs12
)
9907 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
9908 nr
= vcpu
->arch
.exception
.nr
;
9909 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9911 if (kvm_exception_is_soft(nr
)) {
9912 vmcs12
->vm_exit_instruction_len
=
9913 vcpu
->arch
.event_exit_inst_len
;
9914 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
9916 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
9918 if (vcpu
->arch
.exception
.has_error_code
) {
9919 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
9920 vmcs12
->idt_vectoring_error_code
=
9921 vcpu
->arch
.exception
.error_code
;
9924 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9925 } else if (vcpu
->arch
.nmi_injected
) {
9926 vmcs12
->idt_vectoring_info_field
=
9927 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
9928 } else if (vcpu
->arch
.interrupt
.pending
) {
9929 nr
= vcpu
->arch
.interrupt
.nr
;
9930 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9932 if (vcpu
->arch
.interrupt
.soft
) {
9933 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
9934 vmcs12
->vm_entry_instruction_len
=
9935 vcpu
->arch
.event_exit_inst_len
;
9937 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
9939 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9943 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
9945 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9947 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
9948 vmx
->nested
.preemption_timer_expired
) {
9949 if (vmx
->nested
.nested_run_pending
)
9951 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
9955 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
9956 if (vmx
->nested
.nested_run_pending
||
9957 vcpu
->arch
.interrupt
.pending
)
9959 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9960 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
9961 INTR_INFO_VALID_MASK
, 0);
9963 * The NMI-triggered VM exit counts as injection:
9964 * clear this one and block further NMIs.
9966 vcpu
->arch
.nmi_pending
= 0;
9967 vmx_set_nmi_mask(vcpu
, true);
9971 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
9972 nested_exit_on_intr(vcpu
)) {
9973 if (vmx
->nested
.nested_run_pending
)
9975 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
9979 return vmx_complete_nested_posted_interrupt(vcpu
);
9982 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
9985 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
9988 if (ktime_to_ns(remaining
) <= 0)
9991 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
9992 do_div(value
, 1000000);
9993 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9997 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9998 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9999 * and this function updates it to reflect the changes to the guest state while
10000 * L2 was running (and perhaps made some exits which were handled directly by L0
10001 * without going back to L1), and to reflect the exit reason.
10002 * Note that we do not have to copy here all VMCS fields, just those that
10003 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10004 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10005 * which already writes to vmcs12 directly.
10007 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10008 u32 exit_reason
, u32 exit_intr_info
,
10009 unsigned long exit_qualification
)
10011 /* update guest state fields: */
10012 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10013 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10015 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10016 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10017 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10019 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10020 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10021 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10022 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10023 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10024 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10025 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10026 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10027 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10028 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10029 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10030 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10031 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10032 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10033 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10034 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10035 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10036 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10037 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10038 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10039 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10040 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10041 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10042 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10043 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10044 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10045 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10046 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10047 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10048 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10049 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10050 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10051 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10052 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10053 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10054 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10056 vmcs12
->guest_interruptibility_info
=
10057 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10058 vmcs12
->guest_pending_dbg_exceptions
=
10059 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10060 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10061 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10063 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10065 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10066 if (vmcs12
->vm_exit_controls
&
10067 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10068 vmcs12
->vmx_preemption_timer_value
=
10069 vmx_get_preemption_timer_value(vcpu
);
10070 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10074 * In some cases (usually, nested EPT), L2 is allowed to change its
10075 * own CR3 without exiting. If it has changed it, we must keep it.
10076 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10077 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10079 * Additionally, restore L2's PDPTR to vmcs12.
10082 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
10083 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10084 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10085 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10086 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10089 if (nested_cpu_has_vid(vmcs12
))
10090 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10092 vmcs12
->vm_entry_controls
=
10093 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10094 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10096 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10097 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10098 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10101 /* TODO: These cannot have changed unless we have MSR bitmaps and
10102 * the relevant bit asks not to trap the change */
10103 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10104 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10105 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10106 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10107 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10108 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10109 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10110 if (vmx_mpx_supported())
10111 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10112 if (nested_cpu_has_xsaves(vmcs12
))
10113 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10115 /* update exit information fields: */
10117 vmcs12
->vm_exit_reason
= exit_reason
;
10118 vmcs12
->exit_qualification
= exit_qualification
;
10120 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10121 if ((vmcs12
->vm_exit_intr_info
&
10122 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10123 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10124 vmcs12
->vm_exit_intr_error_code
=
10125 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10126 vmcs12
->idt_vectoring_info_field
= 0;
10127 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10128 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10130 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10131 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10132 * instead of reading the real value. */
10133 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10136 * Transfer the event that L0 or L1 may wanted to inject into
10137 * L2 to IDT_VECTORING_INFO_FIELD.
10139 vmcs12_save_pending_event(vcpu
, vmcs12
);
10143 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10144 * preserved above and would only end up incorrectly in L1.
10146 vcpu
->arch
.nmi_injected
= false;
10147 kvm_clear_exception_queue(vcpu
);
10148 kvm_clear_interrupt_queue(vcpu
);
10152 * A part of what we need to when the nested L2 guest exits and we want to
10153 * run its L1 parent, is to reset L1's guest state to the host state specified
10155 * This function is to be called not only on normal nested exit, but also on
10156 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10157 * Failures During or After Loading Guest State").
10158 * This function should be called when the active VMCS is L1's (vmcs01).
10160 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10161 struct vmcs12
*vmcs12
)
10163 struct kvm_segment seg
;
10165 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10166 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10167 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10168 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10170 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10171 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10173 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10174 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10175 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10177 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10178 * actually changed, because it depends on the current state of
10179 * fpu_active (which may have changed).
10180 * Note that vmx_set_cr0 refers to efer set above.
10182 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10184 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10185 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10186 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10188 update_exception_bitmap(vcpu
);
10189 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10190 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10193 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10194 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10196 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10197 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10199 nested_ept_uninit_mmu_context(vcpu
);
10201 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10202 kvm_mmu_reset_context(vcpu
);
10205 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10209 * Trivially support vpid by letting L2s share their parent
10210 * L1's vpid. TODO: move to a more elaborate solution, giving
10211 * each L2 its own vpid and exposing the vpid feature to L1.
10213 vmx_flush_tlb(vcpu
);
10217 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10218 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10219 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10220 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10221 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10223 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10224 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10225 vmcs_write64(GUEST_BNDCFGS
, 0);
10227 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10228 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10229 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10231 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10232 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10233 vmcs12
->host_ia32_perf_global_ctrl
);
10235 /* Set L1 segment info according to Intel SDM
10236 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10237 seg
= (struct kvm_segment
) {
10239 .limit
= 0xFFFFFFFF,
10240 .selector
= vmcs12
->host_cs_selector
,
10246 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10250 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10251 seg
= (struct kvm_segment
) {
10253 .limit
= 0xFFFFFFFF,
10260 seg
.selector
= vmcs12
->host_ds_selector
;
10261 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10262 seg
.selector
= vmcs12
->host_es_selector
;
10263 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10264 seg
.selector
= vmcs12
->host_ss_selector
;
10265 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10266 seg
.selector
= vmcs12
->host_fs_selector
;
10267 seg
.base
= vmcs12
->host_fs_base
;
10268 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10269 seg
.selector
= vmcs12
->host_gs_selector
;
10270 seg
.base
= vmcs12
->host_gs_base
;
10271 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10272 seg
= (struct kvm_segment
) {
10273 .base
= vmcs12
->host_tr_base
,
10275 .selector
= vmcs12
->host_tr_selector
,
10279 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10281 kvm_set_dr(vcpu
, 7, 0x400);
10282 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10284 if (cpu_has_vmx_msr_bitmap())
10285 vmx_set_msr_bitmap(vcpu
);
10287 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10288 vmcs12
->vm_exit_msr_load_count
))
10289 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10293 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10294 * and modify vmcs12 to make it see what it would expect to see there if
10295 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10297 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10298 u32 exit_intr_info
,
10299 unsigned long exit_qualification
)
10301 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10302 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10304 /* trying to cancel vmlaunch/vmresume is a bug */
10305 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10307 leave_guest_mode(vcpu
);
10308 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10309 exit_qualification
);
10311 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10312 vmcs12
->vm_exit_msr_store_count
))
10313 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10315 vmx_load_vmcs01(vcpu
);
10317 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10318 && nested_exit_intr_ack_set(vcpu
)) {
10319 int irq
= kvm_cpu_get_interrupt(vcpu
);
10321 vmcs12
->vm_exit_intr_info
= irq
|
10322 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10325 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10326 vmcs12
->exit_qualification
,
10327 vmcs12
->idt_vectoring_info_field
,
10328 vmcs12
->vm_exit_intr_info
,
10329 vmcs12
->vm_exit_intr_error_code
,
10332 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10333 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10334 vmx_segment_cache_clear(vmx
);
10336 /* if no vmcs02 cache requested, remove the one we used */
10337 if (VMCS02_POOL_SIZE
== 0)
10338 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10340 load_vmcs12_host_state(vcpu
, vmcs12
);
10342 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10343 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10345 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10348 /* Unpin physical memory we referred to in vmcs02 */
10349 if (vmx
->nested
.apic_access_page
) {
10350 nested_release_page(vmx
->nested
.apic_access_page
);
10351 vmx
->nested
.apic_access_page
= NULL
;
10353 if (vmx
->nested
.virtual_apic_page
) {
10354 nested_release_page(vmx
->nested
.virtual_apic_page
);
10355 vmx
->nested
.virtual_apic_page
= NULL
;
10357 if (vmx
->nested
.pi_desc_page
) {
10358 kunmap(vmx
->nested
.pi_desc_page
);
10359 nested_release_page(vmx
->nested
.pi_desc_page
);
10360 vmx
->nested
.pi_desc_page
= NULL
;
10361 vmx
->nested
.pi_desc
= NULL
;
10365 * We are now running in L2, mmu_notifier will force to reload the
10366 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10368 kvm_vcpu_reload_apic_access_page(vcpu
);
10371 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10372 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10373 * success or failure flag accordingly.
10375 if (unlikely(vmx
->fail
)) {
10377 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10379 nested_vmx_succeed(vcpu
);
10380 if (enable_shadow_vmcs
)
10381 vmx
->nested
.sync_shadow_vmcs
= true;
10383 /* in case we halted in L2 */
10384 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10388 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10390 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10392 if (is_guest_mode(vcpu
))
10393 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10394 free_nested(to_vmx(vcpu
));
10398 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10399 * 23.7 "VM-entry failures during or after loading guest state" (this also
10400 * lists the acceptable exit-reason and exit-qualification parameters).
10401 * It should only be called before L2 actually succeeded to run, and when
10402 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10404 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10405 struct vmcs12
*vmcs12
,
10406 u32 reason
, unsigned long qualification
)
10408 load_vmcs12_host_state(vcpu
, vmcs12
);
10409 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10410 vmcs12
->exit_qualification
= qualification
;
10411 nested_vmx_succeed(vcpu
);
10412 if (enable_shadow_vmcs
)
10413 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10416 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10417 struct x86_instruction_info
*info
,
10418 enum x86_intercept_stage stage
)
10420 return X86EMUL_CONTINUE
;
10423 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10426 shrink_ple_window(vcpu
);
10429 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10430 struct kvm_memory_slot
*slot
)
10432 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10433 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10436 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10437 struct kvm_memory_slot
*slot
)
10439 kvm_mmu_slot_set_dirty(kvm
, slot
);
10442 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10444 kvm_flush_pml_buffers(kvm
);
10447 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10448 struct kvm_memory_slot
*memslot
,
10449 gfn_t offset
, unsigned long mask
)
10451 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10455 * This routine does the following things for vCPU which is going
10456 * to be blocked if VT-d PI is enabled.
10457 * - Store the vCPU to the wakeup list, so when interrupts happen
10458 * we can find the right vCPU to wake up.
10459 * - Change the Posted-interrupt descriptor as below:
10460 * 'NDST' <-- vcpu->pre_pcpu
10461 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10462 * - If 'ON' is set during this process, which means at least one
10463 * interrupt is posted for this vCPU, we cannot block it, in
10464 * this case, return 1, otherwise, return 0.
10467 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10469 unsigned long flags
;
10471 struct pi_desc old
, new;
10472 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10474 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10475 !irq_remapping_cap(IRQ_POSTING_CAP
))
10478 vcpu
->pre_pcpu
= vcpu
->cpu
;
10479 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10480 vcpu
->pre_pcpu
), flags
);
10481 list_add_tail(&vcpu
->blocked_vcpu_list
,
10482 &per_cpu(blocked_vcpu_on_cpu
,
10484 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10485 vcpu
->pre_pcpu
), flags
);
10488 old
.control
= new.control
= pi_desc
->control
;
10491 * We should not block the vCPU if
10492 * an interrupt is posted for it.
10494 if (pi_test_on(pi_desc
) == 1) {
10495 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10496 vcpu
->pre_pcpu
), flags
);
10497 list_del(&vcpu
->blocked_vcpu_list
);
10498 spin_unlock_irqrestore(
10499 &per_cpu(blocked_vcpu_on_cpu_lock
,
10500 vcpu
->pre_pcpu
), flags
);
10501 vcpu
->pre_pcpu
= -1;
10506 WARN((pi_desc
->sn
== 1),
10507 "Warning: SN field of posted-interrupts "
10508 "is set before blocking\n");
10511 * Since vCPU can be preempted during this process,
10512 * vcpu->cpu could be different with pre_pcpu, we
10513 * need to set pre_pcpu as the destination of wakeup
10514 * notification event, then we can find the right vCPU
10515 * to wakeup in wakeup handler if interrupts happen
10516 * when the vCPU is in blocked state.
10518 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10520 if (x2apic_enabled())
10523 new.ndst
= (dest
<< 8) & 0xFF00;
10525 /* set 'NV' to 'wakeup vector' */
10526 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10527 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10528 new.control
) != old
.control
);
10533 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
10535 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10536 struct pi_desc old
, new;
10538 unsigned long flags
;
10540 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10541 !irq_remapping_cap(IRQ_POSTING_CAP
))
10545 old
.control
= new.control
= pi_desc
->control
;
10547 dest
= cpu_physical_id(vcpu
->cpu
);
10549 if (x2apic_enabled())
10552 new.ndst
= (dest
<< 8) & 0xFF00;
10554 /* Allow posting non-urgent interrupts */
10557 /* set 'NV' to 'notification vector' */
10558 new.nv
= POSTED_INTR_VECTOR
;
10559 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10560 new.control
) != old
.control
);
10562 if(vcpu
->pre_pcpu
!= -1) {
10564 &per_cpu(blocked_vcpu_on_cpu_lock
,
10565 vcpu
->pre_pcpu
), flags
);
10566 list_del(&vcpu
->blocked_vcpu_list
);
10567 spin_unlock_irqrestore(
10568 &per_cpu(blocked_vcpu_on_cpu_lock
,
10569 vcpu
->pre_pcpu
), flags
);
10570 vcpu
->pre_pcpu
= -1;
10575 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10578 * @host_irq: host irq of the interrupt
10579 * @guest_irq: gsi of the interrupt
10580 * @set: set or unset PI
10581 * returns 0 on success, < 0 on failure
10583 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10584 uint32_t guest_irq
, bool set
)
10586 struct kvm_kernel_irq_routing_entry
*e
;
10587 struct kvm_irq_routing_table
*irq_rt
;
10588 struct kvm_lapic_irq irq
;
10589 struct kvm_vcpu
*vcpu
;
10590 struct vcpu_data vcpu_info
;
10591 int idx
, ret
= -EINVAL
;
10593 if (!kvm_arch_has_assigned_device(kvm
) ||
10594 !irq_remapping_cap(IRQ_POSTING_CAP
))
10597 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10598 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10599 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10601 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10602 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10605 * VT-d PI cannot support posting multicast/broadcast
10606 * interrupts to a vCPU, we still use interrupt remapping
10607 * for these kind of interrupts.
10609 * For lowest-priority interrupts, we only support
10610 * those with single CPU as the destination, e.g. user
10611 * configures the interrupts via /proc/irq or uses
10612 * irqbalance to make the interrupts single-CPU.
10614 * We will support full lowest-priority interrupt later.
10617 kvm_set_msi_irq(e
, &irq
);
10618 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
))
10621 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10622 vcpu_info
.vector
= irq
.vector
;
10624 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, e
->gsi
,
10625 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10628 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10630 /* suppress notification event before unposting */
10631 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10632 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10633 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10637 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10645 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10649 static struct kvm_x86_ops vmx_x86_ops
= {
10650 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10651 .disabled_by_bios
= vmx_disabled_by_bios
,
10652 .hardware_setup
= hardware_setup
,
10653 .hardware_unsetup
= hardware_unsetup
,
10654 .check_processor_compatibility
= vmx_check_processor_compat
,
10655 .hardware_enable
= hardware_enable
,
10656 .hardware_disable
= hardware_disable
,
10657 .cpu_has_accelerated_tpr
= report_flexpriority
,
10658 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10660 .vcpu_create
= vmx_create_vcpu
,
10661 .vcpu_free
= vmx_free_vcpu
,
10662 .vcpu_reset
= vmx_vcpu_reset
,
10664 .prepare_guest_switch
= vmx_save_host_state
,
10665 .vcpu_load
= vmx_vcpu_load
,
10666 .vcpu_put
= vmx_vcpu_put
,
10668 .update_db_bp_intercept
= update_exception_bitmap
,
10669 .get_msr
= vmx_get_msr
,
10670 .set_msr
= vmx_set_msr
,
10671 .get_segment_base
= vmx_get_segment_base
,
10672 .get_segment
= vmx_get_segment
,
10673 .set_segment
= vmx_set_segment
,
10674 .get_cpl
= vmx_get_cpl
,
10675 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10676 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10677 .decache_cr3
= vmx_decache_cr3
,
10678 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10679 .set_cr0
= vmx_set_cr0
,
10680 .set_cr3
= vmx_set_cr3
,
10681 .set_cr4
= vmx_set_cr4
,
10682 .set_efer
= vmx_set_efer
,
10683 .get_idt
= vmx_get_idt
,
10684 .set_idt
= vmx_set_idt
,
10685 .get_gdt
= vmx_get_gdt
,
10686 .set_gdt
= vmx_set_gdt
,
10687 .get_dr6
= vmx_get_dr6
,
10688 .set_dr6
= vmx_set_dr6
,
10689 .set_dr7
= vmx_set_dr7
,
10690 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10691 .cache_reg
= vmx_cache_reg
,
10692 .get_rflags
= vmx_get_rflags
,
10693 .set_rflags
= vmx_set_rflags
,
10694 .fpu_activate
= vmx_fpu_activate
,
10695 .fpu_deactivate
= vmx_fpu_deactivate
,
10697 .tlb_flush
= vmx_flush_tlb
,
10699 .run
= vmx_vcpu_run
,
10700 .handle_exit
= vmx_handle_exit
,
10701 .skip_emulated_instruction
= skip_emulated_instruction
,
10702 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10703 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10704 .patch_hypercall
= vmx_patch_hypercall
,
10705 .set_irq
= vmx_inject_irq
,
10706 .set_nmi
= vmx_inject_nmi
,
10707 .queue_exception
= vmx_queue_exception
,
10708 .cancel_injection
= vmx_cancel_injection
,
10709 .interrupt_allowed
= vmx_interrupt_allowed
,
10710 .nmi_allowed
= vmx_nmi_allowed
,
10711 .get_nmi_mask
= vmx_get_nmi_mask
,
10712 .set_nmi_mask
= vmx_set_nmi_mask
,
10713 .enable_nmi_window
= enable_nmi_window
,
10714 .enable_irq_window
= enable_irq_window
,
10715 .update_cr8_intercept
= update_cr8_intercept
,
10716 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10717 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10718 .cpu_uses_apicv
= vmx_cpu_uses_apicv
,
10719 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10720 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10721 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10722 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10723 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10725 .set_tss_addr
= vmx_set_tss_addr
,
10726 .get_tdp_level
= get_ept_level
,
10727 .get_mt_mask
= vmx_get_mt_mask
,
10729 .get_exit_info
= vmx_get_exit_info
,
10731 .get_lpage_level
= vmx_get_lpage_level
,
10733 .cpuid_update
= vmx_cpuid_update
,
10735 .rdtscp_supported
= vmx_rdtscp_supported
,
10736 .invpcid_supported
= vmx_invpcid_supported
,
10738 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10740 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10742 .set_tsc_khz
= vmx_set_tsc_khz
,
10743 .read_tsc_offset
= vmx_read_tsc_offset
,
10744 .write_tsc_offset
= vmx_write_tsc_offset
,
10745 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
10746 .compute_tsc_offset
= vmx_compute_tsc_offset
,
10747 .read_l1_tsc
= vmx_read_l1_tsc
,
10749 .set_tdp_cr3
= vmx_set_cr3
,
10751 .check_intercept
= vmx_check_intercept
,
10752 .handle_external_intr
= vmx_handle_external_intr
,
10753 .mpx_supported
= vmx_mpx_supported
,
10754 .xsaves_supported
= vmx_xsaves_supported
,
10756 .check_nested_events
= vmx_check_nested_events
,
10758 .sched_in
= vmx_sched_in
,
10760 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10761 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10762 .flush_log_dirty
= vmx_flush_log_dirty
,
10763 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10765 .pre_block
= vmx_pre_block
,
10766 .post_block
= vmx_post_block
,
10768 .pmu_ops
= &intel_pmu_ops
,
10770 .update_pi_irte
= vmx_update_pi_irte
,
10773 static int __init
vmx_init(void)
10775 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10776 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10780 #ifdef CONFIG_KEXEC_CORE
10781 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10782 crash_vmclear_local_loaded_vmcss
);
10788 static void __exit
vmx_exit(void)
10790 #ifdef CONFIG_KEXEC_CORE
10791 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10798 module_init(vmx_init
)
10799 module_exit(vmx_exit
)