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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22 #include "lapic.h"
23
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
37 #include "x86.h"
38
39 #include <asm/cpu.h>
40 #include <asm/io.h>
41 #include <asm/desc.h>
42 #include <asm/vmx.h>
43 #include <asm/virtext.h>
44 #include <asm/mce.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
49 #include <asm/apic.h>
50 #include <asm/irq_remapping.h>
51
52 #include "trace.h"
53 #include "pmu.h"
54
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
61
62 static const struct x86_cpu_id vmx_cpu_id[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX),
64 {}
65 };
66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
67
68 static bool __read_mostly enable_vpid = 1;
69 module_param_named(vpid, enable_vpid, bool, 0444);
70
71 static bool __read_mostly flexpriority_enabled = 1;
72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
73
74 static bool __read_mostly enable_ept = 1;
75 module_param_named(ept, enable_ept, bool, S_IRUGO);
76
77 static bool __read_mostly enable_unrestricted_guest = 1;
78 module_param_named(unrestricted_guest,
79 enable_unrestricted_guest, bool, S_IRUGO);
80
81 static bool __read_mostly enable_ept_ad_bits = 1;
82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
83
84 static bool __read_mostly emulate_invalid_guest_state = true;
85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
86
87 static bool __read_mostly vmm_exclusive = 1;
88 module_param(vmm_exclusive, bool, S_IRUGO);
89
90 static bool __read_mostly fasteoi = 1;
91 module_param(fasteoi, bool, S_IRUGO);
92
93 static bool __read_mostly enable_apicv = 1;
94 module_param(enable_apicv, bool, S_IRUGO);
95
96 static bool __read_mostly enable_shadow_vmcs = 1;
97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
98 /*
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
102 */
103 static bool __read_mostly nested = 0;
104 module_param(nested, bool, S_IRUGO);
105
106 static u64 __read_mostly host_xss;
107
108 static bool __read_mostly enable_pml = 1;
109 module_param_named(pml, enable_pml, bool, S_IRUGO);
110
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112
113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
115 #define KVM_VM_CR0_ALWAYS_ON \
116 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
117 #define KVM_CR4_GUEST_OWNED_BITS \
118 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
119 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120
121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123
124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125
126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
127
128 /*
129 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
130 * ple_gap: upper bound on the amount of time between two successive
131 * executions of PAUSE in a loop. Also indicate if ple enabled.
132 * According to test, this time is usually smaller than 128 cycles.
133 * ple_window: upper bound on the amount of time a guest is allowed to execute
134 * in a PAUSE loop. Tests indicate that most spinlocks are held for
135 * less than 2^12 cycles
136 * Time is measured based on a counter that runs at the same rate as the TSC,
137 * refer SDM volume 3b section 21.6.13 & 22.1.3.
138 */
139 #define KVM_VMX_DEFAULT_PLE_GAP 128
140 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
144 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145
146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
147 module_param(ple_gap, int, S_IRUGO);
148
149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
150 module_param(ple_window, int, S_IRUGO);
151
152 /* Default doubles per-vcpu window every exit. */
153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
154 module_param(ple_window_grow, int, S_IRUGO);
155
156 /* Default resets per-vcpu window every exit to ple_window. */
157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
158 module_param(ple_window_shrink, int, S_IRUGO);
159
160 /* Default is to compute the maximum so we can never overflow. */
161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
162 static int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
163 module_param(ple_window_max, int, S_IRUGO);
164
165 extern const ulong vmx_return;
166
167 #define NR_AUTOLOAD_MSRS 8
168 #define VMCS02_POOL_SIZE 1
169
170 struct vmcs {
171 u32 revision_id;
172 u32 abort;
173 char data[0];
174 };
175
176 /*
177 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
178 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
179 * loaded on this CPU (so we can clear them if the CPU goes down).
180 */
181 struct loaded_vmcs {
182 struct vmcs *vmcs;
183 int cpu;
184 int launched;
185 struct list_head loaded_vmcss_on_cpu_link;
186 };
187
188 struct shared_msr_entry {
189 unsigned index;
190 u64 data;
191 u64 mask;
192 };
193
194 /*
195 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
196 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
197 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
198 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
199 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
200 * More than one of these structures may exist, if L1 runs multiple L2 guests.
201 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
202 * underlying hardware which will be used to run L2.
203 * This structure is packed to ensure that its layout is identical across
204 * machines (necessary for live migration).
205 * If there are changes in this struct, VMCS12_REVISION must be changed.
206 */
207 typedef u64 natural_width;
208 struct __packed vmcs12 {
209 /* According to the Intel spec, a VMCS region must start with the
210 * following two fields. Then follow implementation-specific data.
211 */
212 u32 revision_id;
213 u32 abort;
214
215 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
216 u32 padding[7]; /* room for future expansion */
217
218 u64 io_bitmap_a;
219 u64 io_bitmap_b;
220 u64 msr_bitmap;
221 u64 vm_exit_msr_store_addr;
222 u64 vm_exit_msr_load_addr;
223 u64 vm_entry_msr_load_addr;
224 u64 tsc_offset;
225 u64 virtual_apic_page_addr;
226 u64 apic_access_addr;
227 u64 posted_intr_desc_addr;
228 u64 ept_pointer;
229 u64 eoi_exit_bitmap0;
230 u64 eoi_exit_bitmap1;
231 u64 eoi_exit_bitmap2;
232 u64 eoi_exit_bitmap3;
233 u64 xss_exit_bitmap;
234 u64 guest_physical_address;
235 u64 vmcs_link_pointer;
236 u64 guest_ia32_debugctl;
237 u64 guest_ia32_pat;
238 u64 guest_ia32_efer;
239 u64 guest_ia32_perf_global_ctrl;
240 u64 guest_pdptr0;
241 u64 guest_pdptr1;
242 u64 guest_pdptr2;
243 u64 guest_pdptr3;
244 u64 guest_bndcfgs;
245 u64 host_ia32_pat;
246 u64 host_ia32_efer;
247 u64 host_ia32_perf_global_ctrl;
248 u64 padding64[8]; /* room for future expansion */
249 /*
250 * To allow migration of L1 (complete with its L2 guests) between
251 * machines of different natural widths (32 or 64 bit), we cannot have
252 * unsigned long fields with no explict size. We use u64 (aliased
253 * natural_width) instead. Luckily, x86 is little-endian.
254 */
255 natural_width cr0_guest_host_mask;
256 natural_width cr4_guest_host_mask;
257 natural_width cr0_read_shadow;
258 natural_width cr4_read_shadow;
259 natural_width cr3_target_value0;
260 natural_width cr3_target_value1;
261 natural_width cr3_target_value2;
262 natural_width cr3_target_value3;
263 natural_width exit_qualification;
264 natural_width guest_linear_address;
265 natural_width guest_cr0;
266 natural_width guest_cr3;
267 natural_width guest_cr4;
268 natural_width guest_es_base;
269 natural_width guest_cs_base;
270 natural_width guest_ss_base;
271 natural_width guest_ds_base;
272 natural_width guest_fs_base;
273 natural_width guest_gs_base;
274 natural_width guest_ldtr_base;
275 natural_width guest_tr_base;
276 natural_width guest_gdtr_base;
277 natural_width guest_idtr_base;
278 natural_width guest_dr7;
279 natural_width guest_rsp;
280 natural_width guest_rip;
281 natural_width guest_rflags;
282 natural_width guest_pending_dbg_exceptions;
283 natural_width guest_sysenter_esp;
284 natural_width guest_sysenter_eip;
285 natural_width host_cr0;
286 natural_width host_cr3;
287 natural_width host_cr4;
288 natural_width host_fs_base;
289 natural_width host_gs_base;
290 natural_width host_tr_base;
291 natural_width host_gdtr_base;
292 natural_width host_idtr_base;
293 natural_width host_ia32_sysenter_esp;
294 natural_width host_ia32_sysenter_eip;
295 natural_width host_rsp;
296 natural_width host_rip;
297 natural_width paddingl[8]; /* room for future expansion */
298 u32 pin_based_vm_exec_control;
299 u32 cpu_based_vm_exec_control;
300 u32 exception_bitmap;
301 u32 page_fault_error_code_mask;
302 u32 page_fault_error_code_match;
303 u32 cr3_target_count;
304 u32 vm_exit_controls;
305 u32 vm_exit_msr_store_count;
306 u32 vm_exit_msr_load_count;
307 u32 vm_entry_controls;
308 u32 vm_entry_msr_load_count;
309 u32 vm_entry_intr_info_field;
310 u32 vm_entry_exception_error_code;
311 u32 vm_entry_instruction_len;
312 u32 tpr_threshold;
313 u32 secondary_vm_exec_control;
314 u32 vm_instruction_error;
315 u32 vm_exit_reason;
316 u32 vm_exit_intr_info;
317 u32 vm_exit_intr_error_code;
318 u32 idt_vectoring_info_field;
319 u32 idt_vectoring_error_code;
320 u32 vm_exit_instruction_len;
321 u32 vmx_instruction_info;
322 u32 guest_es_limit;
323 u32 guest_cs_limit;
324 u32 guest_ss_limit;
325 u32 guest_ds_limit;
326 u32 guest_fs_limit;
327 u32 guest_gs_limit;
328 u32 guest_ldtr_limit;
329 u32 guest_tr_limit;
330 u32 guest_gdtr_limit;
331 u32 guest_idtr_limit;
332 u32 guest_es_ar_bytes;
333 u32 guest_cs_ar_bytes;
334 u32 guest_ss_ar_bytes;
335 u32 guest_ds_ar_bytes;
336 u32 guest_fs_ar_bytes;
337 u32 guest_gs_ar_bytes;
338 u32 guest_ldtr_ar_bytes;
339 u32 guest_tr_ar_bytes;
340 u32 guest_interruptibility_info;
341 u32 guest_activity_state;
342 u32 guest_sysenter_cs;
343 u32 host_ia32_sysenter_cs;
344 u32 vmx_preemption_timer_value;
345 u32 padding32[7]; /* room for future expansion */
346 u16 virtual_processor_id;
347 u16 posted_intr_nv;
348 u16 guest_es_selector;
349 u16 guest_cs_selector;
350 u16 guest_ss_selector;
351 u16 guest_ds_selector;
352 u16 guest_fs_selector;
353 u16 guest_gs_selector;
354 u16 guest_ldtr_selector;
355 u16 guest_tr_selector;
356 u16 guest_intr_status;
357 u16 host_es_selector;
358 u16 host_cs_selector;
359 u16 host_ss_selector;
360 u16 host_ds_selector;
361 u16 host_fs_selector;
362 u16 host_gs_selector;
363 u16 host_tr_selector;
364 };
365
366 /*
367 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
368 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
369 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370 */
371 #define VMCS12_REVISION 0x11e57ed0
372
373 /*
374 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
375 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
376 * current implementation, 4K are reserved to avoid future complications.
377 */
378 #define VMCS12_SIZE 0x1000
379
380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct vmcs02_list {
382 struct list_head list;
383 gpa_t vmptr;
384 struct loaded_vmcs vmcs02;
385 };
386
387 /*
388 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
389 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
390 */
391 struct nested_vmx {
392 /* Has the level1 guest done vmxon? */
393 bool vmxon;
394 gpa_t vmxon_ptr;
395
396 /* The guest-physical address of the current VMCS L1 keeps for L2 */
397 gpa_t current_vmptr;
398 /* The host-usable pointer to the above */
399 struct page *current_vmcs12_page;
400 struct vmcs12 *current_vmcs12;
401 struct vmcs *current_shadow_vmcs;
402 /*
403 * Indicates if the shadow vmcs must be updated with the
404 * data hold by vmcs12
405 */
406 bool sync_shadow_vmcs;
407
408 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
409 struct list_head vmcs02_pool;
410 int vmcs02_num;
411 u64 vmcs01_tsc_offset;
412 /* L2 must run next, and mustn't decide to exit to L1. */
413 bool nested_run_pending;
414 /*
415 * Guest pages referred to in vmcs02 with host-physical pointers, so
416 * we must keep them pinned while L2 runs.
417 */
418 struct page *apic_access_page;
419 struct page *virtual_apic_page;
420 struct page *pi_desc_page;
421 struct pi_desc *pi_desc;
422 bool pi_pending;
423 u16 posted_intr_nv;
424 u64 msr_ia32_feature_control;
425
426 struct hrtimer preemption_timer;
427 bool preemption_timer_expired;
428
429 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
430 u64 vmcs01_debugctl;
431
432 u16 vpid02;
433 u16 last_vpid;
434
435 u32 nested_vmx_procbased_ctls_low;
436 u32 nested_vmx_procbased_ctls_high;
437 u32 nested_vmx_true_procbased_ctls_low;
438 u32 nested_vmx_secondary_ctls_low;
439 u32 nested_vmx_secondary_ctls_high;
440 u32 nested_vmx_pinbased_ctls_low;
441 u32 nested_vmx_pinbased_ctls_high;
442 u32 nested_vmx_exit_ctls_low;
443 u32 nested_vmx_exit_ctls_high;
444 u32 nested_vmx_true_exit_ctls_low;
445 u32 nested_vmx_entry_ctls_low;
446 u32 nested_vmx_entry_ctls_high;
447 u32 nested_vmx_true_entry_ctls_low;
448 u32 nested_vmx_misc_low;
449 u32 nested_vmx_misc_high;
450 u32 nested_vmx_ept_caps;
451 u32 nested_vmx_vpid_caps;
452 };
453
454 #define POSTED_INTR_ON 0
455 #define POSTED_INTR_SN 1
456
457 /* Posted-Interrupt Descriptor */
458 struct pi_desc {
459 u32 pir[8]; /* Posted interrupt requested */
460 union {
461 struct {
462 /* bit 256 - Outstanding Notification */
463 u16 on : 1,
464 /* bit 257 - Suppress Notification */
465 sn : 1,
466 /* bit 271:258 - Reserved */
467 rsvd_1 : 14;
468 /* bit 279:272 - Notification Vector */
469 u8 nv;
470 /* bit 287:280 - Reserved */
471 u8 rsvd_2;
472 /* bit 319:288 - Notification Destination */
473 u32 ndst;
474 };
475 u64 control;
476 };
477 u32 rsvd[6];
478 } __aligned(64);
479
480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
481 {
482 return test_and_set_bit(POSTED_INTR_ON,
483 (unsigned long *)&pi_desc->control);
484 }
485
486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
487 {
488 return test_and_clear_bit(POSTED_INTR_ON,
489 (unsigned long *)&pi_desc->control);
490 }
491
492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
493 {
494 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
495 }
496
497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
498 {
499 return clear_bit(POSTED_INTR_SN,
500 (unsigned long *)&pi_desc->control);
501 }
502
503 static inline void pi_set_sn(struct pi_desc *pi_desc)
504 {
505 return set_bit(POSTED_INTR_SN,
506 (unsigned long *)&pi_desc->control);
507 }
508
509 static inline int pi_test_on(struct pi_desc *pi_desc)
510 {
511 return test_bit(POSTED_INTR_ON,
512 (unsigned long *)&pi_desc->control);
513 }
514
515 static inline int pi_test_sn(struct pi_desc *pi_desc)
516 {
517 return test_bit(POSTED_INTR_SN,
518 (unsigned long *)&pi_desc->control);
519 }
520
521 struct vcpu_vmx {
522 struct kvm_vcpu vcpu;
523 unsigned long host_rsp;
524 u8 fail;
525 bool nmi_known_unmasked;
526 u32 exit_intr_info;
527 u32 idt_vectoring_info;
528 ulong rflags;
529 struct shared_msr_entry *guest_msrs;
530 int nmsrs;
531 int save_nmsrs;
532 unsigned long host_idt_base;
533 #ifdef CONFIG_X86_64
534 u64 msr_host_kernel_gs_base;
535 u64 msr_guest_kernel_gs_base;
536 #endif
537 u32 vm_entry_controls_shadow;
538 u32 vm_exit_controls_shadow;
539 /*
540 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
541 * non-nested (L1) guest, it always points to vmcs01. For a nested
542 * guest (L2), it points to a different VMCS.
543 */
544 struct loaded_vmcs vmcs01;
545 struct loaded_vmcs *loaded_vmcs;
546 bool __launched; /* temporary, used in vmx_vcpu_run */
547 struct msr_autoload {
548 unsigned nr;
549 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
550 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
551 } msr_autoload;
552 struct {
553 int loaded;
554 u16 fs_sel, gs_sel, ldt_sel;
555 #ifdef CONFIG_X86_64
556 u16 ds_sel, es_sel;
557 #endif
558 int gs_ldt_reload_needed;
559 int fs_reload_needed;
560 u64 msr_host_bndcfgs;
561 unsigned long vmcs_host_cr4; /* May not match real cr4 */
562 } host_state;
563 struct {
564 int vm86_active;
565 ulong save_rflags;
566 struct kvm_segment segs[8];
567 } rmode;
568 struct {
569 u32 bitmask; /* 4 bits per segment (1 bit per field) */
570 struct kvm_save_segment {
571 u16 selector;
572 unsigned long base;
573 u32 limit;
574 u32 ar;
575 } seg[8];
576 } segment_cache;
577 int vpid;
578 bool emulation_required;
579
580 /* Support for vnmi-less CPUs */
581 int soft_vnmi_blocked;
582 ktime_t entry_time;
583 s64 vnmi_blocked_time;
584 u32 exit_reason;
585
586 /* Posted interrupt descriptor */
587 struct pi_desc pi_desc;
588
589 /* Support for a guest hypervisor (nested VMX) */
590 struct nested_vmx nested;
591
592 /* Dynamic PLE window. */
593 int ple_window;
594 bool ple_window_dirty;
595
596 /* Support for PML */
597 #define PML_ENTITY_NUM 512
598 struct page *pml_pg;
599
600 u64 current_tsc_ratio;
601
602 bool guest_pkru_valid;
603 u32 guest_pkru;
604 u32 host_pkru;
605 };
606
607 enum segment_cache_field {
608 SEG_FIELD_SEL = 0,
609 SEG_FIELD_BASE = 1,
610 SEG_FIELD_LIMIT = 2,
611 SEG_FIELD_AR = 3,
612
613 SEG_FIELD_NR = 4
614 };
615
616 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
617 {
618 return container_of(vcpu, struct vcpu_vmx, vcpu);
619 }
620
621 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
622 {
623 return &(to_vmx(vcpu)->pi_desc);
624 }
625
626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
627 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
628 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
629 [number##_HIGH] = VMCS12_OFFSET(name)+4
630
631
632 static unsigned long shadow_read_only_fields[] = {
633 /*
634 * We do NOT shadow fields that are modified when L0
635 * traps and emulates any vmx instruction (e.g. VMPTRLD,
636 * VMXON...) executed by L1.
637 * For example, VM_INSTRUCTION_ERROR is read
638 * by L1 if a vmx instruction fails (part of the error path).
639 * Note the code assumes this logic. If for some reason
640 * we start shadowing these fields then we need to
641 * force a shadow sync when L0 emulates vmx instructions
642 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
643 * by nested_vmx_failValid)
644 */
645 VM_EXIT_REASON,
646 VM_EXIT_INTR_INFO,
647 VM_EXIT_INSTRUCTION_LEN,
648 IDT_VECTORING_INFO_FIELD,
649 IDT_VECTORING_ERROR_CODE,
650 VM_EXIT_INTR_ERROR_CODE,
651 EXIT_QUALIFICATION,
652 GUEST_LINEAR_ADDRESS,
653 GUEST_PHYSICAL_ADDRESS
654 };
655 static int max_shadow_read_only_fields =
656 ARRAY_SIZE(shadow_read_only_fields);
657
658 static unsigned long shadow_read_write_fields[] = {
659 TPR_THRESHOLD,
660 GUEST_RIP,
661 GUEST_RSP,
662 GUEST_CR0,
663 GUEST_CR3,
664 GUEST_CR4,
665 GUEST_INTERRUPTIBILITY_INFO,
666 GUEST_RFLAGS,
667 GUEST_CS_SELECTOR,
668 GUEST_CS_AR_BYTES,
669 GUEST_CS_LIMIT,
670 GUEST_CS_BASE,
671 GUEST_ES_BASE,
672 GUEST_BNDCFGS,
673 CR0_GUEST_HOST_MASK,
674 CR0_READ_SHADOW,
675 CR4_READ_SHADOW,
676 TSC_OFFSET,
677 EXCEPTION_BITMAP,
678 CPU_BASED_VM_EXEC_CONTROL,
679 VM_ENTRY_EXCEPTION_ERROR_CODE,
680 VM_ENTRY_INTR_INFO_FIELD,
681 VM_ENTRY_INSTRUCTION_LEN,
682 VM_ENTRY_EXCEPTION_ERROR_CODE,
683 HOST_FS_BASE,
684 HOST_GS_BASE,
685 HOST_FS_SELECTOR,
686 HOST_GS_SELECTOR
687 };
688 static int max_shadow_read_write_fields =
689 ARRAY_SIZE(shadow_read_write_fields);
690
691 static const unsigned short vmcs_field_to_offset_table[] = {
692 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
693 FIELD(POSTED_INTR_NV, posted_intr_nv),
694 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
695 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
696 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
697 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
698 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
699 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
700 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
701 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
702 FIELD(GUEST_INTR_STATUS, guest_intr_status),
703 FIELD(HOST_ES_SELECTOR, host_es_selector),
704 FIELD(HOST_CS_SELECTOR, host_cs_selector),
705 FIELD(HOST_SS_SELECTOR, host_ss_selector),
706 FIELD(HOST_DS_SELECTOR, host_ds_selector),
707 FIELD(HOST_FS_SELECTOR, host_fs_selector),
708 FIELD(HOST_GS_SELECTOR, host_gs_selector),
709 FIELD(HOST_TR_SELECTOR, host_tr_selector),
710 FIELD64(IO_BITMAP_A, io_bitmap_a),
711 FIELD64(IO_BITMAP_B, io_bitmap_b),
712 FIELD64(MSR_BITMAP, msr_bitmap),
713 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
714 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
715 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
716 FIELD64(TSC_OFFSET, tsc_offset),
717 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
718 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
719 FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
720 FIELD64(EPT_POINTER, ept_pointer),
721 FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
722 FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
723 FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
724 FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
725 FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
726 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
727 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
728 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
729 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
730 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
731 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
732 FIELD64(GUEST_PDPTR0, guest_pdptr0),
733 FIELD64(GUEST_PDPTR1, guest_pdptr1),
734 FIELD64(GUEST_PDPTR2, guest_pdptr2),
735 FIELD64(GUEST_PDPTR3, guest_pdptr3),
736 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
737 FIELD64(HOST_IA32_PAT, host_ia32_pat),
738 FIELD64(HOST_IA32_EFER, host_ia32_efer),
739 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
740 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
741 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
742 FIELD(EXCEPTION_BITMAP, exception_bitmap),
743 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
744 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
745 FIELD(CR3_TARGET_COUNT, cr3_target_count),
746 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
747 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
748 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
749 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
750 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
751 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
752 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
753 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
754 FIELD(TPR_THRESHOLD, tpr_threshold),
755 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
756 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
757 FIELD(VM_EXIT_REASON, vm_exit_reason),
758 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
759 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
760 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
761 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
762 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
763 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
764 FIELD(GUEST_ES_LIMIT, guest_es_limit),
765 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
766 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
767 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
768 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
769 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
770 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
771 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
772 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
773 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
774 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
775 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
776 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
777 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
778 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
779 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
780 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
781 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
782 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
783 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
784 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
785 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
786 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
787 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
788 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
789 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
790 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
791 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
792 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
793 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
794 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
795 FIELD(EXIT_QUALIFICATION, exit_qualification),
796 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
797 FIELD(GUEST_CR0, guest_cr0),
798 FIELD(GUEST_CR3, guest_cr3),
799 FIELD(GUEST_CR4, guest_cr4),
800 FIELD(GUEST_ES_BASE, guest_es_base),
801 FIELD(GUEST_CS_BASE, guest_cs_base),
802 FIELD(GUEST_SS_BASE, guest_ss_base),
803 FIELD(GUEST_DS_BASE, guest_ds_base),
804 FIELD(GUEST_FS_BASE, guest_fs_base),
805 FIELD(GUEST_GS_BASE, guest_gs_base),
806 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
807 FIELD(GUEST_TR_BASE, guest_tr_base),
808 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
809 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
810 FIELD(GUEST_DR7, guest_dr7),
811 FIELD(GUEST_RSP, guest_rsp),
812 FIELD(GUEST_RIP, guest_rip),
813 FIELD(GUEST_RFLAGS, guest_rflags),
814 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
815 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
816 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
817 FIELD(HOST_CR0, host_cr0),
818 FIELD(HOST_CR3, host_cr3),
819 FIELD(HOST_CR4, host_cr4),
820 FIELD(HOST_FS_BASE, host_fs_base),
821 FIELD(HOST_GS_BASE, host_gs_base),
822 FIELD(HOST_TR_BASE, host_tr_base),
823 FIELD(HOST_GDTR_BASE, host_gdtr_base),
824 FIELD(HOST_IDTR_BASE, host_idtr_base),
825 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
826 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
827 FIELD(HOST_RSP, host_rsp),
828 FIELD(HOST_RIP, host_rip),
829 };
830
831 static inline short vmcs_field_to_offset(unsigned long field)
832 {
833 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
834
835 if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
836 vmcs_field_to_offset_table[field] == 0)
837 return -ENOENT;
838
839 return vmcs_field_to_offset_table[field];
840 }
841
842 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
843 {
844 return to_vmx(vcpu)->nested.current_vmcs12;
845 }
846
847 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
848 {
849 struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
850 if (is_error_page(page))
851 return NULL;
852
853 return page;
854 }
855
856 static void nested_release_page(struct page *page)
857 {
858 kvm_release_page_dirty(page);
859 }
860
861 static void nested_release_page_clean(struct page *page)
862 {
863 kvm_release_page_clean(page);
864 }
865
866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
867 static u64 construct_eptp(unsigned long root_hpa);
868 static void kvm_cpu_vmxon(u64 addr);
869 static void kvm_cpu_vmxoff(void);
870 static bool vmx_xsaves_supported(void);
871 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
872 static void vmx_set_segment(struct kvm_vcpu *vcpu,
873 struct kvm_segment *var, int seg);
874 static void vmx_get_segment(struct kvm_vcpu *vcpu,
875 struct kvm_segment *var, int seg);
876 static bool guest_state_valid(struct kvm_vcpu *vcpu);
877 static u32 vmx_segment_access_rights(struct kvm_segment *var);
878 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
880 static int alloc_identity_pagetable(struct kvm *kvm);
881
882 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
883 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
884 /*
885 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
886 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
887 */
888 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
889 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
890
891 /*
892 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
893 * can find which vCPU should be waken up.
894 */
895 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
896 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
897
898 static unsigned long *vmx_io_bitmap_a;
899 static unsigned long *vmx_io_bitmap_b;
900 static unsigned long *vmx_msr_bitmap_legacy;
901 static unsigned long *vmx_msr_bitmap_longmode;
902 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
903 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
904 static unsigned long *vmx_msr_bitmap_nested;
905 static unsigned long *vmx_vmread_bitmap;
906 static unsigned long *vmx_vmwrite_bitmap;
907
908 static bool cpu_has_load_ia32_efer;
909 static bool cpu_has_load_perf_global_ctrl;
910
911 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
912 static DEFINE_SPINLOCK(vmx_vpid_lock);
913
914 static struct vmcs_config {
915 int size;
916 int order;
917 u32 revision_id;
918 u32 pin_based_exec_ctrl;
919 u32 cpu_based_exec_ctrl;
920 u32 cpu_based_2nd_exec_ctrl;
921 u32 vmexit_ctrl;
922 u32 vmentry_ctrl;
923 } vmcs_config;
924
925 static struct vmx_capability {
926 u32 ept;
927 u32 vpid;
928 } vmx_capability;
929
930 #define VMX_SEGMENT_FIELD(seg) \
931 [VCPU_SREG_##seg] = { \
932 .selector = GUEST_##seg##_SELECTOR, \
933 .base = GUEST_##seg##_BASE, \
934 .limit = GUEST_##seg##_LIMIT, \
935 .ar_bytes = GUEST_##seg##_AR_BYTES, \
936 }
937
938 static const struct kvm_vmx_segment_field {
939 unsigned selector;
940 unsigned base;
941 unsigned limit;
942 unsigned ar_bytes;
943 } kvm_vmx_segment_fields[] = {
944 VMX_SEGMENT_FIELD(CS),
945 VMX_SEGMENT_FIELD(DS),
946 VMX_SEGMENT_FIELD(ES),
947 VMX_SEGMENT_FIELD(FS),
948 VMX_SEGMENT_FIELD(GS),
949 VMX_SEGMENT_FIELD(SS),
950 VMX_SEGMENT_FIELD(TR),
951 VMX_SEGMENT_FIELD(LDTR),
952 };
953
954 static u64 host_efer;
955
956 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
957
958 /*
959 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
960 * away by decrementing the array size.
961 */
962 static const u32 vmx_msr_index[] = {
963 #ifdef CONFIG_X86_64
964 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
965 #endif
966 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
967 };
968
969 static inline bool is_exception_n(u32 intr_info, u8 vector)
970 {
971 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
972 INTR_INFO_VALID_MASK)) ==
973 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
974 }
975
976 static inline bool is_debug(u32 intr_info)
977 {
978 return is_exception_n(intr_info, DB_VECTOR);
979 }
980
981 static inline bool is_breakpoint(u32 intr_info)
982 {
983 return is_exception_n(intr_info, BP_VECTOR);
984 }
985
986 static inline bool is_page_fault(u32 intr_info)
987 {
988 return is_exception_n(intr_info, PF_VECTOR);
989 }
990
991 static inline bool is_no_device(u32 intr_info)
992 {
993 return is_exception_n(intr_info, NM_VECTOR);
994 }
995
996 static inline bool is_invalid_opcode(u32 intr_info)
997 {
998 return is_exception_n(intr_info, UD_VECTOR);
999 }
1000
1001 static inline bool is_external_interrupt(u32 intr_info)
1002 {
1003 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1004 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1005 }
1006
1007 static inline bool is_machine_check(u32 intr_info)
1008 {
1009 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1010 INTR_INFO_VALID_MASK)) ==
1011 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1012 }
1013
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1015 {
1016 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1017 }
1018
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1020 {
1021 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1022 }
1023
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1025 {
1026 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1027 }
1028
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1030 {
1031 return vmcs_config.cpu_based_exec_ctrl &
1032 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1033 }
1034
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1036 {
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1042 {
1043 return vmcs_config.cpu_based_2nd_exec_ctrl &
1044 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1045 }
1046
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1048 {
1049 return vmcs_config.cpu_based_2nd_exec_ctrl &
1050 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1051 }
1052
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1054 {
1055 return vmcs_config.cpu_based_2nd_exec_ctrl &
1056 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1057 }
1058
1059 static inline bool cpu_has_vmx_posted_intr(void)
1060 {
1061 return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1062 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1063 }
1064
1065 static inline bool cpu_has_vmx_apicv(void)
1066 {
1067 return cpu_has_vmx_apic_register_virt() &&
1068 cpu_has_vmx_virtual_intr_delivery() &&
1069 cpu_has_vmx_posted_intr();
1070 }
1071
1072 static inline bool cpu_has_vmx_flexpriority(void)
1073 {
1074 return cpu_has_vmx_tpr_shadow() &&
1075 cpu_has_vmx_virtualize_apic_accesses();
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1079 {
1080 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1084 {
1085 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1089 {
1090 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1094 {
1095 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1099 {
1100 return vmx_capability.ept & VMX_EPT_AD_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invept_context(void)
1104 {
1105 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_invept_global(void)
1109 {
1110 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1111 }
1112
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1114 {
1115 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1116 }
1117
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1119 {
1120 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1121 }
1122
1123 static inline bool cpu_has_vmx_ept(void)
1124 {
1125 return vmcs_config.cpu_based_2nd_exec_ctrl &
1126 SECONDARY_EXEC_ENABLE_EPT;
1127 }
1128
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1130 {
1131 return vmcs_config.cpu_based_2nd_exec_ctrl &
1132 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1133 }
1134
1135 static inline bool cpu_has_vmx_ple(void)
1136 {
1137 return vmcs_config.cpu_based_2nd_exec_ctrl &
1138 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1139 }
1140
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1142 {
1143 return flexpriority_enabled && lapic_in_kernel(vcpu);
1144 }
1145
1146 static inline bool cpu_has_vmx_vpid(void)
1147 {
1148 return vmcs_config.cpu_based_2nd_exec_ctrl &
1149 SECONDARY_EXEC_ENABLE_VPID;
1150 }
1151
1152 static inline bool cpu_has_vmx_rdtscp(void)
1153 {
1154 return vmcs_config.cpu_based_2nd_exec_ctrl &
1155 SECONDARY_EXEC_RDTSCP;
1156 }
1157
1158 static inline bool cpu_has_vmx_invpcid(void)
1159 {
1160 return vmcs_config.cpu_based_2nd_exec_ctrl &
1161 SECONDARY_EXEC_ENABLE_INVPCID;
1162 }
1163
1164 static inline bool cpu_has_virtual_nmis(void)
1165 {
1166 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1167 }
1168
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1170 {
1171 return vmcs_config.cpu_based_2nd_exec_ctrl &
1172 SECONDARY_EXEC_WBINVD_EXITING;
1173 }
1174
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1176 {
1177 u64 vmx_msr;
1178 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1179 /* check if the cpu supports writing r/o exit information fields */
1180 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1181 return false;
1182
1183 return vmcs_config.cpu_based_2nd_exec_ctrl &
1184 SECONDARY_EXEC_SHADOW_VMCS;
1185 }
1186
1187 static inline bool cpu_has_vmx_pml(void)
1188 {
1189 return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1190 }
1191
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1193 {
1194 return vmcs_config.cpu_based_2nd_exec_ctrl &
1195 SECONDARY_EXEC_TSC_SCALING;
1196 }
1197
1198 static inline bool report_flexpriority(void)
1199 {
1200 return flexpriority_enabled;
1201 }
1202
1203 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205 return vmcs12->cpu_based_vm_exec_control & bit;
1206 }
1207
1208 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1209 {
1210 return (vmcs12->cpu_based_vm_exec_control &
1211 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1212 (vmcs12->secondary_vm_exec_control & bit);
1213 }
1214
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1216 {
1217 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1218 }
1219
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1221 {
1222 return vmcs12->pin_based_vm_exec_control &
1223 PIN_BASED_VMX_PREEMPTION_TIMER;
1224 }
1225
1226 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1227 {
1228 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1229 }
1230
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1232 {
1233 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1234 vmx_xsaves_supported();
1235 }
1236
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1238 {
1239 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1240 }
1241
1242 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1243 {
1244 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1245 }
1246
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1248 {
1249 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1250 }
1251
1252 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1253 {
1254 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1255 }
1256
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1258 {
1259 return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1260 }
1261
1262 static inline bool is_exception(u32 intr_info)
1263 {
1264 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1265 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1266 }
1267
1268 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1269 u32 exit_intr_info,
1270 unsigned long exit_qualification);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1272 struct vmcs12 *vmcs12,
1273 u32 reason, unsigned long qualification);
1274
1275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1276 {
1277 int i;
1278
1279 for (i = 0; i < vmx->nmsrs; ++i)
1280 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1281 return i;
1282 return -1;
1283 }
1284
1285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1286 {
1287 struct {
1288 u64 vpid : 16;
1289 u64 rsvd : 48;
1290 u64 gva;
1291 } operand = { vpid, 0, gva };
1292
1293 asm volatile (__ex(ASM_VMX_INVVPID)
1294 /* CF==1 or ZF==1 --> rc = -1 */
1295 "; ja 1f ; ud2 ; 1:"
1296 : : "a"(&operand), "c"(ext) : "cc", "memory");
1297 }
1298
1299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1300 {
1301 struct {
1302 u64 eptp, gpa;
1303 } operand = {eptp, gpa};
1304
1305 asm volatile (__ex(ASM_VMX_INVEPT)
1306 /* CF==1 or ZF==1 --> rc = -1 */
1307 "; ja 1f ; ud2 ; 1:\n"
1308 : : "a" (&operand), "c" (ext) : "cc", "memory");
1309 }
1310
1311 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1312 {
1313 int i;
1314
1315 i = __find_msr_index(vmx, msr);
1316 if (i >= 0)
1317 return &vmx->guest_msrs[i];
1318 return NULL;
1319 }
1320
1321 static void vmcs_clear(struct vmcs *vmcs)
1322 {
1323 u64 phys_addr = __pa(vmcs);
1324 u8 error;
1325
1326 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1327 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1328 : "cc", "memory");
1329 if (error)
1330 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1331 vmcs, phys_addr);
1332 }
1333
1334 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1335 {
1336 vmcs_clear(loaded_vmcs->vmcs);
1337 loaded_vmcs->cpu = -1;
1338 loaded_vmcs->launched = 0;
1339 }
1340
1341 static void vmcs_load(struct vmcs *vmcs)
1342 {
1343 u64 phys_addr = __pa(vmcs);
1344 u8 error;
1345
1346 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1347 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1348 : "cc", "memory");
1349 if (error)
1350 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1351 vmcs, phys_addr);
1352 }
1353
1354 #ifdef CONFIG_KEXEC_CORE
1355 /*
1356 * This bitmap is used to indicate whether the vmclear
1357 * operation is enabled on all cpus. All disabled by
1358 * default.
1359 */
1360 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1361
1362 static inline void crash_enable_local_vmclear(int cpu)
1363 {
1364 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366
1367 static inline void crash_disable_local_vmclear(int cpu)
1368 {
1369 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371
1372 static inline int crash_local_vmclear_enabled(int cpu)
1373 {
1374 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1375 }
1376
1377 static void crash_vmclear_local_loaded_vmcss(void)
1378 {
1379 int cpu = raw_smp_processor_id();
1380 struct loaded_vmcs *v;
1381
1382 if (!crash_local_vmclear_enabled(cpu))
1383 return;
1384
1385 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1386 loaded_vmcss_on_cpu_link)
1387 vmcs_clear(v->vmcs);
1388 }
1389 #else
1390 static inline void crash_enable_local_vmclear(int cpu) { }
1391 static inline void crash_disable_local_vmclear(int cpu) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1393
1394 static void __loaded_vmcs_clear(void *arg)
1395 {
1396 struct loaded_vmcs *loaded_vmcs = arg;
1397 int cpu = raw_smp_processor_id();
1398
1399 if (loaded_vmcs->cpu != cpu)
1400 return; /* vcpu migration can race with cpu offline */
1401 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1402 per_cpu(current_vmcs, cpu) = NULL;
1403 crash_disable_local_vmclear(cpu);
1404 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1405
1406 /*
1407 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408 * is before setting loaded_vmcs->vcpu to -1 which is done in
1409 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410 * then adds the vmcs into percpu list before it is deleted.
1411 */
1412 smp_wmb();
1413
1414 loaded_vmcs_init(loaded_vmcs);
1415 crash_enable_local_vmclear(cpu);
1416 }
1417
1418 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1419 {
1420 int cpu = loaded_vmcs->cpu;
1421
1422 if (cpu != -1)
1423 smp_call_function_single(cpu,
1424 __loaded_vmcs_clear, loaded_vmcs, 1);
1425 }
1426
1427 static inline void vpid_sync_vcpu_single(int vpid)
1428 {
1429 if (vpid == 0)
1430 return;
1431
1432 if (cpu_has_vmx_invvpid_single())
1433 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1434 }
1435
1436 static inline void vpid_sync_vcpu_global(void)
1437 {
1438 if (cpu_has_vmx_invvpid_global())
1439 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1440 }
1441
1442 static inline void vpid_sync_context(int vpid)
1443 {
1444 if (cpu_has_vmx_invvpid_single())
1445 vpid_sync_vcpu_single(vpid);
1446 else
1447 vpid_sync_vcpu_global();
1448 }
1449
1450 static inline void ept_sync_global(void)
1451 {
1452 if (cpu_has_vmx_invept_global())
1453 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1454 }
1455
1456 static inline void ept_sync_context(u64 eptp)
1457 {
1458 if (enable_ept) {
1459 if (cpu_has_vmx_invept_context())
1460 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1461 else
1462 ept_sync_global();
1463 }
1464 }
1465
1466 static __always_inline void vmcs_check16(unsigned long field)
1467 {
1468 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1469 "16-bit accessor invalid for 64-bit field");
1470 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1471 "16-bit accessor invalid for 64-bit high field");
1472 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1473 "16-bit accessor invalid for 32-bit high field");
1474 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1475 "16-bit accessor invalid for natural width field");
1476 }
1477
1478 static __always_inline void vmcs_check32(unsigned long field)
1479 {
1480 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1481 "32-bit accessor invalid for 16-bit field");
1482 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1483 "32-bit accessor invalid for natural width field");
1484 }
1485
1486 static __always_inline void vmcs_check64(unsigned long field)
1487 {
1488 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1489 "64-bit accessor invalid for 16-bit field");
1490 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491 "64-bit accessor invalid for 64-bit high field");
1492 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493 "64-bit accessor invalid for 32-bit field");
1494 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1495 "64-bit accessor invalid for natural width field");
1496 }
1497
1498 static __always_inline void vmcs_checkl(unsigned long field)
1499 {
1500 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1501 "Natural width accessor invalid for 16-bit field");
1502 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1503 "Natural width accessor invalid for 64-bit field");
1504 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1505 "Natural width accessor invalid for 64-bit high field");
1506 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1507 "Natural width accessor invalid for 32-bit field");
1508 }
1509
1510 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1511 {
1512 unsigned long value;
1513
1514 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1515 : "=a"(value) : "d"(field) : "cc");
1516 return value;
1517 }
1518
1519 static __always_inline u16 vmcs_read16(unsigned long field)
1520 {
1521 vmcs_check16(field);
1522 return __vmcs_readl(field);
1523 }
1524
1525 static __always_inline u32 vmcs_read32(unsigned long field)
1526 {
1527 vmcs_check32(field);
1528 return __vmcs_readl(field);
1529 }
1530
1531 static __always_inline u64 vmcs_read64(unsigned long field)
1532 {
1533 vmcs_check64(field);
1534 #ifdef CONFIG_X86_64
1535 return __vmcs_readl(field);
1536 #else
1537 return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1538 #endif
1539 }
1540
1541 static __always_inline unsigned long vmcs_readl(unsigned long field)
1542 {
1543 vmcs_checkl(field);
1544 return __vmcs_readl(field);
1545 }
1546
1547 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1548 {
1549 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1550 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1551 dump_stack();
1552 }
1553
1554 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1555 {
1556 u8 error;
1557
1558 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1559 : "=q"(error) : "a"(value), "d"(field) : "cc");
1560 if (unlikely(error))
1561 vmwrite_error(field, value);
1562 }
1563
1564 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1565 {
1566 vmcs_check16(field);
1567 __vmcs_writel(field, value);
1568 }
1569
1570 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1571 {
1572 vmcs_check32(field);
1573 __vmcs_writel(field, value);
1574 }
1575
1576 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1577 {
1578 vmcs_check64(field);
1579 __vmcs_writel(field, value);
1580 #ifndef CONFIG_X86_64
1581 asm volatile ("");
1582 __vmcs_writel(field+1, value >> 32);
1583 #endif
1584 }
1585
1586 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1587 {
1588 vmcs_checkl(field);
1589 __vmcs_writel(field, value);
1590 }
1591
1592 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1593 {
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1595 "vmcs_clear_bits does not support 64-bit fields");
1596 __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1597 }
1598
1599 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1600 {
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1602 "vmcs_set_bits does not support 64-bit fields");
1603 __vmcs_writel(field, __vmcs_readl(field) | mask);
1604 }
1605
1606 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1607 {
1608 vmcs_write32(VM_ENTRY_CONTROLS, val);
1609 vmx->vm_entry_controls_shadow = val;
1610 }
1611
1612 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1613 {
1614 if (vmx->vm_entry_controls_shadow != val)
1615 vm_entry_controls_init(vmx, val);
1616 }
1617
1618 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1619 {
1620 return vmx->vm_entry_controls_shadow;
1621 }
1622
1623
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1627 }
1628
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1630 {
1631 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1632 }
1633
1634 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1635 {
1636 vmcs_write32(VM_EXIT_CONTROLS, val);
1637 vmx->vm_exit_controls_shadow = val;
1638 }
1639
1640 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1641 {
1642 if (vmx->vm_exit_controls_shadow != val)
1643 vm_exit_controls_init(vmx, val);
1644 }
1645
1646 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1647 {
1648 return vmx->vm_exit_controls_shadow;
1649 }
1650
1651
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1655 }
1656
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1658 {
1659 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1660 }
1661
1662 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1663 {
1664 vmx->segment_cache.bitmask = 0;
1665 }
1666
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1668 unsigned field)
1669 {
1670 bool ret;
1671 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1672
1673 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1674 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1675 vmx->segment_cache.bitmask = 0;
1676 }
1677 ret = vmx->segment_cache.bitmask & mask;
1678 vmx->segment_cache.bitmask |= mask;
1679 return ret;
1680 }
1681
1682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1683 {
1684 u16 *p = &vmx->segment_cache.seg[seg].selector;
1685
1686 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1687 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1688 return *p;
1689 }
1690
1691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1692 {
1693 ulong *p = &vmx->segment_cache.seg[seg].base;
1694
1695 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1696 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1697 return *p;
1698 }
1699
1700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1701 {
1702 u32 *p = &vmx->segment_cache.seg[seg].limit;
1703
1704 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1705 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1706 return *p;
1707 }
1708
1709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1710 {
1711 u32 *p = &vmx->segment_cache.seg[seg].ar;
1712
1713 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1714 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1715 return *p;
1716 }
1717
1718 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1719 {
1720 u32 eb;
1721
1722 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1723 (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1724 if ((vcpu->guest_debug &
1725 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1726 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1727 eb |= 1u << BP_VECTOR;
1728 if (to_vmx(vcpu)->rmode.vm86_active)
1729 eb = ~0;
1730 if (enable_ept)
1731 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1732 if (vcpu->fpu_active)
1733 eb &= ~(1u << NM_VECTOR);
1734
1735 /* When we are running a nested L2 guest and L1 specified for it a
1736 * certain exception bitmap, we must trap the same exceptions and pass
1737 * them to L1. When running L2, we will only handle the exceptions
1738 * specified above if L1 did not want them.
1739 */
1740 if (is_guest_mode(vcpu))
1741 eb |= get_vmcs12(vcpu)->exception_bitmap;
1742
1743 vmcs_write32(EXCEPTION_BITMAP, eb);
1744 }
1745
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1747 unsigned long entry, unsigned long exit)
1748 {
1749 vm_entry_controls_clearbit(vmx, entry);
1750 vm_exit_controls_clearbit(vmx, exit);
1751 }
1752
1753 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1754 {
1755 unsigned i;
1756 struct msr_autoload *m = &vmx->msr_autoload;
1757
1758 switch (msr) {
1759 case MSR_EFER:
1760 if (cpu_has_load_ia32_efer) {
1761 clear_atomic_switch_msr_special(vmx,
1762 VM_ENTRY_LOAD_IA32_EFER,
1763 VM_EXIT_LOAD_IA32_EFER);
1764 return;
1765 }
1766 break;
1767 case MSR_CORE_PERF_GLOBAL_CTRL:
1768 if (cpu_has_load_perf_global_ctrl) {
1769 clear_atomic_switch_msr_special(vmx,
1770 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1771 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1772 return;
1773 }
1774 break;
1775 }
1776
1777 for (i = 0; i < m->nr; ++i)
1778 if (m->guest[i].index == msr)
1779 break;
1780
1781 if (i == m->nr)
1782 return;
1783 --m->nr;
1784 m->guest[i] = m->guest[m->nr];
1785 m->host[i] = m->host[m->nr];
1786 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1787 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1788 }
1789
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1791 unsigned long entry, unsigned long exit,
1792 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1793 u64 guest_val, u64 host_val)
1794 {
1795 vmcs_write64(guest_val_vmcs, guest_val);
1796 vmcs_write64(host_val_vmcs, host_val);
1797 vm_entry_controls_setbit(vmx, entry);
1798 vm_exit_controls_setbit(vmx, exit);
1799 }
1800
1801 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1802 u64 guest_val, u64 host_val)
1803 {
1804 unsigned i;
1805 struct msr_autoload *m = &vmx->msr_autoload;
1806
1807 switch (msr) {
1808 case MSR_EFER:
1809 if (cpu_has_load_ia32_efer) {
1810 add_atomic_switch_msr_special(vmx,
1811 VM_ENTRY_LOAD_IA32_EFER,
1812 VM_EXIT_LOAD_IA32_EFER,
1813 GUEST_IA32_EFER,
1814 HOST_IA32_EFER,
1815 guest_val, host_val);
1816 return;
1817 }
1818 break;
1819 case MSR_CORE_PERF_GLOBAL_CTRL:
1820 if (cpu_has_load_perf_global_ctrl) {
1821 add_atomic_switch_msr_special(vmx,
1822 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1823 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1824 GUEST_IA32_PERF_GLOBAL_CTRL,
1825 HOST_IA32_PERF_GLOBAL_CTRL,
1826 guest_val, host_val);
1827 return;
1828 }
1829 break;
1830 case MSR_IA32_PEBS_ENABLE:
1831 /* PEBS needs a quiescent period after being disabled (to write
1832 * a record). Disabling PEBS through VMX MSR swapping doesn't
1833 * provide that period, so a CPU could write host's record into
1834 * guest's memory.
1835 */
1836 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1837 }
1838
1839 for (i = 0; i < m->nr; ++i)
1840 if (m->guest[i].index == msr)
1841 break;
1842
1843 if (i == NR_AUTOLOAD_MSRS) {
1844 printk_once(KERN_WARNING "Not enough msr switch entries. "
1845 "Can't add msr %x\n", msr);
1846 return;
1847 } else if (i == m->nr) {
1848 ++m->nr;
1849 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1850 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1851 }
1852
1853 m->guest[i].index = msr;
1854 m->guest[i].value = guest_val;
1855 m->host[i].index = msr;
1856 m->host[i].value = host_val;
1857 }
1858
1859 static void reload_tss(void)
1860 {
1861 /*
1862 * VT restores TR but not its size. Useless.
1863 */
1864 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1865 struct desc_struct *descs;
1866
1867 descs = (void *)gdt->address;
1868 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1869 load_TR_desc();
1870 }
1871
1872 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1873 {
1874 u64 guest_efer = vmx->vcpu.arch.efer;
1875 u64 ignore_bits = 0;
1876
1877 if (!enable_ept) {
1878 /*
1879 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1880 * host CPUID is more efficient than testing guest CPUID
1881 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1882 */
1883 if (boot_cpu_has(X86_FEATURE_SMEP))
1884 guest_efer |= EFER_NX;
1885 else if (!(guest_efer & EFER_NX))
1886 ignore_bits |= EFER_NX;
1887 }
1888
1889 /*
1890 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1891 */
1892 ignore_bits |= EFER_SCE;
1893 #ifdef CONFIG_X86_64
1894 ignore_bits |= EFER_LMA | EFER_LME;
1895 /* SCE is meaningful only in long mode on Intel */
1896 if (guest_efer & EFER_LMA)
1897 ignore_bits &= ~(u64)EFER_SCE;
1898 #endif
1899
1900 clear_atomic_switch_msr(vmx, MSR_EFER);
1901
1902 /*
1903 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904 * On CPUs that support "load IA32_EFER", always switch EFER
1905 * atomically, since it's faster than switching it manually.
1906 */
1907 if (cpu_has_load_ia32_efer ||
1908 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1909 if (!(guest_efer & EFER_LMA))
1910 guest_efer &= ~EFER_LME;
1911 if (guest_efer != host_efer)
1912 add_atomic_switch_msr(vmx, MSR_EFER,
1913 guest_efer, host_efer);
1914 return false;
1915 } else {
1916 guest_efer &= ~ignore_bits;
1917 guest_efer |= host_efer & ignore_bits;
1918
1919 vmx->guest_msrs[efer_offset].data = guest_efer;
1920 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1921
1922 return true;
1923 }
1924 }
1925
1926 static unsigned long segment_base(u16 selector)
1927 {
1928 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1929 struct desc_struct *d;
1930 unsigned long table_base;
1931 unsigned long v;
1932
1933 if (!(selector & ~3))
1934 return 0;
1935
1936 table_base = gdt->address;
1937
1938 if (selector & 4) { /* from ldt */
1939 u16 ldt_selector = kvm_read_ldt();
1940
1941 if (!(ldt_selector & ~3))
1942 return 0;
1943
1944 table_base = segment_base(ldt_selector);
1945 }
1946 d = (struct desc_struct *)(table_base + (selector & ~7));
1947 v = get_desc_base(d);
1948 #ifdef CONFIG_X86_64
1949 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1950 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1951 #endif
1952 return v;
1953 }
1954
1955 static inline unsigned long kvm_read_tr_base(void)
1956 {
1957 u16 tr;
1958 asm("str %0" : "=g"(tr));
1959 return segment_base(tr);
1960 }
1961
1962 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1963 {
1964 struct vcpu_vmx *vmx = to_vmx(vcpu);
1965 int i;
1966
1967 if (vmx->host_state.loaded)
1968 return;
1969
1970 vmx->host_state.loaded = 1;
1971 /*
1972 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1973 * allow segment selectors with cpl > 0 or ti == 1.
1974 */
1975 vmx->host_state.ldt_sel = kvm_read_ldt();
1976 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1977 savesegment(fs, vmx->host_state.fs_sel);
1978 if (!(vmx->host_state.fs_sel & 7)) {
1979 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1980 vmx->host_state.fs_reload_needed = 0;
1981 } else {
1982 vmcs_write16(HOST_FS_SELECTOR, 0);
1983 vmx->host_state.fs_reload_needed = 1;
1984 }
1985 savesegment(gs, vmx->host_state.gs_sel);
1986 if (!(vmx->host_state.gs_sel & 7))
1987 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1988 else {
1989 vmcs_write16(HOST_GS_SELECTOR, 0);
1990 vmx->host_state.gs_ldt_reload_needed = 1;
1991 }
1992
1993 #ifdef CONFIG_X86_64
1994 savesegment(ds, vmx->host_state.ds_sel);
1995 savesegment(es, vmx->host_state.es_sel);
1996 #endif
1997
1998 #ifdef CONFIG_X86_64
1999 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2000 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2001 #else
2002 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2003 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2004 #endif
2005
2006 #ifdef CONFIG_X86_64
2007 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2008 if (is_long_mode(&vmx->vcpu))
2009 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2010 #endif
2011 if (boot_cpu_has(X86_FEATURE_MPX))
2012 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2013 for (i = 0; i < vmx->save_nmsrs; ++i)
2014 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2015 vmx->guest_msrs[i].data,
2016 vmx->guest_msrs[i].mask);
2017 }
2018
2019 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2020 {
2021 if (!vmx->host_state.loaded)
2022 return;
2023
2024 ++vmx->vcpu.stat.host_state_reload;
2025 vmx->host_state.loaded = 0;
2026 #ifdef CONFIG_X86_64
2027 if (is_long_mode(&vmx->vcpu))
2028 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2029 #endif
2030 if (vmx->host_state.gs_ldt_reload_needed) {
2031 kvm_load_ldt(vmx->host_state.ldt_sel);
2032 #ifdef CONFIG_X86_64
2033 load_gs_index(vmx->host_state.gs_sel);
2034 #else
2035 loadsegment(gs, vmx->host_state.gs_sel);
2036 #endif
2037 }
2038 if (vmx->host_state.fs_reload_needed)
2039 loadsegment(fs, vmx->host_state.fs_sel);
2040 #ifdef CONFIG_X86_64
2041 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2042 loadsegment(ds, vmx->host_state.ds_sel);
2043 loadsegment(es, vmx->host_state.es_sel);
2044 }
2045 #endif
2046 reload_tss();
2047 #ifdef CONFIG_X86_64
2048 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2049 #endif
2050 if (vmx->host_state.msr_host_bndcfgs)
2051 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2052 /*
2053 * If the FPU is not active (through the host task or
2054 * the guest vcpu), then restore the cr0.TS bit.
2055 */
2056 if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2057 stts();
2058 load_gdt(this_cpu_ptr(&host_gdt));
2059 }
2060
2061 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2062 {
2063 preempt_disable();
2064 __vmx_load_host_state(vmx);
2065 preempt_enable();
2066 }
2067
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2069 {
2070 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2071 struct pi_desc old, new;
2072 unsigned int dest;
2073
2074 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075 !irq_remapping_cap(IRQ_POSTING_CAP))
2076 return;
2077
2078 do {
2079 old.control = new.control = pi_desc->control;
2080
2081 /*
2082 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2083 * are two possible cases:
2084 * 1. After running 'pre_block', context switch
2085 * happened. For this case, 'sn' was set in
2086 * vmx_vcpu_put(), so we need to clear it here.
2087 * 2. After running 'pre_block', we were blocked,
2088 * and woken up by some other guy. For this case,
2089 * we don't need to do anything, 'pi_post_block'
2090 * will do everything for us. However, we cannot
2091 * check whether it is case #1 or case #2 here
2092 * (maybe, not needed), so we also clear sn here,
2093 * I think it is not a big deal.
2094 */
2095 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2096 if (vcpu->cpu != cpu) {
2097 dest = cpu_physical_id(cpu);
2098
2099 if (x2apic_enabled())
2100 new.ndst = dest;
2101 else
2102 new.ndst = (dest << 8) & 0xFF00;
2103 }
2104
2105 /* set 'NV' to 'notification vector' */
2106 new.nv = POSTED_INTR_VECTOR;
2107 }
2108
2109 /* Allow posting non-urgent interrupts */
2110 new.sn = 0;
2111 } while (cmpxchg(&pi_desc->control, old.control,
2112 new.control) != old.control);
2113 }
2114
2115 /*
2116 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2117 * vcpu mutex is already taken.
2118 */
2119 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2120 {
2121 struct vcpu_vmx *vmx = to_vmx(vcpu);
2122 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2123
2124 if (!vmm_exclusive)
2125 kvm_cpu_vmxon(phys_addr);
2126 else if (vmx->loaded_vmcs->cpu != cpu)
2127 loaded_vmcs_clear(vmx->loaded_vmcs);
2128
2129 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2130 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2131 vmcs_load(vmx->loaded_vmcs->vmcs);
2132 }
2133
2134 if (vmx->loaded_vmcs->cpu != cpu) {
2135 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2136 unsigned long sysenter_esp;
2137
2138 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2139 local_irq_disable();
2140 crash_disable_local_vmclear(cpu);
2141
2142 /*
2143 * Read loaded_vmcs->cpu should be before fetching
2144 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2145 * See the comments in __loaded_vmcs_clear().
2146 */
2147 smp_rmb();
2148
2149 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2150 &per_cpu(loaded_vmcss_on_cpu, cpu));
2151 crash_enable_local_vmclear(cpu);
2152 local_irq_enable();
2153
2154 /*
2155 * Linux uses per-cpu TSS and GDT, so set these when switching
2156 * processors.
2157 */
2158 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2159 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
2160
2161 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2162 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2163
2164 vmx->loaded_vmcs->cpu = cpu;
2165 }
2166
2167 /* Setup TSC multiplier */
2168 if (kvm_has_tsc_control &&
2169 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2170 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2171 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2172 }
2173
2174 vmx_vcpu_pi_load(vcpu, cpu);
2175 vmx->host_pkru = read_pkru();
2176 }
2177
2178 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2179 {
2180 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2181
2182 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2183 !irq_remapping_cap(IRQ_POSTING_CAP))
2184 return;
2185
2186 /* Set SN when the vCPU is preempted */
2187 if (vcpu->preempted)
2188 pi_set_sn(pi_desc);
2189 }
2190
2191 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2192 {
2193 vmx_vcpu_pi_put(vcpu);
2194
2195 __vmx_load_host_state(to_vmx(vcpu));
2196 if (!vmm_exclusive) {
2197 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2198 vcpu->cpu = -1;
2199 kvm_cpu_vmxoff();
2200 }
2201 }
2202
2203 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2204 {
2205 ulong cr0;
2206
2207 if (vcpu->fpu_active)
2208 return;
2209 vcpu->fpu_active = 1;
2210 cr0 = vmcs_readl(GUEST_CR0);
2211 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2212 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2213 vmcs_writel(GUEST_CR0, cr0);
2214 update_exception_bitmap(vcpu);
2215 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2216 if (is_guest_mode(vcpu))
2217 vcpu->arch.cr0_guest_owned_bits &=
2218 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2219 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2220 }
2221
2222 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2223
2224 /*
2225 * Return the cr0 value that a nested guest would read. This is a combination
2226 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2227 * its hypervisor (cr0_read_shadow).
2228 */
2229 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2230 {
2231 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2232 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2233 }
2234 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2235 {
2236 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2237 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2238 }
2239
2240 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2241 {
2242 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2243 * set this *before* calling this function.
2244 */
2245 vmx_decache_cr0_guest_bits(vcpu);
2246 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2247 update_exception_bitmap(vcpu);
2248 vcpu->arch.cr0_guest_owned_bits = 0;
2249 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2250 if (is_guest_mode(vcpu)) {
2251 /*
2252 * L1's specified read shadow might not contain the TS bit,
2253 * so now that we turned on shadowing of this bit, we need to
2254 * set this bit of the shadow. Like in nested_vmx_run we need
2255 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2256 * up-to-date here because we just decached cr0.TS (and we'll
2257 * only update vmcs12->guest_cr0 on nested exit).
2258 */
2259 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2260 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2261 (vcpu->arch.cr0 & X86_CR0_TS);
2262 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2263 } else
2264 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2265 }
2266
2267 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2268 {
2269 unsigned long rflags, save_rflags;
2270
2271 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2272 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2273 rflags = vmcs_readl(GUEST_RFLAGS);
2274 if (to_vmx(vcpu)->rmode.vm86_active) {
2275 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2276 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2277 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2278 }
2279 to_vmx(vcpu)->rflags = rflags;
2280 }
2281 return to_vmx(vcpu)->rflags;
2282 }
2283
2284 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2285 {
2286 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2287 to_vmx(vcpu)->rflags = rflags;
2288 if (to_vmx(vcpu)->rmode.vm86_active) {
2289 to_vmx(vcpu)->rmode.save_rflags = rflags;
2290 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2291 }
2292 vmcs_writel(GUEST_RFLAGS, rflags);
2293 }
2294
2295 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2296 {
2297 return to_vmx(vcpu)->guest_pkru;
2298 }
2299
2300 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2301 {
2302 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2303 int ret = 0;
2304
2305 if (interruptibility & GUEST_INTR_STATE_STI)
2306 ret |= KVM_X86_SHADOW_INT_STI;
2307 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2308 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2309
2310 return ret;
2311 }
2312
2313 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2314 {
2315 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2316 u32 interruptibility = interruptibility_old;
2317
2318 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2319
2320 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2321 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2322 else if (mask & KVM_X86_SHADOW_INT_STI)
2323 interruptibility |= GUEST_INTR_STATE_STI;
2324
2325 if ((interruptibility != interruptibility_old))
2326 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2327 }
2328
2329 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2330 {
2331 unsigned long rip;
2332
2333 rip = kvm_rip_read(vcpu);
2334 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2335 kvm_rip_write(vcpu, rip);
2336
2337 /* skipping an emulated instruction also counts */
2338 vmx_set_interrupt_shadow(vcpu, 0);
2339 }
2340
2341 /*
2342 * KVM wants to inject page-faults which it got to the guest. This function
2343 * checks whether in a nested guest, we need to inject them to L1 or L2.
2344 */
2345 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2346 {
2347 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2348
2349 if (!(vmcs12->exception_bitmap & (1u << nr)))
2350 return 0;
2351
2352 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2353 vmcs_read32(VM_EXIT_INTR_INFO),
2354 vmcs_readl(EXIT_QUALIFICATION));
2355 return 1;
2356 }
2357
2358 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2359 bool has_error_code, u32 error_code,
2360 bool reinject)
2361 {
2362 struct vcpu_vmx *vmx = to_vmx(vcpu);
2363 u32 intr_info = nr | INTR_INFO_VALID_MASK;
2364
2365 if (!reinject && is_guest_mode(vcpu) &&
2366 nested_vmx_check_exception(vcpu, nr))
2367 return;
2368
2369 if (has_error_code) {
2370 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2371 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2372 }
2373
2374 if (vmx->rmode.vm86_active) {
2375 int inc_eip = 0;
2376 if (kvm_exception_is_soft(nr))
2377 inc_eip = vcpu->arch.event_exit_inst_len;
2378 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2379 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2380 return;
2381 }
2382
2383 if (kvm_exception_is_soft(nr)) {
2384 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2385 vmx->vcpu.arch.event_exit_inst_len);
2386 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2387 } else
2388 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2389
2390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2391 }
2392
2393 static bool vmx_rdtscp_supported(void)
2394 {
2395 return cpu_has_vmx_rdtscp();
2396 }
2397
2398 static bool vmx_invpcid_supported(void)
2399 {
2400 return cpu_has_vmx_invpcid() && enable_ept;
2401 }
2402
2403 /*
2404 * Swap MSR entry in host/guest MSR entry array.
2405 */
2406 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2407 {
2408 struct shared_msr_entry tmp;
2409
2410 tmp = vmx->guest_msrs[to];
2411 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2412 vmx->guest_msrs[from] = tmp;
2413 }
2414
2415 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2416 {
2417 unsigned long *msr_bitmap;
2418
2419 if (is_guest_mode(vcpu))
2420 msr_bitmap = vmx_msr_bitmap_nested;
2421 else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2422 if (is_long_mode(vcpu))
2423 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2424 else
2425 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2426 } else {
2427 if (is_long_mode(vcpu))
2428 msr_bitmap = vmx_msr_bitmap_longmode;
2429 else
2430 msr_bitmap = vmx_msr_bitmap_legacy;
2431 }
2432
2433 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2434 }
2435
2436 /*
2437 * Set up the vmcs to automatically save and restore system
2438 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2439 * mode, as fiddling with msrs is very expensive.
2440 */
2441 static void setup_msrs(struct vcpu_vmx *vmx)
2442 {
2443 int save_nmsrs, index;
2444
2445 save_nmsrs = 0;
2446 #ifdef CONFIG_X86_64
2447 if (is_long_mode(&vmx->vcpu)) {
2448 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2449 if (index >= 0)
2450 move_msr_up(vmx, index, save_nmsrs++);
2451 index = __find_msr_index(vmx, MSR_LSTAR);
2452 if (index >= 0)
2453 move_msr_up(vmx, index, save_nmsrs++);
2454 index = __find_msr_index(vmx, MSR_CSTAR);
2455 if (index >= 0)
2456 move_msr_up(vmx, index, save_nmsrs++);
2457 index = __find_msr_index(vmx, MSR_TSC_AUX);
2458 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2459 move_msr_up(vmx, index, save_nmsrs++);
2460 /*
2461 * MSR_STAR is only needed on long mode guests, and only
2462 * if efer.sce is enabled.
2463 */
2464 index = __find_msr_index(vmx, MSR_STAR);
2465 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2466 move_msr_up(vmx, index, save_nmsrs++);
2467 }
2468 #endif
2469 index = __find_msr_index(vmx, MSR_EFER);
2470 if (index >= 0 && update_transition_efer(vmx, index))
2471 move_msr_up(vmx, index, save_nmsrs++);
2472
2473 vmx->save_nmsrs = save_nmsrs;
2474
2475 if (cpu_has_vmx_msr_bitmap())
2476 vmx_set_msr_bitmap(&vmx->vcpu);
2477 }
2478
2479 /*
2480 * reads and returns guest's timestamp counter "register"
2481 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2482 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2483 */
2484 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2485 {
2486 u64 host_tsc, tsc_offset;
2487
2488 host_tsc = rdtsc();
2489 tsc_offset = vmcs_read64(TSC_OFFSET);
2490 return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2491 }
2492
2493 /*
2494 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2495 * counter, even if a nested guest (L2) is currently running.
2496 */
2497 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2498 {
2499 u64 tsc_offset;
2500
2501 tsc_offset = is_guest_mode(vcpu) ?
2502 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2503 vmcs_read64(TSC_OFFSET);
2504 return host_tsc + tsc_offset;
2505 }
2506
2507 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2508 {
2509 return vmcs_read64(TSC_OFFSET);
2510 }
2511
2512 /*
2513 * writes 'offset' into guest's timestamp counter offset register
2514 */
2515 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2516 {
2517 if (is_guest_mode(vcpu)) {
2518 /*
2519 * We're here if L1 chose not to trap WRMSR to TSC. According
2520 * to the spec, this should set L1's TSC; The offset that L1
2521 * set for L2 remains unchanged, and still needs to be added
2522 * to the newly set TSC to get L2's TSC.
2523 */
2524 struct vmcs12 *vmcs12;
2525 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2526 /* recalculate vmcs02.TSC_OFFSET: */
2527 vmcs12 = get_vmcs12(vcpu);
2528 vmcs_write64(TSC_OFFSET, offset +
2529 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2530 vmcs12->tsc_offset : 0));
2531 } else {
2532 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2533 vmcs_read64(TSC_OFFSET), offset);
2534 vmcs_write64(TSC_OFFSET, offset);
2535 }
2536 }
2537
2538 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2539 {
2540 u64 offset = vmcs_read64(TSC_OFFSET);
2541
2542 vmcs_write64(TSC_OFFSET, offset + adjustment);
2543 if (is_guest_mode(vcpu)) {
2544 /* Even when running L2, the adjustment needs to apply to L1 */
2545 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2546 } else
2547 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2548 offset + adjustment);
2549 }
2550
2551 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2552 {
2553 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2554 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2555 }
2556
2557 /*
2558 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2559 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2560 * all guests if the "nested" module option is off, and can also be disabled
2561 * for a single guest by disabling its VMX cpuid bit.
2562 */
2563 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2564 {
2565 return nested && guest_cpuid_has_vmx(vcpu);
2566 }
2567
2568 /*
2569 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2570 * returned for the various VMX controls MSRs when nested VMX is enabled.
2571 * The same values should also be used to verify that vmcs12 control fields are
2572 * valid during nested entry from L1 to L2.
2573 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2574 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2575 * bit in the high half is on if the corresponding bit in the control field
2576 * may be on. See also vmx_control_verify().
2577 */
2578 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2579 {
2580 /*
2581 * Note that as a general rule, the high half of the MSRs (bits in
2582 * the control fields which may be 1) should be initialized by the
2583 * intersection of the underlying hardware's MSR (i.e., features which
2584 * can be supported) and the list of features we want to expose -
2585 * because they are known to be properly supported in our code.
2586 * Also, usually, the low half of the MSRs (bits which must be 1) can
2587 * be set to 0, meaning that L1 may turn off any of these bits. The
2588 * reason is that if one of these bits is necessary, it will appear
2589 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2590 * fields of vmcs01 and vmcs02, will turn these bits off - and
2591 * nested_vmx_exit_handled() will not pass related exits to L1.
2592 * These rules have exceptions below.
2593 */
2594
2595 /* pin-based controls */
2596 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2597 vmx->nested.nested_vmx_pinbased_ctls_low,
2598 vmx->nested.nested_vmx_pinbased_ctls_high);
2599 vmx->nested.nested_vmx_pinbased_ctls_low |=
2600 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2601 vmx->nested.nested_vmx_pinbased_ctls_high &=
2602 PIN_BASED_EXT_INTR_MASK |
2603 PIN_BASED_NMI_EXITING |
2604 PIN_BASED_VIRTUAL_NMIS;
2605 vmx->nested.nested_vmx_pinbased_ctls_high |=
2606 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2607 PIN_BASED_VMX_PREEMPTION_TIMER;
2608 if (kvm_vcpu_apicv_active(&vmx->vcpu))
2609 vmx->nested.nested_vmx_pinbased_ctls_high |=
2610 PIN_BASED_POSTED_INTR;
2611
2612 /* exit controls */
2613 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2614 vmx->nested.nested_vmx_exit_ctls_low,
2615 vmx->nested.nested_vmx_exit_ctls_high);
2616 vmx->nested.nested_vmx_exit_ctls_low =
2617 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2618
2619 vmx->nested.nested_vmx_exit_ctls_high &=
2620 #ifdef CONFIG_X86_64
2621 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2622 #endif
2623 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2624 vmx->nested.nested_vmx_exit_ctls_high |=
2625 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2626 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2627 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2628
2629 if (kvm_mpx_supported())
2630 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2631
2632 /* We support free control of debug control saving. */
2633 vmx->nested.nested_vmx_true_exit_ctls_low =
2634 vmx->nested.nested_vmx_exit_ctls_low &
2635 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2636
2637 /* entry controls */
2638 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2639 vmx->nested.nested_vmx_entry_ctls_low,
2640 vmx->nested.nested_vmx_entry_ctls_high);
2641 vmx->nested.nested_vmx_entry_ctls_low =
2642 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2643 vmx->nested.nested_vmx_entry_ctls_high &=
2644 #ifdef CONFIG_X86_64
2645 VM_ENTRY_IA32E_MODE |
2646 #endif
2647 VM_ENTRY_LOAD_IA32_PAT;
2648 vmx->nested.nested_vmx_entry_ctls_high |=
2649 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2650 if (kvm_mpx_supported())
2651 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2652
2653 /* We support free control of debug control loading. */
2654 vmx->nested.nested_vmx_true_entry_ctls_low =
2655 vmx->nested.nested_vmx_entry_ctls_low &
2656 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2657
2658 /* cpu-based controls */
2659 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2660 vmx->nested.nested_vmx_procbased_ctls_low,
2661 vmx->nested.nested_vmx_procbased_ctls_high);
2662 vmx->nested.nested_vmx_procbased_ctls_low =
2663 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2664 vmx->nested.nested_vmx_procbased_ctls_high &=
2665 CPU_BASED_VIRTUAL_INTR_PENDING |
2666 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2667 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2668 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2669 CPU_BASED_CR3_STORE_EXITING |
2670 #ifdef CONFIG_X86_64
2671 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2672 #endif
2673 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2674 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2675 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2676 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2677 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2678 /*
2679 * We can allow some features even when not supported by the
2680 * hardware. For example, L1 can specify an MSR bitmap - and we
2681 * can use it to avoid exits to L1 - even when L0 runs L2
2682 * without MSR bitmaps.
2683 */
2684 vmx->nested.nested_vmx_procbased_ctls_high |=
2685 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2686 CPU_BASED_USE_MSR_BITMAPS;
2687
2688 /* We support free control of CR3 access interception. */
2689 vmx->nested.nested_vmx_true_procbased_ctls_low =
2690 vmx->nested.nested_vmx_procbased_ctls_low &
2691 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2692
2693 /* secondary cpu-based controls */
2694 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2695 vmx->nested.nested_vmx_secondary_ctls_low,
2696 vmx->nested.nested_vmx_secondary_ctls_high);
2697 vmx->nested.nested_vmx_secondary_ctls_low = 0;
2698 vmx->nested.nested_vmx_secondary_ctls_high &=
2699 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2700 SECONDARY_EXEC_RDTSCP |
2701 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2702 SECONDARY_EXEC_ENABLE_VPID |
2703 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2704 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2705 SECONDARY_EXEC_WBINVD_EXITING |
2706 SECONDARY_EXEC_XSAVES |
2707 SECONDARY_EXEC_PCOMMIT;
2708
2709 if (enable_ept) {
2710 /* nested EPT: emulate EPT also to L1 */
2711 vmx->nested.nested_vmx_secondary_ctls_high |=
2712 SECONDARY_EXEC_ENABLE_EPT;
2713 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2714 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2715 VMX_EPT_INVEPT_BIT;
2716 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2717 /*
2718 * For nested guests, we don't do anything specific
2719 * for single context invalidation. Hence, only advertise
2720 * support for global context invalidation.
2721 */
2722 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2723 } else
2724 vmx->nested.nested_vmx_ept_caps = 0;
2725
2726 /*
2727 * Old versions of KVM use the single-context version without
2728 * checking for support, so declare that it is supported even
2729 * though it is treated as global context. The alternative is
2730 * not failing the single-context invvpid, and it is worse.
2731 */
2732 if (enable_vpid)
2733 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2734 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2735 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2736 else
2737 vmx->nested.nested_vmx_vpid_caps = 0;
2738
2739 if (enable_unrestricted_guest)
2740 vmx->nested.nested_vmx_secondary_ctls_high |=
2741 SECONDARY_EXEC_UNRESTRICTED_GUEST;
2742
2743 /* miscellaneous data */
2744 rdmsr(MSR_IA32_VMX_MISC,
2745 vmx->nested.nested_vmx_misc_low,
2746 vmx->nested.nested_vmx_misc_high);
2747 vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2748 vmx->nested.nested_vmx_misc_low |=
2749 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2750 VMX_MISC_ACTIVITY_HLT;
2751 vmx->nested.nested_vmx_misc_high = 0;
2752 }
2753
2754 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2755 {
2756 /*
2757 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2758 */
2759 return ((control & high) | low) == control;
2760 }
2761
2762 static inline u64 vmx_control_msr(u32 low, u32 high)
2763 {
2764 return low | ((u64)high << 32);
2765 }
2766
2767 /* Returns 0 on success, non-0 otherwise. */
2768 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2769 {
2770 struct vcpu_vmx *vmx = to_vmx(vcpu);
2771
2772 switch (msr_index) {
2773 case MSR_IA32_VMX_BASIC:
2774 /*
2775 * This MSR reports some information about VMX support. We
2776 * should return information about the VMX we emulate for the
2777 * guest, and the VMCS structure we give it - not about the
2778 * VMX support of the underlying hardware.
2779 */
2780 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2781 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2782 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2783 break;
2784 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2785 case MSR_IA32_VMX_PINBASED_CTLS:
2786 *pdata = vmx_control_msr(
2787 vmx->nested.nested_vmx_pinbased_ctls_low,
2788 vmx->nested.nested_vmx_pinbased_ctls_high);
2789 break;
2790 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2791 *pdata = vmx_control_msr(
2792 vmx->nested.nested_vmx_true_procbased_ctls_low,
2793 vmx->nested.nested_vmx_procbased_ctls_high);
2794 break;
2795 case MSR_IA32_VMX_PROCBASED_CTLS:
2796 *pdata = vmx_control_msr(
2797 vmx->nested.nested_vmx_procbased_ctls_low,
2798 vmx->nested.nested_vmx_procbased_ctls_high);
2799 break;
2800 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2801 *pdata = vmx_control_msr(
2802 vmx->nested.nested_vmx_true_exit_ctls_low,
2803 vmx->nested.nested_vmx_exit_ctls_high);
2804 break;
2805 case MSR_IA32_VMX_EXIT_CTLS:
2806 *pdata = vmx_control_msr(
2807 vmx->nested.nested_vmx_exit_ctls_low,
2808 vmx->nested.nested_vmx_exit_ctls_high);
2809 break;
2810 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2811 *pdata = vmx_control_msr(
2812 vmx->nested.nested_vmx_true_entry_ctls_low,
2813 vmx->nested.nested_vmx_entry_ctls_high);
2814 break;
2815 case MSR_IA32_VMX_ENTRY_CTLS:
2816 *pdata = vmx_control_msr(
2817 vmx->nested.nested_vmx_entry_ctls_low,
2818 vmx->nested.nested_vmx_entry_ctls_high);
2819 break;
2820 case MSR_IA32_VMX_MISC:
2821 *pdata = vmx_control_msr(
2822 vmx->nested.nested_vmx_misc_low,
2823 vmx->nested.nested_vmx_misc_high);
2824 break;
2825 /*
2826 * These MSRs specify bits which the guest must keep fixed (on or off)
2827 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2828 * We picked the standard core2 setting.
2829 */
2830 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2831 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2832 case MSR_IA32_VMX_CR0_FIXED0:
2833 *pdata = VMXON_CR0_ALWAYSON;
2834 break;
2835 case MSR_IA32_VMX_CR0_FIXED1:
2836 *pdata = -1ULL;
2837 break;
2838 case MSR_IA32_VMX_CR4_FIXED0:
2839 *pdata = VMXON_CR4_ALWAYSON;
2840 break;
2841 case MSR_IA32_VMX_CR4_FIXED1:
2842 *pdata = -1ULL;
2843 break;
2844 case MSR_IA32_VMX_VMCS_ENUM:
2845 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2846 break;
2847 case MSR_IA32_VMX_PROCBASED_CTLS2:
2848 *pdata = vmx_control_msr(
2849 vmx->nested.nested_vmx_secondary_ctls_low,
2850 vmx->nested.nested_vmx_secondary_ctls_high);
2851 break;
2852 case MSR_IA32_VMX_EPT_VPID_CAP:
2853 /* Currently, no nested vpid support */
2854 *pdata = vmx->nested.nested_vmx_ept_caps |
2855 ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2856 break;
2857 default:
2858 return 1;
2859 }
2860
2861 return 0;
2862 }
2863
2864 /*
2865 * Reads an msr value (of 'msr_index') into 'pdata'.
2866 * Returns 0 on success, non-0 otherwise.
2867 * Assumes vcpu_load() was already called.
2868 */
2869 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2870 {
2871 struct shared_msr_entry *msr;
2872
2873 switch (msr_info->index) {
2874 #ifdef CONFIG_X86_64
2875 case MSR_FS_BASE:
2876 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2877 break;
2878 case MSR_GS_BASE:
2879 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2880 break;
2881 case MSR_KERNEL_GS_BASE:
2882 vmx_load_host_state(to_vmx(vcpu));
2883 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2884 break;
2885 #endif
2886 case MSR_EFER:
2887 return kvm_get_msr_common(vcpu, msr_info);
2888 case MSR_IA32_TSC:
2889 msr_info->data = guest_read_tsc(vcpu);
2890 break;
2891 case MSR_IA32_SYSENTER_CS:
2892 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2893 break;
2894 case MSR_IA32_SYSENTER_EIP:
2895 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2896 break;
2897 case MSR_IA32_SYSENTER_ESP:
2898 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2899 break;
2900 case MSR_IA32_BNDCFGS:
2901 if (!kvm_mpx_supported())
2902 return 1;
2903 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2904 break;
2905 case MSR_IA32_FEATURE_CONTROL:
2906 if (!nested_vmx_allowed(vcpu))
2907 return 1;
2908 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2909 break;
2910 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2911 if (!nested_vmx_allowed(vcpu))
2912 return 1;
2913 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2914 case MSR_IA32_XSS:
2915 if (!vmx_xsaves_supported())
2916 return 1;
2917 msr_info->data = vcpu->arch.ia32_xss;
2918 break;
2919 case MSR_TSC_AUX:
2920 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2921 return 1;
2922 /* Otherwise falls through */
2923 default:
2924 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2925 if (msr) {
2926 msr_info->data = msr->data;
2927 break;
2928 }
2929 return kvm_get_msr_common(vcpu, msr_info);
2930 }
2931
2932 return 0;
2933 }
2934
2935 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2936
2937 /*
2938 * Writes msr value into into the appropriate "register".
2939 * Returns 0 on success, non-0 otherwise.
2940 * Assumes vcpu_load() was already called.
2941 */
2942 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2943 {
2944 struct vcpu_vmx *vmx = to_vmx(vcpu);
2945 struct shared_msr_entry *msr;
2946 int ret = 0;
2947 u32 msr_index = msr_info->index;
2948 u64 data = msr_info->data;
2949
2950 switch (msr_index) {
2951 case MSR_EFER:
2952 ret = kvm_set_msr_common(vcpu, msr_info);
2953 break;
2954 #ifdef CONFIG_X86_64
2955 case MSR_FS_BASE:
2956 vmx_segment_cache_clear(vmx);
2957 vmcs_writel(GUEST_FS_BASE, data);
2958 break;
2959 case MSR_GS_BASE:
2960 vmx_segment_cache_clear(vmx);
2961 vmcs_writel(GUEST_GS_BASE, data);
2962 break;
2963 case MSR_KERNEL_GS_BASE:
2964 vmx_load_host_state(vmx);
2965 vmx->msr_guest_kernel_gs_base = data;
2966 break;
2967 #endif
2968 case MSR_IA32_SYSENTER_CS:
2969 vmcs_write32(GUEST_SYSENTER_CS, data);
2970 break;
2971 case MSR_IA32_SYSENTER_EIP:
2972 vmcs_writel(GUEST_SYSENTER_EIP, data);
2973 break;
2974 case MSR_IA32_SYSENTER_ESP:
2975 vmcs_writel(GUEST_SYSENTER_ESP, data);
2976 break;
2977 case MSR_IA32_BNDCFGS:
2978 if (!kvm_mpx_supported())
2979 return 1;
2980 vmcs_write64(GUEST_BNDCFGS, data);
2981 break;
2982 case MSR_IA32_TSC:
2983 kvm_write_tsc(vcpu, msr_info);
2984 break;
2985 case MSR_IA32_CR_PAT:
2986 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2987 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2988 return 1;
2989 vmcs_write64(GUEST_IA32_PAT, data);
2990 vcpu->arch.pat = data;
2991 break;
2992 }
2993 ret = kvm_set_msr_common(vcpu, msr_info);
2994 break;
2995 case MSR_IA32_TSC_ADJUST:
2996 ret = kvm_set_msr_common(vcpu, msr_info);
2997 break;
2998 case MSR_IA32_FEATURE_CONTROL:
2999 if (!nested_vmx_allowed(vcpu) ||
3000 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
3001 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3002 return 1;
3003 vmx->nested.msr_ia32_feature_control = data;
3004 if (msr_info->host_initiated && data == 0)
3005 vmx_leave_nested(vcpu);
3006 break;
3007 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3008 return 1; /* they are read-only */
3009 case MSR_IA32_XSS:
3010 if (!vmx_xsaves_supported())
3011 return 1;
3012 /*
3013 * The only supported bit as of Skylake is bit 8, but
3014 * it is not supported on KVM.
3015 */
3016 if (data != 0)
3017 return 1;
3018 vcpu->arch.ia32_xss = data;
3019 if (vcpu->arch.ia32_xss != host_xss)
3020 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3021 vcpu->arch.ia32_xss, host_xss);
3022 else
3023 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3024 break;
3025 case MSR_TSC_AUX:
3026 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3027 return 1;
3028 /* Check reserved bit, higher 32 bits should be zero */
3029 if ((data >> 32) != 0)
3030 return 1;
3031 /* Otherwise falls through */
3032 default:
3033 msr = find_msr_entry(vmx, msr_index);
3034 if (msr) {
3035 u64 old_msr_data = msr->data;
3036 msr->data = data;
3037 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3038 preempt_disable();
3039 ret = kvm_set_shared_msr(msr->index, msr->data,
3040 msr->mask);
3041 preempt_enable();
3042 if (ret)
3043 msr->data = old_msr_data;
3044 }
3045 break;
3046 }
3047 ret = kvm_set_msr_common(vcpu, msr_info);
3048 }
3049
3050 return ret;
3051 }
3052
3053 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3054 {
3055 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3056 switch (reg) {
3057 case VCPU_REGS_RSP:
3058 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3059 break;
3060 case VCPU_REGS_RIP:
3061 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3062 break;
3063 case VCPU_EXREG_PDPTR:
3064 if (enable_ept)
3065 ept_save_pdptrs(vcpu);
3066 break;
3067 default:
3068 break;
3069 }
3070 }
3071
3072 static __init int cpu_has_kvm_support(void)
3073 {
3074 return cpu_has_vmx();
3075 }
3076
3077 static __init int vmx_disabled_by_bios(void)
3078 {
3079 u64 msr;
3080
3081 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3082 if (msr & FEATURE_CONTROL_LOCKED) {
3083 /* launched w/ TXT and VMX disabled */
3084 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3085 && tboot_enabled())
3086 return 1;
3087 /* launched w/o TXT and VMX only enabled w/ TXT */
3088 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3089 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3090 && !tboot_enabled()) {
3091 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3092 "activate TXT before enabling KVM\n");
3093 return 1;
3094 }
3095 /* launched w/o TXT and VMX disabled */
3096 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3097 && !tboot_enabled())
3098 return 1;
3099 }
3100
3101 return 0;
3102 }
3103
3104 static void kvm_cpu_vmxon(u64 addr)
3105 {
3106 intel_pt_handle_vmx(1);
3107
3108 asm volatile (ASM_VMX_VMXON_RAX
3109 : : "a"(&addr), "m"(addr)
3110 : "memory", "cc");
3111 }
3112
3113 static int hardware_enable(void)
3114 {
3115 int cpu = raw_smp_processor_id();
3116 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3117 u64 old, test_bits;
3118
3119 if (cr4_read_shadow() & X86_CR4_VMXE)
3120 return -EBUSY;
3121
3122 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3123 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3124 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3125
3126 /*
3127 * Now we can enable the vmclear operation in kdump
3128 * since the loaded_vmcss_on_cpu list on this cpu
3129 * has been initialized.
3130 *
3131 * Though the cpu is not in VMX operation now, there
3132 * is no problem to enable the vmclear operation
3133 * for the loaded_vmcss_on_cpu list is empty!
3134 */
3135 crash_enable_local_vmclear(cpu);
3136
3137 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3138
3139 test_bits = FEATURE_CONTROL_LOCKED;
3140 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3141 if (tboot_enabled())
3142 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3143
3144 if ((old & test_bits) != test_bits) {
3145 /* enable and lock */
3146 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3147 }
3148 cr4_set_bits(X86_CR4_VMXE);
3149
3150 if (vmm_exclusive) {
3151 kvm_cpu_vmxon(phys_addr);
3152 ept_sync_global();
3153 }
3154
3155 native_store_gdt(this_cpu_ptr(&host_gdt));
3156
3157 return 0;
3158 }
3159
3160 static void vmclear_local_loaded_vmcss(void)
3161 {
3162 int cpu = raw_smp_processor_id();
3163 struct loaded_vmcs *v, *n;
3164
3165 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3166 loaded_vmcss_on_cpu_link)
3167 __loaded_vmcs_clear(v);
3168 }
3169
3170
3171 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3172 * tricks.
3173 */
3174 static void kvm_cpu_vmxoff(void)
3175 {
3176 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3177
3178 intel_pt_handle_vmx(0);
3179 }
3180
3181 static void hardware_disable(void)
3182 {
3183 if (vmm_exclusive) {
3184 vmclear_local_loaded_vmcss();
3185 kvm_cpu_vmxoff();
3186 }
3187 cr4_clear_bits(X86_CR4_VMXE);
3188 }
3189
3190 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3191 u32 msr, u32 *result)
3192 {
3193 u32 vmx_msr_low, vmx_msr_high;
3194 u32 ctl = ctl_min | ctl_opt;
3195
3196 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3197
3198 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3199 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
3200
3201 /* Ensure minimum (required) set of control bits are supported. */
3202 if (ctl_min & ~ctl)
3203 return -EIO;
3204
3205 *result = ctl;
3206 return 0;
3207 }
3208
3209 static __init bool allow_1_setting(u32 msr, u32 ctl)
3210 {
3211 u32 vmx_msr_low, vmx_msr_high;
3212
3213 rdmsr(msr, vmx_msr_low, vmx_msr_high);
3214 return vmx_msr_high & ctl;
3215 }
3216
3217 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3218 {
3219 u32 vmx_msr_low, vmx_msr_high;
3220 u32 min, opt, min2, opt2;
3221 u32 _pin_based_exec_control = 0;
3222 u32 _cpu_based_exec_control = 0;
3223 u32 _cpu_based_2nd_exec_control = 0;
3224 u32 _vmexit_control = 0;
3225 u32 _vmentry_control = 0;
3226
3227 min = CPU_BASED_HLT_EXITING |
3228 #ifdef CONFIG_X86_64
3229 CPU_BASED_CR8_LOAD_EXITING |
3230 CPU_BASED_CR8_STORE_EXITING |
3231 #endif
3232 CPU_BASED_CR3_LOAD_EXITING |
3233 CPU_BASED_CR3_STORE_EXITING |
3234 CPU_BASED_USE_IO_BITMAPS |
3235 CPU_BASED_MOV_DR_EXITING |
3236 CPU_BASED_USE_TSC_OFFSETING |
3237 CPU_BASED_MWAIT_EXITING |
3238 CPU_BASED_MONITOR_EXITING |
3239 CPU_BASED_INVLPG_EXITING |
3240 CPU_BASED_RDPMC_EXITING;
3241
3242 opt = CPU_BASED_TPR_SHADOW |
3243 CPU_BASED_USE_MSR_BITMAPS |
3244 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3245 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3246 &_cpu_based_exec_control) < 0)
3247 return -EIO;
3248 #ifdef CONFIG_X86_64
3249 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3250 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3251 ~CPU_BASED_CR8_STORE_EXITING;
3252 #endif
3253 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3254 min2 = 0;
3255 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3256 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3257 SECONDARY_EXEC_WBINVD_EXITING |
3258 SECONDARY_EXEC_ENABLE_VPID |
3259 SECONDARY_EXEC_ENABLE_EPT |
3260 SECONDARY_EXEC_UNRESTRICTED_GUEST |
3261 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3262 SECONDARY_EXEC_RDTSCP |
3263 SECONDARY_EXEC_ENABLE_INVPCID |
3264 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3265 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3266 SECONDARY_EXEC_SHADOW_VMCS |
3267 SECONDARY_EXEC_XSAVES |
3268 SECONDARY_EXEC_ENABLE_PML |
3269 SECONDARY_EXEC_PCOMMIT |
3270 SECONDARY_EXEC_TSC_SCALING;
3271 if (adjust_vmx_controls(min2, opt2,
3272 MSR_IA32_VMX_PROCBASED_CTLS2,
3273 &_cpu_based_2nd_exec_control) < 0)
3274 return -EIO;
3275 }
3276 #ifndef CONFIG_X86_64
3277 if (!(_cpu_based_2nd_exec_control &
3278 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3279 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3280 #endif
3281
3282 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3283 _cpu_based_2nd_exec_control &= ~(
3284 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3285 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3286 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3287
3288 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3289 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3290 enabled */
3291 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3292 CPU_BASED_CR3_STORE_EXITING |
3293 CPU_BASED_INVLPG_EXITING);
3294 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3295 vmx_capability.ept, vmx_capability.vpid);
3296 }
3297
3298 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3299 #ifdef CONFIG_X86_64
3300 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3301 #endif
3302 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3303 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3304 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3305 &_vmexit_control) < 0)
3306 return -EIO;
3307
3308 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3309 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3310 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3311 &_pin_based_exec_control) < 0)
3312 return -EIO;
3313
3314 if (!(_cpu_based_2nd_exec_control &
3315 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3316 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3317 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3318
3319 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3320 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3321 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3322 &_vmentry_control) < 0)
3323 return -EIO;
3324
3325 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3326
3327 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3328 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3329 return -EIO;
3330
3331 #ifdef CONFIG_X86_64
3332 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3333 if (vmx_msr_high & (1u<<16))
3334 return -EIO;
3335 #endif
3336
3337 /* Require Write-Back (WB) memory type for VMCS accesses. */
3338 if (((vmx_msr_high >> 18) & 15) != 6)
3339 return -EIO;
3340
3341 vmcs_conf->size = vmx_msr_high & 0x1fff;
3342 vmcs_conf->order = get_order(vmcs_config.size);
3343 vmcs_conf->revision_id = vmx_msr_low;
3344
3345 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3346 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3347 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3348 vmcs_conf->vmexit_ctrl = _vmexit_control;
3349 vmcs_conf->vmentry_ctrl = _vmentry_control;
3350
3351 cpu_has_load_ia32_efer =
3352 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3353 VM_ENTRY_LOAD_IA32_EFER)
3354 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3355 VM_EXIT_LOAD_IA32_EFER);
3356
3357 cpu_has_load_perf_global_ctrl =
3358 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3359 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3360 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3361 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3362
3363 /*
3364 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3365 * but due to arrata below it can't be used. Workaround is to use
3366 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3367 *
3368 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3369 *
3370 * AAK155 (model 26)
3371 * AAP115 (model 30)
3372 * AAT100 (model 37)
3373 * BC86,AAY89,BD102 (model 44)
3374 * BA97 (model 46)
3375 *
3376 */
3377 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3378 switch (boot_cpu_data.x86_model) {
3379 case 26:
3380 case 30:
3381 case 37:
3382 case 44:
3383 case 46:
3384 cpu_has_load_perf_global_ctrl = false;
3385 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3386 "does not work properly. Using workaround\n");
3387 break;
3388 default:
3389 break;
3390 }
3391 }
3392
3393 if (cpu_has_xsaves)
3394 rdmsrl(MSR_IA32_XSS, host_xss);
3395
3396 return 0;
3397 }
3398
3399 static struct vmcs *alloc_vmcs_cpu(int cpu)
3400 {
3401 int node = cpu_to_node(cpu);
3402 struct page *pages;
3403 struct vmcs *vmcs;
3404
3405 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3406 if (!pages)
3407 return NULL;
3408 vmcs = page_address(pages);
3409 memset(vmcs, 0, vmcs_config.size);
3410 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3411 return vmcs;
3412 }
3413
3414 static struct vmcs *alloc_vmcs(void)
3415 {
3416 return alloc_vmcs_cpu(raw_smp_processor_id());
3417 }
3418
3419 static void free_vmcs(struct vmcs *vmcs)
3420 {
3421 free_pages((unsigned long)vmcs, vmcs_config.order);
3422 }
3423
3424 /*
3425 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3426 */
3427 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3428 {
3429 if (!loaded_vmcs->vmcs)
3430 return;
3431 loaded_vmcs_clear(loaded_vmcs);
3432 free_vmcs(loaded_vmcs->vmcs);
3433 loaded_vmcs->vmcs = NULL;
3434 }
3435
3436 static void free_kvm_area(void)
3437 {
3438 int cpu;
3439
3440 for_each_possible_cpu(cpu) {
3441 free_vmcs(per_cpu(vmxarea, cpu));
3442 per_cpu(vmxarea, cpu) = NULL;
3443 }
3444 }
3445
3446 static void init_vmcs_shadow_fields(void)
3447 {
3448 int i, j;
3449
3450 /* No checks for read only fields yet */
3451
3452 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3453 switch (shadow_read_write_fields[i]) {
3454 case GUEST_BNDCFGS:
3455 if (!kvm_mpx_supported())
3456 continue;
3457 break;
3458 default:
3459 break;
3460 }
3461
3462 if (j < i)
3463 shadow_read_write_fields[j] =
3464 shadow_read_write_fields[i];
3465 j++;
3466 }
3467 max_shadow_read_write_fields = j;
3468
3469 /* shadowed fields guest access without vmexit */
3470 for (i = 0; i < max_shadow_read_write_fields; i++) {
3471 clear_bit(shadow_read_write_fields[i],
3472 vmx_vmwrite_bitmap);
3473 clear_bit(shadow_read_write_fields[i],
3474 vmx_vmread_bitmap);
3475 }
3476 for (i = 0; i < max_shadow_read_only_fields; i++)
3477 clear_bit(shadow_read_only_fields[i],
3478 vmx_vmread_bitmap);
3479 }
3480
3481 static __init int alloc_kvm_area(void)
3482 {
3483 int cpu;
3484
3485 for_each_possible_cpu(cpu) {
3486 struct vmcs *vmcs;
3487
3488 vmcs = alloc_vmcs_cpu(cpu);
3489 if (!vmcs) {
3490 free_kvm_area();
3491 return -ENOMEM;
3492 }
3493
3494 per_cpu(vmxarea, cpu) = vmcs;
3495 }
3496 return 0;
3497 }
3498
3499 static bool emulation_required(struct kvm_vcpu *vcpu)
3500 {
3501 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3502 }
3503
3504 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3505 struct kvm_segment *save)
3506 {
3507 if (!emulate_invalid_guest_state) {
3508 /*
3509 * CS and SS RPL should be equal during guest entry according
3510 * to VMX spec, but in reality it is not always so. Since vcpu
3511 * is in the middle of the transition from real mode to
3512 * protected mode it is safe to assume that RPL 0 is a good
3513 * default value.
3514 */
3515 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3516 save->selector &= ~SEGMENT_RPL_MASK;
3517 save->dpl = save->selector & SEGMENT_RPL_MASK;
3518 save->s = 1;
3519 }
3520 vmx_set_segment(vcpu, save, seg);
3521 }
3522
3523 static void enter_pmode(struct kvm_vcpu *vcpu)
3524 {
3525 unsigned long flags;
3526 struct vcpu_vmx *vmx = to_vmx(vcpu);
3527
3528 /*
3529 * Update real mode segment cache. It may be not up-to-date if sement
3530 * register was written while vcpu was in a guest mode.
3531 */
3532 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3533 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3534 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3535 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3536 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3537 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3538
3539 vmx->rmode.vm86_active = 0;
3540
3541 vmx_segment_cache_clear(vmx);
3542
3543 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3544
3545 flags = vmcs_readl(GUEST_RFLAGS);
3546 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3547 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3548 vmcs_writel(GUEST_RFLAGS, flags);
3549
3550 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3551 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3552
3553 update_exception_bitmap(vcpu);
3554
3555 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3556 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3557 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3558 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3559 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3560 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3561 }
3562
3563 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3564 {
3565 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3566 struct kvm_segment var = *save;
3567
3568 var.dpl = 0x3;
3569 if (seg == VCPU_SREG_CS)
3570 var.type = 0x3;
3571
3572 if (!emulate_invalid_guest_state) {
3573 var.selector = var.base >> 4;
3574 var.base = var.base & 0xffff0;
3575 var.limit = 0xffff;
3576 var.g = 0;
3577 var.db = 0;
3578 var.present = 1;
3579 var.s = 1;
3580 var.l = 0;
3581 var.unusable = 0;
3582 var.type = 0x3;
3583 var.avl = 0;
3584 if (save->base & 0xf)
3585 printk_once(KERN_WARNING "kvm: segment base is not "
3586 "paragraph aligned when entering "
3587 "protected mode (seg=%d)", seg);
3588 }
3589
3590 vmcs_write16(sf->selector, var.selector);
3591 vmcs_write32(sf->base, var.base);
3592 vmcs_write32(sf->limit, var.limit);
3593 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3594 }
3595
3596 static void enter_rmode(struct kvm_vcpu *vcpu)
3597 {
3598 unsigned long flags;
3599 struct vcpu_vmx *vmx = to_vmx(vcpu);
3600
3601 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3602 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3603 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3604 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3605 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3606 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3607 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3608
3609 vmx->rmode.vm86_active = 1;
3610
3611 /*
3612 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3613 * vcpu. Warn the user that an update is overdue.
3614 */
3615 if (!vcpu->kvm->arch.tss_addr)
3616 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3617 "called before entering vcpu\n");
3618
3619 vmx_segment_cache_clear(vmx);
3620
3621 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3622 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3623 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3624
3625 flags = vmcs_readl(GUEST_RFLAGS);
3626 vmx->rmode.save_rflags = flags;
3627
3628 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3629
3630 vmcs_writel(GUEST_RFLAGS, flags);
3631 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3632 update_exception_bitmap(vcpu);
3633
3634 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3635 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3636 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3637 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3638 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3639 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3640
3641 kvm_mmu_reset_context(vcpu);
3642 }
3643
3644 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3645 {
3646 struct vcpu_vmx *vmx = to_vmx(vcpu);
3647 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3648
3649 if (!msr)
3650 return;
3651
3652 /*
3653 * Force kernel_gs_base reloading before EFER changes, as control
3654 * of this msr depends on is_long_mode().
3655 */
3656 vmx_load_host_state(to_vmx(vcpu));
3657 vcpu->arch.efer = efer;
3658 if (efer & EFER_LMA) {
3659 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3660 msr->data = efer;
3661 } else {
3662 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3663
3664 msr->data = efer & ~EFER_LME;
3665 }
3666 setup_msrs(vmx);
3667 }
3668
3669 #ifdef CONFIG_X86_64
3670
3671 static void enter_lmode(struct kvm_vcpu *vcpu)
3672 {
3673 u32 guest_tr_ar;
3674
3675 vmx_segment_cache_clear(to_vmx(vcpu));
3676
3677 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3678 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3679 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3680 __func__);
3681 vmcs_write32(GUEST_TR_AR_BYTES,
3682 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3683 | VMX_AR_TYPE_BUSY_64_TSS);
3684 }
3685 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3686 }
3687
3688 static void exit_lmode(struct kvm_vcpu *vcpu)
3689 {
3690 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3691 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3692 }
3693
3694 #endif
3695
3696 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3697 {
3698 vpid_sync_context(vpid);
3699 if (enable_ept) {
3700 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3701 return;
3702 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3703 }
3704 }
3705
3706 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3707 {
3708 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3709 }
3710
3711 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3712 {
3713 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3714
3715 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3716 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3717 }
3718
3719 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3720 {
3721 if (enable_ept && is_paging(vcpu))
3722 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3723 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3724 }
3725
3726 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3727 {
3728 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3729
3730 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3731 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3732 }
3733
3734 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3735 {
3736 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3737
3738 if (!test_bit(VCPU_EXREG_PDPTR,
3739 (unsigned long *)&vcpu->arch.regs_dirty))
3740 return;
3741
3742 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3743 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3744 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3745 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3746 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3747 }
3748 }
3749
3750 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3751 {
3752 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3753
3754 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3755 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3756 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3757 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3758 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3759 }
3760
3761 __set_bit(VCPU_EXREG_PDPTR,
3762 (unsigned long *)&vcpu->arch.regs_avail);
3763 __set_bit(VCPU_EXREG_PDPTR,
3764 (unsigned long *)&vcpu->arch.regs_dirty);
3765 }
3766
3767 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3768
3769 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3770 unsigned long cr0,
3771 struct kvm_vcpu *vcpu)
3772 {
3773 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3774 vmx_decache_cr3(vcpu);
3775 if (!(cr0 & X86_CR0_PG)) {
3776 /* From paging/starting to nonpaging */
3777 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3778 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3779 (CPU_BASED_CR3_LOAD_EXITING |
3780 CPU_BASED_CR3_STORE_EXITING));
3781 vcpu->arch.cr0 = cr0;
3782 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3783 } else if (!is_paging(vcpu)) {
3784 /* From nonpaging to paging */
3785 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3786 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3787 ~(CPU_BASED_CR3_LOAD_EXITING |
3788 CPU_BASED_CR3_STORE_EXITING));
3789 vcpu->arch.cr0 = cr0;
3790 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3791 }
3792
3793 if (!(cr0 & X86_CR0_WP))
3794 *hw_cr0 &= ~X86_CR0_WP;
3795 }
3796
3797 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3798 {
3799 struct vcpu_vmx *vmx = to_vmx(vcpu);
3800 unsigned long hw_cr0;
3801
3802 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3803 if (enable_unrestricted_guest)
3804 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3805 else {
3806 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3807
3808 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3809 enter_pmode(vcpu);
3810
3811 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3812 enter_rmode(vcpu);
3813 }
3814
3815 #ifdef CONFIG_X86_64
3816 if (vcpu->arch.efer & EFER_LME) {
3817 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3818 enter_lmode(vcpu);
3819 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3820 exit_lmode(vcpu);
3821 }
3822 #endif
3823
3824 if (enable_ept)
3825 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3826
3827 if (!vcpu->fpu_active)
3828 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3829
3830 vmcs_writel(CR0_READ_SHADOW, cr0);
3831 vmcs_writel(GUEST_CR0, hw_cr0);
3832 vcpu->arch.cr0 = cr0;
3833
3834 /* depends on vcpu->arch.cr0 to be set to a new value */
3835 vmx->emulation_required = emulation_required(vcpu);
3836 }
3837
3838 static u64 construct_eptp(unsigned long root_hpa)
3839 {
3840 u64 eptp;
3841
3842 /* TODO write the value reading from MSR */
3843 eptp = VMX_EPT_DEFAULT_MT |
3844 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3845 if (enable_ept_ad_bits)
3846 eptp |= VMX_EPT_AD_ENABLE_BIT;
3847 eptp |= (root_hpa & PAGE_MASK);
3848
3849 return eptp;
3850 }
3851
3852 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3853 {
3854 unsigned long guest_cr3;
3855 u64 eptp;
3856
3857 guest_cr3 = cr3;
3858 if (enable_ept) {
3859 eptp = construct_eptp(cr3);
3860 vmcs_write64(EPT_POINTER, eptp);
3861 if (is_paging(vcpu) || is_guest_mode(vcpu))
3862 guest_cr3 = kvm_read_cr3(vcpu);
3863 else
3864 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3865 ept_load_pdptrs(vcpu);
3866 }
3867
3868 vmx_flush_tlb(vcpu);
3869 vmcs_writel(GUEST_CR3, guest_cr3);
3870 }
3871
3872 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3873 {
3874 /*
3875 * Pass through host's Machine Check Enable value to hw_cr4, which
3876 * is in force while we are in guest mode. Do not let guests control
3877 * this bit, even if host CR4.MCE == 0.
3878 */
3879 unsigned long hw_cr4 =
3880 (cr4_read_shadow() & X86_CR4_MCE) |
3881 (cr4 & ~X86_CR4_MCE) |
3882 (to_vmx(vcpu)->rmode.vm86_active ?
3883 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3884
3885 if (cr4 & X86_CR4_VMXE) {
3886 /*
3887 * To use VMXON (and later other VMX instructions), a guest
3888 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3889 * So basically the check on whether to allow nested VMX
3890 * is here.
3891 */
3892 if (!nested_vmx_allowed(vcpu))
3893 return 1;
3894 }
3895 if (to_vmx(vcpu)->nested.vmxon &&
3896 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3897 return 1;
3898
3899 vcpu->arch.cr4 = cr4;
3900 if (enable_ept) {
3901 if (!is_paging(vcpu)) {
3902 hw_cr4 &= ~X86_CR4_PAE;
3903 hw_cr4 |= X86_CR4_PSE;
3904 } else if (!(cr4 & X86_CR4_PAE)) {
3905 hw_cr4 &= ~X86_CR4_PAE;
3906 }
3907 }
3908
3909 if (!enable_unrestricted_guest && !is_paging(vcpu))
3910 /*
3911 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3912 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3913 * to be manually disabled when guest switches to non-paging
3914 * mode.
3915 *
3916 * If !enable_unrestricted_guest, the CPU is always running
3917 * with CR0.PG=1 and CR4 needs to be modified.
3918 * If enable_unrestricted_guest, the CPU automatically
3919 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3920 */
3921 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3922
3923 vmcs_writel(CR4_READ_SHADOW, cr4);
3924 vmcs_writel(GUEST_CR4, hw_cr4);
3925 return 0;
3926 }
3927
3928 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3929 struct kvm_segment *var, int seg)
3930 {
3931 struct vcpu_vmx *vmx = to_vmx(vcpu);
3932 u32 ar;
3933
3934 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3935 *var = vmx->rmode.segs[seg];
3936 if (seg == VCPU_SREG_TR
3937 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3938 return;
3939 var->base = vmx_read_guest_seg_base(vmx, seg);
3940 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3941 return;
3942 }
3943 var->base = vmx_read_guest_seg_base(vmx, seg);
3944 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3945 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3946 ar = vmx_read_guest_seg_ar(vmx, seg);
3947 var->unusable = (ar >> 16) & 1;
3948 var->type = ar & 15;
3949 var->s = (ar >> 4) & 1;
3950 var->dpl = (ar >> 5) & 3;
3951 /*
3952 * Some userspaces do not preserve unusable property. Since usable
3953 * segment has to be present according to VMX spec we can use present
3954 * property to amend userspace bug by making unusable segment always
3955 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3956 * segment as unusable.
3957 */
3958 var->present = !var->unusable;
3959 var->avl = (ar >> 12) & 1;
3960 var->l = (ar >> 13) & 1;
3961 var->db = (ar >> 14) & 1;
3962 var->g = (ar >> 15) & 1;
3963 }
3964
3965 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3966 {
3967 struct kvm_segment s;
3968
3969 if (to_vmx(vcpu)->rmode.vm86_active) {
3970 vmx_get_segment(vcpu, &s, seg);
3971 return s.base;
3972 }
3973 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3974 }
3975
3976 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3977 {
3978 struct vcpu_vmx *vmx = to_vmx(vcpu);
3979
3980 if (unlikely(vmx->rmode.vm86_active))
3981 return 0;
3982 else {
3983 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3984 return VMX_AR_DPL(ar);
3985 }
3986 }
3987
3988 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3989 {
3990 u32 ar;
3991
3992 if (var->unusable || !var->present)
3993 ar = 1 << 16;
3994 else {
3995 ar = var->type & 15;
3996 ar |= (var->s & 1) << 4;
3997 ar |= (var->dpl & 3) << 5;
3998 ar |= (var->present & 1) << 7;
3999 ar |= (var->avl & 1) << 12;
4000 ar |= (var->l & 1) << 13;
4001 ar |= (var->db & 1) << 14;
4002 ar |= (var->g & 1) << 15;
4003 }
4004
4005 return ar;
4006 }
4007
4008 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4009 struct kvm_segment *var, int seg)
4010 {
4011 struct vcpu_vmx *vmx = to_vmx(vcpu);
4012 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4013
4014 vmx_segment_cache_clear(vmx);
4015
4016 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4017 vmx->rmode.segs[seg] = *var;
4018 if (seg == VCPU_SREG_TR)
4019 vmcs_write16(sf->selector, var->selector);
4020 else if (var->s)
4021 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4022 goto out;
4023 }
4024
4025 vmcs_writel(sf->base, var->base);
4026 vmcs_write32(sf->limit, var->limit);
4027 vmcs_write16(sf->selector, var->selector);
4028
4029 /*
4030 * Fix the "Accessed" bit in AR field of segment registers for older
4031 * qemu binaries.
4032 * IA32 arch specifies that at the time of processor reset the
4033 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4034 * is setting it to 0 in the userland code. This causes invalid guest
4035 * state vmexit when "unrestricted guest" mode is turned on.
4036 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4037 * tree. Newer qemu binaries with that qemu fix would not need this
4038 * kvm hack.
4039 */
4040 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4041 var->type |= 0x1; /* Accessed */
4042
4043 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4044
4045 out:
4046 vmx->emulation_required = emulation_required(vcpu);
4047 }
4048
4049 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4050 {
4051 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4052
4053 *db = (ar >> 14) & 1;
4054 *l = (ar >> 13) & 1;
4055 }
4056
4057 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4058 {
4059 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4060 dt->address = vmcs_readl(GUEST_IDTR_BASE);
4061 }
4062
4063 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4064 {
4065 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4066 vmcs_writel(GUEST_IDTR_BASE, dt->address);
4067 }
4068
4069 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4070 {
4071 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4072 dt->address = vmcs_readl(GUEST_GDTR_BASE);
4073 }
4074
4075 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4076 {
4077 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4078 vmcs_writel(GUEST_GDTR_BASE, dt->address);
4079 }
4080
4081 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4082 {
4083 struct kvm_segment var;
4084 u32 ar;
4085
4086 vmx_get_segment(vcpu, &var, seg);
4087 var.dpl = 0x3;
4088 if (seg == VCPU_SREG_CS)
4089 var.type = 0x3;
4090 ar = vmx_segment_access_rights(&var);
4091
4092 if (var.base != (var.selector << 4))
4093 return false;
4094 if (var.limit != 0xffff)
4095 return false;
4096 if (ar != 0xf3)
4097 return false;
4098
4099 return true;
4100 }
4101
4102 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4103 {
4104 struct kvm_segment cs;
4105 unsigned int cs_rpl;
4106
4107 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4108 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4109
4110 if (cs.unusable)
4111 return false;
4112 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4113 return false;
4114 if (!cs.s)
4115 return false;
4116 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4117 if (cs.dpl > cs_rpl)
4118 return false;
4119 } else {
4120 if (cs.dpl != cs_rpl)
4121 return false;
4122 }
4123 if (!cs.present)
4124 return false;
4125
4126 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4127 return true;
4128 }
4129
4130 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4131 {
4132 struct kvm_segment ss;
4133 unsigned int ss_rpl;
4134
4135 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4136 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4137
4138 if (ss.unusable)
4139 return true;
4140 if (ss.type != 3 && ss.type != 7)
4141 return false;
4142 if (!ss.s)
4143 return false;
4144 if (ss.dpl != ss_rpl) /* DPL != RPL */
4145 return false;
4146 if (!ss.present)
4147 return false;
4148
4149 return true;
4150 }
4151
4152 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4153 {
4154 struct kvm_segment var;
4155 unsigned int rpl;
4156
4157 vmx_get_segment(vcpu, &var, seg);
4158 rpl = var.selector & SEGMENT_RPL_MASK;
4159
4160 if (var.unusable)
4161 return true;
4162 if (!var.s)
4163 return false;
4164 if (!var.present)
4165 return false;
4166 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4167 if (var.dpl < rpl) /* DPL < RPL */
4168 return false;
4169 }
4170
4171 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4172 * rights flags
4173 */
4174 return true;
4175 }
4176
4177 static bool tr_valid(struct kvm_vcpu *vcpu)
4178 {
4179 struct kvm_segment tr;
4180
4181 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4182
4183 if (tr.unusable)
4184 return false;
4185 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4186 return false;
4187 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4188 return false;
4189 if (!tr.present)
4190 return false;
4191
4192 return true;
4193 }
4194
4195 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4196 {
4197 struct kvm_segment ldtr;
4198
4199 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4200
4201 if (ldtr.unusable)
4202 return true;
4203 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
4204 return false;
4205 if (ldtr.type != 2)
4206 return false;
4207 if (!ldtr.present)
4208 return false;
4209
4210 return true;
4211 }
4212
4213 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4214 {
4215 struct kvm_segment cs, ss;
4216
4217 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4218 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4219
4220 return ((cs.selector & SEGMENT_RPL_MASK) ==
4221 (ss.selector & SEGMENT_RPL_MASK));
4222 }
4223
4224 /*
4225 * Check if guest state is valid. Returns true if valid, false if
4226 * not.
4227 * We assume that registers are always usable
4228 */
4229 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4230 {
4231 if (enable_unrestricted_guest)
4232 return true;
4233
4234 /* real mode guest state checks */
4235 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4236 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4237 return false;
4238 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4239 return false;
4240 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4241 return false;
4242 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4243 return false;
4244 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4245 return false;
4246 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4247 return false;
4248 } else {
4249 /* protected mode guest state checks */
4250 if (!cs_ss_rpl_check(vcpu))
4251 return false;
4252 if (!code_segment_valid(vcpu))
4253 return false;
4254 if (!stack_segment_valid(vcpu))
4255 return false;
4256 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4257 return false;
4258 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4259 return false;
4260 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4261 return false;
4262 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4263 return false;
4264 if (!tr_valid(vcpu))
4265 return false;
4266 if (!ldtr_valid(vcpu))
4267 return false;
4268 }
4269 /* TODO:
4270 * - Add checks on RIP
4271 * - Add checks on RFLAGS
4272 */
4273
4274 return true;
4275 }
4276
4277 static int init_rmode_tss(struct kvm *kvm)
4278 {
4279 gfn_t fn;
4280 u16 data = 0;
4281 int idx, r;
4282
4283 idx = srcu_read_lock(&kvm->srcu);
4284 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4285 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4286 if (r < 0)
4287 goto out;
4288 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4289 r = kvm_write_guest_page(kvm, fn++, &data,
4290 TSS_IOPB_BASE_OFFSET, sizeof(u16));
4291 if (r < 0)
4292 goto out;
4293 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4294 if (r < 0)
4295 goto out;
4296 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4297 if (r < 0)
4298 goto out;
4299 data = ~0;
4300 r = kvm_write_guest_page(kvm, fn, &data,
4301 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4302 sizeof(u8));
4303 out:
4304 srcu_read_unlock(&kvm->srcu, idx);
4305 return r;
4306 }
4307
4308 static int init_rmode_identity_map(struct kvm *kvm)
4309 {
4310 int i, idx, r = 0;
4311 kvm_pfn_t identity_map_pfn;
4312 u32 tmp;
4313
4314 if (!enable_ept)
4315 return 0;
4316
4317 /* Protect kvm->arch.ept_identity_pagetable_done. */
4318 mutex_lock(&kvm->slots_lock);
4319
4320 if (likely(kvm->arch.ept_identity_pagetable_done))
4321 goto out2;
4322
4323 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4324
4325 r = alloc_identity_pagetable(kvm);
4326 if (r < 0)
4327 goto out2;
4328
4329 idx = srcu_read_lock(&kvm->srcu);
4330 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4331 if (r < 0)
4332 goto out;
4333 /* Set up identity-mapping pagetable for EPT in real mode */
4334 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4335 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4336 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4337 r = kvm_write_guest_page(kvm, identity_map_pfn,
4338 &tmp, i * sizeof(tmp), sizeof(tmp));
4339 if (r < 0)
4340 goto out;
4341 }
4342 kvm->arch.ept_identity_pagetable_done = true;
4343
4344 out:
4345 srcu_read_unlock(&kvm->srcu, idx);
4346
4347 out2:
4348 mutex_unlock(&kvm->slots_lock);
4349 return r;
4350 }
4351
4352 static void seg_setup(int seg)
4353 {
4354 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4355 unsigned int ar;
4356
4357 vmcs_write16(sf->selector, 0);
4358 vmcs_writel(sf->base, 0);
4359 vmcs_write32(sf->limit, 0xffff);
4360 ar = 0x93;
4361 if (seg == VCPU_SREG_CS)
4362 ar |= 0x08; /* code segment */
4363
4364 vmcs_write32(sf->ar_bytes, ar);
4365 }
4366
4367 static int alloc_apic_access_page(struct kvm *kvm)
4368 {
4369 struct page *page;
4370 int r = 0;
4371
4372 mutex_lock(&kvm->slots_lock);
4373 if (kvm->arch.apic_access_page_done)
4374 goto out;
4375 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4376 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4377 if (r)
4378 goto out;
4379
4380 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4381 if (is_error_page(page)) {
4382 r = -EFAULT;
4383 goto out;
4384 }
4385
4386 /*
4387 * Do not pin the page in memory, so that memory hot-unplug
4388 * is able to migrate it.
4389 */
4390 put_page(page);
4391 kvm->arch.apic_access_page_done = true;
4392 out:
4393 mutex_unlock(&kvm->slots_lock);
4394 return r;
4395 }
4396
4397 static int alloc_identity_pagetable(struct kvm *kvm)
4398 {
4399 /* Called with kvm->slots_lock held. */
4400
4401 int r = 0;
4402
4403 BUG_ON(kvm->arch.ept_identity_pagetable_done);
4404
4405 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4406 kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4407
4408 return r;
4409 }
4410
4411 static int allocate_vpid(void)
4412 {
4413 int vpid;
4414
4415 if (!enable_vpid)
4416 return 0;
4417 spin_lock(&vmx_vpid_lock);
4418 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4419 if (vpid < VMX_NR_VPIDS)
4420 __set_bit(vpid, vmx_vpid_bitmap);
4421 else
4422 vpid = 0;
4423 spin_unlock(&vmx_vpid_lock);
4424 return vpid;
4425 }
4426
4427 static void free_vpid(int vpid)
4428 {
4429 if (!enable_vpid || vpid == 0)
4430 return;
4431 spin_lock(&vmx_vpid_lock);
4432 __clear_bit(vpid, vmx_vpid_bitmap);
4433 spin_unlock(&vmx_vpid_lock);
4434 }
4435
4436 #define MSR_TYPE_R 1
4437 #define MSR_TYPE_W 2
4438 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4439 u32 msr, int type)
4440 {
4441 int f = sizeof(unsigned long);
4442
4443 if (!cpu_has_vmx_msr_bitmap())
4444 return;
4445
4446 /*
4447 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4448 * have the write-low and read-high bitmap offsets the wrong way round.
4449 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4450 */
4451 if (msr <= 0x1fff) {
4452 if (type & MSR_TYPE_R)
4453 /* read-low */
4454 __clear_bit(msr, msr_bitmap + 0x000 / f);
4455
4456 if (type & MSR_TYPE_W)
4457 /* write-low */
4458 __clear_bit(msr, msr_bitmap + 0x800 / f);
4459
4460 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4461 msr &= 0x1fff;
4462 if (type & MSR_TYPE_R)
4463 /* read-high */
4464 __clear_bit(msr, msr_bitmap + 0x400 / f);
4465
4466 if (type & MSR_TYPE_W)
4467 /* write-high */
4468 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4469
4470 }
4471 }
4472
4473 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4474 u32 msr, int type)
4475 {
4476 int f = sizeof(unsigned long);
4477
4478 if (!cpu_has_vmx_msr_bitmap())
4479 return;
4480
4481 /*
4482 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4483 * have the write-low and read-high bitmap offsets the wrong way round.
4484 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4485 */
4486 if (msr <= 0x1fff) {
4487 if (type & MSR_TYPE_R)
4488 /* read-low */
4489 __set_bit(msr, msr_bitmap + 0x000 / f);
4490
4491 if (type & MSR_TYPE_W)
4492 /* write-low */
4493 __set_bit(msr, msr_bitmap + 0x800 / f);
4494
4495 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4496 msr &= 0x1fff;
4497 if (type & MSR_TYPE_R)
4498 /* read-high */
4499 __set_bit(msr, msr_bitmap + 0x400 / f);
4500
4501 if (type & MSR_TYPE_W)
4502 /* write-high */
4503 __set_bit(msr, msr_bitmap + 0xc00 / f);
4504
4505 }
4506 }
4507
4508 /*
4509 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4510 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4511 */
4512 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4513 unsigned long *msr_bitmap_nested,
4514 u32 msr, int type)
4515 {
4516 int f = sizeof(unsigned long);
4517
4518 if (!cpu_has_vmx_msr_bitmap()) {
4519 WARN_ON(1);
4520 return;
4521 }
4522
4523 /*
4524 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4525 * have the write-low and read-high bitmap offsets the wrong way round.
4526 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4527 */
4528 if (msr <= 0x1fff) {
4529 if (type & MSR_TYPE_R &&
4530 !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4531 /* read-low */
4532 __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4533
4534 if (type & MSR_TYPE_W &&
4535 !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4536 /* write-low */
4537 __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4538
4539 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4540 msr &= 0x1fff;
4541 if (type & MSR_TYPE_R &&
4542 !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4543 /* read-high */
4544 __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4545
4546 if (type & MSR_TYPE_W &&
4547 !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4548 /* write-high */
4549 __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4550
4551 }
4552 }
4553
4554 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4555 {
4556 if (!longmode_only)
4557 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4558 msr, MSR_TYPE_R | MSR_TYPE_W);
4559 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4560 msr, MSR_TYPE_R | MSR_TYPE_W);
4561 }
4562
4563 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4564 {
4565 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4566 msr, MSR_TYPE_R);
4567 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4568 msr, MSR_TYPE_R);
4569 }
4570
4571 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4572 {
4573 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4574 msr, MSR_TYPE_R);
4575 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4576 msr, MSR_TYPE_R);
4577 }
4578
4579 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4580 {
4581 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4582 msr, MSR_TYPE_W);
4583 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4584 msr, MSR_TYPE_W);
4585 }
4586
4587 static bool vmx_get_enable_apicv(void)
4588 {
4589 return enable_apicv;
4590 }
4591
4592 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4593 {
4594 struct vcpu_vmx *vmx = to_vmx(vcpu);
4595 int max_irr;
4596 void *vapic_page;
4597 u16 status;
4598
4599 if (vmx->nested.pi_desc &&
4600 vmx->nested.pi_pending) {
4601 vmx->nested.pi_pending = false;
4602 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4603 return 0;
4604
4605 max_irr = find_last_bit(
4606 (unsigned long *)vmx->nested.pi_desc->pir, 256);
4607
4608 if (max_irr == 256)
4609 return 0;
4610
4611 vapic_page = kmap(vmx->nested.virtual_apic_page);
4612 if (!vapic_page) {
4613 WARN_ON(1);
4614 return -ENOMEM;
4615 }
4616 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4617 kunmap(vmx->nested.virtual_apic_page);
4618
4619 status = vmcs_read16(GUEST_INTR_STATUS);
4620 if ((u8)max_irr > ((u8)status & 0xff)) {
4621 status &= ~0xff;
4622 status |= (u8)max_irr;
4623 vmcs_write16(GUEST_INTR_STATUS, status);
4624 }
4625 }
4626 return 0;
4627 }
4628
4629 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4630 {
4631 #ifdef CONFIG_SMP
4632 if (vcpu->mode == IN_GUEST_MODE) {
4633 struct vcpu_vmx *vmx = to_vmx(vcpu);
4634
4635 /*
4636 * Currently, we don't support urgent interrupt,
4637 * all interrupts are recognized as non-urgent
4638 * interrupt, so we cannot post interrupts when
4639 * 'SN' is set.
4640 *
4641 * If the vcpu is in guest mode, it means it is
4642 * running instead of being scheduled out and
4643 * waiting in the run queue, and that's the only
4644 * case when 'SN' is set currently, warning if
4645 * 'SN' is set.
4646 */
4647 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4648
4649 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4650 POSTED_INTR_VECTOR);
4651 return true;
4652 }
4653 #endif
4654 return false;
4655 }
4656
4657 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4658 int vector)
4659 {
4660 struct vcpu_vmx *vmx = to_vmx(vcpu);
4661
4662 if (is_guest_mode(vcpu) &&
4663 vector == vmx->nested.posted_intr_nv) {
4664 /* the PIR and ON have been set by L1. */
4665 kvm_vcpu_trigger_posted_interrupt(vcpu);
4666 /*
4667 * If a posted intr is not recognized by hardware,
4668 * we will accomplish it in the next vmentry.
4669 */
4670 vmx->nested.pi_pending = true;
4671 kvm_make_request(KVM_REQ_EVENT, vcpu);
4672 return 0;
4673 }
4674 return -1;
4675 }
4676 /*
4677 * Send interrupt to vcpu via posted interrupt way.
4678 * 1. If target vcpu is running(non-root mode), send posted interrupt
4679 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4680 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4681 * interrupt from PIR in next vmentry.
4682 */
4683 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4684 {
4685 struct vcpu_vmx *vmx = to_vmx(vcpu);
4686 int r;
4687
4688 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4689 if (!r)
4690 return;
4691
4692 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4693 return;
4694
4695 r = pi_test_and_set_on(&vmx->pi_desc);
4696 kvm_make_request(KVM_REQ_EVENT, vcpu);
4697 if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4698 kvm_vcpu_kick(vcpu);
4699 }
4700
4701 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4702 {
4703 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704
4705 if (!pi_test_and_clear_on(&vmx->pi_desc))
4706 return;
4707
4708 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4709 }
4710
4711 /*
4712 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4713 * will not change in the lifetime of the guest.
4714 * Note that host-state that does change is set elsewhere. E.g., host-state
4715 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4716 */
4717 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4718 {
4719 u32 low32, high32;
4720 unsigned long tmpl;
4721 struct desc_ptr dt;
4722 unsigned long cr4;
4723
4724 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
4725 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4726
4727 /* Save the most likely value for this task's CR4 in the VMCS. */
4728 cr4 = cr4_read_shadow();
4729 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
4730 vmx->host_state.vmcs_host_cr4 = cr4;
4731
4732 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
4733 #ifdef CONFIG_X86_64
4734 /*
4735 * Load null selectors, so we can avoid reloading them in
4736 * __vmx_load_host_state(), in case userspace uses the null selectors
4737 * too (the expected case).
4738 */
4739 vmcs_write16(HOST_DS_SELECTOR, 0);
4740 vmcs_write16(HOST_ES_SELECTOR, 0);
4741 #else
4742 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4743 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4744 #endif
4745 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4746 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4747
4748 native_store_idt(&dt);
4749 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
4750 vmx->host_idt_base = dt.address;
4751
4752 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4753
4754 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4755 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4756 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4757 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4758
4759 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4760 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4761 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4762 }
4763 }
4764
4765 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4766 {
4767 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4768 if (enable_ept)
4769 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4770 if (is_guest_mode(&vmx->vcpu))
4771 vmx->vcpu.arch.cr4_guest_owned_bits &=
4772 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4773 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4774 }
4775
4776 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4777 {
4778 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4779
4780 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4781 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4782 return pin_based_exec_ctrl;
4783 }
4784
4785 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4786 {
4787 struct vcpu_vmx *vmx = to_vmx(vcpu);
4788
4789 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4790 }
4791
4792 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4793 {
4794 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4795
4796 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4797 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4798
4799 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4800 exec_control &= ~CPU_BASED_TPR_SHADOW;
4801 #ifdef CONFIG_X86_64
4802 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4803 CPU_BASED_CR8_LOAD_EXITING;
4804 #endif
4805 }
4806 if (!enable_ept)
4807 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4808 CPU_BASED_CR3_LOAD_EXITING |
4809 CPU_BASED_INVLPG_EXITING;
4810 return exec_control;
4811 }
4812
4813 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4814 {
4815 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4816 if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4817 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4818 if (vmx->vpid == 0)
4819 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4820 if (!enable_ept) {
4821 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4822 enable_unrestricted_guest = 0;
4823 /* Enable INVPCID for non-ept guests may cause performance regression. */
4824 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4825 }
4826 if (!enable_unrestricted_guest)
4827 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4828 if (!ple_gap)
4829 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4830 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4831 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4832 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4833 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4834 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4835 (handle_vmptrld).
4836 We can NOT enable shadow_vmcs here because we don't have yet
4837 a current VMCS12
4838 */
4839 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4840
4841 if (!enable_pml)
4842 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4843
4844 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4845 exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4846
4847 return exec_control;
4848 }
4849
4850 static void ept_set_mmio_spte_mask(void)
4851 {
4852 /*
4853 * EPT Misconfigurations can be generated if the value of bits 2:0
4854 * of an EPT paging-structure entry is 110b (write/execute).
4855 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4856 * spte.
4857 */
4858 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4859 }
4860
4861 #define VMX_XSS_EXIT_BITMAP 0
4862 /*
4863 * Sets up the vmcs for emulated real mode.
4864 */
4865 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4866 {
4867 #ifdef CONFIG_X86_64
4868 unsigned long a;
4869 #endif
4870 int i;
4871
4872 /* I/O */
4873 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4874 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4875
4876 if (enable_shadow_vmcs) {
4877 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4878 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4879 }
4880 if (cpu_has_vmx_msr_bitmap())
4881 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4882
4883 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4884
4885 /* Control */
4886 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4887
4888 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4889
4890 if (cpu_has_secondary_exec_ctrls())
4891 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4892 vmx_secondary_exec_control(vmx));
4893
4894 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4895 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4896 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4897 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4898 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4899
4900 vmcs_write16(GUEST_INTR_STATUS, 0);
4901
4902 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4903 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4904 }
4905
4906 if (ple_gap) {
4907 vmcs_write32(PLE_GAP, ple_gap);
4908 vmx->ple_window = ple_window;
4909 vmx->ple_window_dirty = true;
4910 }
4911
4912 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4913 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4914 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4915
4916 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4917 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
4918 vmx_set_constant_host_state(vmx);
4919 #ifdef CONFIG_X86_64
4920 rdmsrl(MSR_FS_BASE, a);
4921 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4922 rdmsrl(MSR_GS_BASE, a);
4923 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4924 #else
4925 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4926 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4927 #endif
4928
4929 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4930 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4931 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4932 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4933 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4934
4935 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4936 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4937
4938 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4939 u32 index = vmx_msr_index[i];
4940 u32 data_low, data_high;
4941 int j = vmx->nmsrs;
4942
4943 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4944 continue;
4945 if (wrmsr_safe(index, data_low, data_high) < 0)
4946 continue;
4947 vmx->guest_msrs[j].index = i;
4948 vmx->guest_msrs[j].data = 0;
4949 vmx->guest_msrs[j].mask = -1ull;
4950 ++vmx->nmsrs;
4951 }
4952
4953
4954 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4955
4956 /* 22.2.1, 20.8.1 */
4957 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4958
4959 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4960 set_cr4_guest_host_mask(vmx);
4961
4962 if (vmx_xsaves_supported())
4963 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4964
4965 return 0;
4966 }
4967
4968 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4969 {
4970 struct vcpu_vmx *vmx = to_vmx(vcpu);
4971 struct msr_data apic_base_msr;
4972 u64 cr0;
4973
4974 vmx->rmode.vm86_active = 0;
4975
4976 vmx->soft_vnmi_blocked = 0;
4977
4978 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4979 kvm_set_cr8(vcpu, 0);
4980
4981 if (!init_event) {
4982 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4983 MSR_IA32_APICBASE_ENABLE;
4984 if (kvm_vcpu_is_reset_bsp(vcpu))
4985 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4986 apic_base_msr.host_initiated = true;
4987 kvm_set_apic_base(vcpu, &apic_base_msr);
4988 }
4989
4990 vmx_segment_cache_clear(vmx);
4991
4992 seg_setup(VCPU_SREG_CS);
4993 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4994 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4995
4996 seg_setup(VCPU_SREG_DS);
4997 seg_setup(VCPU_SREG_ES);
4998 seg_setup(VCPU_SREG_FS);
4999 seg_setup(VCPU_SREG_GS);
5000 seg_setup(VCPU_SREG_SS);
5001
5002 vmcs_write16(GUEST_TR_SELECTOR, 0);
5003 vmcs_writel(GUEST_TR_BASE, 0);
5004 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5005 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5006
5007 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5008 vmcs_writel(GUEST_LDTR_BASE, 0);
5009 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5010 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5011
5012 if (!init_event) {
5013 vmcs_write32(GUEST_SYSENTER_CS, 0);
5014 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5015 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5016 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5017 }
5018
5019 vmcs_writel(GUEST_RFLAGS, 0x02);
5020 kvm_rip_write(vcpu, 0xfff0);
5021
5022 vmcs_writel(GUEST_GDTR_BASE, 0);
5023 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5024
5025 vmcs_writel(GUEST_IDTR_BASE, 0);
5026 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5027
5028 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5029 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5030 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5031
5032 setup_msrs(vmx);
5033
5034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
5035
5036 if (cpu_has_vmx_tpr_shadow() && !init_event) {
5037 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5038 if (cpu_need_tpr_shadow(vcpu))
5039 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5040 __pa(vcpu->arch.apic->regs));
5041 vmcs_write32(TPR_THRESHOLD, 0);
5042 }
5043
5044 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5045
5046 if (kvm_vcpu_apicv_active(vcpu))
5047 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5048
5049 if (vmx->vpid != 0)
5050 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5051
5052 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5053 vmx_set_cr0(vcpu, cr0); /* enter rmode */
5054 vmx->vcpu.arch.cr0 = cr0;
5055 vmx_set_cr4(vcpu, 0);
5056 vmx_set_efer(vcpu, 0);
5057 vmx_fpu_activate(vcpu);
5058 update_exception_bitmap(vcpu);
5059
5060 vpid_sync_context(vmx->vpid);
5061 }
5062
5063 /*
5064 * In nested virtualization, check if L1 asked to exit on external interrupts.
5065 * For most existing hypervisors, this will always return true.
5066 */
5067 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5068 {
5069 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5070 PIN_BASED_EXT_INTR_MASK;
5071 }
5072
5073 /*
5074 * In nested virtualization, check if L1 has set
5075 * VM_EXIT_ACK_INTR_ON_EXIT
5076 */
5077 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5078 {
5079 return get_vmcs12(vcpu)->vm_exit_controls &
5080 VM_EXIT_ACK_INTR_ON_EXIT;
5081 }
5082
5083 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5084 {
5085 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5086 PIN_BASED_NMI_EXITING;
5087 }
5088
5089 static void enable_irq_window(struct kvm_vcpu *vcpu)
5090 {
5091 u32 cpu_based_vm_exec_control;
5092
5093 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5094 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5095 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5096 }
5097
5098 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5099 {
5100 u32 cpu_based_vm_exec_control;
5101
5102 if (!cpu_has_virtual_nmis() ||
5103 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5104 enable_irq_window(vcpu);
5105 return;
5106 }
5107
5108 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5109 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5110 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5111 }
5112
5113 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5114 {
5115 struct vcpu_vmx *vmx = to_vmx(vcpu);
5116 uint32_t intr;
5117 int irq = vcpu->arch.interrupt.nr;
5118
5119 trace_kvm_inj_virq(irq);
5120
5121 ++vcpu->stat.irq_injections;
5122 if (vmx->rmode.vm86_active) {
5123 int inc_eip = 0;
5124 if (vcpu->arch.interrupt.soft)
5125 inc_eip = vcpu->arch.event_exit_inst_len;
5126 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5127 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5128 return;
5129 }
5130 intr = irq | INTR_INFO_VALID_MASK;
5131 if (vcpu->arch.interrupt.soft) {
5132 intr |= INTR_TYPE_SOFT_INTR;
5133 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5134 vmx->vcpu.arch.event_exit_inst_len);
5135 } else
5136 intr |= INTR_TYPE_EXT_INTR;
5137 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5138 }
5139
5140 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5141 {
5142 struct vcpu_vmx *vmx = to_vmx(vcpu);
5143
5144 if (is_guest_mode(vcpu))
5145 return;
5146
5147 if (!cpu_has_virtual_nmis()) {
5148 /*
5149 * Tracking the NMI-blocked state in software is built upon
5150 * finding the next open IRQ window. This, in turn, depends on
5151 * well-behaving guests: They have to keep IRQs disabled at
5152 * least as long as the NMI handler runs. Otherwise we may
5153 * cause NMI nesting, maybe breaking the guest. But as this is
5154 * highly unlikely, we can live with the residual risk.
5155 */
5156 vmx->soft_vnmi_blocked = 1;
5157 vmx->vnmi_blocked_time = 0;
5158 }
5159
5160 ++vcpu->stat.nmi_injections;
5161 vmx->nmi_known_unmasked = false;
5162 if (vmx->rmode.vm86_active) {
5163 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5164 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5165 return;
5166 }
5167 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5168 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5169 }
5170
5171 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5172 {
5173 if (!cpu_has_virtual_nmis())
5174 return to_vmx(vcpu)->soft_vnmi_blocked;
5175 if (to_vmx(vcpu)->nmi_known_unmasked)
5176 return false;
5177 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5178 }
5179
5180 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5181 {
5182 struct vcpu_vmx *vmx = to_vmx(vcpu);
5183
5184 if (!cpu_has_virtual_nmis()) {
5185 if (vmx->soft_vnmi_blocked != masked) {
5186 vmx->soft_vnmi_blocked = masked;
5187 vmx->vnmi_blocked_time = 0;
5188 }
5189 } else {
5190 vmx->nmi_known_unmasked = !masked;
5191 if (masked)
5192 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5193 GUEST_INTR_STATE_NMI);
5194 else
5195 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5196 GUEST_INTR_STATE_NMI);
5197 }
5198 }
5199
5200 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5201 {
5202 if (to_vmx(vcpu)->nested.nested_run_pending)
5203 return 0;
5204
5205 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5206 return 0;
5207
5208 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5209 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5210 | GUEST_INTR_STATE_NMI));
5211 }
5212
5213 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5214 {
5215 return (!to_vmx(vcpu)->nested.nested_run_pending &&
5216 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5217 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5218 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5219 }
5220
5221 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5222 {
5223 int ret;
5224
5225 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5226 PAGE_SIZE * 3);
5227 if (ret)
5228 return ret;
5229 kvm->arch.tss_addr = addr;
5230 return init_rmode_tss(kvm);
5231 }
5232
5233 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5234 {
5235 switch (vec) {
5236 case BP_VECTOR:
5237 /*
5238 * Update instruction length as we may reinject the exception
5239 * from user space while in guest debugging mode.
5240 */
5241 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5242 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5243 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5244 return false;
5245 /* fall through */
5246 case DB_VECTOR:
5247 if (vcpu->guest_debug &
5248 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5249 return false;
5250 /* fall through */
5251 case DE_VECTOR:
5252 case OF_VECTOR:
5253 case BR_VECTOR:
5254 case UD_VECTOR:
5255 case DF_VECTOR:
5256 case SS_VECTOR:
5257 case GP_VECTOR:
5258 case MF_VECTOR:
5259 return true;
5260 break;
5261 }
5262 return false;
5263 }
5264
5265 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5266 int vec, u32 err_code)
5267 {
5268 /*
5269 * Instruction with address size override prefix opcode 0x67
5270 * Cause the #SS fault with 0 error code in VM86 mode.
5271 */
5272 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5273 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5274 if (vcpu->arch.halt_request) {
5275 vcpu->arch.halt_request = 0;
5276 return kvm_vcpu_halt(vcpu);
5277 }
5278 return 1;
5279 }
5280 return 0;
5281 }
5282
5283 /*
5284 * Forward all other exceptions that are valid in real mode.
5285 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5286 * the required debugging infrastructure rework.
5287 */
5288 kvm_queue_exception(vcpu, vec);
5289 return 1;
5290 }
5291
5292 /*
5293 * Trigger machine check on the host. We assume all the MSRs are already set up
5294 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5295 * We pass a fake environment to the machine check handler because we want
5296 * the guest to be always treated like user space, no matter what context
5297 * it used internally.
5298 */
5299 static void kvm_machine_check(void)
5300 {
5301 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5302 struct pt_regs regs = {
5303 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5304 .flags = X86_EFLAGS_IF,
5305 };
5306
5307 do_machine_check(&regs, 0);
5308 #endif
5309 }
5310
5311 static int handle_machine_check(struct kvm_vcpu *vcpu)
5312 {
5313 /* already handled by vcpu_run */
5314 return 1;
5315 }
5316
5317 static int handle_exception(struct kvm_vcpu *vcpu)
5318 {
5319 struct vcpu_vmx *vmx = to_vmx(vcpu);
5320 struct kvm_run *kvm_run = vcpu->run;
5321 u32 intr_info, ex_no, error_code;
5322 unsigned long cr2, rip, dr6;
5323 u32 vect_info;
5324 enum emulation_result er;
5325
5326 vect_info = vmx->idt_vectoring_info;
5327 intr_info = vmx->exit_intr_info;
5328
5329 if (is_machine_check(intr_info))
5330 return handle_machine_check(vcpu);
5331
5332 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5333 return 1; /* already handled by vmx_vcpu_run() */
5334
5335 if (is_no_device(intr_info)) {
5336 vmx_fpu_activate(vcpu);
5337 return 1;
5338 }
5339
5340 if (is_invalid_opcode(intr_info)) {
5341 if (is_guest_mode(vcpu)) {
5342 kvm_queue_exception(vcpu, UD_VECTOR);
5343 return 1;
5344 }
5345 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5346 if (er != EMULATE_DONE)
5347 kvm_queue_exception(vcpu, UD_VECTOR);
5348 return 1;
5349 }
5350
5351 error_code = 0;
5352 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5353 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5354
5355 /*
5356 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5357 * MMIO, it is better to report an internal error.
5358 * See the comments in vmx_handle_exit.
5359 */
5360 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5361 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5362 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5363 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5364 vcpu->run->internal.ndata = 3;
5365 vcpu->run->internal.data[0] = vect_info;
5366 vcpu->run->internal.data[1] = intr_info;
5367 vcpu->run->internal.data[2] = error_code;
5368 return 0;
5369 }
5370
5371 if (is_page_fault(intr_info)) {
5372 /* EPT won't cause page fault directly */
5373 BUG_ON(enable_ept);
5374 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5375 trace_kvm_page_fault(cr2, error_code);
5376
5377 if (kvm_event_needs_reinjection(vcpu))
5378 kvm_mmu_unprotect_page_virt(vcpu, cr2);
5379 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5380 }
5381
5382 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5383
5384 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5385 return handle_rmode_exception(vcpu, ex_no, error_code);
5386
5387 switch (ex_no) {
5388 case AC_VECTOR:
5389 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5390 return 1;
5391 case DB_VECTOR:
5392 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5393 if (!(vcpu->guest_debug &
5394 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5395 vcpu->arch.dr6 &= ~15;
5396 vcpu->arch.dr6 |= dr6 | DR6_RTM;
5397 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5398 skip_emulated_instruction(vcpu);
5399
5400 kvm_queue_exception(vcpu, DB_VECTOR);
5401 return 1;
5402 }
5403 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5404 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5405 /* fall through */
5406 case BP_VECTOR:
5407 /*
5408 * Update instruction length as we may reinject #BP from
5409 * user space while in guest debugging mode. Reading it for
5410 * #DB as well causes no harm, it is not used in that case.
5411 */
5412 vmx->vcpu.arch.event_exit_inst_len =
5413 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5414 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5415 rip = kvm_rip_read(vcpu);
5416 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5417 kvm_run->debug.arch.exception = ex_no;
5418 break;
5419 default:
5420 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5421 kvm_run->ex.exception = ex_no;
5422 kvm_run->ex.error_code = error_code;
5423 break;
5424 }
5425 return 0;
5426 }
5427
5428 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5429 {
5430 ++vcpu->stat.irq_exits;
5431 return 1;
5432 }
5433
5434 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5435 {
5436 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5437 return 0;
5438 }
5439
5440 static int handle_io(struct kvm_vcpu *vcpu)
5441 {
5442 unsigned long exit_qualification;
5443 int size, in, string;
5444 unsigned port;
5445
5446 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5447 string = (exit_qualification & 16) != 0;
5448 in = (exit_qualification & 8) != 0;
5449
5450 ++vcpu->stat.io_exits;
5451
5452 if (string || in)
5453 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5454
5455 port = exit_qualification >> 16;
5456 size = (exit_qualification & 7) + 1;
5457 skip_emulated_instruction(vcpu);
5458
5459 return kvm_fast_pio_out(vcpu, size, port);
5460 }
5461
5462 static void
5463 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5464 {
5465 /*
5466 * Patch in the VMCALL instruction:
5467 */
5468 hypercall[0] = 0x0f;
5469 hypercall[1] = 0x01;
5470 hypercall[2] = 0xc1;
5471 }
5472
5473 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5474 {
5475 unsigned long always_on = VMXON_CR0_ALWAYSON;
5476 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5477
5478 if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5479 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5480 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5481 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5482 return (val & always_on) == always_on;
5483 }
5484
5485 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5486 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5487 {
5488 if (is_guest_mode(vcpu)) {
5489 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5490 unsigned long orig_val = val;
5491
5492 /*
5493 * We get here when L2 changed cr0 in a way that did not change
5494 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5495 * but did change L0 shadowed bits. So we first calculate the
5496 * effective cr0 value that L1 would like to write into the
5497 * hardware. It consists of the L2-owned bits from the new
5498 * value combined with the L1-owned bits from L1's guest_cr0.
5499 */
5500 val = (val & ~vmcs12->cr0_guest_host_mask) |
5501 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5502
5503 if (!nested_cr0_valid(vcpu, val))
5504 return 1;
5505
5506 if (kvm_set_cr0(vcpu, val))
5507 return 1;
5508 vmcs_writel(CR0_READ_SHADOW, orig_val);
5509 return 0;
5510 } else {
5511 if (to_vmx(vcpu)->nested.vmxon &&
5512 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5513 return 1;
5514 return kvm_set_cr0(vcpu, val);
5515 }
5516 }
5517
5518 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5519 {
5520 if (is_guest_mode(vcpu)) {
5521 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5522 unsigned long orig_val = val;
5523
5524 /* analogously to handle_set_cr0 */
5525 val = (val & ~vmcs12->cr4_guest_host_mask) |
5526 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5527 if (kvm_set_cr4(vcpu, val))
5528 return 1;
5529 vmcs_writel(CR4_READ_SHADOW, orig_val);
5530 return 0;
5531 } else
5532 return kvm_set_cr4(vcpu, val);
5533 }
5534
5535 /* called to set cr0 as appropriate for clts instruction exit. */
5536 static void handle_clts(struct kvm_vcpu *vcpu)
5537 {
5538 if (is_guest_mode(vcpu)) {
5539 /*
5540 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5541 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5542 * just pretend it's off (also in arch.cr0 for fpu_activate).
5543 */
5544 vmcs_writel(CR0_READ_SHADOW,
5545 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5546 vcpu->arch.cr0 &= ~X86_CR0_TS;
5547 } else
5548 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5549 }
5550
5551 static int handle_cr(struct kvm_vcpu *vcpu)
5552 {
5553 unsigned long exit_qualification, val;
5554 int cr;
5555 int reg;
5556 int err;
5557
5558 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5559 cr = exit_qualification & 15;
5560 reg = (exit_qualification >> 8) & 15;
5561 switch ((exit_qualification >> 4) & 3) {
5562 case 0: /* mov to cr */
5563 val = kvm_register_readl(vcpu, reg);
5564 trace_kvm_cr_write(cr, val);
5565 switch (cr) {
5566 case 0:
5567 err = handle_set_cr0(vcpu, val);
5568 kvm_complete_insn_gp(vcpu, err);
5569 return 1;
5570 case 3:
5571 err = kvm_set_cr3(vcpu, val);
5572 kvm_complete_insn_gp(vcpu, err);
5573 return 1;
5574 case 4:
5575 err = handle_set_cr4(vcpu, val);
5576 kvm_complete_insn_gp(vcpu, err);
5577 return 1;
5578 case 8: {
5579 u8 cr8_prev = kvm_get_cr8(vcpu);
5580 u8 cr8 = (u8)val;
5581 err = kvm_set_cr8(vcpu, cr8);
5582 kvm_complete_insn_gp(vcpu, err);
5583 if (lapic_in_kernel(vcpu))
5584 return 1;
5585 if (cr8_prev <= cr8)
5586 return 1;
5587 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5588 return 0;
5589 }
5590 }
5591 break;
5592 case 2: /* clts */
5593 handle_clts(vcpu);
5594 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5595 skip_emulated_instruction(vcpu);
5596 vmx_fpu_activate(vcpu);
5597 return 1;
5598 case 1: /*mov from cr*/
5599 switch (cr) {
5600 case 3:
5601 val = kvm_read_cr3(vcpu);
5602 kvm_register_write(vcpu, reg, val);
5603 trace_kvm_cr_read(cr, val);
5604 skip_emulated_instruction(vcpu);
5605 return 1;
5606 case 8:
5607 val = kvm_get_cr8(vcpu);
5608 kvm_register_write(vcpu, reg, val);
5609 trace_kvm_cr_read(cr, val);
5610 skip_emulated_instruction(vcpu);
5611 return 1;
5612 }
5613 break;
5614 case 3: /* lmsw */
5615 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5616 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5617 kvm_lmsw(vcpu, val);
5618
5619 skip_emulated_instruction(vcpu);
5620 return 1;
5621 default:
5622 break;
5623 }
5624 vcpu->run->exit_reason = 0;
5625 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5626 (int)(exit_qualification >> 4) & 3, cr);
5627 return 0;
5628 }
5629
5630 static int handle_dr(struct kvm_vcpu *vcpu)
5631 {
5632 unsigned long exit_qualification;
5633 int dr, dr7, reg;
5634
5635 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5636 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5637
5638 /* First, if DR does not exist, trigger UD */
5639 if (!kvm_require_dr(vcpu, dr))
5640 return 1;
5641
5642 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5643 if (!kvm_require_cpl(vcpu, 0))
5644 return 1;
5645 dr7 = vmcs_readl(GUEST_DR7);
5646 if (dr7 & DR7_GD) {
5647 /*
5648 * As the vm-exit takes precedence over the debug trap, we
5649 * need to emulate the latter, either for the host or the
5650 * guest debugging itself.
5651 */
5652 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5653 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5654 vcpu->run->debug.arch.dr7 = dr7;
5655 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5656 vcpu->run->debug.arch.exception = DB_VECTOR;
5657 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5658 return 0;
5659 } else {
5660 vcpu->arch.dr6 &= ~15;
5661 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5662 kvm_queue_exception(vcpu, DB_VECTOR);
5663 return 1;
5664 }
5665 }
5666
5667 if (vcpu->guest_debug == 0) {
5668 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5669 CPU_BASED_MOV_DR_EXITING);
5670
5671 /*
5672 * No more DR vmexits; force a reload of the debug registers
5673 * and reenter on this instruction. The next vmexit will
5674 * retrieve the full state of the debug registers.
5675 */
5676 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5677 return 1;
5678 }
5679
5680 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5681 if (exit_qualification & TYPE_MOV_FROM_DR) {
5682 unsigned long val;
5683
5684 if (kvm_get_dr(vcpu, dr, &val))
5685 return 1;
5686 kvm_register_write(vcpu, reg, val);
5687 } else
5688 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5689 return 1;
5690
5691 skip_emulated_instruction(vcpu);
5692 return 1;
5693 }
5694
5695 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5696 {
5697 return vcpu->arch.dr6;
5698 }
5699
5700 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5701 {
5702 }
5703
5704 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5705 {
5706 get_debugreg(vcpu->arch.db[0], 0);
5707 get_debugreg(vcpu->arch.db[1], 1);
5708 get_debugreg(vcpu->arch.db[2], 2);
5709 get_debugreg(vcpu->arch.db[3], 3);
5710 get_debugreg(vcpu->arch.dr6, 6);
5711 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5712
5713 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5714 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5715 }
5716
5717 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5718 {
5719 vmcs_writel(GUEST_DR7, val);
5720 }
5721
5722 static int handle_cpuid(struct kvm_vcpu *vcpu)
5723 {
5724 kvm_emulate_cpuid(vcpu);
5725 return 1;
5726 }
5727
5728 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5729 {
5730 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5731 struct msr_data msr_info;
5732
5733 msr_info.index = ecx;
5734 msr_info.host_initiated = false;
5735 if (vmx_get_msr(vcpu, &msr_info)) {
5736 trace_kvm_msr_read_ex(ecx);
5737 kvm_inject_gp(vcpu, 0);
5738 return 1;
5739 }
5740
5741 trace_kvm_msr_read(ecx, msr_info.data);
5742
5743 /* FIXME: handling of bits 32:63 of rax, rdx */
5744 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5745 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5746 skip_emulated_instruction(vcpu);
5747 return 1;
5748 }
5749
5750 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5751 {
5752 struct msr_data msr;
5753 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5754 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5755 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5756
5757 msr.data = data;
5758 msr.index = ecx;
5759 msr.host_initiated = false;
5760 if (kvm_set_msr(vcpu, &msr) != 0) {
5761 trace_kvm_msr_write_ex(ecx, data);
5762 kvm_inject_gp(vcpu, 0);
5763 return 1;
5764 }
5765
5766 trace_kvm_msr_write(ecx, data);
5767 skip_emulated_instruction(vcpu);
5768 return 1;
5769 }
5770
5771 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5772 {
5773 kvm_make_request(KVM_REQ_EVENT, vcpu);
5774 return 1;
5775 }
5776
5777 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5778 {
5779 u32 cpu_based_vm_exec_control;
5780
5781 /* clear pending irq */
5782 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5783 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5784 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5785
5786 kvm_make_request(KVM_REQ_EVENT, vcpu);
5787
5788 ++vcpu->stat.irq_window_exits;
5789 return 1;
5790 }
5791
5792 static int handle_halt(struct kvm_vcpu *vcpu)
5793 {
5794 return kvm_emulate_halt(vcpu);
5795 }
5796
5797 static int handle_vmcall(struct kvm_vcpu *vcpu)
5798 {
5799 return kvm_emulate_hypercall(vcpu);
5800 }
5801
5802 static int handle_invd(struct kvm_vcpu *vcpu)
5803 {
5804 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5805 }
5806
5807 static int handle_invlpg(struct kvm_vcpu *vcpu)
5808 {
5809 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5810
5811 kvm_mmu_invlpg(vcpu, exit_qualification);
5812 skip_emulated_instruction(vcpu);
5813 return 1;
5814 }
5815
5816 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5817 {
5818 int err;
5819
5820 err = kvm_rdpmc(vcpu);
5821 kvm_complete_insn_gp(vcpu, err);
5822
5823 return 1;
5824 }
5825
5826 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5827 {
5828 kvm_emulate_wbinvd(vcpu);
5829 return 1;
5830 }
5831
5832 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5833 {
5834 u64 new_bv = kvm_read_edx_eax(vcpu);
5835 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5836
5837 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5838 skip_emulated_instruction(vcpu);
5839 return 1;
5840 }
5841
5842 static int handle_xsaves(struct kvm_vcpu *vcpu)
5843 {
5844 skip_emulated_instruction(vcpu);
5845 WARN(1, "this should never happen\n");
5846 return 1;
5847 }
5848
5849 static int handle_xrstors(struct kvm_vcpu *vcpu)
5850 {
5851 skip_emulated_instruction(vcpu);
5852 WARN(1, "this should never happen\n");
5853 return 1;
5854 }
5855
5856 static int handle_apic_access(struct kvm_vcpu *vcpu)
5857 {
5858 if (likely(fasteoi)) {
5859 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5860 int access_type, offset;
5861
5862 access_type = exit_qualification & APIC_ACCESS_TYPE;
5863 offset = exit_qualification & APIC_ACCESS_OFFSET;
5864 /*
5865 * Sane guest uses MOV to write EOI, with written value
5866 * not cared. So make a short-circuit here by avoiding
5867 * heavy instruction emulation.
5868 */
5869 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5870 (offset == APIC_EOI)) {
5871 kvm_lapic_set_eoi(vcpu);
5872 skip_emulated_instruction(vcpu);
5873 return 1;
5874 }
5875 }
5876 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5877 }
5878
5879 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5880 {
5881 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5882 int vector = exit_qualification & 0xff;
5883
5884 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5885 kvm_apic_set_eoi_accelerated(vcpu, vector);
5886 return 1;
5887 }
5888
5889 static int handle_apic_write(struct kvm_vcpu *vcpu)
5890 {
5891 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5892 u32 offset = exit_qualification & 0xfff;
5893
5894 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5895 kvm_apic_write_nodecode(vcpu, offset);
5896 return 1;
5897 }
5898
5899 static int handle_task_switch(struct kvm_vcpu *vcpu)
5900 {
5901 struct vcpu_vmx *vmx = to_vmx(vcpu);
5902 unsigned long exit_qualification;
5903 bool has_error_code = false;
5904 u32 error_code = 0;
5905 u16 tss_selector;
5906 int reason, type, idt_v, idt_index;
5907
5908 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5909 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5910 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5911
5912 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5913
5914 reason = (u32)exit_qualification >> 30;
5915 if (reason == TASK_SWITCH_GATE && idt_v) {
5916 switch (type) {
5917 case INTR_TYPE_NMI_INTR:
5918 vcpu->arch.nmi_injected = false;
5919 vmx_set_nmi_mask(vcpu, true);
5920 break;
5921 case INTR_TYPE_EXT_INTR:
5922 case INTR_TYPE_SOFT_INTR:
5923 kvm_clear_interrupt_queue(vcpu);
5924 break;
5925 case INTR_TYPE_HARD_EXCEPTION:
5926 if (vmx->idt_vectoring_info &
5927 VECTORING_INFO_DELIVER_CODE_MASK) {
5928 has_error_code = true;
5929 error_code =
5930 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5931 }
5932 /* fall through */
5933 case INTR_TYPE_SOFT_EXCEPTION:
5934 kvm_clear_exception_queue(vcpu);
5935 break;
5936 default:
5937 break;
5938 }
5939 }
5940 tss_selector = exit_qualification;
5941
5942 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5943 type != INTR_TYPE_EXT_INTR &&
5944 type != INTR_TYPE_NMI_INTR))
5945 skip_emulated_instruction(vcpu);
5946
5947 if (kvm_task_switch(vcpu, tss_selector,
5948 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5949 has_error_code, error_code) == EMULATE_FAIL) {
5950 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5951 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5952 vcpu->run->internal.ndata = 0;
5953 return 0;
5954 }
5955
5956 /*
5957 * TODO: What about debug traps on tss switch?
5958 * Are we supposed to inject them and update dr6?
5959 */
5960
5961 return 1;
5962 }
5963
5964 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5965 {
5966 unsigned long exit_qualification;
5967 gpa_t gpa;
5968 u32 error_code;
5969 int gla_validity;
5970
5971 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5972
5973 gla_validity = (exit_qualification >> 7) & 0x3;
5974 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5975 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5976 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5977 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5978 vmcs_readl(GUEST_LINEAR_ADDRESS));
5979 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5980 (long unsigned int)exit_qualification);
5981 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5982 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5983 return 0;
5984 }
5985
5986 /*
5987 * EPT violation happened while executing iret from NMI,
5988 * "blocked by NMI" bit has to be set before next VM entry.
5989 * There are errata that may cause this bit to not be set:
5990 * AAK134, BY25.
5991 */
5992 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5993 cpu_has_virtual_nmis() &&
5994 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5995 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5996
5997 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5998 trace_kvm_page_fault(gpa, exit_qualification);
5999
6000 /* It is a write fault? */
6001 error_code = exit_qualification & PFERR_WRITE_MASK;
6002 /* It is a fetch fault? */
6003 error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6004 /* ept page table is present? */
6005 error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6006
6007 vcpu->arch.exit_qualification = exit_qualification;
6008
6009 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6010 }
6011
6012 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6013 {
6014 int ret;
6015 gpa_t gpa;
6016
6017 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6018 if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6019 skip_emulated_instruction(vcpu);
6020 trace_kvm_fast_mmio(gpa);
6021 return 1;
6022 }
6023
6024 ret = handle_mmio_page_fault(vcpu, gpa, true);
6025 if (likely(ret == RET_MMIO_PF_EMULATE))
6026 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6027 EMULATE_DONE;
6028
6029 if (unlikely(ret == RET_MMIO_PF_INVALID))
6030 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6031
6032 if (unlikely(ret == RET_MMIO_PF_RETRY))
6033 return 1;
6034
6035 /* It is the real ept misconfig */
6036 WARN_ON(1);
6037
6038 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6039 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6040
6041 return 0;
6042 }
6043
6044 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6045 {
6046 u32 cpu_based_vm_exec_control;
6047
6048 /* clear pending NMI */
6049 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6050 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6051 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6052 ++vcpu->stat.nmi_window_exits;
6053 kvm_make_request(KVM_REQ_EVENT, vcpu);
6054
6055 return 1;
6056 }
6057
6058 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6059 {
6060 struct vcpu_vmx *vmx = to_vmx(vcpu);
6061 enum emulation_result err = EMULATE_DONE;
6062 int ret = 1;
6063 u32 cpu_exec_ctrl;
6064 bool intr_window_requested;
6065 unsigned count = 130;
6066
6067 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6068 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6069
6070 while (vmx->emulation_required && count-- != 0) {
6071 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6072 return handle_interrupt_window(&vmx->vcpu);
6073
6074 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6075 return 1;
6076
6077 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6078
6079 if (err == EMULATE_USER_EXIT) {
6080 ++vcpu->stat.mmio_exits;
6081 ret = 0;
6082 goto out;
6083 }
6084
6085 if (err != EMULATE_DONE) {
6086 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6087 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6088 vcpu->run->internal.ndata = 0;
6089 return 0;
6090 }
6091
6092 if (vcpu->arch.halt_request) {
6093 vcpu->arch.halt_request = 0;
6094 ret = kvm_vcpu_halt(vcpu);
6095 goto out;
6096 }
6097
6098 if (signal_pending(current))
6099 goto out;
6100 if (need_resched())
6101 schedule();
6102 }
6103
6104 out:
6105 return ret;
6106 }
6107
6108 static int __grow_ple_window(int val)
6109 {
6110 if (ple_window_grow < 1)
6111 return ple_window;
6112
6113 val = min(val, ple_window_actual_max);
6114
6115 if (ple_window_grow < ple_window)
6116 val *= ple_window_grow;
6117 else
6118 val += ple_window_grow;
6119
6120 return val;
6121 }
6122
6123 static int __shrink_ple_window(int val, int modifier, int minimum)
6124 {
6125 if (modifier < 1)
6126 return ple_window;
6127
6128 if (modifier < ple_window)
6129 val /= modifier;
6130 else
6131 val -= modifier;
6132
6133 return max(val, minimum);
6134 }
6135
6136 static void grow_ple_window(struct kvm_vcpu *vcpu)
6137 {
6138 struct vcpu_vmx *vmx = to_vmx(vcpu);
6139 int old = vmx->ple_window;
6140
6141 vmx->ple_window = __grow_ple_window(old);
6142
6143 if (vmx->ple_window != old)
6144 vmx->ple_window_dirty = true;
6145
6146 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6147 }
6148
6149 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6150 {
6151 struct vcpu_vmx *vmx = to_vmx(vcpu);
6152 int old = vmx->ple_window;
6153
6154 vmx->ple_window = __shrink_ple_window(old,
6155 ple_window_shrink, ple_window);
6156
6157 if (vmx->ple_window != old)
6158 vmx->ple_window_dirty = true;
6159
6160 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6161 }
6162
6163 /*
6164 * ple_window_actual_max is computed to be one grow_ple_window() below
6165 * ple_window_max. (See __grow_ple_window for the reason.)
6166 * This prevents overflows, because ple_window_max is int.
6167 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6168 * this process.
6169 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6170 */
6171 static void update_ple_window_actual_max(void)
6172 {
6173 ple_window_actual_max =
6174 __shrink_ple_window(max(ple_window_max, ple_window),
6175 ple_window_grow, INT_MIN);
6176 }
6177
6178 /*
6179 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6180 */
6181 static void wakeup_handler(void)
6182 {
6183 struct kvm_vcpu *vcpu;
6184 int cpu = smp_processor_id();
6185
6186 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6187 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6188 blocked_vcpu_list) {
6189 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6190
6191 if (pi_test_on(pi_desc) == 1)
6192 kvm_vcpu_kick(vcpu);
6193 }
6194 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6195 }
6196
6197 static __init int hardware_setup(void)
6198 {
6199 int r = -ENOMEM, i, msr;
6200
6201 rdmsrl_safe(MSR_EFER, &host_efer);
6202
6203 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6204 kvm_define_shared_msr(i, vmx_msr_index[i]);
6205
6206 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6207 if (!vmx_io_bitmap_a)
6208 return r;
6209
6210 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6211 if (!vmx_io_bitmap_b)
6212 goto out;
6213
6214 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6215 if (!vmx_msr_bitmap_legacy)
6216 goto out1;
6217
6218 vmx_msr_bitmap_legacy_x2apic =
6219 (unsigned long *)__get_free_page(GFP_KERNEL);
6220 if (!vmx_msr_bitmap_legacy_x2apic)
6221 goto out2;
6222
6223 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6224 if (!vmx_msr_bitmap_longmode)
6225 goto out3;
6226
6227 vmx_msr_bitmap_longmode_x2apic =
6228 (unsigned long *)__get_free_page(GFP_KERNEL);
6229 if (!vmx_msr_bitmap_longmode_x2apic)
6230 goto out4;
6231
6232 if (nested) {
6233 vmx_msr_bitmap_nested =
6234 (unsigned long *)__get_free_page(GFP_KERNEL);
6235 if (!vmx_msr_bitmap_nested)
6236 goto out5;
6237 }
6238
6239 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6240 if (!vmx_vmread_bitmap)
6241 goto out6;
6242
6243 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6244 if (!vmx_vmwrite_bitmap)
6245 goto out7;
6246
6247 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6248 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6249
6250 /*
6251 * Allow direct access to the PC debug port (it is often used for I/O
6252 * delays, but the vmexits simply slow things down).
6253 */
6254 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6255 clear_bit(0x80, vmx_io_bitmap_a);
6256
6257 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6258
6259 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6260 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6261 if (nested)
6262 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6263
6264 if (setup_vmcs_config(&vmcs_config) < 0) {
6265 r = -EIO;
6266 goto out8;
6267 }
6268
6269 if (boot_cpu_has(X86_FEATURE_NX))
6270 kvm_enable_efer_bits(EFER_NX);
6271
6272 if (!cpu_has_vmx_vpid())
6273 enable_vpid = 0;
6274 if (!cpu_has_vmx_shadow_vmcs())
6275 enable_shadow_vmcs = 0;
6276 if (enable_shadow_vmcs)
6277 init_vmcs_shadow_fields();
6278
6279 if (!cpu_has_vmx_ept() ||
6280 !cpu_has_vmx_ept_4levels()) {
6281 enable_ept = 0;
6282 enable_unrestricted_guest = 0;
6283 enable_ept_ad_bits = 0;
6284 }
6285
6286 if (!cpu_has_vmx_ept_ad_bits())
6287 enable_ept_ad_bits = 0;
6288
6289 if (!cpu_has_vmx_unrestricted_guest())
6290 enable_unrestricted_guest = 0;
6291
6292 if (!cpu_has_vmx_flexpriority())
6293 flexpriority_enabled = 0;
6294
6295 /*
6296 * set_apic_access_page_addr() is used to reload apic access
6297 * page upon invalidation. No need to do anything if not
6298 * using the APIC_ACCESS_ADDR VMCS field.
6299 */
6300 if (!flexpriority_enabled)
6301 kvm_x86_ops->set_apic_access_page_addr = NULL;
6302
6303 if (!cpu_has_vmx_tpr_shadow())
6304 kvm_x86_ops->update_cr8_intercept = NULL;
6305
6306 if (enable_ept && !cpu_has_vmx_ept_2m_page())
6307 kvm_disable_largepages();
6308
6309 if (!cpu_has_vmx_ple())
6310 ple_gap = 0;
6311
6312 if (!cpu_has_vmx_apicv())
6313 enable_apicv = 0;
6314
6315 if (cpu_has_vmx_tsc_scaling()) {
6316 kvm_has_tsc_control = true;
6317 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6318 kvm_tsc_scaling_ratio_frac_bits = 48;
6319 }
6320
6321 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6322 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6323 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6324 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6325 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6326 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6327 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6328
6329 memcpy(vmx_msr_bitmap_legacy_x2apic,
6330 vmx_msr_bitmap_legacy, PAGE_SIZE);
6331 memcpy(vmx_msr_bitmap_longmode_x2apic,
6332 vmx_msr_bitmap_longmode, PAGE_SIZE);
6333
6334 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6335
6336 if (enable_apicv) {
6337 for (msr = 0x800; msr <= 0x8ff; msr++)
6338 vmx_disable_intercept_msr_read_x2apic(msr);
6339
6340 /* According SDM, in x2apic mode, the whole id reg is used.
6341 * But in KVM, it only use the highest eight bits. Need to
6342 * intercept it */
6343 vmx_enable_intercept_msr_read_x2apic(0x802);
6344 /* TMCCT */
6345 vmx_enable_intercept_msr_read_x2apic(0x839);
6346 /* TPR */
6347 vmx_disable_intercept_msr_write_x2apic(0x808);
6348 /* EOI */
6349 vmx_disable_intercept_msr_write_x2apic(0x80b);
6350 /* SELF-IPI */
6351 vmx_disable_intercept_msr_write_x2apic(0x83f);
6352 }
6353
6354 if (enable_ept) {
6355 kvm_mmu_set_mask_ptes(0ull,
6356 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6357 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6358 0ull, VMX_EPT_EXECUTABLE_MASK);
6359 ept_set_mmio_spte_mask();
6360 kvm_enable_tdp();
6361 } else
6362 kvm_disable_tdp();
6363
6364 update_ple_window_actual_max();
6365
6366 /*
6367 * Only enable PML when hardware supports PML feature, and both EPT
6368 * and EPT A/D bit features are enabled -- PML depends on them to work.
6369 */
6370 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6371 enable_pml = 0;
6372
6373 if (!enable_pml) {
6374 kvm_x86_ops->slot_enable_log_dirty = NULL;
6375 kvm_x86_ops->slot_disable_log_dirty = NULL;
6376 kvm_x86_ops->flush_log_dirty = NULL;
6377 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6378 }
6379
6380 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6381
6382 return alloc_kvm_area();
6383
6384 out8:
6385 free_page((unsigned long)vmx_vmwrite_bitmap);
6386 out7:
6387 free_page((unsigned long)vmx_vmread_bitmap);
6388 out6:
6389 if (nested)
6390 free_page((unsigned long)vmx_msr_bitmap_nested);
6391 out5:
6392 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6393 out4:
6394 free_page((unsigned long)vmx_msr_bitmap_longmode);
6395 out3:
6396 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6397 out2:
6398 free_page((unsigned long)vmx_msr_bitmap_legacy);
6399 out1:
6400 free_page((unsigned long)vmx_io_bitmap_b);
6401 out:
6402 free_page((unsigned long)vmx_io_bitmap_a);
6403
6404 return r;
6405 }
6406
6407 static __exit void hardware_unsetup(void)
6408 {
6409 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6410 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6411 free_page((unsigned long)vmx_msr_bitmap_legacy);
6412 free_page((unsigned long)vmx_msr_bitmap_longmode);
6413 free_page((unsigned long)vmx_io_bitmap_b);
6414 free_page((unsigned long)vmx_io_bitmap_a);
6415 free_page((unsigned long)vmx_vmwrite_bitmap);
6416 free_page((unsigned long)vmx_vmread_bitmap);
6417 if (nested)
6418 free_page((unsigned long)vmx_msr_bitmap_nested);
6419
6420 free_kvm_area();
6421 }
6422
6423 /*
6424 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6425 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6426 */
6427 static int handle_pause(struct kvm_vcpu *vcpu)
6428 {
6429 if (ple_gap)
6430 grow_ple_window(vcpu);
6431
6432 skip_emulated_instruction(vcpu);
6433 kvm_vcpu_on_spin(vcpu);
6434
6435 return 1;
6436 }
6437
6438 static int handle_nop(struct kvm_vcpu *vcpu)
6439 {
6440 skip_emulated_instruction(vcpu);
6441 return 1;
6442 }
6443
6444 static int handle_mwait(struct kvm_vcpu *vcpu)
6445 {
6446 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6447 return handle_nop(vcpu);
6448 }
6449
6450 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6451 {
6452 return 1;
6453 }
6454
6455 static int handle_monitor(struct kvm_vcpu *vcpu)
6456 {
6457 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6458 return handle_nop(vcpu);
6459 }
6460
6461 /*
6462 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6463 * We could reuse a single VMCS for all the L2 guests, but we also want the
6464 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6465 * allows keeping them loaded on the processor, and in the future will allow
6466 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6467 * every entry if they never change.
6468 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6469 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6470 *
6471 * The following functions allocate and free a vmcs02 in this pool.
6472 */
6473
6474 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6475 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6476 {
6477 struct vmcs02_list *item;
6478 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6479 if (item->vmptr == vmx->nested.current_vmptr) {
6480 list_move(&item->list, &vmx->nested.vmcs02_pool);
6481 return &item->vmcs02;
6482 }
6483
6484 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6485 /* Recycle the least recently used VMCS. */
6486 item = list_last_entry(&vmx->nested.vmcs02_pool,
6487 struct vmcs02_list, list);
6488 item->vmptr = vmx->nested.current_vmptr;
6489 list_move(&item->list, &vmx->nested.vmcs02_pool);
6490 return &item->vmcs02;
6491 }
6492
6493 /* Create a new VMCS */
6494 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6495 if (!item)
6496 return NULL;
6497 item->vmcs02.vmcs = alloc_vmcs();
6498 if (!item->vmcs02.vmcs) {
6499 kfree(item);
6500 return NULL;
6501 }
6502 loaded_vmcs_init(&item->vmcs02);
6503 item->vmptr = vmx->nested.current_vmptr;
6504 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6505 vmx->nested.vmcs02_num++;
6506 return &item->vmcs02;
6507 }
6508
6509 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6510 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6511 {
6512 struct vmcs02_list *item;
6513 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6514 if (item->vmptr == vmptr) {
6515 free_loaded_vmcs(&item->vmcs02);
6516 list_del(&item->list);
6517 kfree(item);
6518 vmx->nested.vmcs02_num--;
6519 return;
6520 }
6521 }
6522
6523 /*
6524 * Free all VMCSs saved for this vcpu, except the one pointed by
6525 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6526 * must be &vmx->vmcs01.
6527 */
6528 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6529 {
6530 struct vmcs02_list *item, *n;
6531
6532 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6533 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6534 /*
6535 * Something will leak if the above WARN triggers. Better than
6536 * a use-after-free.
6537 */
6538 if (vmx->loaded_vmcs == &item->vmcs02)
6539 continue;
6540
6541 free_loaded_vmcs(&item->vmcs02);
6542 list_del(&item->list);
6543 kfree(item);
6544 vmx->nested.vmcs02_num--;
6545 }
6546 }
6547
6548 /*
6549 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6550 * set the success or error code of an emulated VMX instruction, as specified
6551 * by Vol 2B, VMX Instruction Reference, "Conventions".
6552 */
6553 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6554 {
6555 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6556 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6557 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6558 }
6559
6560 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6561 {
6562 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6563 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6564 X86_EFLAGS_SF | X86_EFLAGS_OF))
6565 | X86_EFLAGS_CF);
6566 }
6567
6568 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6569 u32 vm_instruction_error)
6570 {
6571 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6572 /*
6573 * failValid writes the error number to the current VMCS, which
6574 * can't be done there isn't a current VMCS.
6575 */
6576 nested_vmx_failInvalid(vcpu);
6577 return;
6578 }
6579 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6580 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6581 X86_EFLAGS_SF | X86_EFLAGS_OF))
6582 | X86_EFLAGS_ZF);
6583 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6584 /*
6585 * We don't need to force a shadow sync because
6586 * VM_INSTRUCTION_ERROR is not shadowed
6587 */
6588 }
6589
6590 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6591 {
6592 /* TODO: not to reset guest simply here. */
6593 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6594 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6595 }
6596
6597 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6598 {
6599 struct vcpu_vmx *vmx =
6600 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6601
6602 vmx->nested.preemption_timer_expired = true;
6603 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6604 kvm_vcpu_kick(&vmx->vcpu);
6605
6606 return HRTIMER_NORESTART;
6607 }
6608
6609 /*
6610 * Decode the memory-address operand of a vmx instruction, as recorded on an
6611 * exit caused by such an instruction (run by a guest hypervisor).
6612 * On success, returns 0. When the operand is invalid, returns 1 and throws
6613 * #UD or #GP.
6614 */
6615 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6616 unsigned long exit_qualification,
6617 u32 vmx_instruction_info, bool wr, gva_t *ret)
6618 {
6619 gva_t off;
6620 bool exn;
6621 struct kvm_segment s;
6622
6623 /*
6624 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6625 * Execution", on an exit, vmx_instruction_info holds most of the
6626 * addressing components of the operand. Only the displacement part
6627 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6628 * For how an actual address is calculated from all these components,
6629 * refer to Vol. 1, "Operand Addressing".
6630 */
6631 int scaling = vmx_instruction_info & 3;
6632 int addr_size = (vmx_instruction_info >> 7) & 7;
6633 bool is_reg = vmx_instruction_info & (1u << 10);
6634 int seg_reg = (vmx_instruction_info >> 15) & 7;
6635 int index_reg = (vmx_instruction_info >> 18) & 0xf;
6636 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6637 int base_reg = (vmx_instruction_info >> 23) & 0xf;
6638 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
6639
6640 if (is_reg) {
6641 kvm_queue_exception(vcpu, UD_VECTOR);
6642 return 1;
6643 }
6644
6645 /* Addr = segment_base + offset */
6646 /* offset = base + [index * scale] + displacement */
6647 off = exit_qualification; /* holds the displacement */
6648 if (base_is_valid)
6649 off += kvm_register_read(vcpu, base_reg);
6650 if (index_is_valid)
6651 off += kvm_register_read(vcpu, index_reg)<<scaling;
6652 vmx_get_segment(vcpu, &s, seg_reg);
6653 *ret = s.base + off;
6654
6655 if (addr_size == 1) /* 32 bit */
6656 *ret &= 0xffffffff;
6657
6658 /* Checks for #GP/#SS exceptions. */
6659 exn = false;
6660 if (is_protmode(vcpu)) {
6661 /* Protected mode: apply checks for segment validity in the
6662 * following order:
6663 * - segment type check (#GP(0) may be thrown)
6664 * - usability check (#GP(0)/#SS(0))
6665 * - limit check (#GP(0)/#SS(0))
6666 */
6667 if (wr)
6668 /* #GP(0) if the destination operand is located in a
6669 * read-only data segment or any code segment.
6670 */
6671 exn = ((s.type & 0xa) == 0 || (s.type & 8));
6672 else
6673 /* #GP(0) if the source operand is located in an
6674 * execute-only code segment
6675 */
6676 exn = ((s.type & 0xa) == 8);
6677 }
6678 if (exn) {
6679 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6680 return 1;
6681 }
6682 if (is_long_mode(vcpu)) {
6683 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6684 * non-canonical form. This is an only check for long mode.
6685 */
6686 exn = is_noncanonical_address(*ret);
6687 } else if (is_protmode(vcpu)) {
6688 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6689 */
6690 exn = (s.unusable != 0);
6691 /* Protected mode: #GP(0)/#SS(0) if the memory
6692 * operand is outside the segment limit.
6693 */
6694 exn = exn || (off + sizeof(u64) > s.limit);
6695 }
6696 if (exn) {
6697 kvm_queue_exception_e(vcpu,
6698 seg_reg == VCPU_SREG_SS ?
6699 SS_VECTOR : GP_VECTOR,
6700 0);
6701 return 1;
6702 }
6703
6704 return 0;
6705 }
6706
6707 /*
6708 * This function performs the various checks including
6709 * - if it's 4KB aligned
6710 * - No bits beyond the physical address width are set
6711 * - Returns 0 on success or else 1
6712 * (Intel SDM Section 30.3)
6713 */
6714 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6715 gpa_t *vmpointer)
6716 {
6717 gva_t gva;
6718 gpa_t vmptr;
6719 struct x86_exception e;
6720 struct page *page;
6721 struct vcpu_vmx *vmx = to_vmx(vcpu);
6722 int maxphyaddr = cpuid_maxphyaddr(vcpu);
6723
6724 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6725 vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6726 return 1;
6727
6728 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6729 sizeof(vmptr), &e)) {
6730 kvm_inject_page_fault(vcpu, &e);
6731 return 1;
6732 }
6733
6734 switch (exit_reason) {
6735 case EXIT_REASON_VMON:
6736 /*
6737 * SDM 3: 24.11.5
6738 * The first 4 bytes of VMXON region contain the supported
6739 * VMCS revision identifier
6740 *
6741 * Note - IA32_VMX_BASIC[48] will never be 1
6742 * for the nested case;
6743 * which replaces physical address width with 32
6744 *
6745 */
6746 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6747 nested_vmx_failInvalid(vcpu);
6748 skip_emulated_instruction(vcpu);
6749 return 1;
6750 }
6751
6752 page = nested_get_page(vcpu, vmptr);
6753 if (page == NULL ||
6754 *(u32 *)kmap(page) != VMCS12_REVISION) {
6755 nested_vmx_failInvalid(vcpu);
6756 kunmap(page);
6757 skip_emulated_instruction(vcpu);
6758 return 1;
6759 }
6760 kunmap(page);
6761 vmx->nested.vmxon_ptr = vmptr;
6762 break;
6763 case EXIT_REASON_VMCLEAR:
6764 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6765 nested_vmx_failValid(vcpu,
6766 VMXERR_VMCLEAR_INVALID_ADDRESS);
6767 skip_emulated_instruction(vcpu);
6768 return 1;
6769 }
6770
6771 if (vmptr == vmx->nested.vmxon_ptr) {
6772 nested_vmx_failValid(vcpu,
6773 VMXERR_VMCLEAR_VMXON_POINTER);
6774 skip_emulated_instruction(vcpu);
6775 return 1;
6776 }
6777 break;
6778 case EXIT_REASON_VMPTRLD:
6779 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6780 nested_vmx_failValid(vcpu,
6781 VMXERR_VMPTRLD_INVALID_ADDRESS);
6782 skip_emulated_instruction(vcpu);
6783 return 1;
6784 }
6785
6786 if (vmptr == vmx->nested.vmxon_ptr) {
6787 nested_vmx_failValid(vcpu,
6788 VMXERR_VMCLEAR_VMXON_POINTER);
6789 skip_emulated_instruction(vcpu);
6790 return 1;
6791 }
6792 break;
6793 default:
6794 return 1; /* shouldn't happen */
6795 }
6796
6797 if (vmpointer)
6798 *vmpointer = vmptr;
6799 return 0;
6800 }
6801
6802 /*
6803 * Emulate the VMXON instruction.
6804 * Currently, we just remember that VMX is active, and do not save or even
6805 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6806 * do not currently need to store anything in that guest-allocated memory
6807 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6808 * argument is different from the VMXON pointer (which the spec says they do).
6809 */
6810 static int handle_vmon(struct kvm_vcpu *vcpu)
6811 {
6812 struct kvm_segment cs;
6813 struct vcpu_vmx *vmx = to_vmx(vcpu);
6814 struct vmcs *shadow_vmcs;
6815 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6816 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6817
6818 /* The Intel VMX Instruction Reference lists a bunch of bits that
6819 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6820 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6821 * Otherwise, we should fail with #UD. We test these now:
6822 */
6823 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6824 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6825 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6826 kvm_queue_exception(vcpu, UD_VECTOR);
6827 return 1;
6828 }
6829
6830 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6831 if (is_long_mode(vcpu) && !cs.l) {
6832 kvm_queue_exception(vcpu, UD_VECTOR);
6833 return 1;
6834 }
6835
6836 if (vmx_get_cpl(vcpu)) {
6837 kvm_inject_gp(vcpu, 0);
6838 return 1;
6839 }
6840
6841 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6842 return 1;
6843
6844 if (vmx->nested.vmxon) {
6845 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6846 skip_emulated_instruction(vcpu);
6847 return 1;
6848 }
6849
6850 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6851 != VMXON_NEEDED_FEATURES) {
6852 kvm_inject_gp(vcpu, 0);
6853 return 1;
6854 }
6855
6856 if (enable_shadow_vmcs) {
6857 shadow_vmcs = alloc_vmcs();
6858 if (!shadow_vmcs)
6859 return -ENOMEM;
6860 /* mark vmcs as shadow */
6861 shadow_vmcs->revision_id |= (1u << 31);
6862 /* init shadow vmcs */
6863 vmcs_clear(shadow_vmcs);
6864 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6865 }
6866
6867 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6868 vmx->nested.vmcs02_num = 0;
6869
6870 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6871 HRTIMER_MODE_REL);
6872 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6873
6874 vmx->nested.vmxon = true;
6875
6876 skip_emulated_instruction(vcpu);
6877 nested_vmx_succeed(vcpu);
6878 return 1;
6879 }
6880
6881 /*
6882 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6883 * for running VMX instructions (except VMXON, whose prerequisites are
6884 * slightly different). It also specifies what exception to inject otherwise.
6885 */
6886 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6887 {
6888 struct kvm_segment cs;
6889 struct vcpu_vmx *vmx = to_vmx(vcpu);
6890
6891 if (!vmx->nested.vmxon) {
6892 kvm_queue_exception(vcpu, UD_VECTOR);
6893 return 0;
6894 }
6895
6896 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6897 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6898 (is_long_mode(vcpu) && !cs.l)) {
6899 kvm_queue_exception(vcpu, UD_VECTOR);
6900 return 0;
6901 }
6902
6903 if (vmx_get_cpl(vcpu)) {
6904 kvm_inject_gp(vcpu, 0);
6905 return 0;
6906 }
6907
6908 return 1;
6909 }
6910
6911 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6912 {
6913 if (vmx->nested.current_vmptr == -1ull)
6914 return;
6915
6916 /* current_vmptr and current_vmcs12 are always set/reset together */
6917 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6918 return;
6919
6920 if (enable_shadow_vmcs) {
6921 /* copy to memory all shadowed fields in case
6922 they were modified */
6923 copy_shadow_to_vmcs12(vmx);
6924 vmx->nested.sync_shadow_vmcs = false;
6925 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6926 SECONDARY_EXEC_SHADOW_VMCS);
6927 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6928 }
6929 vmx->nested.posted_intr_nv = -1;
6930 kunmap(vmx->nested.current_vmcs12_page);
6931 nested_release_page(vmx->nested.current_vmcs12_page);
6932 vmx->nested.current_vmptr = -1ull;
6933 vmx->nested.current_vmcs12 = NULL;
6934 }
6935
6936 /*
6937 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6938 * just stops using VMX.
6939 */
6940 static void free_nested(struct vcpu_vmx *vmx)
6941 {
6942 if (!vmx->nested.vmxon)
6943 return;
6944
6945 vmx->nested.vmxon = false;
6946 free_vpid(vmx->nested.vpid02);
6947 nested_release_vmcs12(vmx);
6948 if (enable_shadow_vmcs)
6949 free_vmcs(vmx->nested.current_shadow_vmcs);
6950 /* Unpin physical memory we referred to in current vmcs02 */
6951 if (vmx->nested.apic_access_page) {
6952 nested_release_page(vmx->nested.apic_access_page);
6953 vmx->nested.apic_access_page = NULL;
6954 }
6955 if (vmx->nested.virtual_apic_page) {
6956 nested_release_page(vmx->nested.virtual_apic_page);
6957 vmx->nested.virtual_apic_page = NULL;
6958 }
6959 if (vmx->nested.pi_desc_page) {
6960 kunmap(vmx->nested.pi_desc_page);
6961 nested_release_page(vmx->nested.pi_desc_page);
6962 vmx->nested.pi_desc_page = NULL;
6963 vmx->nested.pi_desc = NULL;
6964 }
6965
6966 nested_free_all_saved_vmcss(vmx);
6967 }
6968
6969 /* Emulate the VMXOFF instruction */
6970 static int handle_vmoff(struct kvm_vcpu *vcpu)
6971 {
6972 if (!nested_vmx_check_permission(vcpu))
6973 return 1;
6974 free_nested(to_vmx(vcpu));
6975 skip_emulated_instruction(vcpu);
6976 nested_vmx_succeed(vcpu);
6977 return 1;
6978 }
6979
6980 /* Emulate the VMCLEAR instruction */
6981 static int handle_vmclear(struct kvm_vcpu *vcpu)
6982 {
6983 struct vcpu_vmx *vmx = to_vmx(vcpu);
6984 gpa_t vmptr;
6985 struct vmcs12 *vmcs12;
6986 struct page *page;
6987
6988 if (!nested_vmx_check_permission(vcpu))
6989 return 1;
6990
6991 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6992 return 1;
6993
6994 if (vmptr == vmx->nested.current_vmptr)
6995 nested_release_vmcs12(vmx);
6996
6997 page = nested_get_page(vcpu, vmptr);
6998 if (page == NULL) {
6999 /*
7000 * For accurate processor emulation, VMCLEAR beyond available
7001 * physical memory should do nothing at all. However, it is
7002 * possible that a nested vmx bug, not a guest hypervisor bug,
7003 * resulted in this case, so let's shut down before doing any
7004 * more damage:
7005 */
7006 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7007 return 1;
7008 }
7009 vmcs12 = kmap(page);
7010 vmcs12->launch_state = 0;
7011 kunmap(page);
7012 nested_release_page(page);
7013
7014 nested_free_vmcs02(vmx, vmptr);
7015
7016 skip_emulated_instruction(vcpu);
7017 nested_vmx_succeed(vcpu);
7018 return 1;
7019 }
7020
7021 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7022
7023 /* Emulate the VMLAUNCH instruction */
7024 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7025 {
7026 return nested_vmx_run(vcpu, true);
7027 }
7028
7029 /* Emulate the VMRESUME instruction */
7030 static int handle_vmresume(struct kvm_vcpu *vcpu)
7031 {
7032
7033 return nested_vmx_run(vcpu, false);
7034 }
7035
7036 enum vmcs_field_type {
7037 VMCS_FIELD_TYPE_U16 = 0,
7038 VMCS_FIELD_TYPE_U64 = 1,
7039 VMCS_FIELD_TYPE_U32 = 2,
7040 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7041 };
7042
7043 static inline int vmcs_field_type(unsigned long field)
7044 {
7045 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
7046 return VMCS_FIELD_TYPE_U32;
7047 return (field >> 13) & 0x3 ;
7048 }
7049
7050 static inline int vmcs_field_readonly(unsigned long field)
7051 {
7052 return (((field >> 10) & 0x3) == 1);
7053 }
7054
7055 /*
7056 * Read a vmcs12 field. Since these can have varying lengths and we return
7057 * one type, we chose the biggest type (u64) and zero-extend the return value
7058 * to that size. Note that the caller, handle_vmread, might need to use only
7059 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7060 * 64-bit fields are to be returned).
7061 */
7062 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7063 unsigned long field, u64 *ret)
7064 {
7065 short offset = vmcs_field_to_offset(field);
7066 char *p;
7067
7068 if (offset < 0)
7069 return offset;
7070
7071 p = ((char *)(get_vmcs12(vcpu))) + offset;
7072
7073 switch (vmcs_field_type(field)) {
7074 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7075 *ret = *((natural_width *)p);
7076 return 0;
7077 case VMCS_FIELD_TYPE_U16:
7078 *ret = *((u16 *)p);
7079 return 0;
7080 case VMCS_FIELD_TYPE_U32:
7081 *ret = *((u32 *)p);
7082 return 0;
7083 case VMCS_FIELD_TYPE_U64:
7084 *ret = *((u64 *)p);
7085 return 0;
7086 default:
7087 WARN_ON(1);
7088 return -ENOENT;
7089 }
7090 }
7091
7092
7093 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7094 unsigned long field, u64 field_value){
7095 short offset = vmcs_field_to_offset(field);
7096 char *p = ((char *) get_vmcs12(vcpu)) + offset;
7097 if (offset < 0)
7098 return offset;
7099
7100 switch (vmcs_field_type(field)) {
7101 case VMCS_FIELD_TYPE_U16:
7102 *(u16 *)p = field_value;
7103 return 0;
7104 case VMCS_FIELD_TYPE_U32:
7105 *(u32 *)p = field_value;
7106 return 0;
7107 case VMCS_FIELD_TYPE_U64:
7108 *(u64 *)p = field_value;
7109 return 0;
7110 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7111 *(natural_width *)p = field_value;
7112 return 0;
7113 default:
7114 WARN_ON(1);
7115 return -ENOENT;
7116 }
7117
7118 }
7119
7120 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7121 {
7122 int i;
7123 unsigned long field;
7124 u64 field_value;
7125 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7126 const unsigned long *fields = shadow_read_write_fields;
7127 const int num_fields = max_shadow_read_write_fields;
7128
7129 preempt_disable();
7130
7131 vmcs_load(shadow_vmcs);
7132
7133 for (i = 0; i < num_fields; i++) {
7134 field = fields[i];
7135 switch (vmcs_field_type(field)) {
7136 case VMCS_FIELD_TYPE_U16:
7137 field_value = vmcs_read16(field);
7138 break;
7139 case VMCS_FIELD_TYPE_U32:
7140 field_value = vmcs_read32(field);
7141 break;
7142 case VMCS_FIELD_TYPE_U64:
7143 field_value = vmcs_read64(field);
7144 break;
7145 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7146 field_value = vmcs_readl(field);
7147 break;
7148 default:
7149 WARN_ON(1);
7150 continue;
7151 }
7152 vmcs12_write_any(&vmx->vcpu, field, field_value);
7153 }
7154
7155 vmcs_clear(shadow_vmcs);
7156 vmcs_load(vmx->loaded_vmcs->vmcs);
7157
7158 preempt_enable();
7159 }
7160
7161 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7162 {
7163 const unsigned long *fields[] = {
7164 shadow_read_write_fields,
7165 shadow_read_only_fields
7166 };
7167 const int max_fields[] = {
7168 max_shadow_read_write_fields,
7169 max_shadow_read_only_fields
7170 };
7171 int i, q;
7172 unsigned long field;
7173 u64 field_value = 0;
7174 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7175
7176 vmcs_load(shadow_vmcs);
7177
7178 for (q = 0; q < ARRAY_SIZE(fields); q++) {
7179 for (i = 0; i < max_fields[q]; i++) {
7180 field = fields[q][i];
7181 vmcs12_read_any(&vmx->vcpu, field, &field_value);
7182
7183 switch (vmcs_field_type(field)) {
7184 case VMCS_FIELD_TYPE_U16:
7185 vmcs_write16(field, (u16)field_value);
7186 break;
7187 case VMCS_FIELD_TYPE_U32:
7188 vmcs_write32(field, (u32)field_value);
7189 break;
7190 case VMCS_FIELD_TYPE_U64:
7191 vmcs_write64(field, (u64)field_value);
7192 break;
7193 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7194 vmcs_writel(field, (long)field_value);
7195 break;
7196 default:
7197 WARN_ON(1);
7198 break;
7199 }
7200 }
7201 }
7202
7203 vmcs_clear(shadow_vmcs);
7204 vmcs_load(vmx->loaded_vmcs->vmcs);
7205 }
7206
7207 /*
7208 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7209 * used before) all generate the same failure when it is missing.
7210 */
7211 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7212 {
7213 struct vcpu_vmx *vmx = to_vmx(vcpu);
7214 if (vmx->nested.current_vmptr == -1ull) {
7215 nested_vmx_failInvalid(vcpu);
7216 skip_emulated_instruction(vcpu);
7217 return 0;
7218 }
7219 return 1;
7220 }
7221
7222 static int handle_vmread(struct kvm_vcpu *vcpu)
7223 {
7224 unsigned long field;
7225 u64 field_value;
7226 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7227 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7228 gva_t gva = 0;
7229
7230 if (!nested_vmx_check_permission(vcpu) ||
7231 !nested_vmx_check_vmcs12(vcpu))
7232 return 1;
7233
7234 /* Decode instruction info and find the field to read */
7235 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7236 /* Read the field, zero-extended to a u64 field_value */
7237 if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7238 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7239 skip_emulated_instruction(vcpu);
7240 return 1;
7241 }
7242 /*
7243 * Now copy part of this value to register or memory, as requested.
7244 * Note that the number of bits actually copied is 32 or 64 depending
7245 * on the guest's mode (32 or 64 bit), not on the given field's length.
7246 */
7247 if (vmx_instruction_info & (1u << 10)) {
7248 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7249 field_value);
7250 } else {
7251 if (get_vmx_mem_address(vcpu, exit_qualification,
7252 vmx_instruction_info, true, &gva))
7253 return 1;
7254 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7255 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7256 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7257 }
7258
7259 nested_vmx_succeed(vcpu);
7260 skip_emulated_instruction(vcpu);
7261 return 1;
7262 }
7263
7264
7265 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7266 {
7267 unsigned long field;
7268 gva_t gva;
7269 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7270 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7271 /* The value to write might be 32 or 64 bits, depending on L1's long
7272 * mode, and eventually we need to write that into a field of several
7273 * possible lengths. The code below first zero-extends the value to 64
7274 * bit (field_value), and then copies only the appropriate number of
7275 * bits into the vmcs12 field.
7276 */
7277 u64 field_value = 0;
7278 struct x86_exception e;
7279
7280 if (!nested_vmx_check_permission(vcpu) ||
7281 !nested_vmx_check_vmcs12(vcpu))
7282 return 1;
7283
7284 if (vmx_instruction_info & (1u << 10))
7285 field_value = kvm_register_readl(vcpu,
7286 (((vmx_instruction_info) >> 3) & 0xf));
7287 else {
7288 if (get_vmx_mem_address(vcpu, exit_qualification,
7289 vmx_instruction_info, false, &gva))
7290 return 1;
7291 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7292 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7293 kvm_inject_page_fault(vcpu, &e);
7294 return 1;
7295 }
7296 }
7297
7298
7299 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7300 if (vmcs_field_readonly(field)) {
7301 nested_vmx_failValid(vcpu,
7302 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7303 skip_emulated_instruction(vcpu);
7304 return 1;
7305 }
7306
7307 if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7308 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7309 skip_emulated_instruction(vcpu);
7310 return 1;
7311 }
7312
7313 nested_vmx_succeed(vcpu);
7314 skip_emulated_instruction(vcpu);
7315 return 1;
7316 }
7317
7318 /* Emulate the VMPTRLD instruction */
7319 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7320 {
7321 struct vcpu_vmx *vmx = to_vmx(vcpu);
7322 gpa_t vmptr;
7323
7324 if (!nested_vmx_check_permission(vcpu))
7325 return 1;
7326
7327 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7328 return 1;
7329
7330 if (vmx->nested.current_vmptr != vmptr) {
7331 struct vmcs12 *new_vmcs12;
7332 struct page *page;
7333 page = nested_get_page(vcpu, vmptr);
7334 if (page == NULL) {
7335 nested_vmx_failInvalid(vcpu);
7336 skip_emulated_instruction(vcpu);
7337 return 1;
7338 }
7339 new_vmcs12 = kmap(page);
7340 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7341 kunmap(page);
7342 nested_release_page_clean(page);
7343 nested_vmx_failValid(vcpu,
7344 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7345 skip_emulated_instruction(vcpu);
7346 return 1;
7347 }
7348
7349 nested_release_vmcs12(vmx);
7350 vmx->nested.current_vmptr = vmptr;
7351 vmx->nested.current_vmcs12 = new_vmcs12;
7352 vmx->nested.current_vmcs12_page = page;
7353 if (enable_shadow_vmcs) {
7354 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7355 SECONDARY_EXEC_SHADOW_VMCS);
7356 vmcs_write64(VMCS_LINK_POINTER,
7357 __pa(vmx->nested.current_shadow_vmcs));
7358 vmx->nested.sync_shadow_vmcs = true;
7359 }
7360 }
7361
7362 nested_vmx_succeed(vcpu);
7363 skip_emulated_instruction(vcpu);
7364 return 1;
7365 }
7366
7367 /* Emulate the VMPTRST instruction */
7368 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7369 {
7370 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7371 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7372 gva_t vmcs_gva;
7373 struct x86_exception e;
7374
7375 if (!nested_vmx_check_permission(vcpu))
7376 return 1;
7377
7378 if (get_vmx_mem_address(vcpu, exit_qualification,
7379 vmx_instruction_info, true, &vmcs_gva))
7380 return 1;
7381 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7382 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7383 (void *)&to_vmx(vcpu)->nested.current_vmptr,
7384 sizeof(u64), &e)) {
7385 kvm_inject_page_fault(vcpu, &e);
7386 return 1;
7387 }
7388 nested_vmx_succeed(vcpu);
7389 skip_emulated_instruction(vcpu);
7390 return 1;
7391 }
7392
7393 /* Emulate the INVEPT instruction */
7394 static int handle_invept(struct kvm_vcpu *vcpu)
7395 {
7396 struct vcpu_vmx *vmx = to_vmx(vcpu);
7397 u32 vmx_instruction_info, types;
7398 unsigned long type;
7399 gva_t gva;
7400 struct x86_exception e;
7401 struct {
7402 u64 eptp, gpa;
7403 } operand;
7404
7405 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7406 SECONDARY_EXEC_ENABLE_EPT) ||
7407 !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7408 kvm_queue_exception(vcpu, UD_VECTOR);
7409 return 1;
7410 }
7411
7412 if (!nested_vmx_check_permission(vcpu))
7413 return 1;
7414
7415 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7416 kvm_queue_exception(vcpu, UD_VECTOR);
7417 return 1;
7418 }
7419
7420 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7421 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7422
7423 types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7424
7425 if (!(types & (1UL << type))) {
7426 nested_vmx_failValid(vcpu,
7427 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7428 skip_emulated_instruction(vcpu);
7429 return 1;
7430 }
7431
7432 /* According to the Intel VMX instruction reference, the memory
7433 * operand is read even if it isn't needed (e.g., for type==global)
7434 */
7435 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7436 vmx_instruction_info, false, &gva))
7437 return 1;
7438 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7439 sizeof(operand), &e)) {
7440 kvm_inject_page_fault(vcpu, &e);
7441 return 1;
7442 }
7443
7444 switch (type) {
7445 case VMX_EPT_EXTENT_GLOBAL:
7446 kvm_mmu_sync_roots(vcpu);
7447 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7448 nested_vmx_succeed(vcpu);
7449 break;
7450 default:
7451 /* Trap single context invalidation invept calls */
7452 BUG_ON(1);
7453 break;
7454 }
7455
7456 skip_emulated_instruction(vcpu);
7457 return 1;
7458 }
7459
7460 static int handle_invvpid(struct kvm_vcpu *vcpu)
7461 {
7462 struct vcpu_vmx *vmx = to_vmx(vcpu);
7463 u32 vmx_instruction_info;
7464 unsigned long type, types;
7465 gva_t gva;
7466 struct x86_exception e;
7467 int vpid;
7468
7469 if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7470 SECONDARY_EXEC_ENABLE_VPID) ||
7471 !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7472 kvm_queue_exception(vcpu, UD_VECTOR);
7473 return 1;
7474 }
7475
7476 if (!nested_vmx_check_permission(vcpu))
7477 return 1;
7478
7479 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7480 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7481
7482 types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7483
7484 if (!(types & (1UL << type))) {
7485 nested_vmx_failValid(vcpu,
7486 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7487 skip_emulated_instruction(vcpu);
7488 return 1;
7489 }
7490
7491 /* according to the intel vmx instruction reference, the memory
7492 * operand is read even if it isn't needed (e.g., for type==global)
7493 */
7494 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7495 vmx_instruction_info, false, &gva))
7496 return 1;
7497 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7498 sizeof(u32), &e)) {
7499 kvm_inject_page_fault(vcpu, &e);
7500 return 1;
7501 }
7502
7503 switch (type) {
7504 case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7505 /*
7506 * Old versions of KVM use the single-context version so we
7507 * have to support it; just treat it the same as all-context.
7508 */
7509 case VMX_VPID_EXTENT_ALL_CONTEXT:
7510 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7511 nested_vmx_succeed(vcpu);
7512 break;
7513 default:
7514 /* Trap individual address invalidation invvpid calls */
7515 BUG_ON(1);
7516 break;
7517 }
7518
7519 skip_emulated_instruction(vcpu);
7520 return 1;
7521 }
7522
7523 static int handle_pml_full(struct kvm_vcpu *vcpu)
7524 {
7525 unsigned long exit_qualification;
7526
7527 trace_kvm_pml_full(vcpu->vcpu_id);
7528
7529 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7530
7531 /*
7532 * PML buffer FULL happened while executing iret from NMI,
7533 * "blocked by NMI" bit has to be set before next VM entry.
7534 */
7535 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7536 cpu_has_virtual_nmis() &&
7537 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7538 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7539 GUEST_INTR_STATE_NMI);
7540
7541 /*
7542 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7543 * here.., and there's no userspace involvement needed for PML.
7544 */
7545 return 1;
7546 }
7547
7548 static int handle_pcommit(struct kvm_vcpu *vcpu)
7549 {
7550 /* we never catch pcommit instruct for L1 guest. */
7551 WARN_ON(1);
7552 return 1;
7553 }
7554
7555 /*
7556 * The exit handlers return 1 if the exit was handled fully and guest execution
7557 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7558 * to be done to userspace and return 0.
7559 */
7560 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7561 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
7562 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
7563 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
7564 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
7565 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
7566 [EXIT_REASON_CR_ACCESS] = handle_cr,
7567 [EXIT_REASON_DR_ACCESS] = handle_dr,
7568 [EXIT_REASON_CPUID] = handle_cpuid,
7569 [EXIT_REASON_MSR_READ] = handle_rdmsr,
7570 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
7571 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
7572 [EXIT_REASON_HLT] = handle_halt,
7573 [EXIT_REASON_INVD] = handle_invd,
7574 [EXIT_REASON_INVLPG] = handle_invlpg,
7575 [EXIT_REASON_RDPMC] = handle_rdpmc,
7576 [EXIT_REASON_VMCALL] = handle_vmcall,
7577 [EXIT_REASON_VMCLEAR] = handle_vmclear,
7578 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
7579 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
7580 [EXIT_REASON_VMPTRST] = handle_vmptrst,
7581 [EXIT_REASON_VMREAD] = handle_vmread,
7582 [EXIT_REASON_VMRESUME] = handle_vmresume,
7583 [EXIT_REASON_VMWRITE] = handle_vmwrite,
7584 [EXIT_REASON_VMOFF] = handle_vmoff,
7585 [EXIT_REASON_VMON] = handle_vmon,
7586 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
7587 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
7588 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
7589 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
7590 [EXIT_REASON_WBINVD] = handle_wbinvd,
7591 [EXIT_REASON_XSETBV] = handle_xsetbv,
7592 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
7593 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
7594 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
7595 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
7596 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
7597 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
7598 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
7599 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
7600 [EXIT_REASON_INVEPT] = handle_invept,
7601 [EXIT_REASON_INVVPID] = handle_invvpid,
7602 [EXIT_REASON_XSAVES] = handle_xsaves,
7603 [EXIT_REASON_XRSTORS] = handle_xrstors,
7604 [EXIT_REASON_PML_FULL] = handle_pml_full,
7605 [EXIT_REASON_PCOMMIT] = handle_pcommit,
7606 };
7607
7608 static const int kvm_vmx_max_exit_handlers =
7609 ARRAY_SIZE(kvm_vmx_exit_handlers);
7610
7611 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7612 struct vmcs12 *vmcs12)
7613 {
7614 unsigned long exit_qualification;
7615 gpa_t bitmap, last_bitmap;
7616 unsigned int port;
7617 int size;
7618 u8 b;
7619
7620 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7621 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7622
7623 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7624
7625 port = exit_qualification >> 16;
7626 size = (exit_qualification & 7) + 1;
7627
7628 last_bitmap = (gpa_t)-1;
7629 b = -1;
7630
7631 while (size > 0) {
7632 if (port < 0x8000)
7633 bitmap = vmcs12->io_bitmap_a;
7634 else if (port < 0x10000)
7635 bitmap = vmcs12->io_bitmap_b;
7636 else
7637 return true;
7638 bitmap += (port & 0x7fff) / 8;
7639
7640 if (last_bitmap != bitmap)
7641 if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7642 return true;
7643 if (b & (1 << (port & 7)))
7644 return true;
7645
7646 port++;
7647 size--;
7648 last_bitmap = bitmap;
7649 }
7650
7651 return false;
7652 }
7653
7654 /*
7655 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7656 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7657 * disinterest in the current event (read or write a specific MSR) by using an
7658 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7659 */
7660 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7661 struct vmcs12 *vmcs12, u32 exit_reason)
7662 {
7663 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7664 gpa_t bitmap;
7665
7666 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7667 return true;
7668
7669 /*
7670 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7671 * for the four combinations of read/write and low/high MSR numbers.
7672 * First we need to figure out which of the four to use:
7673 */
7674 bitmap = vmcs12->msr_bitmap;
7675 if (exit_reason == EXIT_REASON_MSR_WRITE)
7676 bitmap += 2048;
7677 if (msr_index >= 0xc0000000) {
7678 msr_index -= 0xc0000000;
7679 bitmap += 1024;
7680 }
7681
7682 /* Then read the msr_index'th bit from this bitmap: */
7683 if (msr_index < 1024*8) {
7684 unsigned char b;
7685 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7686 return true;
7687 return 1 & (b >> (msr_index & 7));
7688 } else
7689 return true; /* let L1 handle the wrong parameter */
7690 }
7691
7692 /*
7693 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7694 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7695 * intercept (via guest_host_mask etc.) the current event.
7696 */
7697 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7698 struct vmcs12 *vmcs12)
7699 {
7700 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7701 int cr = exit_qualification & 15;
7702 int reg = (exit_qualification >> 8) & 15;
7703 unsigned long val = kvm_register_readl(vcpu, reg);
7704
7705 switch ((exit_qualification >> 4) & 3) {
7706 case 0: /* mov to cr */
7707 switch (cr) {
7708 case 0:
7709 if (vmcs12->cr0_guest_host_mask &
7710 (val ^ vmcs12->cr0_read_shadow))
7711 return true;
7712 break;
7713 case 3:
7714 if ((vmcs12->cr3_target_count >= 1 &&
7715 vmcs12->cr3_target_value0 == val) ||
7716 (vmcs12->cr3_target_count >= 2 &&
7717 vmcs12->cr3_target_value1 == val) ||
7718 (vmcs12->cr3_target_count >= 3 &&
7719 vmcs12->cr3_target_value2 == val) ||
7720 (vmcs12->cr3_target_count >= 4 &&
7721 vmcs12->cr3_target_value3 == val))
7722 return false;
7723 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7724 return true;
7725 break;
7726 case 4:
7727 if (vmcs12->cr4_guest_host_mask &
7728 (vmcs12->cr4_read_shadow ^ val))
7729 return true;
7730 break;
7731 case 8:
7732 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7733 return true;
7734 break;
7735 }
7736 break;
7737 case 2: /* clts */
7738 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7739 (vmcs12->cr0_read_shadow & X86_CR0_TS))
7740 return true;
7741 break;
7742 case 1: /* mov from cr */
7743 switch (cr) {
7744 case 3:
7745 if (vmcs12->cpu_based_vm_exec_control &
7746 CPU_BASED_CR3_STORE_EXITING)
7747 return true;
7748 break;
7749 case 8:
7750 if (vmcs12->cpu_based_vm_exec_control &
7751 CPU_BASED_CR8_STORE_EXITING)
7752 return true;
7753 break;
7754 }
7755 break;
7756 case 3: /* lmsw */
7757 /*
7758 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7759 * cr0. Other attempted changes are ignored, with no exit.
7760 */
7761 if (vmcs12->cr0_guest_host_mask & 0xe &
7762 (val ^ vmcs12->cr0_read_shadow))
7763 return true;
7764 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7765 !(vmcs12->cr0_read_shadow & 0x1) &&
7766 (val & 0x1))
7767 return true;
7768 break;
7769 }
7770 return false;
7771 }
7772
7773 /*
7774 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7775 * should handle it ourselves in L0 (and then continue L2). Only call this
7776 * when in is_guest_mode (L2).
7777 */
7778 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7779 {
7780 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7781 struct vcpu_vmx *vmx = to_vmx(vcpu);
7782 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7783 u32 exit_reason = vmx->exit_reason;
7784
7785 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7786 vmcs_readl(EXIT_QUALIFICATION),
7787 vmx->idt_vectoring_info,
7788 intr_info,
7789 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7790 KVM_ISA_VMX);
7791
7792 if (vmx->nested.nested_run_pending)
7793 return false;
7794
7795 if (unlikely(vmx->fail)) {
7796 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7797 vmcs_read32(VM_INSTRUCTION_ERROR));
7798 return true;
7799 }
7800
7801 switch (exit_reason) {
7802 case EXIT_REASON_EXCEPTION_NMI:
7803 if (!is_exception(intr_info))
7804 return false;
7805 else if (is_page_fault(intr_info))
7806 return enable_ept;
7807 else if (is_no_device(intr_info) &&
7808 !(vmcs12->guest_cr0 & X86_CR0_TS))
7809 return false;
7810 else if (is_debug(intr_info) &&
7811 vcpu->guest_debug &
7812 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7813 return false;
7814 else if (is_breakpoint(intr_info) &&
7815 vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7816 return false;
7817 return vmcs12->exception_bitmap &
7818 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7819 case EXIT_REASON_EXTERNAL_INTERRUPT:
7820 return false;
7821 case EXIT_REASON_TRIPLE_FAULT:
7822 return true;
7823 case EXIT_REASON_PENDING_INTERRUPT:
7824 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7825 case EXIT_REASON_NMI_WINDOW:
7826 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7827 case EXIT_REASON_TASK_SWITCH:
7828 return true;
7829 case EXIT_REASON_CPUID:
7830 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7831 return false;
7832 return true;
7833 case EXIT_REASON_HLT:
7834 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7835 case EXIT_REASON_INVD:
7836 return true;
7837 case EXIT_REASON_INVLPG:
7838 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7839 case EXIT_REASON_RDPMC:
7840 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7841 case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7842 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7843 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7844 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7845 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7846 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7847 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7848 case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7849 /*
7850 * VMX instructions trap unconditionally. This allows L1 to
7851 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7852 */
7853 return true;
7854 case EXIT_REASON_CR_ACCESS:
7855 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7856 case EXIT_REASON_DR_ACCESS:
7857 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7858 case EXIT_REASON_IO_INSTRUCTION:
7859 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7860 case EXIT_REASON_MSR_READ:
7861 case EXIT_REASON_MSR_WRITE:
7862 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7863 case EXIT_REASON_INVALID_STATE:
7864 return true;
7865 case EXIT_REASON_MWAIT_INSTRUCTION:
7866 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7867 case EXIT_REASON_MONITOR_TRAP_FLAG:
7868 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7869 case EXIT_REASON_MONITOR_INSTRUCTION:
7870 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7871 case EXIT_REASON_PAUSE_INSTRUCTION:
7872 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7873 nested_cpu_has2(vmcs12,
7874 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7875 case EXIT_REASON_MCE_DURING_VMENTRY:
7876 return false;
7877 case EXIT_REASON_TPR_BELOW_THRESHOLD:
7878 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7879 case EXIT_REASON_APIC_ACCESS:
7880 return nested_cpu_has2(vmcs12,
7881 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7882 case EXIT_REASON_APIC_WRITE:
7883 case EXIT_REASON_EOI_INDUCED:
7884 /* apic_write and eoi_induced should exit unconditionally. */
7885 return true;
7886 case EXIT_REASON_EPT_VIOLATION:
7887 /*
7888 * L0 always deals with the EPT violation. If nested EPT is
7889 * used, and the nested mmu code discovers that the address is
7890 * missing in the guest EPT table (EPT12), the EPT violation
7891 * will be injected with nested_ept_inject_page_fault()
7892 */
7893 return false;
7894 case EXIT_REASON_EPT_MISCONFIG:
7895 /*
7896 * L2 never uses directly L1's EPT, but rather L0's own EPT
7897 * table (shadow on EPT) or a merged EPT table that L0 built
7898 * (EPT on EPT). So any problems with the structure of the
7899 * table is L0's fault.
7900 */
7901 return false;
7902 case EXIT_REASON_WBINVD:
7903 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7904 case EXIT_REASON_XSETBV:
7905 return true;
7906 case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7907 /*
7908 * This should never happen, since it is not possible to
7909 * set XSS to a non-zero value---neither in L1 nor in L2.
7910 * If if it were, XSS would have to be checked against
7911 * the XSS exit bitmap in vmcs12.
7912 */
7913 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7914 case EXIT_REASON_PCOMMIT:
7915 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7916 default:
7917 return true;
7918 }
7919 }
7920
7921 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7922 {
7923 *info1 = vmcs_readl(EXIT_QUALIFICATION);
7924 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7925 }
7926
7927 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7928 {
7929 struct page *pml_pg;
7930
7931 pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7932 if (!pml_pg)
7933 return -ENOMEM;
7934
7935 vmx->pml_pg = pml_pg;
7936
7937 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7938 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7939
7940 return 0;
7941 }
7942
7943 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7944 {
7945 if (vmx->pml_pg) {
7946 __free_page(vmx->pml_pg);
7947 vmx->pml_pg = NULL;
7948 }
7949 }
7950
7951 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7952 {
7953 struct vcpu_vmx *vmx = to_vmx(vcpu);
7954 u64 *pml_buf;
7955 u16 pml_idx;
7956
7957 pml_idx = vmcs_read16(GUEST_PML_INDEX);
7958
7959 /* Do nothing if PML buffer is empty */
7960 if (pml_idx == (PML_ENTITY_NUM - 1))
7961 return;
7962
7963 /* PML index always points to next available PML buffer entity */
7964 if (pml_idx >= PML_ENTITY_NUM)
7965 pml_idx = 0;
7966 else
7967 pml_idx++;
7968
7969 pml_buf = page_address(vmx->pml_pg);
7970 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7971 u64 gpa;
7972
7973 gpa = pml_buf[pml_idx];
7974 WARN_ON(gpa & (PAGE_SIZE - 1));
7975 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7976 }
7977
7978 /* reset PML index */
7979 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7980 }
7981
7982 /*
7983 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7984 * Called before reporting dirty_bitmap to userspace.
7985 */
7986 static void kvm_flush_pml_buffers(struct kvm *kvm)
7987 {
7988 int i;
7989 struct kvm_vcpu *vcpu;
7990 /*
7991 * We only need to kick vcpu out of guest mode here, as PML buffer
7992 * is flushed at beginning of all VMEXITs, and it's obvious that only
7993 * vcpus running in guest are possible to have unflushed GPAs in PML
7994 * buffer.
7995 */
7996 kvm_for_each_vcpu(i, vcpu, kvm)
7997 kvm_vcpu_kick(vcpu);
7998 }
7999
8000 static void vmx_dump_sel(char *name, uint32_t sel)
8001 {
8002 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8003 name, vmcs_read32(sel),
8004 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8005 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8006 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8007 }
8008
8009 static void vmx_dump_dtsel(char *name, uint32_t limit)
8010 {
8011 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8012 name, vmcs_read32(limit),
8013 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8014 }
8015
8016 static void dump_vmcs(void)
8017 {
8018 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8019 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8020 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8021 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8022 u32 secondary_exec_control = 0;
8023 unsigned long cr4 = vmcs_readl(GUEST_CR4);
8024 u64 efer = vmcs_read64(GUEST_IA32_EFER);
8025 int i, n;
8026
8027 if (cpu_has_secondary_exec_ctrls())
8028 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8029
8030 pr_err("*** Guest State ***\n");
8031 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8032 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8033 vmcs_readl(CR0_GUEST_HOST_MASK));
8034 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8035 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8036 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8037 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8038 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8039 {
8040 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8041 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8042 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8043 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8044 }
8045 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8046 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8047 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8048 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8049 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8050 vmcs_readl(GUEST_SYSENTER_ESP),
8051 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8052 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
8053 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
8054 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
8055 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
8056 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
8057 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
8058 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8059 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8060 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8061 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
8062 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8063 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8064 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8065 efer, vmcs_read64(GUEST_IA32_PAT));
8066 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8067 vmcs_read64(GUEST_IA32_DEBUGCTL),
8068 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8069 if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8070 pr_err("PerfGlobCtl = 0x%016llx\n",
8071 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8072 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8073 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8074 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8075 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8076 vmcs_read32(GUEST_ACTIVITY_STATE));
8077 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8078 pr_err("InterruptStatus = %04x\n",
8079 vmcs_read16(GUEST_INTR_STATUS));
8080
8081 pr_err("*** Host State ***\n");
8082 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8083 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8084 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8085 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8086 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8087 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8088 vmcs_read16(HOST_TR_SELECTOR));
8089 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8090 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8091 vmcs_readl(HOST_TR_BASE));
8092 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8093 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8094 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8095 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8096 vmcs_readl(HOST_CR4));
8097 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8098 vmcs_readl(HOST_IA32_SYSENTER_ESP),
8099 vmcs_read32(HOST_IA32_SYSENTER_CS),
8100 vmcs_readl(HOST_IA32_SYSENTER_EIP));
8101 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8102 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8103 vmcs_read64(HOST_IA32_EFER),
8104 vmcs_read64(HOST_IA32_PAT));
8105 if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8106 pr_err("PerfGlobCtl = 0x%016llx\n",
8107 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8108
8109 pr_err("*** Control State ***\n");
8110 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8111 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8112 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8113 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8114 vmcs_read32(EXCEPTION_BITMAP),
8115 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8116 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8117 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8118 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8119 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8120 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8121 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8122 vmcs_read32(VM_EXIT_INTR_INFO),
8123 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8124 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8125 pr_err(" reason=%08x qualification=%016lx\n",
8126 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8127 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8128 vmcs_read32(IDT_VECTORING_INFO_FIELD),
8129 vmcs_read32(IDT_VECTORING_ERROR_CODE));
8130 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8131 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8132 pr_err("TSC Multiplier = 0x%016llx\n",
8133 vmcs_read64(TSC_MULTIPLIER));
8134 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8135 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8136 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8137 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8138 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8139 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8140 n = vmcs_read32(CR3_TARGET_COUNT);
8141 for (i = 0; i + 1 < n; i += 4)
8142 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8143 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8144 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8145 if (i < n)
8146 pr_err("CR3 target%u=%016lx\n",
8147 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8148 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8149 pr_err("PLE Gap=%08x Window=%08x\n",
8150 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8151 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8152 pr_err("Virtual processor ID = 0x%04x\n",
8153 vmcs_read16(VIRTUAL_PROCESSOR_ID));
8154 }
8155
8156 /*
8157 * The guest has exited. See if we can fix it or if we need userspace
8158 * assistance.
8159 */
8160 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8161 {
8162 struct vcpu_vmx *vmx = to_vmx(vcpu);
8163 u32 exit_reason = vmx->exit_reason;
8164 u32 vectoring_info = vmx->idt_vectoring_info;
8165
8166 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8167
8168 /*
8169 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8170 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8171 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8172 * mode as if vcpus is in root mode, the PML buffer must has been
8173 * flushed already.
8174 */
8175 if (enable_pml)
8176 vmx_flush_pml_buffer(vcpu);
8177
8178 /* If guest state is invalid, start emulating */
8179 if (vmx->emulation_required)
8180 return handle_invalid_guest_state(vcpu);
8181
8182 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8183 nested_vmx_vmexit(vcpu, exit_reason,
8184 vmcs_read32(VM_EXIT_INTR_INFO),
8185 vmcs_readl(EXIT_QUALIFICATION));
8186 return 1;
8187 }
8188
8189 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8190 dump_vmcs();
8191 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8192 vcpu->run->fail_entry.hardware_entry_failure_reason
8193 = exit_reason;
8194 return 0;
8195 }
8196
8197 if (unlikely(vmx->fail)) {
8198 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8199 vcpu->run->fail_entry.hardware_entry_failure_reason
8200 = vmcs_read32(VM_INSTRUCTION_ERROR);
8201 return 0;
8202 }
8203
8204 /*
8205 * Note:
8206 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8207 * delivery event since it indicates guest is accessing MMIO.
8208 * The vm-exit can be triggered again after return to guest that
8209 * will cause infinite loop.
8210 */
8211 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8212 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8213 exit_reason != EXIT_REASON_EPT_VIOLATION &&
8214 exit_reason != EXIT_REASON_TASK_SWITCH)) {
8215 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8216 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8217 vcpu->run->internal.ndata = 2;
8218 vcpu->run->internal.data[0] = vectoring_info;
8219 vcpu->run->internal.data[1] = exit_reason;
8220 return 0;
8221 }
8222
8223 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8224 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8225 get_vmcs12(vcpu))))) {
8226 if (vmx_interrupt_allowed(vcpu)) {
8227 vmx->soft_vnmi_blocked = 0;
8228 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8229 vcpu->arch.nmi_pending) {
8230 /*
8231 * This CPU don't support us in finding the end of an
8232 * NMI-blocked window if the guest runs with IRQs
8233 * disabled. So we pull the trigger after 1 s of
8234 * futile waiting, but inform the user about this.
8235 */
8236 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8237 "state on VCPU %d after 1 s timeout\n",
8238 __func__, vcpu->vcpu_id);
8239 vmx->soft_vnmi_blocked = 0;
8240 }
8241 }
8242
8243 if (exit_reason < kvm_vmx_max_exit_handlers
8244 && kvm_vmx_exit_handlers[exit_reason])
8245 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8246 else {
8247 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8248 kvm_queue_exception(vcpu, UD_VECTOR);
8249 return 1;
8250 }
8251 }
8252
8253 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8254 {
8255 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8256
8257 if (is_guest_mode(vcpu) &&
8258 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8259 return;
8260
8261 if (irr == -1 || tpr < irr) {
8262 vmcs_write32(TPR_THRESHOLD, 0);
8263 return;
8264 }
8265
8266 vmcs_write32(TPR_THRESHOLD, irr);
8267 }
8268
8269 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8270 {
8271 u32 sec_exec_control;
8272
8273 /*
8274 * There is not point to enable virtualize x2apic without enable
8275 * apicv
8276 */
8277 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8278 !kvm_vcpu_apicv_active(vcpu))
8279 return;
8280
8281 if (!cpu_need_tpr_shadow(vcpu))
8282 return;
8283
8284 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8285
8286 if (set) {
8287 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8288 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8289 } else {
8290 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8291 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8292 }
8293 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8294
8295 vmx_set_msr_bitmap(vcpu);
8296 }
8297
8298 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8299 {
8300 struct vcpu_vmx *vmx = to_vmx(vcpu);
8301
8302 /*
8303 * Currently we do not handle the nested case where L2 has an
8304 * APIC access page of its own; that page is still pinned.
8305 * Hence, we skip the case where the VCPU is in guest mode _and_
8306 * L1 prepared an APIC access page for L2.
8307 *
8308 * For the case where L1 and L2 share the same APIC access page
8309 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8310 * in the vmcs12), this function will only update either the vmcs01
8311 * or the vmcs02. If the former, the vmcs02 will be updated by
8312 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8313 * the next L2->L1 exit.
8314 */
8315 if (!is_guest_mode(vcpu) ||
8316 !nested_cpu_has2(vmx->nested.current_vmcs12,
8317 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8318 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8319 }
8320
8321 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8322 {
8323 u16 status;
8324 u8 old;
8325
8326 if (isr == -1)
8327 isr = 0;
8328
8329 status = vmcs_read16(GUEST_INTR_STATUS);
8330 old = status >> 8;
8331 if (isr != old) {
8332 status &= 0xff;
8333 status |= isr << 8;
8334 vmcs_write16(GUEST_INTR_STATUS, status);
8335 }
8336 }
8337
8338 static void vmx_set_rvi(int vector)
8339 {
8340 u16 status;
8341 u8 old;
8342
8343 if (vector == -1)
8344 vector = 0;
8345
8346 status = vmcs_read16(GUEST_INTR_STATUS);
8347 old = (u8)status & 0xff;
8348 if ((u8)vector != old) {
8349 status &= ~0xff;
8350 status |= (u8)vector;
8351 vmcs_write16(GUEST_INTR_STATUS, status);
8352 }
8353 }
8354
8355 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8356 {
8357 if (!is_guest_mode(vcpu)) {
8358 vmx_set_rvi(max_irr);
8359 return;
8360 }
8361
8362 if (max_irr == -1)
8363 return;
8364
8365 /*
8366 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8367 * handles it.
8368 */
8369 if (nested_exit_on_intr(vcpu))
8370 return;
8371
8372 /*
8373 * Else, fall back to pre-APICv interrupt injection since L2
8374 * is run without virtual interrupt delivery.
8375 */
8376 if (!kvm_event_needs_reinjection(vcpu) &&
8377 vmx_interrupt_allowed(vcpu)) {
8378 kvm_queue_interrupt(vcpu, max_irr, false);
8379 vmx_inject_irq(vcpu);
8380 }
8381 }
8382
8383 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8384 {
8385 if (!kvm_vcpu_apicv_active(vcpu))
8386 return;
8387
8388 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8389 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8390 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8391 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8392 }
8393
8394 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8395 {
8396 u32 exit_intr_info;
8397
8398 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8399 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8400 return;
8401
8402 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8403 exit_intr_info = vmx->exit_intr_info;
8404
8405 /* Handle machine checks before interrupts are enabled */
8406 if (is_machine_check(exit_intr_info))
8407 kvm_machine_check();
8408
8409 /* We need to handle NMIs before interrupts are enabled */
8410 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8411 (exit_intr_info & INTR_INFO_VALID_MASK)) {
8412 kvm_before_handle_nmi(&vmx->vcpu);
8413 asm("int $2");
8414 kvm_after_handle_nmi(&vmx->vcpu);
8415 }
8416 }
8417
8418 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8419 {
8420 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8421 register void *__sp asm(_ASM_SP);
8422
8423 /*
8424 * If external interrupt exists, IF bit is set in rflags/eflags on the
8425 * interrupt stack frame, and interrupt will be enabled on a return
8426 * from interrupt handler.
8427 */
8428 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8429 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8430 unsigned int vector;
8431 unsigned long entry;
8432 gate_desc *desc;
8433 struct vcpu_vmx *vmx = to_vmx(vcpu);
8434 #ifdef CONFIG_X86_64
8435 unsigned long tmp;
8436 #endif
8437
8438 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8439 desc = (gate_desc *)vmx->host_idt_base + vector;
8440 entry = gate_offset(*desc);
8441 asm volatile(
8442 #ifdef CONFIG_X86_64
8443 "mov %%" _ASM_SP ", %[sp]\n\t"
8444 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8445 "push $%c[ss]\n\t"
8446 "push %[sp]\n\t"
8447 #endif
8448 "pushf\n\t"
8449 "orl $0x200, (%%" _ASM_SP ")\n\t"
8450 __ASM_SIZE(push) " $%c[cs]\n\t"
8451 "call *%[entry]\n\t"
8452 :
8453 #ifdef CONFIG_X86_64
8454 [sp]"=&r"(tmp),
8455 #endif
8456 "+r"(__sp)
8457 :
8458 [entry]"r"(entry),
8459 [ss]"i"(__KERNEL_DS),
8460 [cs]"i"(__KERNEL_CS)
8461 );
8462 } else
8463 local_irq_enable();
8464 }
8465
8466 static bool vmx_has_high_real_mode_segbase(void)
8467 {
8468 return enable_unrestricted_guest || emulate_invalid_guest_state;
8469 }
8470
8471 static bool vmx_mpx_supported(void)
8472 {
8473 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8474 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8475 }
8476
8477 static bool vmx_xsaves_supported(void)
8478 {
8479 return vmcs_config.cpu_based_2nd_exec_ctrl &
8480 SECONDARY_EXEC_XSAVES;
8481 }
8482
8483 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8484 {
8485 u32 exit_intr_info;
8486 bool unblock_nmi;
8487 u8 vector;
8488 bool idtv_info_valid;
8489
8490 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8491
8492 if (cpu_has_virtual_nmis()) {
8493 if (vmx->nmi_known_unmasked)
8494 return;
8495 /*
8496 * Can't use vmx->exit_intr_info since we're not sure what
8497 * the exit reason is.
8498 */
8499 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8500 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8501 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8502 /*
8503 * SDM 3: 27.7.1.2 (September 2008)
8504 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8505 * a guest IRET fault.
8506 * SDM 3: 23.2.2 (September 2008)
8507 * Bit 12 is undefined in any of the following cases:
8508 * If the VM exit sets the valid bit in the IDT-vectoring
8509 * information field.
8510 * If the VM exit is due to a double fault.
8511 */
8512 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8513 vector != DF_VECTOR && !idtv_info_valid)
8514 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8515 GUEST_INTR_STATE_NMI);
8516 else
8517 vmx->nmi_known_unmasked =
8518 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8519 & GUEST_INTR_STATE_NMI);
8520 } else if (unlikely(vmx->soft_vnmi_blocked))
8521 vmx->vnmi_blocked_time +=
8522 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8523 }
8524
8525 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8526 u32 idt_vectoring_info,
8527 int instr_len_field,
8528 int error_code_field)
8529 {
8530 u8 vector;
8531 int type;
8532 bool idtv_info_valid;
8533
8534 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8535
8536 vcpu->arch.nmi_injected = false;
8537 kvm_clear_exception_queue(vcpu);
8538 kvm_clear_interrupt_queue(vcpu);
8539
8540 if (!idtv_info_valid)
8541 return;
8542
8543 kvm_make_request(KVM_REQ_EVENT, vcpu);
8544
8545 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8546 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8547
8548 switch (type) {
8549 case INTR_TYPE_NMI_INTR:
8550 vcpu->arch.nmi_injected = true;
8551 /*
8552 * SDM 3: 27.7.1.2 (September 2008)
8553 * Clear bit "block by NMI" before VM entry if a NMI
8554 * delivery faulted.
8555 */
8556 vmx_set_nmi_mask(vcpu, false);
8557 break;
8558 case INTR_TYPE_SOFT_EXCEPTION:
8559 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8560 /* fall through */
8561 case INTR_TYPE_HARD_EXCEPTION:
8562 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8563 u32 err = vmcs_read32(error_code_field);
8564 kvm_requeue_exception_e(vcpu, vector, err);
8565 } else
8566 kvm_requeue_exception(vcpu, vector);
8567 break;
8568 case INTR_TYPE_SOFT_INTR:
8569 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8570 /* fall through */
8571 case INTR_TYPE_EXT_INTR:
8572 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8573 break;
8574 default:
8575 break;
8576 }
8577 }
8578
8579 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8580 {
8581 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8582 VM_EXIT_INSTRUCTION_LEN,
8583 IDT_VECTORING_ERROR_CODE);
8584 }
8585
8586 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8587 {
8588 __vmx_complete_interrupts(vcpu,
8589 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8590 VM_ENTRY_INSTRUCTION_LEN,
8591 VM_ENTRY_EXCEPTION_ERROR_CODE);
8592
8593 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8594 }
8595
8596 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8597 {
8598 int i, nr_msrs;
8599 struct perf_guest_switch_msr *msrs;
8600
8601 msrs = perf_guest_get_msrs(&nr_msrs);
8602
8603 if (!msrs)
8604 return;
8605
8606 for (i = 0; i < nr_msrs; i++)
8607 if (msrs[i].host == msrs[i].guest)
8608 clear_atomic_switch_msr(vmx, msrs[i].msr);
8609 else
8610 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8611 msrs[i].host);
8612 }
8613
8614 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8615 {
8616 struct vcpu_vmx *vmx = to_vmx(vcpu);
8617 unsigned long debugctlmsr, cr4;
8618
8619 /* Record the guest's net vcpu time for enforced NMI injections. */
8620 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8621 vmx->entry_time = ktime_get();
8622
8623 /* Don't enter VMX if guest state is invalid, let the exit handler
8624 start emulation until we arrive back to a valid state */
8625 if (vmx->emulation_required)
8626 return;
8627
8628 if (vmx->ple_window_dirty) {
8629 vmx->ple_window_dirty = false;
8630 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8631 }
8632
8633 if (vmx->nested.sync_shadow_vmcs) {
8634 copy_vmcs12_to_shadow(vmx);
8635 vmx->nested.sync_shadow_vmcs = false;
8636 }
8637
8638 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8639 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8640 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8641 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8642
8643 cr4 = cr4_read_shadow();
8644 if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8645 vmcs_writel(HOST_CR4, cr4);
8646 vmx->host_state.vmcs_host_cr4 = cr4;
8647 }
8648
8649 /* When single-stepping over STI and MOV SS, we must clear the
8650 * corresponding interruptibility bits in the guest state. Otherwise
8651 * vmentry fails as it then expects bit 14 (BS) in pending debug
8652 * exceptions being set, but that's not correct for the guest debugging
8653 * case. */
8654 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8655 vmx_set_interrupt_shadow(vcpu, 0);
8656
8657 if (vmx->guest_pkru_valid)
8658 __write_pkru(vmx->guest_pkru);
8659
8660 atomic_switch_perf_msrs(vmx);
8661 debugctlmsr = get_debugctlmsr();
8662
8663 vmx->__launched = vmx->loaded_vmcs->launched;
8664 asm(
8665 /* Store host registers */
8666 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8667 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8668 "push %%" _ASM_CX " \n\t"
8669 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8670 "je 1f \n\t"
8671 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8672 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8673 "1: \n\t"
8674 /* Reload cr2 if changed */
8675 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8676 "mov %%cr2, %%" _ASM_DX " \n\t"
8677 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8678 "je 2f \n\t"
8679 "mov %%" _ASM_AX", %%cr2 \n\t"
8680 "2: \n\t"
8681 /* Check if vmlaunch of vmresume is needed */
8682 "cmpl $0, %c[launched](%0) \n\t"
8683 /* Load guest registers. Don't clobber flags. */
8684 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8685 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8686 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8687 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8688 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8689 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8690 #ifdef CONFIG_X86_64
8691 "mov %c[r8](%0), %%r8 \n\t"
8692 "mov %c[r9](%0), %%r9 \n\t"
8693 "mov %c[r10](%0), %%r10 \n\t"
8694 "mov %c[r11](%0), %%r11 \n\t"
8695 "mov %c[r12](%0), %%r12 \n\t"
8696 "mov %c[r13](%0), %%r13 \n\t"
8697 "mov %c[r14](%0), %%r14 \n\t"
8698 "mov %c[r15](%0), %%r15 \n\t"
8699 #endif
8700 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8701
8702 /* Enter guest mode */
8703 "jne 1f \n\t"
8704 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8705 "jmp 2f \n\t"
8706 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8707 "2: "
8708 /* Save guest registers, load host registers, keep flags */
8709 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8710 "pop %0 \n\t"
8711 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8712 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8713 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8714 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8715 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8716 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8717 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8718 #ifdef CONFIG_X86_64
8719 "mov %%r8, %c[r8](%0) \n\t"
8720 "mov %%r9, %c[r9](%0) \n\t"
8721 "mov %%r10, %c[r10](%0) \n\t"
8722 "mov %%r11, %c[r11](%0) \n\t"
8723 "mov %%r12, %c[r12](%0) \n\t"
8724 "mov %%r13, %c[r13](%0) \n\t"
8725 "mov %%r14, %c[r14](%0) \n\t"
8726 "mov %%r15, %c[r15](%0) \n\t"
8727 #endif
8728 "mov %%cr2, %%" _ASM_AX " \n\t"
8729 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8730
8731 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
8732 "setbe %c[fail](%0) \n\t"
8733 ".pushsection .rodata \n\t"
8734 ".global vmx_return \n\t"
8735 "vmx_return: " _ASM_PTR " 2b \n\t"
8736 ".popsection"
8737 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8738 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8739 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8740 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8741 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8742 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8743 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8744 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8745 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8746 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8747 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8748 #ifdef CONFIG_X86_64
8749 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8750 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8751 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8752 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8753 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8754 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8755 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8756 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8757 #endif
8758 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8759 [wordsize]"i"(sizeof(ulong))
8760 : "cc", "memory"
8761 #ifdef CONFIG_X86_64
8762 , "rax", "rbx", "rdi", "rsi"
8763 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8764 #else
8765 , "eax", "ebx", "edi", "esi"
8766 #endif
8767 );
8768
8769 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8770 if (debugctlmsr)
8771 update_debugctlmsr(debugctlmsr);
8772
8773 #ifndef CONFIG_X86_64
8774 /*
8775 * The sysexit path does not restore ds/es, so we must set them to
8776 * a reasonable value ourselves.
8777 *
8778 * We can't defer this to vmx_load_host_state() since that function
8779 * may be executed in interrupt context, which saves and restore segments
8780 * around it, nullifying its effect.
8781 */
8782 loadsegment(ds, __USER_DS);
8783 loadsegment(es, __USER_DS);
8784 #endif
8785
8786 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8787 | (1 << VCPU_EXREG_RFLAGS)
8788 | (1 << VCPU_EXREG_PDPTR)
8789 | (1 << VCPU_EXREG_SEGMENTS)
8790 | (1 << VCPU_EXREG_CR3));
8791 vcpu->arch.regs_dirty = 0;
8792
8793 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8794
8795 vmx->loaded_vmcs->launched = 1;
8796
8797 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8798
8799 /*
8800 * eager fpu is enabled if PKEY is supported and CR4 is switched
8801 * back on host, so it is safe to read guest PKRU from current
8802 * XSAVE.
8803 */
8804 if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8805 vmx->guest_pkru = __read_pkru();
8806 if (vmx->guest_pkru != vmx->host_pkru) {
8807 vmx->guest_pkru_valid = true;
8808 __write_pkru(vmx->host_pkru);
8809 } else
8810 vmx->guest_pkru_valid = false;
8811 }
8812
8813 /*
8814 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8815 * we did not inject a still-pending event to L1 now because of
8816 * nested_run_pending, we need to re-enable this bit.
8817 */
8818 if (vmx->nested.nested_run_pending)
8819 kvm_make_request(KVM_REQ_EVENT, vcpu);
8820
8821 vmx->nested.nested_run_pending = 0;
8822
8823 vmx_complete_atomic_exit(vmx);
8824 vmx_recover_nmi_blocking(vmx);
8825 vmx_complete_interrupts(vmx);
8826 }
8827
8828 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8829 {
8830 struct vcpu_vmx *vmx = to_vmx(vcpu);
8831 int cpu;
8832
8833 if (vmx->loaded_vmcs == &vmx->vmcs01)
8834 return;
8835
8836 cpu = get_cpu();
8837 vmx->loaded_vmcs = &vmx->vmcs01;
8838 vmx_vcpu_put(vcpu);
8839 vmx_vcpu_load(vcpu, cpu);
8840 vcpu->cpu = cpu;
8841 put_cpu();
8842 }
8843
8844 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8845 {
8846 struct vcpu_vmx *vmx = to_vmx(vcpu);
8847
8848 if (enable_pml)
8849 vmx_destroy_pml_buffer(vmx);
8850 free_vpid(vmx->vpid);
8851 leave_guest_mode(vcpu);
8852 vmx_load_vmcs01(vcpu);
8853 free_nested(vmx);
8854 free_loaded_vmcs(vmx->loaded_vmcs);
8855 kfree(vmx->guest_msrs);
8856 kvm_vcpu_uninit(vcpu);
8857 kmem_cache_free(kvm_vcpu_cache, vmx);
8858 }
8859
8860 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8861 {
8862 int err;
8863 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8864 int cpu;
8865
8866 if (!vmx)
8867 return ERR_PTR(-ENOMEM);
8868
8869 vmx->vpid = allocate_vpid();
8870
8871 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8872 if (err)
8873 goto free_vcpu;
8874
8875 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8876 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8877 > PAGE_SIZE);
8878
8879 err = -ENOMEM;
8880 if (!vmx->guest_msrs) {
8881 goto uninit_vcpu;
8882 }
8883
8884 vmx->loaded_vmcs = &vmx->vmcs01;
8885 vmx->loaded_vmcs->vmcs = alloc_vmcs();
8886 if (!vmx->loaded_vmcs->vmcs)
8887 goto free_msrs;
8888 if (!vmm_exclusive)
8889 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8890 loaded_vmcs_init(vmx->loaded_vmcs);
8891 if (!vmm_exclusive)
8892 kvm_cpu_vmxoff();
8893
8894 cpu = get_cpu();
8895 vmx_vcpu_load(&vmx->vcpu, cpu);
8896 vmx->vcpu.cpu = cpu;
8897 err = vmx_vcpu_setup(vmx);
8898 vmx_vcpu_put(&vmx->vcpu);
8899 put_cpu();
8900 if (err)
8901 goto free_vmcs;
8902 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8903 err = alloc_apic_access_page(kvm);
8904 if (err)
8905 goto free_vmcs;
8906 }
8907
8908 if (enable_ept) {
8909 if (!kvm->arch.ept_identity_map_addr)
8910 kvm->arch.ept_identity_map_addr =
8911 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8912 err = init_rmode_identity_map(kvm);
8913 if (err)
8914 goto free_vmcs;
8915 }
8916
8917 if (nested) {
8918 nested_vmx_setup_ctls_msrs(vmx);
8919 vmx->nested.vpid02 = allocate_vpid();
8920 }
8921
8922 vmx->nested.posted_intr_nv = -1;
8923 vmx->nested.current_vmptr = -1ull;
8924 vmx->nested.current_vmcs12 = NULL;
8925
8926 /*
8927 * If PML is turned on, failure on enabling PML just results in failure
8928 * of creating the vcpu, therefore we can simplify PML logic (by
8929 * avoiding dealing with cases, such as enabling PML partially on vcpus
8930 * for the guest, etc.
8931 */
8932 if (enable_pml) {
8933 err = vmx_create_pml_buffer(vmx);
8934 if (err)
8935 goto free_vmcs;
8936 }
8937
8938 return &vmx->vcpu;
8939
8940 free_vmcs:
8941 free_vpid(vmx->nested.vpid02);
8942 free_loaded_vmcs(vmx->loaded_vmcs);
8943 free_msrs:
8944 kfree(vmx->guest_msrs);
8945 uninit_vcpu:
8946 kvm_vcpu_uninit(&vmx->vcpu);
8947 free_vcpu:
8948 free_vpid(vmx->vpid);
8949 kmem_cache_free(kvm_vcpu_cache, vmx);
8950 return ERR_PTR(err);
8951 }
8952
8953 static void __init vmx_check_processor_compat(void *rtn)
8954 {
8955 struct vmcs_config vmcs_conf;
8956
8957 *(int *)rtn = 0;
8958 if (setup_vmcs_config(&vmcs_conf) < 0)
8959 *(int *)rtn = -EIO;
8960 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8961 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8962 smp_processor_id());
8963 *(int *)rtn = -EIO;
8964 }
8965 }
8966
8967 static int get_ept_level(void)
8968 {
8969 return VMX_EPT_DEFAULT_GAW + 1;
8970 }
8971
8972 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8973 {
8974 u8 cache;
8975 u64 ipat = 0;
8976
8977 /* For VT-d and EPT combination
8978 * 1. MMIO: always map as UC
8979 * 2. EPT with VT-d:
8980 * a. VT-d without snooping control feature: can't guarantee the
8981 * result, try to trust guest.
8982 * b. VT-d with snooping control feature: snooping control feature of
8983 * VT-d engine can guarantee the cache correctness. Just set it
8984 * to WB to keep consistent with host. So the same as item 3.
8985 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8986 * consistent with host MTRR
8987 */
8988 if (is_mmio) {
8989 cache = MTRR_TYPE_UNCACHABLE;
8990 goto exit;
8991 }
8992
8993 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8994 ipat = VMX_EPT_IPAT_BIT;
8995 cache = MTRR_TYPE_WRBACK;
8996 goto exit;
8997 }
8998
8999 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9000 ipat = VMX_EPT_IPAT_BIT;
9001 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9002 cache = MTRR_TYPE_WRBACK;
9003 else
9004 cache = MTRR_TYPE_UNCACHABLE;
9005 goto exit;
9006 }
9007
9008 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9009
9010 exit:
9011 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9012 }
9013
9014 static int vmx_get_lpage_level(void)
9015 {
9016 if (enable_ept && !cpu_has_vmx_ept_1g_page())
9017 return PT_DIRECTORY_LEVEL;
9018 else
9019 /* For shadow and EPT supported 1GB page */
9020 return PT_PDPE_LEVEL;
9021 }
9022
9023 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9024 {
9025 /*
9026 * These bits in the secondary execution controls field
9027 * are dynamic, the others are mostly based on the hypervisor
9028 * architecture and the guest's CPUID. Do not touch the
9029 * dynamic bits.
9030 */
9031 u32 mask =
9032 SECONDARY_EXEC_SHADOW_VMCS |
9033 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9034 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9035
9036 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9037
9038 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9039 (new_ctl & ~mask) | (cur_ctl & mask));
9040 }
9041
9042 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9043 {
9044 struct kvm_cpuid_entry2 *best;
9045 struct vcpu_vmx *vmx = to_vmx(vcpu);
9046 u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9047
9048 if (vmx_rdtscp_supported()) {
9049 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9050 if (!rdtscp_enabled)
9051 secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9052
9053 if (nested) {
9054 if (rdtscp_enabled)
9055 vmx->nested.nested_vmx_secondary_ctls_high |=
9056 SECONDARY_EXEC_RDTSCP;
9057 else
9058 vmx->nested.nested_vmx_secondary_ctls_high &=
9059 ~SECONDARY_EXEC_RDTSCP;
9060 }
9061 }
9062
9063 /* Exposing INVPCID only when PCID is exposed */
9064 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9065 if (vmx_invpcid_supported() &&
9066 (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9067 !guest_cpuid_has_pcid(vcpu))) {
9068 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9069
9070 if (best)
9071 best->ebx &= ~bit(X86_FEATURE_INVPCID);
9072 }
9073
9074 if (cpu_has_secondary_exec_ctrls())
9075 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9076
9077 if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9078 if (guest_cpuid_has_pcommit(vcpu))
9079 vmx->nested.nested_vmx_secondary_ctls_high |=
9080 SECONDARY_EXEC_PCOMMIT;
9081 else
9082 vmx->nested.nested_vmx_secondary_ctls_high &=
9083 ~SECONDARY_EXEC_PCOMMIT;
9084 }
9085 }
9086
9087 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9088 {
9089 if (func == 1 && nested)
9090 entry->ecx |= bit(X86_FEATURE_VMX);
9091 }
9092
9093 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9094 struct x86_exception *fault)
9095 {
9096 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9097 u32 exit_reason;
9098
9099 if (fault->error_code & PFERR_RSVD_MASK)
9100 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9101 else
9102 exit_reason = EXIT_REASON_EPT_VIOLATION;
9103 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9104 vmcs12->guest_physical_address = fault->address;
9105 }
9106
9107 /* Callbacks for nested_ept_init_mmu_context: */
9108
9109 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9110 {
9111 /* return the page table to be shadowed - in our case, EPT12 */
9112 return get_vmcs12(vcpu)->ept_pointer;
9113 }
9114
9115 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9116 {
9117 WARN_ON(mmu_is_nested(vcpu));
9118 kvm_init_shadow_ept_mmu(vcpu,
9119 to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9120 VMX_EPT_EXECUTE_ONLY_BIT);
9121 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
9122 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
9123 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9124
9125 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
9126 }
9127
9128 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9129 {
9130 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9131 }
9132
9133 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9134 u16 error_code)
9135 {
9136 bool inequality, bit;
9137
9138 bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9139 inequality =
9140 (error_code & vmcs12->page_fault_error_code_mask) !=
9141 vmcs12->page_fault_error_code_match;
9142 return inequality ^ bit;
9143 }
9144
9145 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9146 struct x86_exception *fault)
9147 {
9148 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9149
9150 WARN_ON(!is_guest_mode(vcpu));
9151
9152 if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9153 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9154 vmcs_read32(VM_EXIT_INTR_INFO),
9155 vmcs_readl(EXIT_QUALIFICATION));
9156 else
9157 kvm_inject_page_fault(vcpu, fault);
9158 }
9159
9160 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9161 struct vmcs12 *vmcs12)
9162 {
9163 struct vcpu_vmx *vmx = to_vmx(vcpu);
9164 int maxphyaddr = cpuid_maxphyaddr(vcpu);
9165
9166 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9167 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9168 vmcs12->apic_access_addr >> maxphyaddr)
9169 return false;
9170
9171 /*
9172 * Translate L1 physical address to host physical
9173 * address for vmcs02. Keep the page pinned, so this
9174 * physical address remains valid. We keep a reference
9175 * to it so we can release it later.
9176 */
9177 if (vmx->nested.apic_access_page) /* shouldn't happen */
9178 nested_release_page(vmx->nested.apic_access_page);
9179 vmx->nested.apic_access_page =
9180 nested_get_page(vcpu, vmcs12->apic_access_addr);
9181 }
9182
9183 if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9184 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9185 vmcs12->virtual_apic_page_addr >> maxphyaddr)
9186 return false;
9187
9188 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9189 nested_release_page(vmx->nested.virtual_apic_page);
9190 vmx->nested.virtual_apic_page =
9191 nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9192
9193 /*
9194 * Failing the vm entry is _not_ what the processor does
9195 * but it's basically the only possibility we have.
9196 * We could still enter the guest if CR8 load exits are
9197 * enabled, CR8 store exits are enabled, and virtualize APIC
9198 * access is disabled; in this case the processor would never
9199 * use the TPR shadow and we could simply clear the bit from
9200 * the execution control. But such a configuration is useless,
9201 * so let's keep the code simple.
9202 */
9203 if (!vmx->nested.virtual_apic_page)
9204 return false;
9205 }
9206
9207 if (nested_cpu_has_posted_intr(vmcs12)) {
9208 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9209 vmcs12->posted_intr_desc_addr >> maxphyaddr)
9210 return false;
9211
9212 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9213 kunmap(vmx->nested.pi_desc_page);
9214 nested_release_page(vmx->nested.pi_desc_page);
9215 }
9216 vmx->nested.pi_desc_page =
9217 nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9218 if (!vmx->nested.pi_desc_page)
9219 return false;
9220
9221 vmx->nested.pi_desc =
9222 (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9223 if (!vmx->nested.pi_desc) {
9224 nested_release_page_clean(vmx->nested.pi_desc_page);
9225 return false;
9226 }
9227 vmx->nested.pi_desc =
9228 (struct pi_desc *)((void *)vmx->nested.pi_desc +
9229 (unsigned long)(vmcs12->posted_intr_desc_addr &
9230 (PAGE_SIZE - 1)));
9231 }
9232
9233 return true;
9234 }
9235
9236 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9237 {
9238 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9239 struct vcpu_vmx *vmx = to_vmx(vcpu);
9240
9241 if (vcpu->arch.virtual_tsc_khz == 0)
9242 return;
9243
9244 /* Make sure short timeouts reliably trigger an immediate vmexit.
9245 * hrtimer_start does not guarantee this. */
9246 if (preemption_timeout <= 1) {
9247 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9248 return;
9249 }
9250
9251 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9252 preemption_timeout *= 1000000;
9253 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9254 hrtimer_start(&vmx->nested.preemption_timer,
9255 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9256 }
9257
9258 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9259 struct vmcs12 *vmcs12)
9260 {
9261 int maxphyaddr;
9262 u64 addr;
9263
9264 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9265 return 0;
9266
9267 if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9268 WARN_ON(1);
9269 return -EINVAL;
9270 }
9271 maxphyaddr = cpuid_maxphyaddr(vcpu);
9272
9273 if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9274 ((addr + PAGE_SIZE) >> maxphyaddr))
9275 return -EINVAL;
9276
9277 return 0;
9278 }
9279
9280 /*
9281 * Merge L0's and L1's MSR bitmap, return false to indicate that
9282 * we do not use the hardware.
9283 */
9284 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9285 struct vmcs12 *vmcs12)
9286 {
9287 int msr;
9288 struct page *page;
9289 unsigned long *msr_bitmap;
9290
9291 if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9292 return false;
9293
9294 page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9295 if (!page) {
9296 WARN_ON(1);
9297 return false;
9298 }
9299 msr_bitmap = (unsigned long *)kmap(page);
9300 if (!msr_bitmap) {
9301 nested_release_page_clean(page);
9302 WARN_ON(1);
9303 return false;
9304 }
9305
9306 if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9307 if (nested_cpu_has_apic_reg_virt(vmcs12))
9308 for (msr = 0x800; msr <= 0x8ff; msr++)
9309 nested_vmx_disable_intercept_for_msr(
9310 msr_bitmap,
9311 vmx_msr_bitmap_nested,
9312 msr, MSR_TYPE_R);
9313 /* TPR is allowed */
9314 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9315 vmx_msr_bitmap_nested,
9316 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9317 MSR_TYPE_R | MSR_TYPE_W);
9318 if (nested_cpu_has_vid(vmcs12)) {
9319 /* EOI and self-IPI are allowed */
9320 nested_vmx_disable_intercept_for_msr(
9321 msr_bitmap,
9322 vmx_msr_bitmap_nested,
9323 APIC_BASE_MSR + (APIC_EOI >> 4),
9324 MSR_TYPE_W);
9325 nested_vmx_disable_intercept_for_msr(
9326 msr_bitmap,
9327 vmx_msr_bitmap_nested,
9328 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9329 MSR_TYPE_W);
9330 }
9331 } else {
9332 /*
9333 * Enable reading intercept of all the x2apic
9334 * MSRs. We should not rely on vmcs12 to do any
9335 * optimizations here, it may have been modified
9336 * by L1.
9337 */
9338 for (msr = 0x800; msr <= 0x8ff; msr++)
9339 __vmx_enable_intercept_for_msr(
9340 vmx_msr_bitmap_nested,
9341 msr,
9342 MSR_TYPE_R);
9343
9344 __vmx_enable_intercept_for_msr(
9345 vmx_msr_bitmap_nested,
9346 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9347 MSR_TYPE_W);
9348 __vmx_enable_intercept_for_msr(
9349 vmx_msr_bitmap_nested,
9350 APIC_BASE_MSR + (APIC_EOI >> 4),
9351 MSR_TYPE_W);
9352 __vmx_enable_intercept_for_msr(
9353 vmx_msr_bitmap_nested,
9354 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9355 MSR_TYPE_W);
9356 }
9357 kunmap(page);
9358 nested_release_page_clean(page);
9359
9360 return true;
9361 }
9362
9363 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9364 struct vmcs12 *vmcs12)
9365 {
9366 if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9367 !nested_cpu_has_apic_reg_virt(vmcs12) &&
9368 !nested_cpu_has_vid(vmcs12) &&
9369 !nested_cpu_has_posted_intr(vmcs12))
9370 return 0;
9371
9372 /*
9373 * If virtualize x2apic mode is enabled,
9374 * virtualize apic access must be disabled.
9375 */
9376 if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9377 nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9378 return -EINVAL;
9379
9380 /*
9381 * If virtual interrupt delivery is enabled,
9382 * we must exit on external interrupts.
9383 */
9384 if (nested_cpu_has_vid(vmcs12) &&
9385 !nested_exit_on_intr(vcpu))
9386 return -EINVAL;
9387
9388 /*
9389 * bits 15:8 should be zero in posted_intr_nv,
9390 * the descriptor address has been already checked
9391 * in nested_get_vmcs12_pages.
9392 */
9393 if (nested_cpu_has_posted_intr(vmcs12) &&
9394 (!nested_cpu_has_vid(vmcs12) ||
9395 !nested_exit_intr_ack_set(vcpu) ||
9396 vmcs12->posted_intr_nv & 0xff00))
9397 return -EINVAL;
9398
9399 /* tpr shadow is needed by all apicv features. */
9400 if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9401 return -EINVAL;
9402
9403 return 0;
9404 }
9405
9406 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9407 unsigned long count_field,
9408 unsigned long addr_field)
9409 {
9410 int maxphyaddr;
9411 u64 count, addr;
9412
9413 if (vmcs12_read_any(vcpu, count_field, &count) ||
9414 vmcs12_read_any(vcpu, addr_field, &addr)) {
9415 WARN_ON(1);
9416 return -EINVAL;
9417 }
9418 if (count == 0)
9419 return 0;
9420 maxphyaddr = cpuid_maxphyaddr(vcpu);
9421 if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9422 (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9423 pr_warn_ratelimited(
9424 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9425 addr_field, maxphyaddr, count, addr);
9426 return -EINVAL;
9427 }
9428 return 0;
9429 }
9430
9431 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9432 struct vmcs12 *vmcs12)
9433 {
9434 if (vmcs12->vm_exit_msr_load_count == 0 &&
9435 vmcs12->vm_exit_msr_store_count == 0 &&
9436 vmcs12->vm_entry_msr_load_count == 0)
9437 return 0; /* Fast path */
9438 if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9439 VM_EXIT_MSR_LOAD_ADDR) ||
9440 nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9441 VM_EXIT_MSR_STORE_ADDR) ||
9442 nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9443 VM_ENTRY_MSR_LOAD_ADDR))
9444 return -EINVAL;
9445 return 0;
9446 }
9447
9448 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9449 struct vmx_msr_entry *e)
9450 {
9451 /* x2APIC MSR accesses are not allowed */
9452 if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9453 return -EINVAL;
9454 if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9455 e->index == MSR_IA32_UCODE_REV)
9456 return -EINVAL;
9457 if (e->reserved != 0)
9458 return -EINVAL;
9459 return 0;
9460 }
9461
9462 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9463 struct vmx_msr_entry *e)
9464 {
9465 if (e->index == MSR_FS_BASE ||
9466 e->index == MSR_GS_BASE ||
9467 e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9468 nested_vmx_msr_check_common(vcpu, e))
9469 return -EINVAL;
9470 return 0;
9471 }
9472
9473 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9474 struct vmx_msr_entry *e)
9475 {
9476 if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9477 nested_vmx_msr_check_common(vcpu, e))
9478 return -EINVAL;
9479 return 0;
9480 }
9481
9482 /*
9483 * Load guest's/host's msr at nested entry/exit.
9484 * return 0 for success, entry index for failure.
9485 */
9486 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9487 {
9488 u32 i;
9489 struct vmx_msr_entry e;
9490 struct msr_data msr;
9491
9492 msr.host_initiated = false;
9493 for (i = 0; i < count; i++) {
9494 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9495 &e, sizeof(e))) {
9496 pr_warn_ratelimited(
9497 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9498 __func__, i, gpa + i * sizeof(e));
9499 goto fail;
9500 }
9501 if (nested_vmx_load_msr_check(vcpu, &e)) {
9502 pr_warn_ratelimited(
9503 "%s check failed (%u, 0x%x, 0x%x)\n",
9504 __func__, i, e.index, e.reserved);
9505 goto fail;
9506 }
9507 msr.index = e.index;
9508 msr.data = e.value;
9509 if (kvm_set_msr(vcpu, &msr)) {
9510 pr_warn_ratelimited(
9511 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9512 __func__, i, e.index, e.value);
9513 goto fail;
9514 }
9515 }
9516 return 0;
9517 fail:
9518 return i + 1;
9519 }
9520
9521 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9522 {
9523 u32 i;
9524 struct vmx_msr_entry e;
9525
9526 for (i = 0; i < count; i++) {
9527 struct msr_data msr_info;
9528 if (kvm_vcpu_read_guest(vcpu,
9529 gpa + i * sizeof(e),
9530 &e, 2 * sizeof(u32))) {
9531 pr_warn_ratelimited(
9532 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9533 __func__, i, gpa + i * sizeof(e));
9534 return -EINVAL;
9535 }
9536 if (nested_vmx_store_msr_check(vcpu, &e)) {
9537 pr_warn_ratelimited(
9538 "%s check failed (%u, 0x%x, 0x%x)\n",
9539 __func__, i, e.index, e.reserved);
9540 return -EINVAL;
9541 }
9542 msr_info.host_initiated = false;
9543 msr_info.index = e.index;
9544 if (kvm_get_msr(vcpu, &msr_info)) {
9545 pr_warn_ratelimited(
9546 "%s cannot read MSR (%u, 0x%x)\n",
9547 __func__, i, e.index);
9548 return -EINVAL;
9549 }
9550 if (kvm_vcpu_write_guest(vcpu,
9551 gpa + i * sizeof(e) +
9552 offsetof(struct vmx_msr_entry, value),
9553 &msr_info.data, sizeof(msr_info.data))) {
9554 pr_warn_ratelimited(
9555 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9556 __func__, i, e.index, msr_info.data);
9557 return -EINVAL;
9558 }
9559 }
9560 return 0;
9561 }
9562
9563 /*
9564 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9565 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9566 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9567 * guest in a way that will both be appropriate to L1's requests, and our
9568 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9569 * function also has additional necessary side-effects, like setting various
9570 * vcpu->arch fields.
9571 */
9572 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9573 {
9574 struct vcpu_vmx *vmx = to_vmx(vcpu);
9575 u32 exec_control;
9576
9577 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9578 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9579 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9580 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9581 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9582 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9583 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9584 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9585 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9586 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9587 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9588 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9589 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9590 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9591 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9592 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9593 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9594 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9595 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9596 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9597 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9598 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9599 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9600 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9601 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9602 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9603 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9604 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9605 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9606 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9607 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9608 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9609 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9610 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9611 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9612 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9613
9614 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9615 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9616 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9617 } else {
9618 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9619 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9620 }
9621 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9622 vmcs12->vm_entry_intr_info_field);
9623 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9624 vmcs12->vm_entry_exception_error_code);
9625 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9626 vmcs12->vm_entry_instruction_len);
9627 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9628 vmcs12->guest_interruptibility_info);
9629 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9630 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9631 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9632 vmcs12->guest_pending_dbg_exceptions);
9633 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9634 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9635
9636 if (nested_cpu_has_xsaves(vmcs12))
9637 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9638 vmcs_write64(VMCS_LINK_POINTER, -1ull);
9639
9640 exec_control = vmcs12->pin_based_vm_exec_control;
9641 exec_control |= vmcs_config.pin_based_exec_ctrl;
9642 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9643
9644 if (nested_cpu_has_posted_intr(vmcs12)) {
9645 /*
9646 * Note that we use L0's vector here and in
9647 * vmx_deliver_nested_posted_interrupt.
9648 */
9649 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9650 vmx->nested.pi_pending = false;
9651 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9652 vmcs_write64(POSTED_INTR_DESC_ADDR,
9653 page_to_phys(vmx->nested.pi_desc_page) +
9654 (unsigned long)(vmcs12->posted_intr_desc_addr &
9655 (PAGE_SIZE - 1)));
9656 } else
9657 exec_control &= ~PIN_BASED_POSTED_INTR;
9658
9659 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9660
9661 vmx->nested.preemption_timer_expired = false;
9662 if (nested_cpu_has_preemption_timer(vmcs12))
9663 vmx_start_preemption_timer(vcpu);
9664
9665 /*
9666 * Whether page-faults are trapped is determined by a combination of
9667 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9668 * If enable_ept, L0 doesn't care about page faults and we should
9669 * set all of these to L1's desires. However, if !enable_ept, L0 does
9670 * care about (at least some) page faults, and because it is not easy
9671 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9672 * to exit on each and every L2 page fault. This is done by setting
9673 * MASK=MATCH=0 and (see below) EB.PF=1.
9674 * Note that below we don't need special code to set EB.PF beyond the
9675 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9676 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9677 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9678 *
9679 * A problem with this approach (when !enable_ept) is that L1 may be
9680 * injected with more page faults than it asked for. This could have
9681 * caused problems, but in practice existing hypervisors don't care.
9682 * To fix this, we will need to emulate the PFEC checking (on the L1
9683 * page tables), using walk_addr(), when injecting PFs to L1.
9684 */
9685 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9686 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9687 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9688 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9689
9690 if (cpu_has_secondary_exec_ctrls()) {
9691 exec_control = vmx_secondary_exec_control(vmx);
9692
9693 /* Take the following fields only from vmcs12 */
9694 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9695 SECONDARY_EXEC_RDTSCP |
9696 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9697 SECONDARY_EXEC_APIC_REGISTER_VIRT |
9698 SECONDARY_EXEC_PCOMMIT);
9699 if (nested_cpu_has(vmcs12,
9700 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9701 exec_control |= vmcs12->secondary_vm_exec_control;
9702
9703 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9704 /*
9705 * If translation failed, no matter: This feature asks
9706 * to exit when accessing the given address, and if it
9707 * can never be accessed, this feature won't do
9708 * anything anyway.
9709 */
9710 if (!vmx->nested.apic_access_page)
9711 exec_control &=
9712 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9713 else
9714 vmcs_write64(APIC_ACCESS_ADDR,
9715 page_to_phys(vmx->nested.apic_access_page));
9716 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9717 cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9718 exec_control |=
9719 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9720 kvm_vcpu_reload_apic_access_page(vcpu);
9721 }
9722
9723 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9724 vmcs_write64(EOI_EXIT_BITMAP0,
9725 vmcs12->eoi_exit_bitmap0);
9726 vmcs_write64(EOI_EXIT_BITMAP1,
9727 vmcs12->eoi_exit_bitmap1);
9728 vmcs_write64(EOI_EXIT_BITMAP2,
9729 vmcs12->eoi_exit_bitmap2);
9730 vmcs_write64(EOI_EXIT_BITMAP3,
9731 vmcs12->eoi_exit_bitmap3);
9732 vmcs_write16(GUEST_INTR_STATUS,
9733 vmcs12->guest_intr_status);
9734 }
9735
9736 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9737 }
9738
9739
9740 /*
9741 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9742 * Some constant fields are set here by vmx_set_constant_host_state().
9743 * Other fields are different per CPU, and will be set later when
9744 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9745 */
9746 vmx_set_constant_host_state(vmx);
9747
9748 /*
9749 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9750 * entry, but only if the current (host) sp changed from the value
9751 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9752 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9753 * here we just force the write to happen on entry.
9754 */
9755 vmx->host_rsp = 0;
9756
9757 exec_control = vmx_exec_control(vmx); /* L0's desires */
9758 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9759 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9760 exec_control &= ~CPU_BASED_TPR_SHADOW;
9761 exec_control |= vmcs12->cpu_based_vm_exec_control;
9762
9763 if (exec_control & CPU_BASED_TPR_SHADOW) {
9764 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9765 page_to_phys(vmx->nested.virtual_apic_page));
9766 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9767 }
9768
9769 if (cpu_has_vmx_msr_bitmap() &&
9770 exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9771 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9772 /* MSR_BITMAP will be set by following vmx_set_efer. */
9773 } else
9774 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9775
9776 /*
9777 * Merging of IO bitmap not currently supported.
9778 * Rather, exit every time.
9779 */
9780 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9781 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9782
9783 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9784
9785 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9786 * bitwise-or of what L1 wants to trap for L2, and what we want to
9787 * trap. Note that CR0.TS also needs updating - we do this later.
9788 */
9789 update_exception_bitmap(vcpu);
9790 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9791 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9792
9793 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9794 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9795 * bits are further modified by vmx_set_efer() below.
9796 */
9797 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9798
9799 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9800 * emulated by vmx_set_efer(), below.
9801 */
9802 vm_entry_controls_init(vmx,
9803 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9804 ~VM_ENTRY_IA32E_MODE) |
9805 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9806
9807 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9808 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9809 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9810 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9811 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9812
9813
9814 set_cr4_guest_host_mask(vmx);
9815
9816 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9817 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9818
9819 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9820 vmcs_write64(TSC_OFFSET,
9821 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9822 else
9823 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9824
9825 if (enable_vpid) {
9826 /*
9827 * There is no direct mapping between vpid02 and vpid12, the
9828 * vpid02 is per-vCPU for L0 and reused while the value of
9829 * vpid12 is changed w/ one invvpid during nested vmentry.
9830 * The vpid12 is allocated by L1 for L2, so it will not
9831 * influence global bitmap(for vpid01 and vpid02 allocation)
9832 * even if spawn a lot of nested vCPUs.
9833 */
9834 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9835 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9836 if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9837 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9838 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9839 }
9840 } else {
9841 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9842 vmx_flush_tlb(vcpu);
9843 }
9844
9845 }
9846
9847 if (nested_cpu_has_ept(vmcs12)) {
9848 kvm_mmu_unload(vcpu);
9849 nested_ept_init_mmu_context(vcpu);
9850 }
9851
9852 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9853 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9854 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9855 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9856 else
9857 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9858 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9859 vmx_set_efer(vcpu, vcpu->arch.efer);
9860
9861 /*
9862 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9863 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9864 * The CR0_READ_SHADOW is what L2 should have expected to read given
9865 * the specifications by L1; It's not enough to take
9866 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9867 * have more bits than L1 expected.
9868 */
9869 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9870 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9871
9872 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9873 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9874
9875 /* shadow page tables on either EPT or shadow page tables */
9876 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9877 kvm_mmu_reset_context(vcpu);
9878
9879 if (!enable_ept)
9880 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9881
9882 /*
9883 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9884 */
9885 if (enable_ept) {
9886 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9887 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9888 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9889 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9890 }
9891
9892 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9893 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9894 }
9895
9896 /*
9897 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9898 * for running an L2 nested guest.
9899 */
9900 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9901 {
9902 struct vmcs12 *vmcs12;
9903 struct vcpu_vmx *vmx = to_vmx(vcpu);
9904 int cpu;
9905 struct loaded_vmcs *vmcs02;
9906 bool ia32e;
9907 u32 msr_entry_idx;
9908
9909 if (!nested_vmx_check_permission(vcpu) ||
9910 !nested_vmx_check_vmcs12(vcpu))
9911 return 1;
9912
9913 skip_emulated_instruction(vcpu);
9914 vmcs12 = get_vmcs12(vcpu);
9915
9916 if (enable_shadow_vmcs)
9917 copy_shadow_to_vmcs12(vmx);
9918
9919 /*
9920 * The nested entry process starts with enforcing various prerequisites
9921 * on vmcs12 as required by the Intel SDM, and act appropriately when
9922 * they fail: As the SDM explains, some conditions should cause the
9923 * instruction to fail, while others will cause the instruction to seem
9924 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9925 * To speed up the normal (success) code path, we should avoid checking
9926 * for misconfigurations which will anyway be caught by the processor
9927 * when using the merged vmcs02.
9928 */
9929 if (vmcs12->launch_state == launch) {
9930 nested_vmx_failValid(vcpu,
9931 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9932 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9933 return 1;
9934 }
9935
9936 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9937 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9938 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9939 return 1;
9940 }
9941
9942 if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9943 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9944 return 1;
9945 }
9946
9947 if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9948 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9949 return 1;
9950 }
9951
9952 if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9953 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9954 return 1;
9955 }
9956
9957 if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9958 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9959 return 1;
9960 }
9961
9962 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9963 vmx->nested.nested_vmx_true_procbased_ctls_low,
9964 vmx->nested.nested_vmx_procbased_ctls_high) ||
9965 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9966 vmx->nested.nested_vmx_secondary_ctls_low,
9967 vmx->nested.nested_vmx_secondary_ctls_high) ||
9968 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9969 vmx->nested.nested_vmx_pinbased_ctls_low,
9970 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9971 !vmx_control_verify(vmcs12->vm_exit_controls,
9972 vmx->nested.nested_vmx_true_exit_ctls_low,
9973 vmx->nested.nested_vmx_exit_ctls_high) ||
9974 !vmx_control_verify(vmcs12->vm_entry_controls,
9975 vmx->nested.nested_vmx_true_entry_ctls_low,
9976 vmx->nested.nested_vmx_entry_ctls_high))
9977 {
9978 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9979 return 1;
9980 }
9981
9982 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9983 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9984 nested_vmx_failValid(vcpu,
9985 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9986 return 1;
9987 }
9988
9989 if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9990 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9991 nested_vmx_entry_failure(vcpu, vmcs12,
9992 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9993 return 1;
9994 }
9995 if (vmcs12->vmcs_link_pointer != -1ull) {
9996 nested_vmx_entry_failure(vcpu, vmcs12,
9997 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9998 return 1;
9999 }
10000
10001 /*
10002 * If the load IA32_EFER VM-entry control is 1, the following checks
10003 * are performed on the field for the IA32_EFER MSR:
10004 * - Bits reserved in the IA32_EFER MSR must be 0.
10005 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10006 * the IA-32e mode guest VM-exit control. It must also be identical
10007 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10008 * CR0.PG) is 1.
10009 */
10010 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10011 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10012 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10013 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10014 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10015 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10016 nested_vmx_entry_failure(vcpu, vmcs12,
10017 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10018 return 1;
10019 }
10020 }
10021
10022 /*
10023 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10024 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10025 * the values of the LMA and LME bits in the field must each be that of
10026 * the host address-space size VM-exit control.
10027 */
10028 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10029 ia32e = (vmcs12->vm_exit_controls &
10030 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10031 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10032 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10033 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10034 nested_vmx_entry_failure(vcpu, vmcs12,
10035 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10036 return 1;
10037 }
10038 }
10039
10040 /*
10041 * We're finally done with prerequisite checking, and can start with
10042 * the nested entry.
10043 */
10044
10045 vmcs02 = nested_get_current_vmcs02(vmx);
10046 if (!vmcs02)
10047 return -ENOMEM;
10048
10049 enter_guest_mode(vcpu);
10050
10051 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10052
10053 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10054 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10055
10056 cpu = get_cpu();
10057 vmx->loaded_vmcs = vmcs02;
10058 vmx_vcpu_put(vcpu);
10059 vmx_vcpu_load(vcpu, cpu);
10060 vcpu->cpu = cpu;
10061 put_cpu();
10062
10063 vmx_segment_cache_clear(vmx);
10064
10065 prepare_vmcs02(vcpu, vmcs12);
10066
10067 msr_entry_idx = nested_vmx_load_msr(vcpu,
10068 vmcs12->vm_entry_msr_load_addr,
10069 vmcs12->vm_entry_msr_load_count);
10070 if (msr_entry_idx) {
10071 leave_guest_mode(vcpu);
10072 vmx_load_vmcs01(vcpu);
10073 nested_vmx_entry_failure(vcpu, vmcs12,
10074 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10075 return 1;
10076 }
10077
10078 vmcs12->launch_state = 1;
10079
10080 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10081 return kvm_vcpu_halt(vcpu);
10082
10083 vmx->nested.nested_run_pending = 1;
10084
10085 /*
10086 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10087 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10088 * returned as far as L1 is concerned. It will only return (and set
10089 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10090 */
10091 return 1;
10092 }
10093
10094 /*
10095 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10096 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10097 * This function returns the new value we should put in vmcs12.guest_cr0.
10098 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10099 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10100 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10101 * didn't trap the bit, because if L1 did, so would L0).
10102 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10103 * been modified by L2, and L1 knows it. So just leave the old value of
10104 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10105 * isn't relevant, because if L0 traps this bit it can set it to anything.
10106 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10107 * changed these bits, and therefore they need to be updated, but L0
10108 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10109 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10110 */
10111 static inline unsigned long
10112 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10113 {
10114 return
10115 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10116 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10117 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10118 vcpu->arch.cr0_guest_owned_bits));
10119 }
10120
10121 static inline unsigned long
10122 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10123 {
10124 return
10125 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10126 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10127 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10128 vcpu->arch.cr4_guest_owned_bits));
10129 }
10130
10131 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10132 struct vmcs12 *vmcs12)
10133 {
10134 u32 idt_vectoring;
10135 unsigned int nr;
10136
10137 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10138 nr = vcpu->arch.exception.nr;
10139 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10140
10141 if (kvm_exception_is_soft(nr)) {
10142 vmcs12->vm_exit_instruction_len =
10143 vcpu->arch.event_exit_inst_len;
10144 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10145 } else
10146 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10147
10148 if (vcpu->arch.exception.has_error_code) {
10149 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10150 vmcs12->idt_vectoring_error_code =
10151 vcpu->arch.exception.error_code;
10152 }
10153
10154 vmcs12->idt_vectoring_info_field = idt_vectoring;
10155 } else if (vcpu->arch.nmi_injected) {
10156 vmcs12->idt_vectoring_info_field =
10157 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10158 } else if (vcpu->arch.interrupt.pending) {
10159 nr = vcpu->arch.interrupt.nr;
10160 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10161
10162 if (vcpu->arch.interrupt.soft) {
10163 idt_vectoring |= INTR_TYPE_SOFT_INTR;
10164 vmcs12->vm_entry_instruction_len =
10165 vcpu->arch.event_exit_inst_len;
10166 } else
10167 idt_vectoring |= INTR_TYPE_EXT_INTR;
10168
10169 vmcs12->idt_vectoring_info_field = idt_vectoring;
10170 }
10171 }
10172
10173 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10174 {
10175 struct vcpu_vmx *vmx = to_vmx(vcpu);
10176
10177 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10178 vmx->nested.preemption_timer_expired) {
10179 if (vmx->nested.nested_run_pending)
10180 return -EBUSY;
10181 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10182 return 0;
10183 }
10184
10185 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10186 if (vmx->nested.nested_run_pending ||
10187 vcpu->arch.interrupt.pending)
10188 return -EBUSY;
10189 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10190 NMI_VECTOR | INTR_TYPE_NMI_INTR |
10191 INTR_INFO_VALID_MASK, 0);
10192 /*
10193 * The NMI-triggered VM exit counts as injection:
10194 * clear this one and block further NMIs.
10195 */
10196 vcpu->arch.nmi_pending = 0;
10197 vmx_set_nmi_mask(vcpu, true);
10198 return 0;
10199 }
10200
10201 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10202 nested_exit_on_intr(vcpu)) {
10203 if (vmx->nested.nested_run_pending)
10204 return -EBUSY;
10205 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10206 return 0;
10207 }
10208
10209 return vmx_complete_nested_posted_interrupt(vcpu);
10210 }
10211
10212 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10213 {
10214 ktime_t remaining =
10215 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10216 u64 value;
10217
10218 if (ktime_to_ns(remaining) <= 0)
10219 return 0;
10220
10221 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10222 do_div(value, 1000000);
10223 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10224 }
10225
10226 /*
10227 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10228 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10229 * and this function updates it to reflect the changes to the guest state while
10230 * L2 was running (and perhaps made some exits which were handled directly by L0
10231 * without going back to L1), and to reflect the exit reason.
10232 * Note that we do not have to copy here all VMCS fields, just those that
10233 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10234 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10235 * which already writes to vmcs12 directly.
10236 */
10237 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10238 u32 exit_reason, u32 exit_intr_info,
10239 unsigned long exit_qualification)
10240 {
10241 /* update guest state fields: */
10242 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10243 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10244
10245 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10246 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10247 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10248
10249 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10250 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10251 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10252 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10253 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10254 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10255 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10256 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10257 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10258 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10259 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10260 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10261 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10262 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10263 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10264 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10265 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10266 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10267 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10268 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10269 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10270 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10271 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10272 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10273 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10274 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10275 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10276 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10277 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10278 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10279 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10280 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10281 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10282 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10283 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10284 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10285
10286 vmcs12->guest_interruptibility_info =
10287 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10288 vmcs12->guest_pending_dbg_exceptions =
10289 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10290 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10291 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10292 else
10293 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10294
10295 if (nested_cpu_has_preemption_timer(vmcs12)) {
10296 if (vmcs12->vm_exit_controls &
10297 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10298 vmcs12->vmx_preemption_timer_value =
10299 vmx_get_preemption_timer_value(vcpu);
10300 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10301 }
10302
10303 /*
10304 * In some cases (usually, nested EPT), L2 is allowed to change its
10305 * own CR3 without exiting. If it has changed it, we must keep it.
10306 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10307 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10308 *
10309 * Additionally, restore L2's PDPTR to vmcs12.
10310 */
10311 if (enable_ept) {
10312 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10313 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10314 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10315 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10316 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10317 }
10318
10319 if (nested_cpu_has_vid(vmcs12))
10320 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10321
10322 vmcs12->vm_entry_controls =
10323 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10324 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10325
10326 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10327 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10328 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10329 }
10330
10331 /* TODO: These cannot have changed unless we have MSR bitmaps and
10332 * the relevant bit asks not to trap the change */
10333 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10334 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10335 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10336 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10337 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10338 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10339 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10340 if (kvm_mpx_supported())
10341 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10342 if (nested_cpu_has_xsaves(vmcs12))
10343 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10344
10345 /* update exit information fields: */
10346
10347 vmcs12->vm_exit_reason = exit_reason;
10348 vmcs12->exit_qualification = exit_qualification;
10349
10350 vmcs12->vm_exit_intr_info = exit_intr_info;
10351 if ((vmcs12->vm_exit_intr_info &
10352 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10353 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10354 vmcs12->vm_exit_intr_error_code =
10355 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10356 vmcs12->idt_vectoring_info_field = 0;
10357 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10358 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10359
10360 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10361 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10362 * instead of reading the real value. */
10363 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10364
10365 /*
10366 * Transfer the event that L0 or L1 may wanted to inject into
10367 * L2 to IDT_VECTORING_INFO_FIELD.
10368 */
10369 vmcs12_save_pending_event(vcpu, vmcs12);
10370 }
10371
10372 /*
10373 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10374 * preserved above and would only end up incorrectly in L1.
10375 */
10376 vcpu->arch.nmi_injected = false;
10377 kvm_clear_exception_queue(vcpu);
10378 kvm_clear_interrupt_queue(vcpu);
10379 }
10380
10381 /*
10382 * A part of what we need to when the nested L2 guest exits and we want to
10383 * run its L1 parent, is to reset L1's guest state to the host state specified
10384 * in vmcs12.
10385 * This function is to be called not only on normal nested exit, but also on
10386 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10387 * Failures During or After Loading Guest State").
10388 * This function should be called when the active VMCS is L1's (vmcs01).
10389 */
10390 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10391 struct vmcs12 *vmcs12)
10392 {
10393 struct kvm_segment seg;
10394
10395 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10396 vcpu->arch.efer = vmcs12->host_ia32_efer;
10397 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10398 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10399 else
10400 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10401 vmx_set_efer(vcpu, vcpu->arch.efer);
10402
10403 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10404 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10405 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10406 /*
10407 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10408 * actually changed, because it depends on the current state of
10409 * fpu_active (which may have changed).
10410 * Note that vmx_set_cr0 refers to efer set above.
10411 */
10412 vmx_set_cr0(vcpu, vmcs12->host_cr0);
10413 /*
10414 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10415 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10416 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10417 */
10418 update_exception_bitmap(vcpu);
10419 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10420 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10421
10422 /*
10423 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10424 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10425 */
10426 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10427 kvm_set_cr4(vcpu, vmcs12->host_cr4);
10428
10429 nested_ept_uninit_mmu_context(vcpu);
10430
10431 kvm_set_cr3(vcpu, vmcs12->host_cr3);
10432 kvm_mmu_reset_context(vcpu);
10433
10434 if (!enable_ept)
10435 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10436
10437 if (enable_vpid) {
10438 /*
10439 * Trivially support vpid by letting L2s share their parent
10440 * L1's vpid. TODO: move to a more elaborate solution, giving
10441 * each L2 its own vpid and exposing the vpid feature to L1.
10442 */
10443 vmx_flush_tlb(vcpu);
10444 }
10445
10446
10447 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10448 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10449 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10450 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10451 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10452
10453 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10454 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10455 vmcs_write64(GUEST_BNDCFGS, 0);
10456
10457 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10458 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10459 vcpu->arch.pat = vmcs12->host_ia32_pat;
10460 }
10461 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10462 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10463 vmcs12->host_ia32_perf_global_ctrl);
10464
10465 /* Set L1 segment info according to Intel SDM
10466 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10467 seg = (struct kvm_segment) {
10468 .base = 0,
10469 .limit = 0xFFFFFFFF,
10470 .selector = vmcs12->host_cs_selector,
10471 .type = 11,
10472 .present = 1,
10473 .s = 1,
10474 .g = 1
10475 };
10476 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10477 seg.l = 1;
10478 else
10479 seg.db = 1;
10480 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10481 seg = (struct kvm_segment) {
10482 .base = 0,
10483 .limit = 0xFFFFFFFF,
10484 .type = 3,
10485 .present = 1,
10486 .s = 1,
10487 .db = 1,
10488 .g = 1
10489 };
10490 seg.selector = vmcs12->host_ds_selector;
10491 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10492 seg.selector = vmcs12->host_es_selector;
10493 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10494 seg.selector = vmcs12->host_ss_selector;
10495 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10496 seg.selector = vmcs12->host_fs_selector;
10497 seg.base = vmcs12->host_fs_base;
10498 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10499 seg.selector = vmcs12->host_gs_selector;
10500 seg.base = vmcs12->host_gs_base;
10501 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10502 seg = (struct kvm_segment) {
10503 .base = vmcs12->host_tr_base,
10504 .limit = 0x67,
10505 .selector = vmcs12->host_tr_selector,
10506 .type = 11,
10507 .present = 1
10508 };
10509 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10510
10511 kvm_set_dr(vcpu, 7, 0x400);
10512 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10513
10514 if (cpu_has_vmx_msr_bitmap())
10515 vmx_set_msr_bitmap(vcpu);
10516
10517 if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10518 vmcs12->vm_exit_msr_load_count))
10519 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10520 }
10521
10522 /*
10523 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10524 * and modify vmcs12 to make it see what it would expect to see there if
10525 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10526 */
10527 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10528 u32 exit_intr_info,
10529 unsigned long exit_qualification)
10530 {
10531 struct vcpu_vmx *vmx = to_vmx(vcpu);
10532 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10533
10534 /* trying to cancel vmlaunch/vmresume is a bug */
10535 WARN_ON_ONCE(vmx->nested.nested_run_pending);
10536
10537 leave_guest_mode(vcpu);
10538 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10539 exit_qualification);
10540
10541 if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10542 vmcs12->vm_exit_msr_store_count))
10543 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10544
10545 vmx_load_vmcs01(vcpu);
10546
10547 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10548 && nested_exit_intr_ack_set(vcpu)) {
10549 int irq = kvm_cpu_get_interrupt(vcpu);
10550 WARN_ON(irq < 0);
10551 vmcs12->vm_exit_intr_info = irq |
10552 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10553 }
10554
10555 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10556 vmcs12->exit_qualification,
10557 vmcs12->idt_vectoring_info_field,
10558 vmcs12->vm_exit_intr_info,
10559 vmcs12->vm_exit_intr_error_code,
10560 KVM_ISA_VMX);
10561
10562 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10563 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10564 vmx_segment_cache_clear(vmx);
10565
10566 /* if no vmcs02 cache requested, remove the one we used */
10567 if (VMCS02_POOL_SIZE == 0)
10568 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10569
10570 load_vmcs12_host_state(vcpu, vmcs12);
10571
10572 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10573 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10574
10575 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10576 vmx->host_rsp = 0;
10577
10578 /* Unpin physical memory we referred to in vmcs02 */
10579 if (vmx->nested.apic_access_page) {
10580 nested_release_page(vmx->nested.apic_access_page);
10581 vmx->nested.apic_access_page = NULL;
10582 }
10583 if (vmx->nested.virtual_apic_page) {
10584 nested_release_page(vmx->nested.virtual_apic_page);
10585 vmx->nested.virtual_apic_page = NULL;
10586 }
10587 if (vmx->nested.pi_desc_page) {
10588 kunmap(vmx->nested.pi_desc_page);
10589 nested_release_page(vmx->nested.pi_desc_page);
10590 vmx->nested.pi_desc_page = NULL;
10591 vmx->nested.pi_desc = NULL;
10592 }
10593
10594 /*
10595 * We are now running in L2, mmu_notifier will force to reload the
10596 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10597 */
10598 kvm_vcpu_reload_apic_access_page(vcpu);
10599
10600 /*
10601 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10602 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10603 * success or failure flag accordingly.
10604 */
10605 if (unlikely(vmx->fail)) {
10606 vmx->fail = 0;
10607 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10608 } else
10609 nested_vmx_succeed(vcpu);
10610 if (enable_shadow_vmcs)
10611 vmx->nested.sync_shadow_vmcs = true;
10612
10613 /* in case we halted in L2 */
10614 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10615 }
10616
10617 /*
10618 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10619 */
10620 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10621 {
10622 if (is_guest_mode(vcpu))
10623 nested_vmx_vmexit(vcpu, -1, 0, 0);
10624 free_nested(to_vmx(vcpu));
10625 }
10626
10627 /*
10628 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10629 * 23.7 "VM-entry failures during or after loading guest state" (this also
10630 * lists the acceptable exit-reason and exit-qualification parameters).
10631 * It should only be called before L2 actually succeeded to run, and when
10632 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10633 */
10634 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10635 struct vmcs12 *vmcs12,
10636 u32 reason, unsigned long qualification)
10637 {
10638 load_vmcs12_host_state(vcpu, vmcs12);
10639 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10640 vmcs12->exit_qualification = qualification;
10641 nested_vmx_succeed(vcpu);
10642 if (enable_shadow_vmcs)
10643 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10644 }
10645
10646 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10647 struct x86_instruction_info *info,
10648 enum x86_intercept_stage stage)
10649 {
10650 return X86EMUL_CONTINUE;
10651 }
10652
10653 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10654 {
10655 if (ple_gap)
10656 shrink_ple_window(vcpu);
10657 }
10658
10659 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10660 struct kvm_memory_slot *slot)
10661 {
10662 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10663 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10664 }
10665
10666 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10667 struct kvm_memory_slot *slot)
10668 {
10669 kvm_mmu_slot_set_dirty(kvm, slot);
10670 }
10671
10672 static void vmx_flush_log_dirty(struct kvm *kvm)
10673 {
10674 kvm_flush_pml_buffers(kvm);
10675 }
10676
10677 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10678 struct kvm_memory_slot *memslot,
10679 gfn_t offset, unsigned long mask)
10680 {
10681 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10682 }
10683
10684 /*
10685 * This routine does the following things for vCPU which is going
10686 * to be blocked if VT-d PI is enabled.
10687 * - Store the vCPU to the wakeup list, so when interrupts happen
10688 * we can find the right vCPU to wake up.
10689 * - Change the Posted-interrupt descriptor as below:
10690 * 'NDST' <-- vcpu->pre_pcpu
10691 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10692 * - If 'ON' is set during this process, which means at least one
10693 * interrupt is posted for this vCPU, we cannot block it, in
10694 * this case, return 1, otherwise, return 0.
10695 *
10696 */
10697 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10698 {
10699 unsigned long flags;
10700 unsigned int dest;
10701 struct pi_desc old, new;
10702 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10703
10704 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10705 !irq_remapping_cap(IRQ_POSTING_CAP))
10706 return 0;
10707
10708 vcpu->pre_pcpu = vcpu->cpu;
10709 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10710 vcpu->pre_pcpu), flags);
10711 list_add_tail(&vcpu->blocked_vcpu_list,
10712 &per_cpu(blocked_vcpu_on_cpu,
10713 vcpu->pre_pcpu));
10714 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10715 vcpu->pre_pcpu), flags);
10716
10717 do {
10718 old.control = new.control = pi_desc->control;
10719
10720 /*
10721 * We should not block the vCPU if
10722 * an interrupt is posted for it.
10723 */
10724 if (pi_test_on(pi_desc) == 1) {
10725 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10726 vcpu->pre_pcpu), flags);
10727 list_del(&vcpu->blocked_vcpu_list);
10728 spin_unlock_irqrestore(
10729 &per_cpu(blocked_vcpu_on_cpu_lock,
10730 vcpu->pre_pcpu), flags);
10731 vcpu->pre_pcpu = -1;
10732
10733 return 1;
10734 }
10735
10736 WARN((pi_desc->sn == 1),
10737 "Warning: SN field of posted-interrupts "
10738 "is set before blocking\n");
10739
10740 /*
10741 * Since vCPU can be preempted during this process,
10742 * vcpu->cpu could be different with pre_pcpu, we
10743 * need to set pre_pcpu as the destination of wakeup
10744 * notification event, then we can find the right vCPU
10745 * to wakeup in wakeup handler if interrupts happen
10746 * when the vCPU is in blocked state.
10747 */
10748 dest = cpu_physical_id(vcpu->pre_pcpu);
10749
10750 if (x2apic_enabled())
10751 new.ndst = dest;
10752 else
10753 new.ndst = (dest << 8) & 0xFF00;
10754
10755 /* set 'NV' to 'wakeup vector' */
10756 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10757 } while (cmpxchg(&pi_desc->control, old.control,
10758 new.control) != old.control);
10759
10760 return 0;
10761 }
10762
10763 static void vmx_post_block(struct kvm_vcpu *vcpu)
10764 {
10765 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10766 struct pi_desc old, new;
10767 unsigned int dest;
10768 unsigned long flags;
10769
10770 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10771 !irq_remapping_cap(IRQ_POSTING_CAP))
10772 return;
10773
10774 do {
10775 old.control = new.control = pi_desc->control;
10776
10777 dest = cpu_physical_id(vcpu->cpu);
10778
10779 if (x2apic_enabled())
10780 new.ndst = dest;
10781 else
10782 new.ndst = (dest << 8) & 0xFF00;
10783
10784 /* Allow posting non-urgent interrupts */
10785 new.sn = 0;
10786
10787 /* set 'NV' to 'notification vector' */
10788 new.nv = POSTED_INTR_VECTOR;
10789 } while (cmpxchg(&pi_desc->control, old.control,
10790 new.control) != old.control);
10791
10792 if(vcpu->pre_pcpu != -1) {
10793 spin_lock_irqsave(
10794 &per_cpu(blocked_vcpu_on_cpu_lock,
10795 vcpu->pre_pcpu), flags);
10796 list_del(&vcpu->blocked_vcpu_list);
10797 spin_unlock_irqrestore(
10798 &per_cpu(blocked_vcpu_on_cpu_lock,
10799 vcpu->pre_pcpu), flags);
10800 vcpu->pre_pcpu = -1;
10801 }
10802 }
10803
10804 /*
10805 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10806 *
10807 * @kvm: kvm
10808 * @host_irq: host irq of the interrupt
10809 * @guest_irq: gsi of the interrupt
10810 * @set: set or unset PI
10811 * returns 0 on success, < 0 on failure
10812 */
10813 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10814 uint32_t guest_irq, bool set)
10815 {
10816 struct kvm_kernel_irq_routing_entry *e;
10817 struct kvm_irq_routing_table *irq_rt;
10818 struct kvm_lapic_irq irq;
10819 struct kvm_vcpu *vcpu;
10820 struct vcpu_data vcpu_info;
10821 int idx, ret = -EINVAL;
10822
10823 if (!kvm_arch_has_assigned_device(kvm) ||
10824 !irq_remapping_cap(IRQ_POSTING_CAP))
10825 return 0;
10826
10827 idx = srcu_read_lock(&kvm->irq_srcu);
10828 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10829 BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10830
10831 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10832 if (e->type != KVM_IRQ_ROUTING_MSI)
10833 continue;
10834 /*
10835 * VT-d PI cannot support posting multicast/broadcast
10836 * interrupts to a vCPU, we still use interrupt remapping
10837 * for these kind of interrupts.
10838 *
10839 * For lowest-priority interrupts, we only support
10840 * those with single CPU as the destination, e.g. user
10841 * configures the interrupts via /proc/irq or uses
10842 * irqbalance to make the interrupts single-CPU.
10843 *
10844 * We will support full lowest-priority interrupt later.
10845 */
10846
10847 kvm_set_msi_irq(e, &irq);
10848 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10849 /*
10850 * Make sure the IRTE is in remapped mode if
10851 * we don't handle it in posted mode.
10852 */
10853 ret = irq_set_vcpu_affinity(host_irq, NULL);
10854 if (ret < 0) {
10855 printk(KERN_INFO
10856 "failed to back to remapped mode, irq: %u\n",
10857 host_irq);
10858 goto out;
10859 }
10860
10861 continue;
10862 }
10863
10864 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10865 vcpu_info.vector = irq.vector;
10866
10867 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10868 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10869
10870 if (set)
10871 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10872 else {
10873 /* suppress notification event before unposting */
10874 pi_set_sn(vcpu_to_pi_desc(vcpu));
10875 ret = irq_set_vcpu_affinity(host_irq, NULL);
10876 pi_clear_sn(vcpu_to_pi_desc(vcpu));
10877 }
10878
10879 if (ret < 0) {
10880 printk(KERN_INFO "%s: failed to update PI IRTE\n",
10881 __func__);
10882 goto out;
10883 }
10884 }
10885
10886 ret = 0;
10887 out:
10888 srcu_read_unlock(&kvm->irq_srcu, idx);
10889 return ret;
10890 }
10891
10892 static struct kvm_x86_ops vmx_x86_ops = {
10893 .cpu_has_kvm_support = cpu_has_kvm_support,
10894 .disabled_by_bios = vmx_disabled_by_bios,
10895 .hardware_setup = hardware_setup,
10896 .hardware_unsetup = hardware_unsetup,
10897 .check_processor_compatibility = vmx_check_processor_compat,
10898 .hardware_enable = hardware_enable,
10899 .hardware_disable = hardware_disable,
10900 .cpu_has_accelerated_tpr = report_flexpriority,
10901 .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10902
10903 .vcpu_create = vmx_create_vcpu,
10904 .vcpu_free = vmx_free_vcpu,
10905 .vcpu_reset = vmx_vcpu_reset,
10906
10907 .prepare_guest_switch = vmx_save_host_state,
10908 .vcpu_load = vmx_vcpu_load,
10909 .vcpu_put = vmx_vcpu_put,
10910
10911 .update_bp_intercept = update_exception_bitmap,
10912 .get_msr = vmx_get_msr,
10913 .set_msr = vmx_set_msr,
10914 .get_segment_base = vmx_get_segment_base,
10915 .get_segment = vmx_get_segment,
10916 .set_segment = vmx_set_segment,
10917 .get_cpl = vmx_get_cpl,
10918 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10919 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10920 .decache_cr3 = vmx_decache_cr3,
10921 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10922 .set_cr0 = vmx_set_cr0,
10923 .set_cr3 = vmx_set_cr3,
10924 .set_cr4 = vmx_set_cr4,
10925 .set_efer = vmx_set_efer,
10926 .get_idt = vmx_get_idt,
10927 .set_idt = vmx_set_idt,
10928 .get_gdt = vmx_get_gdt,
10929 .set_gdt = vmx_set_gdt,
10930 .get_dr6 = vmx_get_dr6,
10931 .set_dr6 = vmx_set_dr6,
10932 .set_dr7 = vmx_set_dr7,
10933 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10934 .cache_reg = vmx_cache_reg,
10935 .get_rflags = vmx_get_rflags,
10936 .set_rflags = vmx_set_rflags,
10937
10938 .get_pkru = vmx_get_pkru,
10939
10940 .fpu_activate = vmx_fpu_activate,
10941 .fpu_deactivate = vmx_fpu_deactivate,
10942
10943 .tlb_flush = vmx_flush_tlb,
10944
10945 .run = vmx_vcpu_run,
10946 .handle_exit = vmx_handle_exit,
10947 .skip_emulated_instruction = skip_emulated_instruction,
10948 .set_interrupt_shadow = vmx_set_interrupt_shadow,
10949 .get_interrupt_shadow = vmx_get_interrupt_shadow,
10950 .patch_hypercall = vmx_patch_hypercall,
10951 .set_irq = vmx_inject_irq,
10952 .set_nmi = vmx_inject_nmi,
10953 .queue_exception = vmx_queue_exception,
10954 .cancel_injection = vmx_cancel_injection,
10955 .interrupt_allowed = vmx_interrupt_allowed,
10956 .nmi_allowed = vmx_nmi_allowed,
10957 .get_nmi_mask = vmx_get_nmi_mask,
10958 .set_nmi_mask = vmx_set_nmi_mask,
10959 .enable_nmi_window = enable_nmi_window,
10960 .enable_irq_window = enable_irq_window,
10961 .update_cr8_intercept = update_cr8_intercept,
10962 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10963 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10964 .get_enable_apicv = vmx_get_enable_apicv,
10965 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10966 .load_eoi_exitmap = vmx_load_eoi_exitmap,
10967 .hwapic_irr_update = vmx_hwapic_irr_update,
10968 .hwapic_isr_update = vmx_hwapic_isr_update,
10969 .sync_pir_to_irr = vmx_sync_pir_to_irr,
10970 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10971
10972 .set_tss_addr = vmx_set_tss_addr,
10973 .get_tdp_level = get_ept_level,
10974 .get_mt_mask = vmx_get_mt_mask,
10975
10976 .get_exit_info = vmx_get_exit_info,
10977
10978 .get_lpage_level = vmx_get_lpage_level,
10979
10980 .cpuid_update = vmx_cpuid_update,
10981
10982 .rdtscp_supported = vmx_rdtscp_supported,
10983 .invpcid_supported = vmx_invpcid_supported,
10984
10985 .set_supported_cpuid = vmx_set_supported_cpuid,
10986
10987 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10988
10989 .read_tsc_offset = vmx_read_tsc_offset,
10990 .write_tsc_offset = vmx_write_tsc_offset,
10991 .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10992 .read_l1_tsc = vmx_read_l1_tsc,
10993
10994 .set_tdp_cr3 = vmx_set_cr3,
10995
10996 .check_intercept = vmx_check_intercept,
10997 .handle_external_intr = vmx_handle_external_intr,
10998 .mpx_supported = vmx_mpx_supported,
10999 .xsaves_supported = vmx_xsaves_supported,
11000
11001 .check_nested_events = vmx_check_nested_events,
11002
11003 .sched_in = vmx_sched_in,
11004
11005 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11006 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11007 .flush_log_dirty = vmx_flush_log_dirty,
11008 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11009
11010 .pre_block = vmx_pre_block,
11011 .post_block = vmx_post_block,
11012
11013 .pmu_ops = &intel_pmu_ops,
11014
11015 .update_pi_irte = vmx_update_pi_irte,
11016 };
11017
11018 static int __init vmx_init(void)
11019 {
11020 int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11021 __alignof__(struct vcpu_vmx), THIS_MODULE);
11022 if (r)
11023 return r;
11024
11025 #ifdef CONFIG_KEXEC_CORE
11026 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11027 crash_vmclear_local_loaded_vmcss);
11028 #endif
11029
11030 return 0;
11031 }
11032
11033 static void __exit vmx_exit(void)
11034 {
11035 #ifdef CONFIG_KEXEC_CORE
11036 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11037 synchronize_rcu();
11038 #endif
11039
11040 kvm_exit();
11041 }
11042
11043 module_init(vmx_init)
11044 module_exit(vmx_exit)
Linux kernel - Deliverables
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