arch/x86/ras/mce_amd_inj.c

   1 /*
   2  * A simple MCE injection facility for testing different aspects of the RAS
   3  * code. This driver should be built as module so that it can be loaded
   4  * on production kernels for testing purposes.
   5  *
   6  * This file may be distributed under the terms of the GNU General Public
   7  * License version 2.
   8  *
   9  * Copyright (c) 2010-15:  Borislav Petkov <bp@alien8.de>
  10  *                      Advanced Micro Devices Inc.
  11  */
  12
  13 #include <linux/kobject.h>
  14 #include <linux/debugfs.h>
  15 #include <linux/device.h>
  16 #include <linux/module.h>
  17 #include <linux/cpu.h>
  18 #include <linux/string.h>
  19 #include <linux/uaccess.h>
  20 #include <linux/pci.h>
  21
  22 #include <asm/mce.h>
  23 #include <asm/amd_nb.h>
  24 #include <asm/irq_vectors.h>
  25
  26 #include "../kernel/cpu/mcheck/mce-internal.h"
  27
  28 /*
  29  * Collect all the MCi_XXX settings
  30  */
  31 static struct mce i_mce;
  32 static struct dentry *dfs_inj;
  33
  34 static u8 n_banks;
  35
  36 #define MAX_FLAG_OPT_SIZE       3
  37 #define NBCFG                   0x44
  38
  39 enum injection_type {
  40         SW_INJ = 0,     /* SW injection, simply decode the error */
  41         HW_INJ,         /* Trigger a #MC */
  42         DFR_INT_INJ,    /* Trigger Deferred error interrupt */
  43         THR_INT_INJ,    /* Trigger threshold interrupt */
  44         N_INJ_TYPES,
  45 };
  46
  47 static const char * const flags_options[] = {
  48         [SW_INJ] = "sw",
  49         [HW_INJ] = "hw",
  50         [DFR_INT_INJ] = "df",
  51         [THR_INT_INJ] = "th",
  52         NULL
  53 };
  54
  55 /* Set default injection to SW_INJ */
  56 static enum injection_type inj_type = SW_INJ;
  57
  58 #define MCE_INJECT_SET(reg)                                             \
  59 static int inj_##reg##_set(void *data, u64 val)                         \
  60 {                                                                       \
  61         struct mce *m = (struct mce *)data;                             \
  62                                                                         \
  63         m->reg = val;                                                   \
  64         return 0;                                                       \
  65 }
  66
  67 MCE_INJECT_SET(status);
  68 MCE_INJECT_SET(misc);
  69 MCE_INJECT_SET(addr);
  70
  71 #define MCE_INJECT_GET(reg)                                             \
  72 static int inj_##reg##_get(void *data, u64 *val)                        \
  73 {                                                                       \
  74         struct mce *m = (struct mce *)data;                             \
  75                                                                         \
  76         *val = m->reg;                                                  \
  77         return 0;                                                       \
  78 }
  79
  80 MCE_INJECT_GET(status);
  81 MCE_INJECT_GET(misc);
  82 MCE_INJECT_GET(addr);
  83
  84 DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
  85 DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
  86 DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
  87
  88 /*
  89  * Caller needs to be make sure this cpu doesn't disappear
  90  * from under us, i.e.: get_cpu/put_cpu.
  91  */
  92 static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
  93 {
  94         u32 l, h;
  95         int err;
  96
  97         err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
  98         if (err) {
  99                 pr_err("%s: error reading HWCR\n", __func__);
 100                 return err;
 101         }
 102
 103         enable ? (l |= BIT(18)) : (l &= ~BIT(18));
 104
 105         err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
 106         if (err)
 107                 pr_err("%s: error writing HWCR\n", __func__);
 108
 109         return err;
 110 }
 111
 112 static int __set_inj(const char *buf)
 113 {
 114         int i;
 115
 116         for (i = 0; i < N_INJ_TYPES; i++) {
 117                 if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
 118                         inj_type = i;
 119                         return 0;
 120                 }
 121         }
 122         return -EINVAL;
 123 }
 124
 125 static ssize_t flags_read(struct file *filp, char __user *ubuf,
 126                           size_t cnt, loff_t *ppos)
 127 {
 128         char buf[MAX_FLAG_OPT_SIZE];
 129         int n;
 130
 131         n = sprintf(buf, "%s\n", flags_options[inj_type]);
 132
 133         return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
 134 }
 135
 136 static ssize_t flags_write(struct file *filp, const char __user *ubuf,
 137                            size_t cnt, loff_t *ppos)
 138 {
 139         char buf[MAX_FLAG_OPT_SIZE], *__buf;
 140         int err;
 141
 142         if (cnt > MAX_FLAG_OPT_SIZE)
 143                 return -EINVAL;
 144
 145         if (copy_from_user(&buf, ubuf, cnt))
 146                 return -EFAULT;
 147
 148         buf[cnt - 1] = 0;
 149
 150         /* strip whitespace */
 151         __buf = strstrip(buf);
 152
 153         err = __set_inj(__buf);
 154         if (err) {
 155                 pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
 156                 return err;
 157         }
 158
 159         *ppos += cnt;
 160
 161         return cnt;
 162 }
 163
 164 static const struct file_operations flags_fops = {
 165         .read           = flags_read,
 166         .write          = flags_write,
 167         .llseek         = generic_file_llseek,
 168 };
 169
 170 /*
 171  * On which CPU to inject?
 172  */
 173 MCE_INJECT_GET(extcpu);
 174
 175 static int inj_extcpu_set(void *data, u64 val)
 176 {
 177         struct mce *m = (struct mce *)data;
 178
 179         if (val >= nr_cpu_ids || !cpu_online(val)) {
 180                 pr_err("%s: Invalid CPU: %llu\n", __func__, val);
 181                 return -EINVAL;
 182         }
 183         m->extcpu = val;
 184         return 0;
 185 }
 186
 187 DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");
 188
 189 static void trigger_mce(void *info)
 190 {
 191         asm volatile("int $18");
 192 }
 193
 194 static void trigger_dfr_int(void *info)
 195 {
 196         asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR));
 197 }
 198
 199 static void trigger_thr_int(void *info)
 200 {
 201         asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR));
 202 }
 203
 204 static u32 get_nbc_for_node(int node_id)
 205 {
 206         struct cpuinfo_x86 *c = &boot_cpu_data;
 207         u32 cores_per_node;
 208
 209         cores_per_node = c->x86_max_cores / amd_get_nodes_per_socket();
 210
 211         return cores_per_node * node_id;
 212 }
 213
 214 static void toggle_nb_mca_mst_cpu(u16 nid)
 215 {
 216         struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
 217         u32 val;
 218         int err;
 219
 220         if (!F3)
 221                 return;
 222
 223         err = pci_read_config_dword(F3, NBCFG, &val);
 224         if (err) {
 225                 pr_err("%s: Error reading F%dx%03x.\n",
 226                        __func__, PCI_FUNC(F3->devfn), NBCFG);
 227                 return;
 228         }
 229
 230         if (val & BIT(27))
 231                 return;
 232
 233         pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n",
 234                __func__);
 235
 236         val |= BIT(27);
 237         err = pci_write_config_dword(F3, NBCFG, val);
 238         if (err)
 239                 pr_err("%s: Error writing F%dx%03x.\n",
 240                        __func__, PCI_FUNC(F3->devfn), NBCFG);
 241 }
 242
 243 static void do_inject(void)
 244 {
 245         u64 mcg_status = 0;
 246         unsigned int cpu = i_mce.extcpu;
 247         u8 b = i_mce.bank;
 248
 249         if (i_mce.misc)
 250                 i_mce.status |= MCI_STATUS_MISCV;
 251
 252         if (inj_type == SW_INJ) {
 253                 mce_inject_log(&i_mce);
 254                 return;
 255         }
 256
 257         /* prep MCE global settings for the injection */
 258         mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
 259
 260         if (!(i_mce.status & MCI_STATUS_PCC))
 261                 mcg_status |= MCG_STATUS_RIPV;
 262
 263         /*
 264          * Ensure necessary status bits for deferred errors:
 265          * - MCx_STATUS[Deferred]: make sure it is a deferred error
 266          * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC
 267          */
 268         if (inj_type == DFR_INT_INJ) {
 269                 i_mce.status |= MCI_STATUS_DEFERRED;
 270                 i_mce.status |= (i_mce.status & ~MCI_STATUS_UC);
 271         }
 272
 273         /*
 274          * For multi node CPUs, logging and reporting of bank 4 errors happens
 275          * only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for
 276          * Fam10h and later BKDGs.
 277          */
 278         if (static_cpu_has(X86_FEATURE_AMD_DCM) && b == 4) {
 279                 toggle_nb_mca_mst_cpu(amd_get_nb_id(cpu));
 280                 cpu = get_nbc_for_node(amd_get_nb_id(cpu));
 281         }
 282
 283         get_online_cpus();
 284         if (!cpu_online(cpu))
 285                 goto err;
 286
 287         toggle_hw_mce_inject(cpu, true);
 288
 289         wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
 290                      (u32)mcg_status, (u32)(mcg_status >> 32));
 291
 292         wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
 293                      (u32)i_mce.status, (u32)(i_mce.status >> 32));
 294
 295         wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
 296                      (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
 297
 298         wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
 299                      (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
 300
 301         toggle_hw_mce_inject(cpu, false);
 302
 303         switch (inj_type) {
 304         case DFR_INT_INJ:
 305                 smp_call_function_single(cpu, trigger_dfr_int, NULL, 0);
 306                 break;
 307         case THR_INT_INJ:
 308                 smp_call_function_single(cpu, trigger_thr_int, NULL, 0);
 309                 break;
 310         default:
 311                 smp_call_function_single(cpu, trigger_mce, NULL, 0);
 312         }
 313
 314 err:
 315         put_online_cpus();
 316
 317 }
 318
 319 /*
 320  * This denotes into which bank we're injecting and triggers
 321  * the injection, at the same time.
 322  */
 323 static int inj_bank_set(void *data, u64 val)
 324 {
 325         struct mce *m = (struct mce *)data;
 326
 327         if (val >= n_banks) {
 328                 pr_err("Non-existent MCE bank: %llu\n", val);
 329                 return -EINVAL;
 330         }
 331
 332         m->bank = val;
 333         do_inject();
 334
 335         return 0;
 336 }
 337
 338 MCE_INJECT_GET(bank);
 339
 340 DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");
 341
 342 static const char readme_msg[] =
 343 "Description of the files and their usages:\n"
 344 "\n"
 345 "Note1: i refers to the bank number below.\n"
 346 "Note2: See respective BKDGs for the exact bit definitions of the files below\n"
 347 "as they mirror the hardware registers.\n"
 348 "\n"
 349 "status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
 350 "\t attributes of the error which caused the MCE.\n"
 351 "\n"
 352 "misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
 353 "\t used for error thresholding purposes and its validity is indicated by\n"
 354 "\t MCi_STATUS[MiscV].\n"
 355 "\n"
 356 "addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
 357 "\t associated with the error.\n"
 358 "\n"
 359 "cpu:\t The CPU to inject the error on.\n"
 360 "\n"
 361 "bank:\t Specify the bank you want to inject the error into: the number of\n"
 362 "\t banks in a processor varies and is family/model-specific, therefore, the\n"
 363 "\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
 364 "\t injection.\n"
 365 "\n"
 366 "flags:\t Injection type to be performed. Writing to this file will trigger a\n"
 367 "\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
 368 "\t for AMD processors.\n"
 369 "\n"
 370 "\t Allowed error injection types:\n"
 371 "\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
 372 "\t    format only. Safe to use.\n"
 373 "\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
 374 "\t    handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
 375 "\t    is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
 376 "\t    before injecting.\n"
 377 "\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
 378 "\t    error APIC interrupt handler to handle the error if the feature is \n"
 379 "\t    is present in hardware. \n"
 380 "\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
 381 "\t    APIC interrupt handler to handle the error. \n"
 382 "\n";
 383
 384 static ssize_t
 385 inj_readme_read(struct file *filp, char __user *ubuf,
 386                        size_t cnt, loff_t *ppos)
 387 {
 388         return simple_read_from_buffer(ubuf, cnt, ppos,
 389                                         readme_msg, strlen(readme_msg));
 390 }
 391
 392 static const struct file_operations readme_fops = {
 393         .read           = inj_readme_read,
 394 };
 395
 396 static struct dfs_node {
 397         char *name;
 398         struct dentry *d;
 399         const struct file_operations *fops;
 400         umode_t perm;
 401 } dfs_fls[] = {
 402         { .name = "status",     .fops = &status_fops, .perm = S_IRUSR | S_IWUSR },
 403         { .name = "misc",       .fops = &misc_fops,   .perm = S_IRUSR | S_IWUSR },
 404         { .name = "addr",       .fops = &addr_fops,   .perm = S_IRUSR | S_IWUSR },
 405         { .name = "bank",       .fops = &bank_fops,   .perm = S_IRUSR | S_IWUSR },
 406         { .name = "flags",      .fops = &flags_fops,  .perm = S_IRUSR | S_IWUSR },
 407         { .name = "cpu",        .fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR },
 408         { .name = "README",     .fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH },
 409 };
 410
 411 static int __init init_mce_inject(void)
 412 {
 413         int i;
 414         u64 cap;
 415
 416         rdmsrl(MSR_IA32_MCG_CAP, cap);
 417         n_banks = cap & MCG_BANKCNT_MASK;
 418
 419         dfs_inj = debugfs_create_dir("mce-inject", NULL);
 420         if (!dfs_inj)
 421                 return -EINVAL;
 422
 423         for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
 424                 dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
 425                                                     dfs_fls[i].perm,
 426                                                     dfs_inj,
 427                                                     &i_mce,
 428                                                     dfs_fls[i].fops);
 429
 430                 if (!dfs_fls[i].d)
 431                         goto err_dfs_add;
 432         }
 433
 434         return 0;
 435
 436 err_dfs_add:
 437         while (--i >= 0)
 438                 debugfs_remove(dfs_fls[i].d);
 439
 440         debugfs_remove(dfs_inj);
 441         dfs_inj = NULL;
 442
 443         return -ENOMEM;
 444 }
 445
 446 static void __exit exit_mce_inject(void)
 447 {
 448         int i;
 449
 450         for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
 451                 debugfs_remove(dfs_fls[i].d);
 452
 453         memset(&dfs_fls, 0, sizeof(dfs_fls));
 454
 455         debugfs_remove(dfs_inj);
 456         dfs_inj = NULL;
 457 }
 458 module_init(init_mce_inject);
 459 module_exit(exit_mce_inject);
 460
 461 MODULE_LICENSE("GPL");
 462 MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
 463 MODULE_AUTHOR("AMD Inc.");
 464 MODULE_DESCRIPTION("MCE injection facility for RAS testing");