binutils/testsuite/binutils-all/arm/out-of-order-all.d

   1 #PROG: objcopy
   2 #source: out-of-order.s
   3 #ld: -T out-of-order.T
   4 #objdump: -D
   5 #name: Check if disassembler can handle all sections in different order than header
   6
   7 .*: +file format .*arm.*
   8
   9 Disassembly of section \.global:
  10
  11 ffe00000 <\.global>:
  12 ffe00000:       00000001        andeq   r0, r0, r1
  13 ffe00004:       00000001        andeq   r0, r0, r1
  14 ffe00008:       00000001        andeq   r0, r0, r1
  15
  16 Disassembly of section \.func2:
  17
  18 04018280 <\.func2>:
  19  4018280:       e0800001        add     r0, r0, r1
  20
  21 Disassembly of section \.func1:
  22
  23 04005000 <v1>:
  24  4005000:       e0800001        add     r0, r0, r1
  25  4005004:       00000000        andeq   r0, r0, r0
  26
  27 Disassembly of section \.func3:
  28
  29 04015000 <\.func3>:
  30  4015000:       e0800001        add     r0, r0, r1
  31  4015004:       e0800001        add     r0, r0, r1
  32  4015008:       e0800001        add     r0, r0, r1
  33  401500c:       e0800001        add     r0, r0, r1
  34  4015010:       e0800001        add     r0, r0, r1
  35  4015014:       00000000        andeq   r0, r0, r0
  36
  37 Disassembly of section \.rodata:
  38
  39 04015018 <\.rodata>:
  40  4015018:       00000004        andeq   r0, r0, r4
  41
  42 Disassembly of section \.ARM\.attributes:
  43
  44 00000000 <\.ARM\.attributes>:
  45    0:   00001141        andeq   r1, r0, r1, asr #2
  46    4:   61656100        cmnvs   r5, r0, lsl #2
  47    8:   01006962        tsteq   r0, r2, ror #18
  48    c:   00000007        andeq   r0, r0, r7
  49   10:   Address 0x0000000000000010 is out of bounds.
  50