1 /*****************************************************************
4 * @purpose 1:20.4, Validate that interleave statements are properly handled.
5 * @verdict pass accept, noexecution
6 *****************************************************************/
7 module Syn_2004_InterleaveStatement_001 {
8 type port MyMessagePortType message {
10 } with {extension "internal"}
12 type component GeneralComp {
13 port MyMessagePortType pt_myPort1, pt_myPort2;
16 type record MyMessageType {
22 testcase TC_Syn_2004_InterleaveStatement_001() runs on GeneralComp {
24 template MyMessageType MySig1 := {2, "abcxyz", true}
25 template MyMessageType MySig2 := MySig1;
26 template MyMessageType MySig3 := MySig1;
27 template MyMessageType MySig4 := MySig1;
28 template MyMessageType MySig5 := MySig1;
29 template MyMessageType MySig6 := MySig1;
31 connect(self:pt_myPort1, self:pt_myPort2);
41 interleave { // order of messages
42 [] pt_myPort1.receive(MySig1) { //3.
43 pt_myPort1.send(MySig2); //4.
44 pt_myPort1.receive(MySig3); //6.
47 [] pt_myPort2.receive(MySig4) { // 1.
48 pt_myPort2.send(MySig5); //2.
49 pt_myPort2.receive(MySig6); //5.
50 pt_myPort2.send(MySig1); //7.
55 execute(TC_Syn_2004_InterleaveStatement_001());