cpu/ms1.cpu

   1 ; Morpho Technologies mRISC CPU description.  -*- Scheme -*-
   2 ; Copyright 2001 Free Software Foundation, Inc.
   3 ;
   4 ; Contributed by Red Hat Inc; developed under contract from
   5 ; Morpho Technologies.
   6 ;
   7 ; This file is part of the GNU Binutils.
   8 ;
   9 ; This program is free software; you can redistribute it and/or modify
  10 ; it under the terms of the GNU General Public License as published by
  11 ; the Free Software Foundation; either version 2 of the License, or
  12 ; (at your option) any later version.
  13 ;
  14 ; This program is distributed in the hope that it will be useful,
  15 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ; GNU General Public License for more details.
  18 ;
  19 ; You should have received a copy of the GNU General Public License
  20 ; along with this program; if not, write to the Free Software
  21 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 (include "simplify.inc")
  24
  25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  26 ;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;;
  27 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  28
  29 ; define-arch must appear first
  30 (define-arch
  31   (name ms1) ; name of cpu family
  32   (comment "Morpho Technologies mRISC family")
  33   (default-alignment aligned)
  34   (insn-lsb0? #t)
  35   (machs ms1 ms1-003)
  36   (isas ms1)
  37 )
  38
  39 ; Instruction set parameters.
  40
  41 (define-isa
  42   (name ms1)
  43   (comment "Morpho Technologies mrisc ISA")
  44   (default-insn-word-bitsize 32)
  45   (default-insn-bitsize 32)
  46   (base-insn-bitsize 32)
  47   (parallel-insns 2)
  48 )
  49 \f
  50 ; Cpu family definitions.
  51
  52
  53 (define-cpu
  54   ; cpu names must be distinct from the architecture name and machine names.
  55   (name ms1bf)
  56   (comment "Morpho Technologies mRISC family")
  57   (endian big)
  58   (word-bitsize 32)
  59 )
  60
  61 (define-cpu
  62   ; cpu names must be distinct from the architecture name and machine names.
  63   (name ms1-003bf)
  64   (comment "Morpho Technologies mRISC family")
  65   (endian big)
  66   (word-bitsize 32)
  67 )
  68
  69 (define-mach
  70   (name ms1)
  71   (comment "Morpho Technologies mrisc")
  72   (cpu ms1bf)
  73   (isas ms1)
  74 )
  75
  76 (define-mach
  77   (name ms1-003)
  78   (comment "Morpho Technologies mrisc")
  79   (cpu ms1-003bf)
  80   (isas ms1)
  81 )
  82
  83 \f
  84 ; Model descriptions.
  85 ; Can probably take the u-exec out.  We'll see.
  86 (define-model
  87   (name ms1)
  88   (comment "Morpho Technologies mrisc")
  89   (mach ms1)
  90   (unit u-exec "Execution Unit" ()
  91         1 1 ; issue done
  92         () ; state
  93         () ; inputs
  94         () ; outputs
  95         () ; profile action (default)
  96         )
  97 )
  98
  99 (define-model
 100   (name ms1-003)
 101   (comment "Morpho Technologies mrisc")
 102   (mach ms1-003)
 103   (unit u-exec "Execution Unit" ()
 104         1 1 ; issue done
 105         () ; state
 106         () ; inputs
 107         () ; outputs
 108         () ; profile action (default)
 109         )
 110 )
 111
 112 ; Macros to simplify MACH attribute specification.
 113
 114 (define-pmacro MACHMS1 (MACH ms1))
 115 (define-pmacro MACHMS1-003 (MACH ms1-003))
 116
 117 ; FIXME: It might simplify things to separate the execute process from the
 118 ; one that updates the PC.
 119 \f
 120
 121 ;;;;;;;;;;;;;;;;;;;;;;;;
 122 ;; Instruction Fields ;;
 123 ;;;;;;;;;;;;;;;;;;;;;;;;
 124
 125 ; Attributes:
 126 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
 127 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
 128 ; RESERVED: bits are not used to decode insn, must be all 0
 129 ; RELOC: there is a relocation associated with this field (experiment)
 130 ;
 131 ; f-msys: Identify a a morphosys insns.  1 if msys, 0 if not.
 132 ; f-opc: 6 bit opcode for non-morphosys instructions.
 133 ; f-msopc: 6 bit opcode for morphosys instructions.
 134 ; f-imm: flag to indicate use of an immediate operand.  1 if yes, 0 if no.
 135 ; f-sr1: source resgister 1. (also used for MSYS insns)
 136 ; f-sr2: source register 2. (also used for MSYS insns)
 137 ; f-dr: destination register when located in bits 19:16.
 138 ; f-drrr: destination register when located in bits 15:12. (also for MSYS insns)
 139 ; f-imm16: 16 bit immediate value when not an offset.
 140 ; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
 141 ; f-uu4a: unused 4 bit field.
 142 ; f-uu4b: second unsed 4 bit field.
 143 ; f-uu12: unused 12 bit field.
 144 ; f-uu16: unused 16 bit field.
 145 ; f-uu24: unused 24 bit field.
 146
 147 (dnf f-msys      "morphosys insn flag"          () 31 1)
 148 (dnf f-opc       "opcode field"                 () 30 6)
 149 (dnf f-imm       "immedate flag"                () 24 1)
 150 (dnf f-uu24      "unused 24 bits"               () 23 24)
 151 (dnf f-sr1       "sr1 register field"   (ABS-ADDR) 23 4)
 152 (dnf f-sr2       "sr2 register field"   (ABS-ADDR) 19 4)
 153 (dnf f-dr        "dr register field"    (ABS-ADDR) 19 4)
 154 (dnf f-drrr      "drrr register field"  (ABS-ADDR) 15 4)
 155 (dnf f-imm16u    "unsigned 16 bit immediate"    () 15 16)
 156 (df  f-imm16s    "signed 16 bit immediate"      () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0)))
 157 (dnf f-imm16a    "pc-rel offset"      (PCREL-ADDR) 15 16)
 158 (dnf f-uu4a      "unused 4 bit field"           () 19 4)
 159 (dnf f-uu4b      "unused 4 bit field"           () 23 4)
 160 (dnf f-uu12      "unused 12 bit field"          () 11 12)
 161 (dnf f-uu16      "unused 16 bit field"          () 15 16)
 162
 163 ; The following ifields are used exclusively for the MorphoSys instructions.
 164 ; In a few cases, a bit field is used for something in addition to what its
 165 ; name suggests.  For the most part, the names are meaningful though.
 166
 167 (dnf f-msopc     "opcode field"                 () 30 5)
 168 (dnf f-uu-26-25  "unused 26 bits"               () 25 26)
 169 (dnf f-mask      "mask"                         () 25 16)
 170 (dnf f-bankaddr  "bank address"                 () 25 13)
 171 (dnf f-rda       "rda"                          () 25 1)
 172 (dnf f-uu-2-25   "unused bits  25 & 24"         () 25 2)
 173 (dnf f-rbbc      "Omega network configuration"  () 25 2)
 174 (dnf f-perm      "perm"                         () 25 2)
 175 (dnf f-mode      "mode"                         () 25 2)
 176 (dnf f-uu-1-24   "testing"                      () 24 1)
 177 (dnf f-wr        "wr"                           () 24 1)
 178 (dnf f-fbincr    "fb incr"                      () 23 4)
 179 (dnf f-uu-2-23   "unused bits 23 and 22"        () 23 2)
 180 (dnf f-xmode     "xmode"                        () 23 1)
 181 (dnf f-a23       "a23"                          () 23 1)
 182 (dnf f-mask1     "mask1"                        () 22 3)
 183 (dnf f-cr        "cr"                           () 22 3)
 184 (dnf f-type      "type"                         () 21 2)
 185 (dnf f-incamt    "increment amount"             () 19 8)
 186 (dnf f-cbs       "cbs"                          () 19 2)
 187 (dnf f-uu-1-19   "unused bit 19"                () 19 1)
 188 (dnf f-ball      "b_all"                        () 19 1)
 189 (dnf f-colnum    "column number"                () 18 3)
 190 (dnf f-brc       "b_r_c"                        () 18 3)
 191 (dnf f-incr      "incr"                         () 17 6)
 192 (dnf f-fbdisp    "frame buffer displacement"    () 15 6)
 193 (dnf f-uu-4-15   "unused bits 15,14,13,12"      () 15 4)
 194 (dnf f-length    "length"                       () 15 3)
 195 (dnf f-uu-1-15   "unused bit 15"                () 15 1)
 196 (dnf f-rc        "row/column context"           () 15 1)
 197 (dnf f-rcnum     "starting cell of cntxt mem."  () 14 3)
 198 (dnf f-rownum    "row number"                   () 14 3)
 199 (dnf f-cbx       "cbx"                          () 14 3)
 200 (dnf f-id        "id"                           () 14 1)
 201 (dnf f-size      "size"                         () 13 14)
 202 (dnf f-rownum1   "row number"                   () 12 3)
 203 (dnf f-uu-3-11   "unused 3 bits (11-9)"         () 11 3)
 204 (dnf f-rc1       "row/column context"           () 11 1)
 205 (dnf f-ccb       "ccb"                          () 11 1)
 206 (dnf f-cbrb      "data-bus orientation"         () 10 1)
 207 (dnf f-cdb       "cdb"                          () 10 1)
 208 (dnf f-rownum2   "row number"                   ()  9 3)
 209 (dnf f-cell      "cell"                         ()  9 3)
 210 (dnf f-uu-3-9    "unused 3 bits (9-7)"          ()  9 3)
 211 (dnf f-contnum   "context number"               ()  8 9)
 212 (dnf f-uu-1-6    "unused bit 6"                 ()  6 1)
 213 (dnf f-dup       "dup"                          ()  6 1)
 214 (dnf f-rc2       "rc2"                          ()  6 1)
 215 (dnf f-ctxdisp   "context displacement"         ()  5 6)
 216
 217
 218 ; The following is just for a test
 219 (dnf f-msysfrsr2 "sr2 for msys"                 () 19 4)
 220 (dnf f-brc2      "b_r_c2"                       () 14 3)
 221 (dnf f-ball2     "b_all2"                       () 15 1)
 222
 223 \f
 224 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 225 ;; Enumerations Of Instruction Fields ;;
 226 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 227
 228 ; insn-msys: bit 31.  1 for Morphosys Insns, 0 if not.
 229 (define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys
 230   (NO YES)
 231 )
 232
 233 ; insn-opc: bits 30 through 25 .  Non-MorphoSys Instructions
 234 ; Note - the documentation is wrong for the encoding of the DBNZ
 235 ; instruction.  It is actually 011110.  See Issue 67699.
 236 (define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc
 237   (ADD  ADDU SUB  SUBU MUL   -      -    -
 238    AND  OR   XOR  NAND NOR   XNOR   LDUI -
 239    LSL  LSR  ASR  -    -     -      -    -
 240    BRLT BRLE BREQ JMP  JAL   BRNEQ  DBNZ -
 241    LDW  STW  -    -    -     -      -    -
 242    -    -    -    -    -     -      -    -
 243    EI   DI   SI   RETI BREAK IFLUSH -    -
 244   )
 245 )
 246
 247 ; insn-msopc: bits 30 through 26 .  MorphoSys Instructions
 248 (define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc
 249   (LDCTXT LDFB      STFB    FBCB     MFBCB    FBCCI     FBRCI     FBCRI
 250    FBRRI  MFBCCI    MFBRCI  MFBCRI   MFBRRI   FBCBDR    RCFBCB    MRCFBCB
 251    CBCAST DUPCBCAST WFBI    WFB      RCRISC   FBCBINC   RCXMODE   INTLVR
 252    WFBINC MWFBINC   WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS
 253    -      -         -       -        -        -         -         -
 254   )
 255 )
 256
 257 ; insn-imm: bit 24.  Immediate operand indicator.
 258 (define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm
 259   ; This bit specifies whether and immediate operand will be present.
 260   ; It's 1 if ther is, 0 if there is not.
 261   (NO YES)
 262 )
 263 ;;;;;;;;;;;;;;;;
 264 ;; Attributes ;;
 265 ;;;;;;;;;;;;;;;;
 266
 267 ; Might not need this.  Keep if for the sim just in case.
 268 ;(define-attr
 269 ;  (for insn)
 270 ;  (type boolean)
 271 ;  (name EXT-SKIP-INSN)
 272 ;  (comment "instruction is a PAGE, LOADL or LOADH instruction")
 273 ;)
 274
 275 (define-attr
 276   (for insn)
 277   (type boolean)
 278   (name LOAD-DELAY)
 279   (comment "insn has a load delay")
 280 )
 281
 282 (define-attr
 283   (for insn)
 284   (type boolean)
 285   (name MEMORY-ACCESS)
 286   (comment "insn performs a memory access")
 287 )
 288
 289 (define-attr
 290   (for insn)
 291   (type boolean)
 292   (name AL-INSN)
 293   (comment "insn is an arithmetic or logic insn.")
 294 )
 295
 296 (define-attr
 297   (for insn)
 298   (type boolean)
 299   (name IO-INSN)
 300   (comment "insn performs an I/O operation")
 301 )
 302
 303 (define-attr
 304   (for insn)
 305   (type boolean)
 306   (name BR-INSN)
 307   (comment "insn performs an I/O operation")
 308 )
 309
 310 (define-pmacro (define-reg-use-attr regfield)
 311   (define-attr
 312     (for insn)
 313     (type boolean)
 314     (name (.sym "USES-" (.upcase regfield)))
 315     (comment ("insn accesses register operand " regfield))))
 316
 317 (define-reg-use-attr "frdr")
 318 (define-reg-use-attr "frdrrr")
 319 (define-reg-use-attr "frsr1")
 320 (define-reg-use-attr "frsr2")
 321
 322
 323 ; Might not need this.  Keep it for the sim just in case.
 324 (define-attr
 325   (for insn)
 326   (type boolean)
 327   (name SKIPA)
 328   (comment "instruction is a SKIP instruction")
 329 )
 330
 331
 332 ;;;;;;;;;;;;;;;;;;;;;
 333 ;; Hardware Pieces ;;
 334 ;;;;;;;;;;;;;;;;;;;;;
 335
 336 ;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n))
 337
 338 ; These are the 16 registers that the chip has.  In later versions
 339 ; where there will be more registers, this will need to be expanded.
 340 ; Note that there are two entries for the registers with two names.
 341 (define-hardware
 342   (name h-spr)
 343   (comment "special-purpose registers")
 344   (type register SI (16))
 345   (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5)
 346   ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12)
 347   ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15)))
 348 ;  (get (index) (and (raw-reg h-spr) #xffffffff))
 349 ;  (set (index value) (set (raw-reg h-spr) (and value #xffffffff)))
 350 )
 351
 352 ; This is the  program counter.
 353 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
 354
 355 (define-keyword
 356    (name msys-syms)
 357    (print-name h-nil)
 358    (prefix "")
 359    (values (DUP 1) (XX 0))
 360 )
 361
 362 ;;;;;;;;;;;;;;
 363 ;; Operands ;;
 364 ;;;;;;;;;;;;;;
 365
 366 (define-operand (name frsr1) (comment "register") (attrs)
 367   (type h-spr) (index f-sr1) )
 368 (define-operand (name frsr2) (comment "register") (attrs)
 369   (type h-spr) (index f-sr2) )
 370 (define-operand (name frdr) (comment "register") (attrs)
 371   (type h-spr) (index f-dr) )
 372 (define-operand (name frdrrr) (comment "register") (attrs)
 373   (type h-spr) (index f-drrr) )
 374 (define-operand (name imm16) (comment "immediate value - sign extd") (attrs)
 375   (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
 376 (define-operand (name imm16z) (comment "immediate value - zero extd") (attrs)
 377   (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex")))
 378 (define-operand (name imm16o) (comment "immediate value") (attrs)
 379   (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
 380
 381 ; Operands for MorphoSys Instructions
 382
 383 (define-operand (name rc) (comment "rc") (attrs)
 384   (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex")))
 385
 386 (define-operand (name rcnum) (comment "rcnum") (attrs)
 387   (type h-uint) (index f-rcnum) (handlers (print "dollarhex")))
 388
 389 (define-operand (name contnum) (comment "context number") (attrs)
 390   (type h-uint) (index f-contnum) (handlers (print "dollarhex")))
 391
 392 (define-operand (name rbbc) (comment "omega network configuration") (attrs)
 393   (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex")))
 394
 395 (define-operand (name colnum) (comment "column number") (attrs)
 396   (type h-uint) (index f-colnum) (handlers (print "dollarhex")))
 397
 398 (define-operand (name rownum) (comment "row number") (attrs)
 399   (type h-uint) (index f-rownum) (handlers (print "dollarhex")))
 400
 401 (define-operand (name rownum1) (comment "row number") (attrs)
 402   (type h-uint) (index f-rownum1) (handlers (print "dollarhex")))
 403
 404 (define-operand (name rownum2) (comment "row number") (attrs)
 405   (type h-uint) (index f-rownum2) (handlers (print "dollarhex")))
 406
 407 (define-operand (name rc1) (comment "rc1") (attrs)
 408   (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex")))
 409
 410 (define-operand (name rc2) (comment "rc2") (attrs)
 411   (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex")))
 412
 413 (define-operand (name cbrb) (comment "data-bus orientation") (attrs)
 414   (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex")))
 415
 416 (define-operand (name cell) (comment "cell") (attrs)
 417   (type h-uint) (index f-cell) (handlers (print "dollarhex")))
 418
 419 (define-operand (name dup) (comment "dup") (attrs)
 420   (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex")))
 421
 422 (define-operand (name ctxdisp) (comment "context displacement") (attrs)
 423   (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex")))
 424
 425 (define-operand (name fbdisp) (comment "frame buffer displacement") (attrs)
 426   (type h-uint) (index f-fbdisp) (handlers (print "dollarhex")))
 427
 428 (define-operand (name type) (comment "type") (attrs)
 429   (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex")))
 430
 431 (define-operand (name mask) (comment "mask") (attrs)
 432   (type h-uint) (index f-mask) (handlers (print "dollarhex")))
 433
 434 (define-operand (name bankaddr) (comment "bank address") (attrs)
 435   (type h-uint) (index f-bankaddr) (handlers (print "dollarhex")))
 436
 437 (define-operand (name incamt) (comment "increment amount") (attrs)
 438   (type h-uint) (index f-incamt) (handlers (print "dollarhex")))
 439
 440 (define-operand (name xmode) (comment "xmode") (attrs)
 441   (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex")))
 442
 443 (define-operand (name mask1) (comment "mask1") (attrs)
 444   (type h-uint) (index f-mask1) (handlers (print "dollarhex")))
 445
 446 (define-operand (name ball) (comment "b_all") (attrs)
 447   (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex")))
 448
 449 (define-operand (name brc) (comment "b_r_c") (attrs)
 450   (type h-uint) (index f-brc) (handlers (print "dollarhex")))
 451
 452 (define-operand (name rda) (comment "rd") (attrs)
 453   (type h-uint) (index f-rda) (handlers (print "dollarhex")))
 454
 455 (define-operand (name wr) (comment "wr") (attrs)
 456   (type h-uint) (index f-wr) (handlers (print "dollarhex")))
 457
 458 (define-operand (name ball2) (comment "b_all2") (attrs)
 459   (type h-uint) (index f-ball2) (handlers (parse "ball") (print "dollarhex")))
 460
 461 (define-operand (name brc2) (comment "b_r_c2") (attrs)
 462   (type h-uint) (index f-brc2) (handlers (print "dollarhex")))
 463 (define-operand (name perm) (comment "perm") (attrs)
 464   (type h-uint) (index f-perm) (handlers (print "dollarhex")))
 465 (define-operand (name a23)   (comment "a23") (attrs)
 466   (type h-uint) (index f-a23) (handlers (print "dollarhex")))
 467 (define-operand (name cr)   (comment "c-r") (attrs)
 468   (type h-uint) (index f-cr) (handlers (print "dollarhex")))
 469 (define-operand (name cbs)      (comment "cbs") (attrs)
 470   (type h-uint) (index f-cbs) (handlers (print "dollarhex")))
 471 (define-operand (name incr)     (comment "incr") (attrs)
 472   (type h-uint) (index f-incr) (handlers (print "dollarhex")))
 473 (define-operand (name length)   (comment "length") (attrs)
 474   (type h-uint) (index f-length) (handlers (print "dollarhex")))
 475 (define-operand (name cbx)      (comment "cbx") (attrs)
 476   (type h-uint) (index f-cbx) (handlers (print "dollarhex")))
 477 (define-operand (name ccb)      (comment "ccb") (attrs)
 478   (type h-uint) (index f-ccb) (handlers (print "dollarhex")))
 479 (define-operand (name cdb)      (comment "cdb") (attrs)
 480   (type h-uint) (index f-cdb) (handlers (print "dollarhex")))
 481
 482 ; For the INTLVR insn
 483 (define-operand (name mode) (comment "mode") (attrs)
 484   (type h-uint) (index f-mode) (handlers (print "dollarhex")))
 485 (define-operand (name id) (comment "i/d") (attrs)
 486   (type h-uint) (index f-id) (handlers (print "dollarhex")))
 487 (define-operand (name size) (comment "size") (attrs)
 488   (type h-uint) (index f-size) (handlers (print "dollarhex")))
 489
 490 (define-operand (name fbincr)   (comment "fb incr") (attrs)
 491   (type h-uint) (index f-fbincr) (handlers (print "dollarhex")))
 492
 493 ; Probaby won't need most of these.
 494 (define-pmacro r0    (reg h-spr #x0))
 495 (define-pmacro r1    (reg h-spr #x01))
 496 (define-pmacro r2    (reg h-spr #x02))
 497 (define-pmacro r3    (reg h-spr #x03))
 498 (define-pmacro r4    (reg h-spr #x04))
 499 (define-pmacro r5    (reg h-spr #x05))
 500 (define-pmacro r6    (reg h-spr #x06))
 501 (define-pmacro r7    (reg h-spr #x07))
 502 (define-pmacro r8    (reg h-spr #x08))
 503 (define-pmacro r9    (reg h-spr #x09))
 504 (define-pmacro r10   (reg h-spr #xA))
 505 (define-pmacro r11   (reg h-spr #xB))
 506 (define-pmacro r12   (reg h-spr #xC))
 507 (define-pmacro fp    (reg h-spr #xC))
 508 (define-pmacro r13   (reg h-spr #xD))
 509 (define-pmacro sp    (reg h-spr #xD))
 510 (define-pmacro r14   (reg h-spr #xE))
 511 (define-pmacro ra    (reg h-spr #xE))
 512 (define-pmacro r15   (reg h-spr #xF))
 513 (define-pmacro ira   (reg h-spr #xF))
 514
 515 ; delayed set
 516 (define-pmacro (dset dest src) (set (delay 1 dest) src))
 517
 518
 519 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 520 ;; Instructions As Defined In the MorphoRisc ISA Document ;;
 521 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 522
 523 ; Arithmetic Instructions
 524
 525 (dni add "ADD DstReg, SrcReg1, SrcReg2"
 526      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 527      "add $frdrrr,$frsr1,$frsr2"
 528      (+ MSYS_NO OPC_ADD IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 529      (set frdrrr (add SI frsr1 frsr2))
 530      ()
 531 )
 532
 533 (dni addu "ADDU DstReg, SrcReg1, SrcReg2"
 534      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 535      "addu $frdrrr,$frsr1,$frsr2"
 536      (+ MSYS_NO OPC_ADDU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 537      (set frdrrr (add USI frsr1 frsr2))
 538      ()
 539 )
 540
 541 (dni addi "ADDI DstReg, SrcReg1 UnsImm"
 542      (AL-INSN USES-FRDR USES-FRSR1)
 543      "addi $frdr,$frsr1,#$imm16"
 544      (+ MSYS_NO OPC_ADD IMM_YES frsr1 frdr imm16)
 545      (sequence((HI tmp))
 546         (set HI tmp (and imm16 #xffff))
 547         (set frdr (add SI frsr1 (ext SI tmp)))
 548      )
 549      ()
 550 )
 551
 552 (dni addui "ADDUI DstReg, SrcReg1, UnsImm"
 553      (AL-INSN USES-FRDR USES-FRSR1)
 554      "addui $frdr,$frsr1,#$imm16z"
 555      (+ MSYS_NO OPC_ADDU IMM_YES frsr1 frdr imm16z)
 556      (set frdr (add USI frsr1 (ext USI imm16z)))
 557      ()
 558 )
 559
 560 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
 561      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 562      "sub $frdrrr,$frsr1,$frsr2"
 563      (+ MSYS_NO OPC_SUB IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 564      (set frdrrr (sub SI frsr1 frsr2))
 565      ()
 566 )
 567
 568 (dni subu "SUBU DstReg, SrcReg1, SrcReg2"
 569      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 570      "subu $frdrrr,$frsr1,$frsr2"
 571      (+ MSYS_NO OPC_SUBU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 572      (set frdrrr (sub USI frsr1 frsr2))
 573      ()
 574 )
 575
 576 (dni subi "SUBI DstReg, SrcReg1, UnsImm"
 577      (AL-INSN USES-FRDR USES-FRSR1)
 578      "subi $frdr,$frsr1,#$imm16"
 579      (+ MSYS_NO OPC_SUB IMM_YES frsr1 frdr imm16)
 580      (sequence((HI tmp))
 581         (set HI tmp (and imm16 #xffff))
 582         (set frdr (sub SI frsr1 (ext SI tmp)))
 583      )
 584      ;(set frdr (sub SI frsr1 (ext SI imm16)))
 585      ()
 586 )
 587
 588 (dni subui "SUBUI DstReg, SrcReg1, UnsImm"
 589      (AL-INSN USES-FRDR USES-FRSR1)
 590      "subui $frdr,$frsr1,#$imm16z"
 591      (+ MSYS_NO OPC_SUBU IMM_YES frsr1 frdr imm16z)
 592      (set frdr (sub USI frsr1 (ext USI imm16z)))
 593      ()
 594 )
 595
 596 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
 597      (MACHMS1-003 AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 598      "mul $frdrrr,$frsr1,$frsr2"
 599      (+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 600      (sequence((HI op1) (HI op2))
 601          (set op1 (and frsr1 #xffff))
 602          (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
 603             (error "operand out of range")
 604          )
 605          (set op2 (and frsr2 #xffff))
 606          (if (or (lt op2 (const -32768)) (gt op2 (const 32767)))
 607             (error "operand out of range")
 608          )
 609          (set frdrrr (mul SI (ext SI op1) (ext SI op2)))
 610      )
 611      ()
 612 )
 613
 614 (dni muli "MULI DstReg, SrcReg1, UnsImm"
 615      (MACHMS1-003 AL-INSN USES-FRDR USES-FRSR1)
 616      "muli $frdr,$frsr1,#$imm16"
 617      (+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16)
 618      (sequence((HI op1) (HI op2))
 619          (set op1 (and frsr1 #xffff))
 620          (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
 621             (error "operand out of range")
 622          )
 623          (set op2 (and imm16 #xffff))
 624          (if (eq op1 (const 0))
 625           (error "op1 is 0")
 626          )
 627          (if (eq op2 (const 0))
 628           (error "op2 is 0")
 629          )
 630          (set frdr (mul SI (ext SI op1) (ext SI op2)))
 631      )
 632      ()
 633 )
 634
 635 ; Logical Instructions
 636
 637 (dni and "AND DstReg, SrcReg1, SrcReg2"
 638      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 639      "and $frdrrr,$frsr1,$frsr2"
 640      (+ MSYS_NO OPC_AND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 641      (set frdrrr (and frsr1 frsr2))
 642      ()
 643 )
 644
 645 (dni andi "ANDI DstReg, SrcReg1, UnsImm"
 646      (AL-INSN USES-FRDR USES-FRSR1)
 647      "andi $frdr,$frsr1,#$imm16z"
 648      (+ MSYS_NO OPC_AND IMM_YES frsr1 frdr imm16z)
 649      (set frdr (and frsr1 (ext USI imm16z)))
 650      ()
 651 )
 652
 653 (dni or "OR DstReg, SrcReg1, SrcReg2"
 654      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 655      "or $frdrrr,$frsr1,$frsr2"
 656      (+ MSYS_NO OPC_OR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 657      (set frdrrr (or frsr1 frsr2))
 658      ()
 659 )
 660
 661 (dni nop "nop"
 662      ()
 663      "nop"
 664      (+ MSYS_NO OPC_OR IMM_NO (f-uu24 0))
 665      (nop)
 666      ()
 667 )
 668
 669 (dni ori "ORI DstReg, SrcReg1, UnsImm"
 670      (AL-INSN USES-FRDR USES-FRSR1)
 671      "ori $frdr,$frsr1,#$imm16z"
 672      (+ MSYS_NO OPC_OR IMM_YES frsr1 frdr imm16z)
 673      (set frdr (or frsr1 (ext USI imm16z)))
 674      ()
 675 )
 676
 677 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
 678      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 679      "xor $frdrrr,$frsr1,$frsr2"
 680      (+ MSYS_NO OPC_XOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 681      (set frdrrr (xor frsr1 frsr2))
 682      ()
 683 )
 684
 685 (dni xori "XORI DstReg, SrcReg1, UnsImm"
 686      (AL-INSN USES-FRDR USES-FRSR1)
 687      "xori $frdr,$frsr1,#$imm16z"
 688      (+ MSYS_NO OPC_XOR IMM_YES frsr1 frdr imm16z)
 689      (set frdr (xor frsr1 (ext USI imm16z)))
 690      ()
 691 )
 692
 693 (dni nand "NAND DstReg, SrcReg1, SrcReg2"
 694      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 695      "nand $frdrrr,$frsr1,$frsr2"
 696      (+ MSYS_NO OPC_NAND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 697      (set frdrrr (inv (and frsr1 frsr2)))
 698      ()
 699 )
 700
 701 (dni nandi "NANDI DstReg, SrcReg1, UnsImm"
 702      (AL-INSN USES-FRDR USES-FRSR1)
 703      "nandi $frdr,$frsr1,#$imm16z"
 704      (+ MSYS_NO OPC_NAND IMM_YES frsr1 frdr imm16z)
 705      (set frdr (inv (and frsr1 (ext USI imm16z))))
 706      ()
 707 )
 708
 709 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
 710      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 711      "nor $frdrrr,$frsr1,$frsr2"
 712      (+ MSYS_NO OPC_NOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 713      (set frdrrr (inv (or frsr1 frsr2)))
 714      ()
 715 )
 716
 717 (dni nori "NORI DstReg, SrcReg1, UnsImm"
 718      (AL-INSN USES-FRDR USES-FRSR1)
 719      "nori $frdr,$frsr1,#$imm16z"
 720      (+ MSYS_NO OPC_NOR IMM_YES frsr1 frdr imm16z)
 721      (set frdr (inv (or frsr1 (ext USI imm16z))))
 722      ()
 723 )
 724
 725 (dni xnor "XNOR DstReg, SrcReg1, SrcReg2"
 726      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 727      "xnor $frdrrr,$frsr1,$frsr2"
 728      (+ MSYS_NO OPC_XNOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 729      (set frdrrr (inv (xor frsr1 frsr2)))
 730      ()
 731 )
 732
 733 (dni xnori "XNORI DstReg, SrcReg1, UnsImm"
 734      (AL-INSN USES-FRDR USES-FRSR1)
 735      "xnori $frdr,$frsr1,#$imm16z"
 736      (+ MSYS_NO OPC_XNOR IMM_YES frsr1 frdr imm16z)
 737      (set frdr (inv (xor frsr1 (ext USI imm16z))))
 738      ()
 739 )
 740
 741 (dni ldui "LDUI DstReg, UnsImm"
 742      (AL-INSN USES-FRDR)
 743      "ldui $frdr,#$imm16z"
 744      (+ MSYS_NO OPC_LDUI IMM_YES (f-uu4b 0) frdr imm16z)
 745      (set frdr (and (sll imm16z 16) #xffff0000))
 746      ()
 747 )
 748
 749 ; Shift Instructions
 750
 751 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
 752      (USES-FRDRRR USES-FRSR1 USES-FRSR2)
 753      "lsl $frdrrr,$frsr1,$frsr2"
 754      (+ MSYS_NO OPC_LSL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 755      (set frdrrr (sll frsr1 frsr2))
 756      ()
 757 )
 758
 759 (dni lsli "LSLI DstReg, SrcReg1, UnsImm"
 760      (USES-FRDR USES-FRSR1)
 761      "lsli $frdr,$frsr1,#$imm16"
 762      (+ MSYS_NO OPC_LSL IMM_YES frsr1 frdr imm16)
 763      (set frdr (sll frsr1 imm16))
 764      ()
 765 )
 766
 767 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
 768      (USES-FRDRRR USES-FRSR1 USES-FRSR2)
 769      "lsr $frdrrr,$frsr1,$frsr2"
 770      (+ MSYS_NO OPC_LSR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 771      (set frdrrr (srl frsr1 frsr2))
 772      ()
 773 )
 774
 775 (dni lsri "LSRI DstReg, SrcReg1, UnsImm"
 776      (USES-FRDR USES-FRSR1)
 777      "lsri $frdr,$frsr1,#$imm16"
 778      (+ MSYS_NO OPC_LSR IMM_YES frsr1 frdr imm16)
 779      (set frdr (srl frsr1 imm16))
 780      ()
 781 )
 782
 783 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
 784      (USES-FRDRRR USES-FRSR1 USES-FRSR2)
 785      "asr $frdrrr,$frsr1,$frsr2"
 786      (+ MSYS_NO OPC_ASR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 787      (set frdrrr (sra frsr1 frsr2))
 788      ()
 789 )
 790
 791 (dni asri "ASRI DstReg, SrcReg1, UnsImm"
 792      (USES-FRDR USES-FRSR1)
 793      "asri $frdr,$frsr1,#$imm16"
 794      (+ MSYS_NO OPC_ASR IMM_YES frsr1 frdr imm16)
 795      (set frdr (sra frsr1 imm16))
 796      ()
 797 )
 798
 799 ; Control Transfer Instructions
 800
 801 (dni brlt "BRLT SrcReg1, SrcReg2, label"
 802      (BR-INSN DELAY-SLOT USES-FRDRRR USES-FRSR1 USES-FRSR2)
 803      "brlt $frsr1,$frsr2,$imm16o"
 804      (+ MSYS_NO OPC_BRLT IMM_YES frsr1 frsr2 imm16o)
 805      (sequence()
 806         (if (lt USI frsr1 frsr2)
 807             (dset pc (add pc (ext SI imm16o))))
 808      )
 809      ()
 810 )
 811
 812 (dni brle "BRLE SrcReg1, SrcReg2, label"
 813      (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
 814      "brle $frsr1,$frsr2,$imm16o"
 815      (+ MSYS_NO OPC_BRLE IMM_YES frsr1 frsr2 imm16o)
 816      (sequence()
 817         (if (le USI frsr1 frsr2)
 818             (dset pc (add pc (ext SI imm16o))))
 819      )
 820      ()
 821 )
 822
 823 (dni breq "BREQ SrcReg1, SrcReg2, label"
 824      (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
 825      "breq $frsr1,$frsr2,$imm16o"
 826      (+ MSYS_NO OPC_BREQ IMM_YES frsr1 frsr2 imm16o)
 827      (sequence()
 828         (if (eq USI frsr1 frsr2)
 829             (dset pc (add pc (ext SI imm16o))))
 830      )
 831      ()
 832 )
 833
 834 (dni brne "BRNE SrcReg1, SrcReg2, label"
 835      (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
 836      "brne $frsr1,$frsr2,$imm16o"
 837      (+ MSYS_NO OPC_BRNEQ IMM_YES frsr1 frsr2 imm16o)
 838      (sequence()
 839         (if (not (eq USI frsr1 frsr2))
 840             (dset pc (add pc (ext SI imm16o))))
 841      )
 842      ()
 843 )
 844
 845 (dni jmp "JMP, label"
 846      (DELAY-SLOT BR-INSN)
 847      "jmp $imm16o"
 848      (+ MSYS_NO OPC_JMP IMM_YES (f-uu4b 0) (f-uu4a 0) imm16o)
 849      (dset pc (add pc (ext SI imm16o)))
 850      ()
 851 )
 852
 853 (dni jal "JAL DstReg, SrcReg1"
 854      (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1)
 855      "jal $frdrrr,$frsr1"
 856      (+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0))
 857      (sequence()
 858          (if (eq frsr1 #x0)
 859             (c-call VOID "do_syscall" pc)
 860             (sequence()   ; else part.  Do non-syscall stuff here.
 861                 (dset frdrrr (add pc #x8))
 862                 (dset pc frsr1)
 863             )
 864          )
 865      )
 866      ()
 867 )
 868
 869 (dni dbnz "DBNZ SrcReg1, label"
 870      (MACHMS1-003 BR-INSN DELAY-SLOT USES-FRSR1)
 871      "dbnz $frsr1,$imm16o"
 872      (+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o)
 873      (sequence()
 874          (if (not (eq USI frsr1 0))
 875             (dset pc (add pc (ext SI imm16o))))
 876      )
 877      ()
 878 )
 879
 880 ; Interrupt Control Instructions
 881
 882 (dni ei "EI - Enable Interrupt Processing"
 883      ()
 884      "ei"
 885      (+ MSYS_NO OPC_EI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
 886      (c-call VOID "enable_interrupts")
 887      ()
 888 )
 889
 890 (dni di "DI - Disable Interrupt Processing"
 891      ()
 892      "di"
 893      (+ MSYS_NO OPC_DI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
 894      (c-call VOID "disable_interrupts")
 895      ()
 896 )
 897
 898 (dni si "SI - Send software Interrupt"
 899      (DELAY-SLOT BR-INSN USES-FRDR)
 900      "si $frdrrr"
 901      (+ MSYS_NO OPC_SI IMM_NO (f-uu4b 0) (f-uu4a 0) frdrrr (f-uu12 0))
 902      ;(sequence()
 903      ;   (dset frdr (add pc #x4))
 904      ;   (c-call VOID "do_syscall1" pc)
 905      ;   ; (dset pc frsr1) Do this later when we have the address.
 906      ;)
 907      (sequence()
 908         (set frdrrr (add pc #x4))
 909         (c-call VOID "do_syscall" pc)
 910         ; (set pc frsr1) Do this later when we have the address.
 911      )
 912      ()
 913 )
 914
 915 (dni reti "RETI SrcReg1"
 916      (DELAY-SLOT BR-INSN USES-FRSR1)
 917      "reti $frsr1"
 918      (+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0))
 919      (sequence()
 920        (c-call VOID "enable_interrupts")
 921        (dset pc frsr1)
 922      )
 923      ()
 924 )
 925
 926 ; Memory Access Instructions
 927
 928 (dni ldw "LDW DstReg, SrcReg1, Imm"
 929      (LOAD-DELAY MEMORY-ACCESS USES-FRDR USES-FRSR1)
 930      "ldw $frdr,$frsr1,#$imm16"
 931      (+ MSYS_NO OPC_LDW IMM_YES frsr1 frdr imm16)
 932      (sequence((USI ea) (HI tmp))
 933       (set HI tmp (and imm16 #xffff))
 934       (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
 935       (set frdr (mem SI ea))
 936      )
 937      ()
 938 )
 939
 940 (dni stw "STW SrcReg2, SrcReg1, Imm"
 941      (MEMORY-ACCESS USES-FRSR1 USES-FRSR2)
 942      "stw $frsr2,$frsr1,#$imm16"
 943      (+ MSYS_NO OPC_STW IMM_YES frsr1 frsr2 imm16)
 944      (sequence((USI ea) (HI tmp))
 945       (set HI tmp (and imm16 #xffff))
 946       (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
 947       (set (mem SI ea) frsr2)
 948      )
 949      ()
 950 )
 951
 952 ; Break Instruction
 953
 954 (dni break "BREAK"
 955      ()
 956      "break"
 957      (+ MSYS_NO OPC_BREAK (f-imm 0) (f-uu24 0))
 958      (c-call VOID "do_break" pc)
 959      ()
 960 )
 961
 962 ; Cache Flush Instruction
 963
 964 (dni iflush "IFLUSH"
 965      (MACHMS1-003)
 966      "iflush"
 967      (+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0))
 968      (nop)
 969      ()
 970 )
 971
 972 ; MorphoSys Instructions
 973
 974 (dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#"
 975      ()
 976      "ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum"
 977      (+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0)
 978         contnum )
 979      (nop)
 980      ()
 981 )
 982
 983 (dni ldfb "LDFB SRC1, byte#"
 984      ()
 985      "ldfb $frsr1,$frsr2,#$imm16z"
 986      (+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
 987      (nop)
 988      ()
 989 )
 990
 991 (dni stfb "STFB SRC1, SRC2, byte "
 992      ()
 993      "stfb $frsr1,$frsr2,#$imm16z"
 994      (+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
 995      (nop)
 996      ()
 997 )
 998
 999 (dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
1000      ()
1001      "fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1002      (+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp)
1003      (nop)
1004      ()
1005 )
1006
1007 (dni mfbcb "MFBCB SRC1, RT/BR1/BR2/CS, SRC2, r/c, CB/RB, cell, dup, ctx_disp"
1008      ()
1009      "mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1010      (+ MSYS_YES MSOPC_MFBCB rbbc frsr1 frsr2 (f-uu-4-15 0) rc1 cbrb cell dup ctxdisp)
1011      (nop)
1012      ()
1013 )
1014
1015 (dni fbcci "FBCCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1016      ()
1017      "fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1018      (+ MSYS_YES MSOPC_FBCCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1019      (nop)
1020      ()
1021 )
1022
1023 (dni fbrci "FBRCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1024      ()
1025      "fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1026      (+ MSYS_YES MSOPC_FBRCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1027      (nop)
1028      ()
1029 )
1030
1031 (dni fbcri "FBCRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1032      ()
1033      "fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1034      (+ MSYS_YES MSOPC_FBCRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1035      (nop)
1036      ()
1037 )
1038
1039 (dni fbrri "FBRRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1040      ()
1041      "fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1042      (+ MSYS_YES MSOPC_FBRRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1043      (nop)
1044      ()
1045 )
1046
1047 (dni mfbcci "MFBCCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1048      ()
1049      "mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1050      (+ MSYS_YES MSOPC_MFBCCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1051      (nop)
1052      ()
1053 )
1054
1055 (dni mfbrci "MFBRCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1056      ()
1057      "mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1058      (+ MSYS_YES MSOPC_MFBRCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1059      (nop)
1060      ()
1061 )
1062
1063 (dni mfbcri "MFBCRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1064      ()
1065      "mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1066      (+ MSYS_YES MSOPC_MFBCRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1067      (nop)
1068      ()
1069 )
1070
1071 (dni mfbrri "MFBRRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1072      ()
1073      "mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1074      (+ MSYS_YES MSOPC_MFBRRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1075      (nop)
1076      ()
1077 )
1078
1079 (dni fbcbdr "FBCBDR SRC1, RT/BR1/BR2/CS, SRC2, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
1080      ()
1081      "fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1082      (+ MSYS_YES MSOPC_FBCBDR rbbc frsr1 frsr2 ball2 brc2 rc1 cbrb cell dup ctxdisp)
1083      (nop)
1084      ()
1085 )
1086
1087 (dni rcfbcb "RCFBCB RT/BR1/BR2/CS, type, B_all, B_r_c, row#, r/c, CB/RB, cell, dup, ctx_disp"
1088      ()
1089      "rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1090      (+ MSYS_YES MSOPC_RCFBCB rbbc (f-uu-2-23 0) type ball brc (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
1091      (nop)
1092      ()
1093 )
1094
1095 (dni mrcfbcb "MRCFBCB SRC2, RT/BR1/BR2/CS, type, row#, r/c, CB/RB, cell, dup, ctx_disp"
1096      ()
1097      "mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1098      (+ MSYS_YES MSOPC_MRCFBCB rbbc (f-uu-2-23 0) type frsr2 (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
1099      (nop)
1100      ()
1101 )
1102
1103 (dni cbcast "CBCAST mask, r/c, ctx_disp "
1104      ()
1105      "cbcast #$mask,#$rc2,#$ctxdisp"
1106      (+ MSYS_YES MSOPC_CBCAST mask (f-uu-3-9 0) rc2 ctxdisp)
1107      (nop)
1108      ()
1109 )
1110
1111 (dni dupcbcast "DUPCBCAST mask, cell, r/c, ctx_disp "
1112      ()
1113      "dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp"
1114      (+ MSYS_YES MSOPC_DUPCBCAST mask cell rc2 ctxdisp)
1115      (nop)
1116      ()
1117 )
1118
1119 (dni wfbi "WFBI Bank_address, row#, cell, dup, ctx_disp "
1120      ()
1121     "wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp"
1122      (+ MSYS_YES MSOPC_WFBI bankaddr rownum1 cell dup ctxdisp)
1123      (nop)
1124      ()
1125 )
1126
1127 ;(dni wfb "WFB SRC1, SRC2, FB_disp, row#, ctx_disp"
1128 ;     ()
1129 ;     "wfb $frsr1,$frsr2,#$fbdisp,#$rownum,#$ctxdisp"
1130 ;     (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum (f-uu-1-6 0) ctxdisp)
1131 ;     (nop)
1132 ;     ()
1133 ;)
1134
1135 (dni wfb "WFB, DRC1,SRC2,FB_disp,row#,ctx_disp"
1136       ()
1137       "wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp"
1138       (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum2 (f-uu-1-6 0) ctxdisp)
1139       (nop)
1140       ()
1141 )
1142
1143
1144 (dni rcrisc "RCRISC DEST, RT/BR1/BR2/CS, SRC1, column#, r/c, CB/RB, cell, dup, ctx_disp"
1145      ()
1146      "rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1147      (+ MSYS_YES MSOPC_RCRISC rbbc frsr1 (f-uu-1-19 0) colnum frdrrr rc1 cbrb cell dup ctxdisp)
1148      (nop)
1149      ()
1150 )
1151
1152 (dni fbcbinc "FBCBINC SRC1, RT/BR1/BR2/CS, Incr_amount, r/c, CB/RB, cell, dup, ctx_disp "
1153      ()
1154      "fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1155      (+ MSYS_YES MSOPC_FBCBINC rbbc frsr1 incamt rc1 cbrb cell dup ctxdisp)
1156      (nop)
1157      ()
1158 )
1159
1160 (dni rcxmode "RCXMODE SRC2, rd, wr, xmode, mask, FB_disp, row#, r/c, ctx_disp"
1161      ()
1162      "rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp"
1163      (+ MSYS_YES MSOPC_RCXMODE rda wr xmode mask1 frsr2 fbdisp rownum2 rc2 ctxdisp)
1164      (nop)
1165      ()
1166 )
1167
1168 (dni interleaver "INTLVR ireg, mode, ireg, i/d, size"
1169      ()
1170      "intlvr $frsr1,#$mode,$frsr2,#$id,#$size"
1171      (+ MSYS_YES MSOPC_INTLVR mode frsr1 frsr2 (f-uu-1-15 0) id size)
1172      (nop)
1173      ()
1174 )
1175
1176 ;; Issue 66262: The documenatation gives the wrong order for
1177 ;;               the arguments to the WFBINC instruction.
1178 (dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp"
1179      (MACHMS1-003)
1180      "wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1181      (+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp)
1182      (nop)
1183      ()
1184 )
1185
1186 (dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp"
1187      (MACHMS1-003)
1188      "mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1189      (+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp)
1190      (nop)
1191      ()
1192 )
1193
1194 (dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp"
1195      (MACHMS1-003)
1196      "wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1197      (+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp)
1198      (nop)
1199      ()
1200 )
1201
1202 (dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp"
1203      (MACHMS1-003)
1204      "mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1205      (+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp)
1206      (nop)
1207      ()
1208 )
1209
1210 (dni fbcbincs "FBCBINCS      perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1211      (MACHMS1-003)
1212      "fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1213      (+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp)
1214      (nop)
1215      ()
1216 )
1217
1218 (dni mfbcbincs "MFBCBINCS               ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1219      (MACHMS1-003)
1220      "mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1221      (+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp)
1222      (nop)
1223      ()
1224 )
1225
1226 (dni fbcbincrs "FBCBINCRS            ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1227      (MACHMS1-003)
1228      "fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1229      (+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
1230      (nop)
1231      ()
1232 )
1233
1234 (dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1235      (MACHMS1-003)
1236      "mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1237      (+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
1238      (nop)
1239      ()
1240 )