cpu/mt.cpu

   1 ; Morpho Technologies MT Arch description.  -*- Scheme -*-
   2 ; Copyright 2001 Free Software Foundation, Inc.
   3 ;
   4 ; Contributed by Red Hat Inc; developed under contract from
   5 ; Morpho Technologies.
   6 ;
   7 ; This file is part of the GNU Binutils.
   8 ;
   9 ; This program is free software; you can redistribute it and/or modify
  10 ; it under the terms of the GNU General Public License as published by
  11 ; the Free Software Foundation; either version 2 of the License, or
  12 ; (at your option) any later version.
  13 ;
  14 ; This program is distributed in the hope that it will be useful,
  15 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ; GNU General Public License for more details.
  18 ;
  19 ; You should have received a copy of the GNU General Public License
  20 ; along with this program; if not, write to the Free Software
  21 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 (include "simplify.inc")
  24
  25 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  26 ;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;;
  27 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  28
  29 ; define-arch must appear first
  30 (define-arch
  31   (name mt) ; name of cpu family
  32   (comment "Morpho Technologies mRISC family")
  33   (default-alignment aligned)
  34   (insn-lsb0? #t)
  35   (machs ms1 ms1-003 ms2)
  36   (isas mt)
  37 )
  38
  39 ; Instruction set parameters.
  40
  41 (define-isa
  42   (name mt)
  43   (comment "Morpho Technologies MT ISA")
  44   (default-insn-word-bitsize 32)
  45   (default-insn-bitsize 32)
  46   (base-insn-bitsize 32)
  47   (parallel-insns 2)
  48 )
  49 \f
  50 ; Cpu family definitions.
  51
  52
  53 (define-cpu
  54   ; cpu names must be distinct from the architecture name and machine names.
  55   (name ms1bf)
  56   (comment "Morpho Technologies mRISC family")
  57   (endian big)
  58   (word-bitsize 32)
  59 )
  60
  61 (define-cpu
  62   ; cpu names must be distinct from the architecture name and machine names.
  63   (name ms1-003bf)
  64   (comment "Morpho Technologies mRISC family")
  65   (endian big)
  66   (word-bitsize 32)
  67 )
  68
  69 (define-cpu
  70   ; cpu names must be distinct from the architecture name and machine names.
  71   (name ms2bf)
  72   (comment "Morpho Technologies mRISC family")
  73   (endian big)
  74   (word-bitsize 32)
  75 )
  76
  77 (define-mach
  78   (name ms1)
  79   (comment "Morpho Technologies mrisc")
  80   (cpu ms1bf)
  81   (isas mt)
  82 )
  83
  84 (define-mach
  85   (name ms1-003)
  86   (comment "Morpho Technologies mrisc")
  87   (cpu ms1-003bf)
  88   (isas mt)
  89 )
  90
  91 (define-mach
  92   (name ms2)
  93   (comment "Morpho Technologies ms2")
  94   (cpu ms2bf)
  95   (isas mt)
  96 )
  97
  98 \f
  99 ; Model descriptions.
 100 ; Can probably take the u-exec out.  We'll see.
 101 (define-model
 102   (name ms1)
 103   (comment "Morpho Technologies mrisc")
 104   (mach ms1)
 105   (unit u-exec "Execution Unit" ()
 106         1 1 ; issue done
 107         () ; state
 108         () ; inputs
 109         () ; outputs
 110         () ; profile action (default)
 111         )
 112 )
 113
 114 (define-model
 115   (name ms1-003)
 116   (comment "Morpho Technologies mrisc")
 117   (mach ms1-003)
 118   (unit u-exec "Execution Unit" ()
 119         1 1 ; issue done
 120         () ; state
 121         () ; inputs
 122         () ; outputs
 123         () ; profile action (default)
 124         )
 125 )
 126
 127 (define-model
 128   (name ms2)
 129   (comment "Morpho Technologies ms2")
 130   (mach ms2)
 131   (unit u-exec "Execution Unit" ()
 132         1 1 ; issue done
 133         () ; state
 134         () ; inputs
 135         () ; outputs
 136         () ; profile action (default)
 137         )
 138 )
 139
 140 ; FIXME: It might simplify things to separate the execute process from the
 141 ; one that updates the PC.
 142 \f
 143
 144 ;;;;;;;;;;;;;;;;;;;;;;;;
 145 ;; Instruction Fields ;;
 146 ;;;;;;;;;;;;;;;;;;;;;;;;
 147
 148 ; Attributes:
 149 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
 150 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
 151 ; RESERVED: bits are not used to decode insn, must be all 0
 152 ; RELOC: there is a relocation associated with this field (experiment)
 153 ;
 154 ; f-msys: Identify a a morphosys insns.  1 if msys, 0 if not.
 155 ; f-opc: 6 bit opcode for non-morphosys instructions.
 156 ; f-msopc: 6 bit opcode for morphosys instructions.
 157 ; f-imm: flag to indicate use of an immediate operand.  1 if yes, 0 if no.
 158 ; f-sr1: source resgister 1. (also used for MSYS insns)
 159 ; f-sr2: source register 2. (also used for MSYS insns)
 160 ; f-dr: destination register when located in bits 19:16.
 161 ; f-drrr: destination register when located in bits 15:12. (also for MSYS insns)
 162 ; f-imm16: 16 bit immediate value when not an offset.
 163 ; f-imm16a: 16 bit immediate value when it's a pc-rel offset.
 164 ; f-uu4a: unused 4 bit field.
 165 ; f-uu4b: second unsed 4 bit field.
 166 ; f-uu1: unused 1 bit field
 167 ; f-uu12: unused 12 bit field.
 168 ; f-uu16: unused 16 bit field.
 169 ; f-uu24: unused 24 bit field.
 170
 171 (dnf f-msys      "morphosys insn flag"          () 31 1)
 172 (dnf f-opc       "opcode field"                 () 30 6)
 173 (dnf f-imm       "immedate flag"                () 24 1)
 174 (dnf f-uu24      "unused 24 bits"               () 23 24)
 175 (dnf f-sr1       "sr1 register field"   (ABS-ADDR) 23 4)
 176 (dnf f-sr2       "sr2 register field"   (ABS-ADDR) 19 4)
 177 (dnf f-dr        "dr register field"    (ABS-ADDR) 19 4)
 178 (dnf f-drrr      "drrr register field"  (ABS-ADDR) 15 4)
 179 (dnf f-imm16u    "unsigned 16 bit immediate"    () 15 16)
 180 (df  f-imm16s    "signed 16 bit immediate"      () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0)))
 181 (dnf f-imm16a    "pc-rel offset"      (PCREL-ADDR) 15 16)
 182 (dnf f-uu4a      "unused 4 bit field"           () 19 4)
 183 (dnf f-uu4b      "unused 4 bit field"           () 23 4)
 184 (dnf f-uu12      "unused 12 bit field"          () 11 12)
 185 (dnf f-uu8       "unused 8 bit field"           () 15 8)
 186 (dnf f-uu16      "unused 16 bit field"          () 15 16)
 187 (dnf f-uu1       "unused 1 bit field"           ()  7 1)
 188
 189 ; The following ifields are used exclusively for the MorphoSys instructions.
 190 ; In a few cases, a bit field is used for something in addition to what its
 191 ; name suggests.  For the most part, the names are meaningful though.
 192
 193 (dnf f-msopc     "opcode field"                 () 30 5)
 194 (dnf f-uu-26-25  "unused 26 bits"               () 25 26)
 195 (dnf f-mask      "mask"                         () 25 16)
 196 (dnf f-bankaddr  "bank address"                 () 25 13)
 197 (dnf f-rda       "rda"                          () 25 1)
 198 (dnf f-uu-2-25   "unused bits  25 & 24"         () 25 2)
 199 (dnf f-rbbc      "Omega network configuration"  () 25 2)
 200 (dnf f-perm      "perm"                         () 25 2)
 201 (dnf f-mode      "mode"                         () 25 2)
 202 (dnf f-uu-1-24   "testing"                      () 24 1)
 203 (dnf f-wr        "wr"                           () 24 1)
 204 (dnf f-fbincr    "fb incr"                      () 23 4)
 205 (dnf f-uu-2-23   "unused bits 23 and 22"        () 23 2)
 206 (dnf f-xmode     "xmode"                        () 23 1)
 207 (dnf f-a23       "a23"                          () 23 1)
 208 (dnf f-mask1     "mask1"                        () 22 3)
 209 (dnf f-cr        "cr"                           () 22 3)
 210 (dnf f-type      "type"                         () 21 2)
 211 (dnf f-incamt    "increment amount"             () 19 8)
 212 (dnf f-cbs       "cbs"                          () 19 2)
 213 (dnf f-uu-1-19   "unused bit 19"                () 19 1)
 214 (dnf f-ball      "b_all"                        () 19 1)
 215 (dnf f-colnum    "column number"                () 18 3)
 216 (dnf f-brc       "b_r_c"                        () 18 3)
 217 (dnf f-incr      "incr"                         () 17 6)
 218 (dnf f-fbdisp    "frame buffer displacement"    () 15 6)
 219 (dnf f-uu-4-15   "unused bits 15,14,13,12"      () 15 4)
 220 (dnf f-length    "length"                       () 15 3)
 221 (dnf f-uu-1-15   "unused bit 15"                () 15 1)
 222 (dnf f-rc        "row/column context"           () 15 1)
 223 (dnf f-rcnum     "starting cell of cntxt mem."  () 14 3)
 224 (dnf f-rownum    "row number"                   () 14 3)
 225 (dnf f-cbx       "cbx"                          () 14 3)
 226 (dnf f-id        "id"                           () 14 1)
 227 (dnf f-size      "size"                         () 13 14)
 228 (dnf f-rownum1   "row number"                   () 12 3)
 229 (dnf f-uu-3-11   "unused 3 bits (11-9)"         () 11 3)
 230 (dnf f-rc1       "row/column context"           () 11 1)
 231 (dnf f-ccb       "ccb"                          () 11 1)
 232 (dnf f-cbrb      "data-bus orientation"         () 10 1)
 233 (dnf f-cdb       "cdb"                          () 10 1)
 234 (dnf f-rownum2   "row number"                   ()  9 3)
 235 (dnf f-cell      "cell"                         ()  9 3)
 236 (dnf f-uu-3-9    "unused 3 bits (9-7)"          ()  9 3)
 237 (dnf f-contnum   "context number"               ()  8 9)
 238 (dnf f-uu-1-6    "unused bit 6"                 ()  6 1)
 239 (dnf f-dup       "dup"                          ()  6 1)
 240 (dnf f-rc2       "rc2"                          ()  6 1)
 241 (dnf f-ctxdisp   "context displacement"         ()  5 6)
 242
 243 ; additional fields in ms2
 244 (dnf f-imm16l    "loop count"                   () 23 16)
 245 (df  f-loopo     "loop offset"                  () 7 8 UINT
 246     ((value pc) (srl SI value 2))
 247     ((value pc) (add SI (sll value 2) 8))
 248  )
 249 (dnf f-cb1sel    "cb1 select"                   () 25 3)
 250 (dnf f-cb2sel    "cb2 select"                   () 22 3)
 251 (dnf f-cb1incr   "cb1 increment"                (SIGNED) 19 6)
 252 (dnf f-cb2incr   "cb2 increment"                (SIGNED) 13 6)
 253 (dnf f-rc3       "row/colum context"            ()  7 1)
 254
 255 ; The following is just for a test
 256 (dnf f-msysfrsr2 "sr2 for msys"                 () 19 4)
 257 (dnf f-brc2      "b_r_c2"                       () 14 3)
 258 (dnf f-ball2     "b_all2"                       () 15 1)
 259
 260 \f
 261 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 262 ;; Enumerations Of Instruction Fields ;;
 263 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 264
 265 ; insn-msys: bit 31.  1 for Morphosys Insns, 0 if not.
 266 (define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys
 267   (NO YES)
 268 )
 269
 270 ; insn-opc: bits 30 through 25 .  Non-MorphoSys Instructions
 271 ; Note - the documentation is wrong for the encoding of the DBNZ
 272 ; instruction.  It is actually 011110.  See Issue 67699.
 273 (define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc
 274   (ADD  ADDU SUB  SUBU MUL   -      -    -
 275    AND  OR   XOR  NAND NOR   XNOR   LDUI -
 276    LSL  LSR  ASR  -    -     -      -    -
 277    BRLT BRLE BREQ JMP  JAL   BRNEQ  DBNZ LOOP
 278    LDW  STW  -    -    -     -      -    -
 279    -    -    -    -    -     -      -    -
 280    EI   DI   SI   RETI BREAK IFLUSH -    -
 281   )
 282 )
 283
 284 ; insn-msopc: bits 30 through 26 .  MorphoSys Instructions
 285 (define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc
 286   (LDCTXT LDFB      STFB    FBCB     MFBCB    FBCCI     FBRCI     FBCRI
 287    FBRRI  MFBCCI    MFBRCI  MFBCRI   MFBRRI   FBCBDR    RCFBCB    MRCFBCB
 288    CBCAST DUPCBCAST WFBI    WFB      RCRISC   FBCBINC   RCXMODE   INTLVR
 289    WFBINC MWFBINC   WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS
 290    -      -         -       -        -        -         -         -
 291   )
 292 )
 293
 294 ; insn-imm: bit 24.  Immediate operand indicator.
 295 (define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm
 296   ; This bit specifies whether and immediate operand will be present.
 297   ; It's 1 if there is, 0 if there is not.
 298   (NO YES)
 299 )
 300 ;;;;;;;;;;;;;;;;
 301 ;; Attributes ;;
 302 ;;;;;;;;;;;;;;;;
 303
 304 ; Might not need this.  Keep if for the sim just in case.
 305 ;(define-attr
 306 ;  (for insn)
 307 ;  (type boolean)
 308 ;  (name EXT-SKIP-INSN)
 309 ;  (comment "instruction is a PAGE, LOADL or LOADH instruction")
 310 ;)
 311
 312 (define-attr
 313   (for insn)
 314   (type boolean)
 315   (name LOAD-DELAY)
 316   (comment "insn has a load delay")
 317 )
 318
 319 (define-attr
 320   (for insn)
 321   (type boolean)
 322   (name MEMORY-ACCESS)
 323   (comment "insn performs a memory access")
 324 )
 325
 326 (define-attr
 327   (for insn)
 328   (type boolean)
 329   (name AL-INSN)
 330   (comment "insn is an arithmetic or logic insn.")
 331 )
 332
 333 (define-attr
 334   (for insn)
 335   (type boolean)
 336   (name IO-INSN)
 337   (comment "insn performs an I/O operation")
 338 )
 339
 340 (define-attr
 341   (for insn)
 342   (type boolean)
 343   (name BR-INSN)
 344   (comment "insn performs an I/O operation")
 345 )
 346
 347 (define-attr
 348   (for insn)
 349   (type boolean)
 350   (name JAL-HAZARD)
 351   (comment "insn has jal-like hazard")
 352 )
 353
 354 (define-pmacro (define-reg-use-attr regfield)
 355   (define-attr
 356     (for insn)
 357     (type boolean)
 358     (name (.sym "USES-" (.upcase regfield)))
 359     (comment ("insn accesses register operand " regfield))))
 360
 361 (define-reg-use-attr "frdr")
 362 (define-reg-use-attr "frdrrr")
 363 (define-reg-use-attr "frsr1")
 364 (define-reg-use-attr "frsr2")
 365
 366
 367 ; Might not need this.  Keep it for the sim just in case.
 368 (define-attr
 369   (for insn)
 370   (type boolean)
 371   (name SKIPA)
 372   (comment "instruction is a SKIP instruction")
 373 )
 374
 375
 376 ;;;;;;;;;;;;;;;;;;;;;
 377 ;; Hardware Pieces ;;
 378 ;;;;;;;;;;;;;;;;;;;;;
 379
 380 ;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n))
 381
 382 ; These are the 16 registers that the chip has.  In later versions
 383 ; where there will be more registers, this will need to be expanded.
 384 ; Note that there are two entries for the registers with two names.
 385 (define-hardware
 386   (name h-spr)
 387   (comment "special-purpose registers")
 388   (type register SI (16))
 389   (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5)
 390   ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12)
 391   ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15)))
 392 ;  (get (index) (and (raw-reg h-spr) #xffffffff))
 393 ;  (set (index value) (set (raw-reg h-spr) (and value #xffffffff)))
 394 )
 395
 396 ; This is the  program counter.
 397 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
 398
 399 (define-keyword
 400    (name msys-syms)
 401    (print-name h-nil)
 402    (prefix "")
 403    (values (DUP 1) (XX 0))
 404 )
 405
 406 ;;;;;;;;;;;;;;
 407 ;; Operands ;;
 408 ;;;;;;;;;;;;;;
 409
 410 (define-operand (name frsr1) (comment "register") (attrs)
 411   (type h-spr) (index f-sr1) )
 412 (define-operand (name frsr2) (comment "register") (attrs)
 413   (type h-spr) (index f-sr2) )
 414 (define-operand (name frdr) (comment "register") (attrs)
 415   (type h-spr) (index f-dr) )
 416 (define-operand (name frdrrr) (comment "register") (attrs)
 417   (type h-spr) (index f-drrr) )
 418 (define-operand (name imm16) (comment "immediate value - sign extd") (attrs)
 419   (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex")))
 420 (define-operand (name imm16z) (comment "immediate value - zero extd") (attrs)
 421   (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex")))
 422 (define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR)
 423   (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel")))
 424
 425 ; Operands for MorphoSys Instructions
 426
 427 (define-operand (name rc) (comment "rc") (attrs)
 428   (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex")))
 429
 430 (define-operand (name rcnum) (comment "rcnum") (attrs)
 431   (type h-uint) (index f-rcnum) (handlers (print "dollarhex")))
 432
 433 (define-operand (name contnum) (comment "context number") (attrs)
 434   (type h-uint) (index f-contnum) (handlers (print "dollarhex")))
 435
 436 (define-operand (name rbbc) (comment "omega network configuration") (attrs)
 437   (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex")))
 438
 439 (define-operand (name colnum) (comment "column number") (attrs)
 440   (type h-uint) (index f-colnum) (handlers (print "dollarhex")))
 441
 442 (define-operand (name rownum) (comment "row number") (attrs)
 443   (type h-uint) (index f-rownum) (handlers (print "dollarhex")))
 444
 445 (define-operand (name rownum1) (comment "row number") (attrs)
 446   (type h-uint) (index f-rownum1) (handlers (print "dollarhex")))
 447
 448 (define-operand (name rownum2) (comment "row number") (attrs)
 449   (type h-uint) (index f-rownum2) (handlers (print "dollarhex")))
 450
 451 (define-operand (name rc1) (comment "rc1") (attrs)
 452   (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex")))
 453
 454 (define-operand (name rc2) (comment "rc2") (attrs)
 455   (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex")))
 456
 457 (define-operand (name cbrb) (comment "data-bus orientation") (attrs)
 458   (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex")))
 459
 460 (define-operand (name cell) (comment "cell") (attrs)
 461   (type h-uint) (index f-cell) (handlers (print "dollarhex")))
 462
 463 (define-operand (name dup) (comment "dup") (attrs)
 464   (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex")))
 465
 466 (define-operand (name ctxdisp) (comment "context displacement") (attrs)
 467   (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex")))
 468
 469 (define-operand (name fbdisp) (comment "frame buffer displacement") (attrs)
 470   (type h-uint) (index f-fbdisp) (handlers (print "dollarhex")))
 471
 472 (define-operand (name type) (comment "type") (attrs)
 473   (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex")))
 474
 475 (define-operand (name mask) (comment "mask") (attrs)
 476   (type h-uint) (index f-mask) (handlers (print "dollarhex")))
 477
 478 (define-operand (name bankaddr) (comment "bank address") (attrs)
 479   (type h-uint) (index f-bankaddr) (handlers (print "dollarhex")))
 480
 481 (define-operand (name incamt) (comment "increment amount") (attrs)
 482   (type h-uint) (index f-incamt) (handlers (print "dollarhex")))
 483
 484 (define-operand (name xmode) (comment "xmode") (attrs)
 485   (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex")))
 486
 487 (define-operand (name mask1) (comment "mask1") (attrs)
 488   (type h-uint) (index f-mask1) (handlers (print "dollarhex")))
 489
 490 (define-operand (name ball) (comment "b_all") (attrs)
 491   (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex")))
 492
 493 (define-operand (name brc) (comment "b_r_c") (attrs)
 494   (type h-uint) (index f-brc) (handlers (print "dollarhex")))
 495
 496 (define-operand (name rda) (comment "rd") (attrs)
 497   (type h-uint) (index f-rda) (handlers (print "dollarhex")))
 498
 499 (define-operand (name wr) (comment "wr") (attrs)
 500   (type h-uint) (index f-wr) (handlers (print "dollarhex")))
 501
 502 (define-operand (name ball2) (comment "b_all2") (attrs)
 503   (type h-uint) (index f-ball2) (handlers (parse "ball") (print "dollarhex")))
 504
 505 (define-operand (name brc2) (comment "b_r_c2") (attrs)
 506   (type h-uint) (index f-brc2) (handlers (print "dollarhex")))
 507 (define-operand (name perm) (comment "perm") (attrs)
 508   (type h-uint) (index f-perm) (handlers (print "dollarhex")))
 509 (define-operand (name a23)   (comment "a23") (attrs)
 510   (type h-uint) (index f-a23) (handlers (print "dollarhex")))
 511 (define-operand (name cr)   (comment "c-r") (attrs)
 512   (type h-uint) (index f-cr) (handlers (print "dollarhex")))
 513 (define-operand (name cbs)      (comment "cbs") (attrs)
 514   (type h-uint) (index f-cbs) (handlers (print "dollarhex")))
 515 (define-operand (name incr)     (comment "incr") (attrs)
 516   (type h-uint) (index f-incr) (handlers (print "dollarhex")))
 517 (define-operand (name length)   (comment "length") (attrs)
 518   (type h-uint) (index f-length) (handlers (print "dollarhex")))
 519 (define-operand (name cbx)      (comment "cbx") (attrs)
 520   (type h-uint) (index f-cbx) (handlers (print "dollarhex")))
 521 (define-operand (name ccb)      (comment "ccb") (attrs)
 522   (type h-uint) (index f-ccb) (handlers (print "dollarhex")))
 523 (define-operand (name cdb)      (comment "cdb") (attrs)
 524   (type h-uint) (index f-cdb) (handlers (print "dollarhex")))
 525
 526 ; For the INTLVR insn
 527 (define-operand (name mode) (comment "mode") (attrs)
 528   (type h-uint) (index f-mode) (handlers (print "dollarhex")))
 529 (define-operand (name id) (comment "i/d") (attrs)
 530   (type h-uint) (index f-id) (handlers (print "dollarhex")))
 531 (define-operand (name size) (comment "size") (attrs)
 532   (type h-uint) (index f-size) (handlers (print "dollarhex")))
 533
 534 (define-operand (name fbincr)   (comment "fb incr") (attrs)
 535   (type h-uint) (index f-fbincr) (handlers (print "dollarhex")))
 536
 537 ; For the ms2 insns
 538 (define-operand (name loopsize) (comment "immediate value")
 539   (attrs (MACH ms2) PCREL-ADDR)
 540   (type h-uint) (index f-loopo) (handlers (parse "loopsize") (print "pcrel")))
 541 (define-operand (name imm16l) (comment "immediate value")
 542   (attrs (MACH ms2))
 543   (type h-uint) (index f-imm16l) (handlers (print "dollarhex")))
 544 (define-operand (name rc3) (comment "rc3") (attrs (MACH ms2))
 545   (type h-uint) (index f-rc3) (handlers (parse "rc") (print "dollarhex")))
 546 (define-operand (name cb1sel) (comment "cb1sel") (attrs (MACH ms2))
 547   (type h-uint) (index f-cb1sel) (handlers (print "dollarhex")))
 548 (define-operand (name cb2sel) (comment "cb2sel") (attrs (MACH ms2))
 549   (type h-uint) (index f-cb2sel) (handlers (print "dollarhex")))
 550 (define-operand (name cb1incr) (comment "cb1incr") (attrs (MACH ms2))
 551   (type h-sint) (index f-cb1incr) (handlers (print "dollarhex")))
 552 (define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2))
 553   (type h-sint) (index f-cb2incr) (handlers (print "dollarhex")))
 554
 555 ; Probaby won't need most of these.
 556 (define-pmacro r0    (reg h-spr #x0))
 557 (define-pmacro r1    (reg h-spr #x01))
 558 (define-pmacro r2    (reg h-spr #x02))
 559 (define-pmacro r3    (reg h-spr #x03))
 560 (define-pmacro r4    (reg h-spr #x04))
 561 (define-pmacro r5    (reg h-spr #x05))
 562 (define-pmacro r6    (reg h-spr #x06))
 563 (define-pmacro r7    (reg h-spr #x07))
 564 (define-pmacro r8    (reg h-spr #x08))
 565 (define-pmacro r9    (reg h-spr #x09))
 566 (define-pmacro r10   (reg h-spr #xA))
 567 (define-pmacro r11   (reg h-spr #xB))
 568 (define-pmacro r12   (reg h-spr #xC))
 569 (define-pmacro fp    (reg h-spr #xC))
 570 (define-pmacro r13   (reg h-spr #xD))
 571 (define-pmacro sp    (reg h-spr #xD))
 572 (define-pmacro r14   (reg h-spr #xE))
 573 (define-pmacro ra    (reg h-spr #xE))
 574 (define-pmacro r15   (reg h-spr #xF))
 575 (define-pmacro ira   (reg h-spr #xF))
 576
 577 ; delayed set
 578 (define-pmacro (dset dest src) (set (delay 1 dest) src))
 579
 580
 581 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 582 ;; Instructions As Defined In the MorphoRisc ISA Document ;;
 583 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 584
 585 ; Arithmetic Instructions
 586
 587 (dni add "ADD DstReg, SrcReg1, SrcReg2"
 588      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 589      "add $frdrrr,$frsr1,$frsr2"
 590      (+ MSYS_NO OPC_ADD IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 591      (set frdrrr (add SI frsr1 frsr2))
 592      ()
 593 )
 594
 595 (dni addu "ADDU DstReg, SrcReg1, SrcReg2"
 596      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 597      "addu $frdrrr,$frsr1,$frsr2"
 598      (+ MSYS_NO OPC_ADDU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 599      (set frdrrr (add USI frsr1 frsr2))
 600      ()
 601 )
 602
 603 (dni addi "ADDI DstReg, SrcReg1 UnsImm"
 604      (AL-INSN USES-FRDR USES-FRSR1)
 605      "addi $frdr,$frsr1,#$imm16"
 606      (+ MSYS_NO OPC_ADD IMM_YES frsr1 frdr imm16)
 607      (sequence((HI tmp))
 608         (set HI tmp (and imm16 #xffff))
 609         (set frdr (add SI frsr1 (ext SI tmp)))
 610      )
 611      ()
 612 )
 613
 614 (dni addui "ADDUI DstReg, SrcReg1, UnsImm"
 615      (AL-INSN USES-FRDR USES-FRSR1)
 616      "addui $frdr,$frsr1,#$imm16z"
 617      (+ MSYS_NO OPC_ADDU IMM_YES frsr1 frdr imm16z)
 618      (set frdr (add USI frsr1 (ext USI imm16z)))
 619      ()
 620 )
 621
 622 (dni sub "SUB DstReg, SrcReg1, SrcReg2"
 623      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 624      "sub $frdrrr,$frsr1,$frsr2"
 625      (+ MSYS_NO OPC_SUB IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 626      (set frdrrr (sub SI frsr1 frsr2))
 627      ()
 628 )
 629
 630 (dni subu "SUBU DstReg, SrcReg1, SrcReg2"
 631      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 632      "subu $frdrrr,$frsr1,$frsr2"
 633      (+ MSYS_NO OPC_SUBU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 634      (set frdrrr (sub USI frsr1 frsr2))
 635      ()
 636 )
 637
 638 (dni subi "SUBI DstReg, SrcReg1, UnsImm"
 639      (AL-INSN USES-FRDR USES-FRSR1)
 640      "subi $frdr,$frsr1,#$imm16"
 641      (+ MSYS_NO OPC_SUB IMM_YES frsr1 frdr imm16)
 642      (sequence((HI tmp))
 643         (set HI tmp (and imm16 #xffff))
 644         (set frdr (sub SI frsr1 (ext SI tmp)))
 645      )
 646      ;(set frdr (sub SI frsr1 (ext SI imm16)))
 647      ()
 648 )
 649
 650 (dni subui "SUBUI DstReg, SrcReg1, UnsImm"
 651      (AL-INSN USES-FRDR USES-FRSR1)
 652      "subui $frdr,$frsr1,#$imm16z"
 653      (+ MSYS_NO OPC_SUBU IMM_YES frsr1 frdr imm16z)
 654      (set frdr (sub USI frsr1 (ext USI imm16z)))
 655      ()
 656 )
 657
 658 (dni mul "MUL DstReg, SrcReg1, SrcReg2"
 659      ((MACH ms1-003,ms2) AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 660      "mul $frdrrr,$frsr1,$frsr2"
 661      (+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 662      (sequence((HI op1) (HI op2))
 663          (set op1 (and frsr1 #xffff))
 664          (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
 665             (error "operand out of range")
 666          )
 667          (set op2 (and frsr2 #xffff))
 668          (if (or (lt op2 (const -32768)) (gt op2 (const 32767)))
 669             (error "operand out of range")
 670          )
 671          (set frdrrr (mul SI (ext SI op1) (ext SI op2)))
 672      )
 673      ()
 674 )
 675
 676 (dni muli "MULI DstReg, SrcReg1, UnsImm"
 677      ((MACH ms1-003,ms2) AL-INSN USES-FRDR USES-FRSR1)
 678      "muli $frdr,$frsr1,#$imm16"
 679      (+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16)
 680      (sequence((HI op1) (HI op2))
 681          (set op1 (and frsr1 #xffff))
 682          (if (or (lt op1 (const -32768)) (gt op1 (const 32767)))
 683             (error "operand out of range")
 684          )
 685          (set op2 (and imm16 #xffff))
 686          (if (eq op1 (const 0))
 687           (error "op1 is 0")
 688          )
 689          (if (eq op2 (const 0))
 690           (error "op2 is 0")
 691          )
 692          (set frdr (mul SI (ext SI op1) (ext SI op2)))
 693      )
 694      ()
 695 )
 696
 697 ; Logical Instructions
 698
 699 (dni and "AND DstReg, SrcReg1, SrcReg2"
 700      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 701      "and $frdrrr,$frsr1,$frsr2"
 702      (+ MSYS_NO OPC_AND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 703      (set frdrrr (and frsr1 frsr2))
 704      ()
 705 )
 706
 707 (dni andi "ANDI DstReg, SrcReg1, UnsImm"
 708      (AL-INSN USES-FRDR USES-FRSR1)
 709      "andi $frdr,$frsr1,#$imm16z"
 710      (+ MSYS_NO OPC_AND IMM_YES frsr1 frdr imm16z)
 711      (set frdr (and frsr1 (ext USI imm16z)))
 712      ()
 713 )
 714
 715 (dni or "OR DstReg, SrcReg1, SrcReg2"
 716      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 717      "or $frdrrr,$frsr1,$frsr2"
 718      (+ MSYS_NO OPC_OR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 719      (set frdrrr (or frsr1 frsr2))
 720      ()
 721 )
 722
 723 (dni nop "nop"
 724      ()
 725      "nop"
 726      (+ MSYS_NO OPC_OR IMM_NO (f-uu24 0))
 727      (nop)
 728      ()
 729 )
 730
 731 (dni ori "ORI DstReg, SrcReg1, UnsImm"
 732      (AL-INSN USES-FRDR USES-FRSR1)
 733      "ori $frdr,$frsr1,#$imm16z"
 734      (+ MSYS_NO OPC_OR IMM_YES frsr1 frdr imm16z)
 735      (set frdr (or frsr1 (ext USI imm16z)))
 736      ()
 737 )
 738
 739 (dni xor "XOR DstReg, SrcReg1, SrcReg2"
 740      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 741      "xor $frdrrr,$frsr1,$frsr2"
 742      (+ MSYS_NO OPC_XOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 743      (set frdrrr (xor frsr1 frsr2))
 744      ()
 745 )
 746
 747 (dni xori "XORI DstReg, SrcReg1, UnsImm"
 748      (AL-INSN USES-FRDR USES-FRSR1)
 749      "xori $frdr,$frsr1,#$imm16z"
 750      (+ MSYS_NO OPC_XOR IMM_YES frsr1 frdr imm16z)
 751      (set frdr (xor frsr1 (ext USI imm16z)))
 752      ()
 753 )
 754
 755 (dni nand "NAND DstReg, SrcReg1, SrcReg2"
 756      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 757      "nand $frdrrr,$frsr1,$frsr2"
 758      (+ MSYS_NO OPC_NAND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 759      (set frdrrr (inv (and frsr1 frsr2)))
 760      ()
 761 )
 762
 763 (dni nandi "NANDI DstReg, SrcReg1, UnsImm"
 764      (AL-INSN USES-FRDR USES-FRSR1)
 765      "nandi $frdr,$frsr1,#$imm16z"
 766      (+ MSYS_NO OPC_NAND IMM_YES frsr1 frdr imm16z)
 767      (set frdr (inv (and frsr1 (ext USI imm16z))))
 768      ()
 769 )
 770
 771 (dni nor "NOR DstReg, SrcReg1, SrcReg2"
 772      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 773      "nor $frdrrr,$frsr1,$frsr2"
 774      (+ MSYS_NO OPC_NOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 775      (set frdrrr (inv (or frsr1 frsr2)))
 776      ()
 777 )
 778
 779 (dni nori "NORI DstReg, SrcReg1, UnsImm"
 780      (AL-INSN USES-FRDR USES-FRSR1)
 781      "nori $frdr,$frsr1,#$imm16z"
 782      (+ MSYS_NO OPC_NOR IMM_YES frsr1 frdr imm16z)
 783      (set frdr (inv (or frsr1 (ext USI imm16z))))
 784      ()
 785 )
 786
 787 (dni xnor "XNOR DstReg, SrcReg1, SrcReg2"
 788      (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2)
 789      "xnor $frdrrr,$frsr1,$frsr2"
 790      (+ MSYS_NO OPC_XNOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 791      (set frdrrr (inv (xor frsr1 frsr2)))
 792      ()
 793 )
 794
 795 (dni xnori "XNORI DstReg, SrcReg1, UnsImm"
 796      (AL-INSN USES-FRDR USES-FRSR1)
 797      "xnori $frdr,$frsr1,#$imm16z"
 798      (+ MSYS_NO OPC_XNOR IMM_YES frsr1 frdr imm16z)
 799      (set frdr (inv (xor frsr1 (ext USI imm16z))))
 800      ()
 801 )
 802
 803 (dni ldui "LDUI DstReg, UnsImm"
 804      (AL-INSN USES-FRDR)
 805      "ldui $frdr,#$imm16z"
 806      (+ MSYS_NO OPC_LDUI IMM_YES (f-uu4b 0) frdr imm16z)
 807      (set frdr (and (sll imm16z 16) #xffff0000))
 808      ()
 809 )
 810
 811 ; Shift Instructions
 812
 813 (dni lsl "LSL DstReg, SrcReg1, SrcReg2"
 814      (USES-FRDRRR USES-FRSR1 USES-FRSR2)
 815      "lsl $frdrrr,$frsr1,$frsr2"
 816      (+ MSYS_NO OPC_LSL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 817      (set frdrrr (sll frsr1 frsr2))
 818      ()
 819 )
 820
 821 (dni lsli "LSLI DstReg, SrcReg1, UnsImm"
 822      (USES-FRDR USES-FRSR1)
 823      "lsli $frdr,$frsr1,#$imm16"
 824      (+ MSYS_NO OPC_LSL IMM_YES frsr1 frdr imm16)
 825      (set frdr (sll frsr1 imm16))
 826      ()
 827 )
 828
 829 (dni lsr "LSR DstReg, SrcReg1, SrcReg2"
 830      (USES-FRDRRR USES-FRSR1 USES-FRSR2)
 831      "lsr $frdrrr,$frsr1,$frsr2"
 832      (+ MSYS_NO OPC_LSR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 833      (set frdrrr (srl frsr1 frsr2))
 834      ()
 835 )
 836
 837 (dni lsri "LSRI DstReg, SrcReg1, UnsImm"
 838      (USES-FRDR USES-FRSR1)
 839      "lsri $frdr,$frsr1,#$imm16"
 840      (+ MSYS_NO OPC_LSR IMM_YES frsr1 frdr imm16)
 841      (set frdr (srl frsr1 imm16))
 842      ()
 843 )
 844
 845 (dni asr "ASR DstReg, SrcReg1, SrcReg2"
 846      (USES-FRDRRR USES-FRSR1 USES-FRSR2)
 847      "asr $frdrrr,$frsr1,$frsr2"
 848      (+ MSYS_NO OPC_ASR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0))
 849      (set frdrrr (sra frsr1 frsr2))
 850      ()
 851 )
 852
 853 (dni asri "ASRI DstReg, SrcReg1, UnsImm"
 854      (USES-FRDR USES-FRSR1)
 855      "asri $frdr,$frsr1,#$imm16"
 856      (+ MSYS_NO OPC_ASR IMM_YES frsr1 frdr imm16)
 857      (set frdr (sra frsr1 imm16))
 858      ()
 859 )
 860
 861 ; Control Transfer Instructions
 862
 863 (dni brlt "BRLT SrcReg1, SrcReg2, label"
 864      (BR-INSN DELAY-SLOT USES-FRDRRR USES-FRSR1 USES-FRSR2)
 865      "brlt $frsr1,$frsr2,$imm16o"
 866      (+ MSYS_NO OPC_BRLT IMM_YES frsr1 frsr2 imm16o)
 867      (sequence()
 868         (if (lt USI frsr1 frsr2)
 869             (dset pc (add pc (ext SI imm16o))))
 870      )
 871      ()
 872 )
 873
 874 (dni brle "BRLE SrcReg1, SrcReg2, label"
 875      (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
 876      "brle $frsr1,$frsr2,$imm16o"
 877      (+ MSYS_NO OPC_BRLE IMM_YES frsr1 frsr2 imm16o)
 878      (sequence()
 879         (if (le USI frsr1 frsr2)
 880             (dset pc (add pc (ext SI imm16o))))
 881      )
 882      ()
 883 )
 884
 885 (dni breq "BREQ SrcReg1, SrcReg2, label"
 886      (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
 887      "breq $frsr1,$frsr2,$imm16o"
 888      (+ MSYS_NO OPC_BREQ IMM_YES frsr1 frsr2 imm16o)
 889      (sequence()
 890         (if (eq USI frsr1 frsr2)
 891             (dset pc (add pc (ext SI imm16o))))
 892      )
 893      ()
 894 )
 895
 896 (dni brne "BRNE SrcReg1, SrcReg2, label"
 897      (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2)
 898      "brne $frsr1,$frsr2,$imm16o"
 899      (+ MSYS_NO OPC_BRNEQ IMM_YES frsr1 frsr2 imm16o)
 900      (sequence()
 901         (if (not (eq USI frsr1 frsr2))
 902             (dset pc (add pc (ext SI imm16o))))
 903      )
 904      ()
 905 )
 906
 907 (dni jmp "JMP, label"
 908      (DELAY-SLOT BR-INSN)
 909      "jmp $imm16o"
 910      (+ MSYS_NO OPC_JMP IMM_YES (f-uu4b 0) (f-uu4a 0) imm16o)
 911      (dset pc (add pc (ext SI imm16o)))
 912      ()
 913 )
 914
 915 (dni jal "JAL DstReg, SrcReg1"
 916      (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1 JAL-HAZARD)
 917      "jal $frdrrr,$frsr1"
 918      (+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0))
 919      (sequence()
 920          (if (eq frsr1 #x0)
 921             (c-call VOID "do_syscall" pc)
 922             (sequence()   ; else part.  Do non-syscall stuff here.
 923                 (dset frdrrr (add pc #x8))
 924                 (dset pc frsr1)
 925             )
 926          )
 927      )
 928      ()
 929 )
 930
 931 (dni dbnz "DBNZ SrcReg1, label"
 932      ((MACH ms1-003,ms2) BR-INSN DELAY-SLOT USES-FRSR1)
 933      "dbnz $frsr1,$imm16o"
 934      (+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o)
 935      (sequence()
 936          (if (not (eq USI frsr1 0))
 937             (dset pc (add pc (ext SI imm16o))))
 938      )
 939      ()
 940 )
 941
 942 ; Interrupt Control Instructions
 943
 944 (dni ei "EI - Enable Interrupt Processing"
 945      ()
 946      "ei"
 947      (+ MSYS_NO OPC_EI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
 948      (c-call VOID "enable_interrupts")
 949      ()
 950 )
 951
 952 (dni di "DI - Disable Interrupt Processing"
 953      ()
 954      "di"
 955      (+ MSYS_NO OPC_DI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0))
 956      (c-call VOID "disable_interrupts")
 957      ()
 958 )
 959
 960 (dni si "SI - Send software Interrupt"
 961      (DELAY-SLOT BR-INSN USES-FRDR)
 962      "si $frdrrr"
 963      (+ MSYS_NO OPC_SI IMM_NO (f-uu4b 0) (f-uu4a 0) frdrrr (f-uu12 0))
 964      ;(sequence()
 965      ;   (dset frdr (add pc #x4))
 966      ;   (c-call VOID "do_syscall1" pc)
 967      ;   ; (dset pc frsr1) Do this later when we have the address.
 968      ;)
 969      (sequence()
 970         (set frdrrr (add pc #x4))
 971         (c-call VOID "do_syscall" pc)
 972         ; (set pc frsr1) Do this later when we have the address.
 973      )
 974      ()
 975 )
 976
 977 (dni reti "RETI SrcReg1"
 978      (DELAY-SLOT BR-INSN USES-FRSR1 JAL-HAZARD)
 979      "reti $frsr1"
 980      (+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0))
 981      (sequence()
 982        (c-call VOID "enable_interrupts")
 983        (dset pc frsr1)
 984      )
 985      ()
 986 )
 987
 988 ; Memory Access Instructions
 989
 990 (dni ldw "LDW DstReg, SrcReg1, Imm"
 991      (LOAD-DELAY MEMORY-ACCESS USES-FRDR USES-FRSR1)
 992      "ldw $frdr,$frsr1,#$imm16"
 993      (+ MSYS_NO OPC_LDW IMM_YES frsr1 frdr imm16)
 994      (sequence((USI ea) (HI tmp))
 995       (set HI tmp (and imm16 #xffff))
 996       (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
 997       (set frdr (mem SI ea))
 998      )
 999      ()
1000 )
1001
1002 (dni stw "STW SrcReg2, SrcReg1, Imm"
1003      (MEMORY-ACCESS USES-FRSR1 USES-FRSR2)
1004      "stw $frsr2,$frsr1,#$imm16"
1005      (+ MSYS_NO OPC_STW IMM_YES frsr1 frsr2 imm16)
1006      (sequence((USI ea) (HI tmp))
1007       (set HI tmp (and imm16 #xffff))
1008       (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc))
1009       (set (mem SI ea) frsr2)
1010      )
1011      ()
1012 )
1013
1014 ; Break Instruction
1015
1016 (dni break "BREAK"
1017      ()
1018      "break"
1019      (+ MSYS_NO OPC_BREAK (f-imm 0) (f-uu24 0))
1020      (c-call VOID "do_break" pc)
1021      ()
1022 )
1023
1024 ; Cache Flush Instruction
1025
1026 (dni iflush "IFLUSH"
1027      ((MACH ms1-003,ms2))
1028      "iflush"
1029      (+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0))
1030      (nop)
1031      ()
1032 )
1033
1034 ; MorphoSys Instructions
1035
1036 (dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#"
1037      ((MACH ms1))
1038      "ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum"
1039      (+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0)
1040         contnum )
1041      (nop)
1042      ()
1043 )
1044
1045 (dni ldfb "LDFB SRC1, byte#"
1046      ((MACH ms1))
1047      "ldfb $frsr1,$frsr2,#$imm16z"
1048      (+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
1049      (nop)
1050      ()
1051 )
1052
1053 (dni stfb "STFB SRC1, SRC2, byte "
1054      ((MACH ms1))
1055      "stfb $frsr1,$frsr2,#$imm16z"
1056      (+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z)
1057      (nop)
1058      ()
1059 )
1060
1061 (dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
1062      ((MACH ms1,ms1-003))
1063      "fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1064      (+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp)
1065      (nop)
1066      ()
1067 )
1068
1069 (dni mfbcb "MFBCB SRC1, RT/BR1/BR2/CS, SRC2, r/c, CB/RB, cell, dup, ctx_disp"
1070      ()
1071      "mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1072      (+ MSYS_YES MSOPC_MFBCB rbbc frsr1 frsr2 (f-uu-4-15 0) rc1 cbrb cell dup ctxdisp)
1073      (nop)
1074      ()
1075 )
1076
1077 (dni fbcci "FBCCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1078      ()
1079      "fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1080      (+ MSYS_YES MSOPC_FBCCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1081      (nop)
1082      ()
1083 )
1084
1085 (dni fbrci "FBRCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1086      ()
1087      "fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1088      (+ MSYS_YES MSOPC_FBRCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1089      (nop)
1090      ()
1091 )
1092
1093 (dni fbcri "FBCRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1094      ()
1095      "fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1096      (+ MSYS_YES MSOPC_FBCRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1097      (nop)
1098      ()
1099 )
1100
1101 (dni fbrri "FBRRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp"
1102      ()
1103      "fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1104      (+ MSYS_YES MSOPC_FBRRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp)
1105      (nop)
1106      ()
1107 )
1108
1109 (dni mfbcci "MFBCCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1110      ()
1111      "mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1112      (+ MSYS_YES MSOPC_MFBCCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1113      (nop)
1114      ()
1115 )
1116
1117 (dni mfbrci "MFBRCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1118      ()
1119      "mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1120      (+ MSYS_YES MSOPC_MFBRCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1121      (nop)
1122      ()
1123 )
1124
1125 (dni mfbcri "MFBCRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1126      ()
1127      "mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1128      (+ MSYS_YES MSOPC_MFBCRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1129      (nop)
1130      ()
1131 )
1132
1133 (dni mfbrri "MFBRRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp"
1134      ()
1135      "mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp"
1136      (+ MSYS_YES MSOPC_MFBRRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp)
1137      (nop)
1138      ()
1139 )
1140
1141 (dni fbcbdr "FBCBDR SRC1, RT/BR1/BR2/CS, SRC2, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp"
1142      ()
1143      "fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1144      (+ MSYS_YES MSOPC_FBCBDR rbbc frsr1 frsr2 ball2 brc2 rc1 cbrb cell dup ctxdisp)
1145      (nop)
1146      ()
1147 )
1148
1149 (dni rcfbcb "RCFBCB RT/BR1/BR2/CS, type, B_all, B_r_c, row#, r/c, CB/RB, cell, dup, ctx_disp"
1150      ()
1151      "rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1152      (+ MSYS_YES MSOPC_RCFBCB rbbc (f-uu-2-23 0) type ball brc (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
1153      (nop)
1154      ()
1155 )
1156
1157 (dni mrcfbcb "MRCFBCB SRC2, RT/BR1/BR2/CS, type, row#, r/c, CB/RB, cell, dup, ctx_disp"
1158      ()
1159      "mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1160      (+ MSYS_YES MSOPC_MRCFBCB rbbc (f-uu-2-23 0) type frsr2 (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp)
1161      (nop)
1162      ()
1163 )
1164
1165 (dni cbcast "CBCAST mask, r/c, ctx_disp "
1166      ()
1167      "cbcast #$mask,#$rc2,#$ctxdisp"
1168      (+ MSYS_YES MSOPC_CBCAST mask (f-uu-3-9 0) rc2 ctxdisp)
1169      (nop)
1170      ()
1171 )
1172
1173 (dni dupcbcast "DUPCBCAST mask, cell, r/c, ctx_disp "
1174      ()
1175      "dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp"
1176      (+ MSYS_YES MSOPC_DUPCBCAST mask cell rc2 ctxdisp)
1177      (nop)
1178      ()
1179 )
1180
1181 (dni wfbi "WFBI Bank_address, row#, cell, dup, ctx_disp "
1182      ()
1183     "wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp"
1184      (+ MSYS_YES MSOPC_WFBI bankaddr rownum1 cell dup ctxdisp)
1185      (nop)
1186      ()
1187 )
1188
1189 ;(dni wfb "WFB SRC1, SRC2, FB_disp, row#, ctx_disp"
1190 ;     ()
1191 ;     "wfb $frsr1,$frsr2,#$fbdisp,#$rownum,#$ctxdisp"
1192 ;     (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum (f-uu-1-6 0) ctxdisp)
1193 ;     (nop)
1194 ;     ()
1195 ;)
1196
1197 (dni wfb "WFB, DRC1,SRC2,FB_disp,row#,ctx_disp"
1198       ()
1199       "wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp"
1200       (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum2 (f-uu-1-6 0) ctxdisp)
1201       (nop)
1202       ()
1203 )
1204
1205
1206 (dni rcrisc "RCRISC DEST, RT/BR1/BR2/CS, SRC1, column#, r/c, CB/RB, cell, dup, ctx_disp"
1207      ()
1208      "rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1209      (+ MSYS_YES MSOPC_RCRISC rbbc frsr1 (f-uu-1-19 0) colnum frdrrr rc1 cbrb cell dup ctxdisp)
1210      (nop)
1211      ()
1212 )
1213
1214 (dni fbcbinc "FBCBINC SRC1, RT/BR1/BR2/CS, Incr_amount, r/c, CB/RB, cell, dup, ctx_disp "
1215      ()
1216      "fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp"
1217      (+ MSYS_YES MSOPC_FBCBINC rbbc frsr1 incamt rc1 cbrb cell dup ctxdisp)
1218      (nop)
1219      ()
1220 )
1221
1222 (dni rcxmode "RCXMODE SRC2, rd, wr, xmode, mask, FB_disp, row#, r/c, ctx_disp"
1223      ()
1224      "rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp"
1225      (+ MSYS_YES MSOPC_RCXMODE rda wr xmode mask1 frsr2 fbdisp rownum2 rc2 ctxdisp)
1226      (nop)
1227      ()
1228 )
1229
1230 (dni interleaver "INTLVR ireg, mode, ireg, i/d, size"
1231      ()
1232      "intlvr $frsr1,#$mode,$frsr2,#$id,#$size"
1233      (+ MSYS_YES MSOPC_INTLVR mode frsr1 frsr2 (f-uu-1-15 0) id size)
1234      (nop)
1235      ()
1236 )
1237
1238 ;; Issue 66262: The documenatation gives the wrong order for
1239 ;;               the arguments to the WFBINC instruction.
1240 (dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp"
1241      ((MACH ms1-003,ms2))
1242      "wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1243      (+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp)
1244      (nop)
1245      ()
1246 )
1247
1248 (dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp"
1249      ((MACH ms1-003,ms2))
1250      "mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1251      (+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp)
1252      (nop)
1253      ()
1254 )
1255
1256 (dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp"
1257      ((MACH ms1-003,ms2))
1258      "wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1259      (+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp)
1260      (nop)
1261      ()
1262 )
1263
1264 (dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp"
1265      ((MACH ms1-003,ms2))
1266      "mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp"
1267      (+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp)
1268      (nop)
1269      ()
1270 )
1271
1272 (dni fbcbincs "FBCBINCS      perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1273      ((MACH ms1-003,ms2))
1274      "fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1275      (+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp)
1276      (nop)
1277      ()
1278 )
1279
1280 (dni mfbcbincs "MFBCBINCS               ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1281      ((MACH ms1-003,ms2))
1282      "mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1283      (+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp)
1284      (nop)
1285      ()
1286 )
1287
1288 (dni fbcbincrs "FBCBINCRS            ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1289      ((MACH ms1-003,ms2))
1290      "fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1291      (+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
1292      (nop)
1293      ()
1294 )
1295
1296 (dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp"
1297      ((MACH ms1-003,ms2))
1298      "mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp"
1299      (+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp)
1300      (nop)
1301      ()
1302 )
1303
1304 ; MS2 instructions
1305 (dni loop "LOOP SrcReg1, label"
1306      ((MACH ms2) DELAY-SLOT USES-FRSR1)
1307      "loop $frsr1,$loopsize"
1308      (+ MSYS_NO OPC_LOOP IMM_NO frsr1 (f-uu4a 0) (f-uu8 0) loopsize)
1309      (nop)      ;; to be filled in
1310      ()
1311 )
1312
1313 (dni loopi "LOOPI niter, label"
1314      ((MACH ms2) DELAY-SLOT)
1315      "loopi #$imm16l,$loopsize"
1316      (+ MSYS_NO OPC_LOOP IMM_YES imm16l loopsize)
1317      (nop)      ;; to be filled in
1318      ()
1319 )
1320
1321 (dni dfbc "dfbc cb1sel,cb2sel,cb1inc,cb2inc,dr/c,cr/c,ctxdisp"
1322      ((MACH ms2))
1323      "dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp"
1324      (+ MSYS_YES MSOPC_LDCTXT cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp)
1325      (nop)
1326      ()
1327 )
1328
1329 (dni dwfb "dwfb cb1sel,cb2sel,cb1inc,cb2inc,cr/c,ctxdisp"
1330      ((MACH ms2))
1331      "dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp"
1332      (+ MSYS_YES MSOPC_LDFB cb1sel cb2sel cb1incr cb2incr (f-uu1 0) rc2 ctxdisp)
1333      (nop)
1334      ()
1335 )
1336
1337 (dni fbwfb "fbwfb cb1sel,cb2sel,cb1inc,cb2inc,r0/1,cr/c,ctxdisp"
1338      ((MACH ms2))
1339      "fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp"
1340      (+ MSYS_YES MSOPC_STFB cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp)
1341      (nop)
1342      ()
1343 )
1344
1345 (dni dfbr "dfbr cb1sel,cb2sel,reg,W/O1,W/O2,mode,cr/c,ctxdisp"
1346      ((MACH ms2) USES-FRSR2)
1347      "dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp"
1348      (+ MSYS_YES MSOPC_FBCB cb1sel cb2sel frsr2 length rownum1 rownum2 rc2 ctxdisp)
1349      (nop)
1350      ()
1351 )