cpu/or1korbis.cpu

   1 ; OpenRISC Basic Instruction Set 32-bit (ORBIS)  -*- Scheme -*-
   2 ; Copyright 2000-2014 Free Software Foundation, Inc.
   3 ; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
   4 ; Modified by Julius Baxter, juliusbaxter@gmail.com
   5 ; Modified by Peter Gavin, pgavin@gmail.com
   6 ;
   7 ; This program is free software; you can redistribute it and/or modify
   8 ; it under the terms of the GNU General Public License as published by
   9 ; the Free Software Foundation; either version 3 of the License, or
  10 ; (at your option) any later version.
  11 ;
  12 ; This program is distributed in the hope that it will be useful,
  13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ; GNU General Public License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with this program; if not, see <http://www.gnu.org/licenses/>
  19
  20 ; Instruction fields.
  21
  22 ; Hardware for immediate operands
  23 (dnh h-simm16      "16-bit signed immediate"   ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ())
  24 (dnh h-uimm16      "16-bit unsigned immediate" ()                   (immediate (UINT 16)) () () ())
  25 (dnh h-uimm6       "6-bit unsigned immediate"  ()                   (immediate (UINT 6)) () () ())
  26
  27 ; Hardware for the (internal) atomic registers
  28 (dsh h-atomic-reserve "atomic reserve flag" () (register BI))
  29 (dsh h-atomic-address "atomic reserve address" () (register SI))
  30
  31 ; Instruction classes.
  32 (dnf f-opcode      "insn opcode"               ((MACH ORBIS-MACHS)) 31 6)
  33
  34 ; Register fields.
  35 (dnf f-r1          "r1"                        ((MACH ORBIS-MACHS)) 25 5)
  36 (dnf f-r2          "r2"                        ((MACH ORBIS-MACHS)) 20 5)
  37 (dnf f-r3          "r3"                        ((MACH ORBIS-MACHS)) 15 5)
  38
  39 ; Sub fields
  40 (dnf f-op-25-2     "op-25-2"                   ((MACH ORBIS-MACHS)) 25 2) ;; nop
  41 (dnf f-op-25-5     "op-25-5"                   ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf*
  42 (dnf f-op-16-1     "op-16-1"                   ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc
  43 (dnf f-op-7-4      "op-7-4"                    ((MACH ORBIS-MACHS)) 7 4)
  44 (dnf f-op-3-4      "op-3-4"                    ((MACH ORBIS-MACHS)) 3 4)
  45 (dnf f-op-9-2      "op-9-2"                    ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode
  46 (dnf f-op-9-4      "op-9-4"                    ((MACH ORBIS-MACHS)) 9 4) ;;
  47 (dnf f-op-7-8      "op-7-8"                    ((MACH ORBIS-MACHS)) 7 8)
  48 (dnf f-op-7-2      "op-7-2"                    ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti
  49
  50 ; Reserved fields
  51 (dnf f-resv-25-26  "resv-25-26"                ((MACH ORBIS-MACHS) RESERVED) 25 26)
  52 (dnf f-resv-25-10  "resv-25-10"                ((MACH ORBIS-MACHS) RESERVED) 25 10)
  53 (dnf f-resv-25-5   "resv-25-5"                 ((MACH ORBIS-MACHS) RESERVED) 25 5)
  54 (dnf f-resv-23-8   "resv-23-8"                 ((MACH ORBIS-MACHS) RESERVED) 23 8)
  55 (dnf f-resv-20-21  "resv-20-21"                ((MACH ORBIS-MACHS) RESERVED) 20 21)
  56 (dnf f-resv-20-5   "resv-20-5"                 ((MACH ORBIS-MACHS) RESERVED) 20 5)
  57 (dnf f-resv-20-4   "resv-20-4"                 ((MACH ORBIS-MACHS) RESERVED) 20 4)
  58 (dnf f-resv-15-8   "resv-15-8"                 ((MACH ORBIS-MACHS) RESERVED) 15 8)
  59 (dnf f-resv-15-6   "resv-15-6"                 ((MACH ORBIS-MACHS) RESERVED) 15 6)
  60 (dnf f-resv-10-11  "resv-10-11"                ((MACH ORBIS-MACHS) RESERVED) 10 11)
  61 (dnf f-resv-10-7   "resv-10-7"                 ((MACH ORBIS-MACHS) RESERVED) 10 7)
  62 (dnf f-resv-10-3   "resv-10-3"                 ((MACH ORBIS-MACHS) RESERVED) 10 3)
  63 (dnf f-resv-10-1   "resv-10-1"                 ((MACH ORBIS-MACHS) RESERVED) 10 1)
  64 (dnf f-resv-7-4    "resv-7-4"                  ((MACH ORBIS-MACHS) RESERVED) 7 4)
  65 (dnf f-resv-5-2    "resv-5-2"                  ((MACH ORBIS-MACHS) RESERVED) 5 2)
  66
  67 (dnf f-imm16-25-5  "imm16-25-5"                ((MACH ORBIS-MACHS)) 25  5)
  68 (dnf f-imm16-10-11 "imm16-10-11"               ((MACH ORBIS-MACHS)) 10 11)
  69
  70 ; PC relative, 26-bit (2 shifted to right)
  71 (df f-disp26
  72     "disp26"
  73     ((MACH ORBIS-MACHS) PCREL-ADDR)
  74     25
  75     26
  76     INT
  77     ((value pc) (sra IAI (sub IAI value pc) (const 2)))
  78     ((value pc) (add IAI (sll IAI value (const 2)) pc))
  79     )
  80
  81 ; PC relative, 21-bit, 13 shifted to right, aligned.
  82 ; Note that the alignment means that we can't simplify relocations in the
  83 ; same way as we do for pc-relative, so we use ABS-ADDR instead of PCREL-ADDR.
  84 (df f-disp21
  85     "disp21"
  86     ((MACH ORBIS-MACHS) ABS-ADDR)
  87     20
  88     21
  89     INT
  90     ((value pc)
  91      (sub IAI (sra IAI value (const 13)) (sra IAI pc (const 13))))
  92     ((value pc)
  93      (sll IAI (add IAI value (sra IAI pc (const 13))) (const 13)))
  94     )
  95
  96 ; Immediates.
  97 (dnf f-uimm16    "uimm16"                      ((MACH ORBIS-MACHS))          15 16)
  98 (df  f-simm16    "simm16"                      ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f)
  99 (dnf f-uimm6     "uimm6"                       ((MACH ORBIS-MACHS))          5  6) ;; shroti
 100
 101 (define-multi-ifield
 102   (name f-uimm16-split)
 103   (comment "16-bit split unsigned immediate")
 104   (attrs (MACH ORBIS-MACHS))
 105   (mode UINT)
 106   (subfields f-imm16-25-5 f-imm16-10-11)
 107   (insert (sequence ()
 108                     (set (ifield f-imm16-25-5)
 109                          (and (srl (ifield f-uimm16-split)
 110                                    (const 11))
 111                               (const #x1f)))
 112                     (set (ifield f-imm16-10-11)
 113                          (and (ifield f-uimm16-split)
 114                               (const #x7ff)))))
 115   (extract
 116            (set (ifield f-uimm16-split)
 117                 (trunc UHI
 118                        (or (sll (ifield f-imm16-25-5)
 119                                 (const 11))
 120                            (ifield f-imm16-10-11)))))
 121   )
 122
 123 (define-multi-ifield
 124   (name f-simm16-split)
 125   (comment "16-bit split signed immediate")
 126   (attrs (MACH ORBIS-MACHS) SIGN-OPT)
 127   (mode INT)
 128   (subfields f-imm16-25-5 f-imm16-10-11)
 129   (insert (sequence ()
 130                     (set (ifield f-imm16-25-5)
 131                          (and (sra (ifield f-simm16-split)
 132                                    (const 11))
 133                               (const #x1f)))
 134                     (set (ifield f-imm16-10-11)
 135                          (and (ifield f-simm16-split)
 136                               (const #x7ff)))))
 137   (extract
 138            (set (ifield f-simm16-split)
 139                 (trunc HI
 140                        (or (sll (ifield f-imm16-25-5)
 141                                 (const 11))
 142                            (ifield f-imm16-10-11)))))
 143   )
 144
 145 ; Enums.
 146
 147 ; insn-opcode: bits 31-26
 148 (define-normal-insn-enum
 149   insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode
 150   (("J"            #x00)
 151    ("JAL"          #x01)
 152    ("ADRP"         #x02)
 153    ("BNF"          #x03)
 154    ("BF"           #x04)
 155    ("NOP"          #x05)
 156    ("MOVHIMACRC"   #x06)
 157    ("SYSTRAPSYNCS" #x08)
 158    ("RFE"          #x09)
 159    ("VECTOR"       #x0a)
 160    ("JR"           #x11)
 161    ("JALR"         #x12)
 162    ("MACI"         #x13)
 163    ("LWA"          #x1b)
 164    ("CUST1"        #x1c)
 165    ("CUST2"        #x1d)
 166    ("CUST3"        #x1e)
 167    ("CUST4"        #x1f)
 168    ("LD"           #x20)
 169    ("LWZ"          #x21)
 170    ("LWS"          #x22)
 171    ("LBZ"          #x23)
 172    ("LBS"          #x24)
 173    ("LHZ"          #x25)
 174    ("LHS"          #x26)
 175    ("ADDI"         #x27)
 176    ("ADDIC"        #x28)
 177    ("ANDI"         #x29)
 178    ("ORI"          #x2a)
 179    ("XORI"         #x2b)
 180    ("MULI"         #x2c)
 181    ("MFSPR"        #x2d)
 182    ("SHROTI"       #x2e)
 183    ("SFI"          #x2f)
 184    ("MTSPR"        #x30)
 185    ("MAC"          #x31)
 186    ("FLOAT"        #x32)
 187    ("SWA"          #x33)
 188    ("SD"           #x34)
 189    ("SW"           #x35)
 190    ("SB"           #x36)
 191    ("SH"           #x37)
 192    ("ALU"          #x38)
 193    ("SF"           #x39)
 194    ("CUST5"        #x3c)
 195    ("CUST6"        #x3d)
 196    ("CUST7"        #x3e)
 197    ("CUST8"        #x3f)
 198   )
 199 )
 200
 201 (define-normal-insn-enum insn-opcode-systrapsyncs
 202   "systrapsync insn opcode enums" ((MACH ORBIS-MACHS))
 203   OPC_SYSTRAPSYNCS_ f-op-25-5
 204     (("SYSCALL" #x00 )
 205      ("TRAP" #x08 )
 206      ("MSYNC" #x10 )
 207      ("PSYNC" #x14 )
 208      ("CSYNC" #x18 )
 209     )
 210 )
 211
 212 (define-normal-insn-enum insn-opcode-movehimacrc
 213   "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS))
 214   OPC_MOVHIMACRC_ f-op-16-1
 215   (("MOVHI" #x0)
 216    ("MACRC" #x1)
 217   )
 218 )
 219
 220 (define-normal-insn-enum insn-opcode-mac
 221   "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS))
 222   OPC_MAC_ f-op-3-4
 223   (("MAC" #x1)
 224    ("MSB" #x2)
 225    )
 226   )
 227
 228 (define-normal-insn-enum insn-opcode-shorts
 229   "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS))
 230   OPC_SHROTS_ f-op-7-2
 231     (("SLL" #x0 )
 232      ("SRL" #x1 )
 233      ("SRA" #x2 )
 234      ("ROR" #x3 )
 235     )
 236 )
 237
 238 (define-normal-insn-enum insn-opcode-extbhs
 239   "extend byte/half opcode enums" ((MACH ORBIS-MACHS))
 240   OPC_EXTBHS_ f-op-9-4
 241   (("EXTHS" #x0)
 242    ("EXTBS" #x1)
 243    ("EXTHZ" #x2)
 244    ("EXTBZ" #x3)
 245    )
 246 )
 247
 248 (define-normal-insn-enum insn-opcode-extws
 249   "extend word opcode enums" ((MACH ORBIS-MACHS))
 250   OPC_EXTWS_ f-op-9-4
 251   (("EXTWS" #x0)
 252    ("EXTWZ" #x1)
 253    )
 254 )
 255
 256 (define-normal-insn-enum insn-opcode-alu-regreg
 257   "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS))
 258   OPC_ALU_REGREG_ f-op-3-4
 259   (("ADD"   #x0)
 260    ("ADDC"  #x1)
 261    ("SUB"   #x2)
 262    ("AND"   #x3)
 263    ("OR"    #x4)
 264    ("XOR"   #x5)
 265    ("MUL"   #x6)
 266    ("SHROT" #x8)
 267    ("DIV"   #x9)
 268    ("DIVU"  #xA)
 269    ("MULU"  #xB)
 270    ("EXTBH" #xC)
 271    ("EXTW"  #xD)
 272    ("CMOV"  #xE)
 273    ("FFL1"  #xF)
 274    )
 275 )
 276
 277 (define-normal-insn-enum insn-opcode-setflag
 278   "setflag insn opcode enums" ((MACH ORBIS-MACHS))
 279   OPC_SF_ f-op-25-5
 280     (("EQ"  #x00)
 281      ("NE"  #x01)
 282      ("GTU" #x02)
 283      ("GEU" #x03)
 284      ("LTU" #x04)
 285      ("LEU" #x05)
 286      ("GTS" #x0A)
 287      ("GES" #x0B)
 288      ("LTS" #x0C)
 289      ("LES" #x0D)
 290     )
 291 )
 292
 293 \f
 294 ; Instruction operands.
 295
 296 (dnop sys-sr            "supervision register"             ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr            f-nil)
 297 (dnop sys-esr0          "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0          f-nil)
 298 (dnop sys-epcr0         "exception PC register 0"          ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0         f-nil)
 299
 300 (dnop sys-sr-lee        "SR little endian enable bit"      ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee        f-nil)
 301 (dnop sys-sr-f          "SR flag bit"                      ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f          f-nil)
 302 (dnop sys-sr-cy         "SR carry bit"                     ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy         f-nil)
 303 (dnop sys-sr-ov         "SR overflow bit"                  ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov         f-nil)
 304 (dnop sys-sr-ove        "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove        f-nil)
 305 (dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit"    ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil)
 306 (dnop sys-cpucfgr-nd    "CPUCFGR no delay bit"             ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd    f-nil)
 307 (dnop sys-fpcsr-rm      "floating point round mode"        ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm      f-nil)
 308
 309 (dnop mac-machi         "MAC HI result register"           ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi         f-nil)
 310 (dnop mac-maclo         "MAC LO result register"           ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo         f-nil)
 311
 312 (dnop atomic-reserve    "atomic reserve flag"              ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-reserve    f-nil)
 313 (dnop atomic-address    "atomic address"                   ((MACH ORBIS-MACHS) SEM-ONLY) h-atomic-address    f-nil)
 314
 315 (dnop uimm6             "uimm6"                            ((MACH ORBIS-MACHS))          h-uimm6             f-uimm6)
 316
 317 (dnop rD                "destination register"             ((MACH ORBIS-MACHS))          h-gpr               f-r1)
 318 (dnop rA                "source register A"                ((MACH ORBIS-MACHS))          h-gpr               f-r2)
 319 (dnop rB                "source register B"                ((MACH ORBIS-MACHS))          h-gpr               f-r3)
 320
 321 (define-operand
 322   (name disp26)
 323   (comment "pc-rel 26 bit")
 324   (attrs (MACH ORBIS-MACHS))
 325   (type h-iaddr)
 326   (index f-disp26)
 327   (handlers (parse "disp26"))
 328   )
 329
 330 (define-operand
 331   (name disp21)
 332   (comment "pc-rel 21 bit")
 333   (attrs (MACH ORBIS-MACHS))
 334   (type h-iaddr)
 335   (index f-disp21)
 336   (handlers (parse "disp21"))
 337   )
 338
 339 (define-operand
 340   (name simm16)
 341   (comment "16-bit signed immediate")
 342   (attrs (MACH ORBIS-MACHS) SIGN-OPT)
 343   (type h-simm16)
 344   (index f-simm16)
 345   (handlers (parse "simm16"))
 346   )
 347
 348 (define-operand
 349   (name uimm16)
 350   (comment "16-bit unsigned immediate")
 351   (attrs (MACH ORBIS-MACHS))
 352   (type h-uimm16)
 353   (index f-uimm16)
 354   (handlers (parse "uimm16"))
 355   )
 356
 357 (define-operand
 358   (name simm16-split)
 359   (comment "split 16-bit signed immediate")
 360   (attrs (MACH ORBIS-MACHS) SIGN-OPT)
 361   (type h-simm16)
 362   (index f-simm16-split)
 363   (handlers (parse "simm16_split"))
 364 )
 365
 366 (define-operand
 367   (name uimm16-split)
 368   (comment "split 16-bit unsigned immediate")
 369   (attrs (MACH ORBIS-MACHS))
 370   (type h-uimm16)
 371   (index f-uimm16-split)
 372   (handlers (parse "uimm16_split"))
 373 )
 374
 375 ; Instructions.
 376
 377 ; Branch releated instructions
 378
 379 (define-pmacro (cti-link-return)
 380   (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8)))
 381   )
 382 (define-pmacro (cti-transfer-control condition target)
 383   ;; this mess is necessary because we're
 384   ;; skipping the delay slot, but it's
 385   ;; actually the start of the next basic
 386   ;; block
 387   (sequence ()
 388             (if condition
 389                 (delay 1 (set IAI pc target))
 390                 (if sys-cpucfgr-nd
 391                     (delay 1 (set IAI pc (add pc 4))))
 392                 )
 393             (if sys-cpucfgr-nd
 394                 (skip 1)
 395                 )
 396             )
 397   )
 398
 399 (define-pmacro
 400   (define-cti
 401     cti-name
 402     cti-comment
 403     cti-attrs
 404     cti-syntax
 405     cti-format
 406     cti-semantics)
 407   (begin
 408     (dni
 409       cti-name
 410       cti-comment
 411       (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs))
 412       cti-syntax
 413       cti-format
 414       (cti-semantics)
 415       ()
 416       )
 417     )
 418   )
 419
 420 (define-cti
 421   l-j
 422   "jump (pc-relative iaddr)"
 423   (!COND-CTI UNCOND-CTI)
 424   "l.j ${disp26}"
 425   (+ OPC_J disp26)
 426   (.pmacro ()
 427            (cti-transfer-control 1 disp26)
 428            )
 429   )
 430
 431 (dni l-adrp "adrp reg/disp21"
 432     ((MACH ORBIS-MACHS))
 433     "l.adrp $rD,${disp21}"
 434     (+ OPC_ADRP rD disp21)
 435     (set UWI rD disp21)
 436     ()
 437   )
 438
 439 (define-cti
 440   l-jal
 441   "jump and link (pc-relative iaddr)"
 442   (!COND-CTI UNCOND-CTI)
 443   "l.jal ${disp26}"
 444   (+ OPC_JAL disp26)
 445   (.pmacro ()
 446            (sequence ()
 447                      (cti-link-return)
 448                      (cti-transfer-control 1 disp26)
 449                      )
 450            )
 451   )
 452
 453 (define-cti
 454   l-jr
 455   "jump register (absolute iaddr)"
 456   (!COND-CTI UNCOND-CTI)
 457   "l.jr $rB"
 458   (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0))
 459   (.pmacro ()
 460            (cti-transfer-control 1 rB)
 461            )
 462   )
 463
 464 (define-cti
 465   l-jalr
 466   "jump register and link (absolute iaddr)"
 467   (!COND-CTI UNCOND-CTI)
 468   "l.jalr $rB"
 469   (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) )
 470   (.pmacro ()
 471            (sequence ()
 472                      (cti-link-return)
 473                      (cti-transfer-control 1 rB)
 474                      )
 475            )
 476   )
 477
 478 (define-cti
 479   l-bnf
 480   "branch if condition bit not set (pc relative iaddr)"
 481   (COND-CTI !UNCOND-CTI)
 482   "l.bnf ${disp26}"
 483   (+ OPC_BNF disp26)
 484   (.pmacro ()
 485            (cti-transfer-control (not sys-sr-f) disp26)
 486            )
 487   )
 488
 489 (define-cti
 490   l-bf
 491   "branch if condition bit set (pc relative iaddr)"
 492   (COND-CTI !UNCOND-CTI)
 493   "l.bf ${disp26}"
 494   (+ OPC_BF disp26)
 495   (.pmacro ()
 496            (cti-transfer-control sys-sr-f disp26)
 497            )
 498   )
 499
 500 (dni l-trap "trap (exception)"
 501      ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT)
 502      "l.trap ${uimm16}"
 503      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16)
 504      ; Do exception entry handling in C function, PC set based on SR state
 505      (raise-exception EXCEPT-TRAP)
 506      ()
 507 )
 508
 509
 510 (dni l-sys "syscall (exception)"
 511      ; This function may not be in delay slot
 512      ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT)
 513
 514      "l.sys ${uimm16}"
 515      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16)
 516      ; Do exception entry handling in C function, PC set based on SR state
 517      (raise-exception EXCEPT-SYSCALL)
 518      ()
 519 )
 520
 521 (dni l-msync "memory sync"
 522      ((MACH ORBIS-MACHS))
 523      "l.msync"
 524      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_MSYNC (f-resv-20-21 0))
 525      (nop)
 526      ()
 527 )
 528
 529 (dni l-psync "pipeline sync"
 530      ((MACH ORBIS-MACHS))
 531      "l.psync"
 532      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_PSYNC (f-resv-20-21 0))
 533      (nop)
 534      ()
 535 )
 536
 537 (dni l-csync "context sync"
 538      ((MACH ORBIS-MACHS))
 539      "l.csync"
 540      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_CSYNC (f-resv-20-21 0))
 541      (nop)
 542      ()
 543 )
 544
 545 (dni l-rfe "return from exception"
 546      ; This function may not be in delay slot
 547      ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI)
 548
 549      "l.rfe"
 550      (+ OPC_RFE (f-resv-25-26 0))
 551      (c-call VOID "@cpu@_rfe")
 552      ()
 553 )
 554
 555 \f
 556 ; Misc instructions
 557
 558 ; l.nop with immediate must be first so it handles all l.nops in sim
 559 (dni l-nop-imm "nop uimm16"
 560      ((MACH ORBIS-MACHS))
 561      "l.nop ${uimm16}"
 562      (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16)
 563      (c-call VOID "@cpu@_nop" (zext UWI uimm16))
 564      ()
 565      )
 566
 567 (if (application-is? SIMULATOR)
 568     (begin)
 569     (begin
 570       (dni l-nop "nop"
 571            ((MACH ORBIS-MACHS))
 572            "l.nop"
 573            (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16)
 574            (nop)
 575            ()
 576            )
 577       )
 578 )
 579
 580 (dni l-movhi "movhi reg/uimm16"
 581      ((MACH ORBIS-MACHS))
 582      "l.movhi $rD,$uimm16"
 583      (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16)
 584      (set UWI rD (sll UWI (zext UWI uimm16) (const 16)))
 585      ()
 586 )
 587
 588 (dni l-macrc "macrc reg"
 589      ((MACH ORBIS-MACHS))
 590      "l.macrc $rD"
 591      (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0))
 592      (sequence ()
 593                (set UWI rD mac-maclo)
 594                (set UWI mac-maclo 0)
 595                (set UWI mac-machi 0)
 596                )
 597      ()
 598      )
 599
 600 \f
 601 ; System releated instructions
 602
 603 (dni l-mfspr "mfspr"
 604      ((MACH ORBIS-MACHS))
 605      "l.mfspr $rD,$rA,${uimm16}"
 606      (+ OPC_MFSPR rD rA uimm16)
 607      (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16))))
 608      ()
 609 )
 610
 611 (dni l-mtspr "mtspr"
 612      ((MACH ORBIS-MACHS))
 613      "l.mtspr $rA,$rB,${uimm16-split}"
 614      (+ OPC_MTSPR rA rB uimm16-split )
 615      (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB)
 616      ()
 617 )
 618
 619 \f
 620 ; Load instructions
 621 (define-pmacro (load-store-addr base offset size)
 622   (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size))
 623
 624 (dni l-lwz "l.lwz reg/simm16(reg)"
 625      ((MACH ORBIS-MACHS))
 626      "l.lwz $rD,${simm16}($rA)"
 627      (+ OPC_LWZ rD rA simm16)
 628      (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
 629      ()
 630 )
 631
 632
 633 (dni l-lws "l.lws reg/simm16(reg)"
 634      ((MACH ORBIS-MACHS))
 635      "l.lws $rD,${simm16}($rA)"
 636      (+ OPC_LWS rD rA simm16)
 637      (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4))))
 638      ()
 639 )
 640
 641 (dni l-lwa "l.lwa reg/simm16(reg)"
 642      ((MACH ORBIS-MACHS))
 643      "l.lwa $rD,${simm16}($rA)"
 644      (+ OPC_LWA rD rA simm16)
 645      (sequence ()
 646                (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
 647                (set atomic-reserve (const 1))
 648                (set atomic-address (load-store-addr rA simm16 4))
 649                )
 650      ()
 651 )
 652
 653 (dni l-lbz "l.lbz reg/simm16(reg)"
 654      ((MACH ORBIS-MACHS))
 655      "l.lbz $rD,${simm16}($rA)"
 656      (+ OPC_LBZ rD rA simm16)
 657      (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1))))
 658      ()
 659 )
 660
 661 (dni l-lbs "l.lbs reg/simm16(reg)"
 662      ((MACH ORBIS-MACHS))
 663      "l.lbs $rD,${simm16}($rA)"
 664      (+ OPC_LBS rD rA simm16)
 665      (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1))))
 666      ()
 667 )
 668
 669 (dni l-lhz "l.lhz reg/simm16(reg)"
 670      ((MACH ORBIS-MACHS))
 671      "l.lhz $rD,${simm16}($rA)"
 672      (+ OPC_LHZ rD simm16 rA)
 673      (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2))))
 674      ()
 675 )
 676
 677 (dni l-lhs "l.lhs reg/simm16(reg)"
 678      ((MACH ORBIS-MACHS))
 679      "l.lhs $rD,${simm16}($rA)"
 680      (+ OPC_LHS rD rA simm16)
 681      (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2))))
 682      ()
 683 )
 684
 685 \f
 686 ; Store instructions
 687
 688 (define-pmacro (store-insn mnemonic opc-op mode size)
 689   (begin
 690      (dni (.sym l- mnemonic)
 691           (.str "l." mnemonic " simm16(reg)/reg")
 692           ((MACH ORBIS-MACHS))
 693           (.str "l." mnemonic " ${simm16-split}($rA),$rB")
 694           (+ opc-op rA rB simm16-split)
 695           (sequence ((SI addr))
 696                     (set addr (load-store-addr rA simm16-split size))
 697                     (set mode (mem mode addr) (trunc mode rB))
 698                     (if (eq (and addr #xffffffc) atomic-address)
 699                         (set atomic-reserve (const 0))
 700                         )
 701                     )
 702           ()
 703      )
 704    )
 705 )
 706
 707 (store-insn sw OPC_SW USI 4)
 708 (store-insn sb OPC_SB UQI 1)
 709 (store-insn sh OPC_SH UHI 2)
 710
 711 (dni l-swa "l.swa simm16(reg)/reg"
 712      ((MACH ORBIS-MACHS))
 713      "l.swa ${simm16-split}($rA),$rB"
 714      (+ OPC_SWA rA rB simm16)
 715      (sequence ((SI addr) (BI flag))
 716                (set addr (load-store-addr rA simm16-split 4))
 717                (set sys-sr-f (and atomic-reserve (eq addr atomic-address)))
 718                (if sys-sr-f
 719                    (set USI (mem USI addr) (trunc USI rB))
 720                    )
 721                (set atomic-reserve (const 0))
 722                )
 723      ()
 724 )
 725
 726 \f
 727 ; Shift and rotate instructions
 728
 729 (define-pmacro (shift-insn mnemonic)
 730   (begin
 731      (dni (.sym l- mnemonic)
 732           (.str "l." mnemonic " reg/reg/reg")
 733           ((MACH ORBIS-MACHS))
 734           (.str "l." mnemonic " $rD,$rA,$rB")
 735           (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0)
 736              OPC_ALU_REGREG_SHROT )
 737           (set UWI rD (mnemonic rA rB))
 738           ()
 739      )
 740      (dni (.sym l- mnemonic "i")
 741           (.str "l." mnemonic " reg/reg/uimm6")
 742           ((MACH ORBIS-MACHS))
 743           (.str "l." mnemonic "i $rD,$rA,${uimm6}")
 744           (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6)
 745           (set rD (mnemonic rA uimm6))
 746           ()
 747      )
 748    )
 749 )
 750
 751 (shift-insn sll)
 752 (shift-insn srl)
 753 (shift-insn sra)
 754 (shift-insn ror)
 755
 756 \f
 757 ; Arithmetic insns
 758
 759 ; ALU op macro
 760 (define-pmacro (alu-insn mnemonic)
 761   (begin
 762      (dni (.sym l- mnemonic)
 763           (.str "l." mnemonic " reg/reg/reg")
 764           ((MACH ORBIS-MACHS))
 765           (.str "l." mnemonic " $rD,$rA,$rB")
 766           (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic)))
 767           (set rD (mnemonic rA rB))
 768           ()
 769      )
 770   )
 771 )
 772
 773 (alu-insn and)
 774 (alu-insn or)
 775 (alu-insn xor)
 776
 777 (define-pmacro (alu-carry-insn mnemonic)
 778   (begin
 779     (dni (.sym l- mnemonic)
 780          (.str "l." mnemonic " reg/reg/reg")
 781          ((MACH ORBIS-MACHS))
 782          (.str "l." mnemonic " $rD,$rA,$rB")
 783          (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic)))
 784          (sequence ()
 785                    (sequence ()
 786                              (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0))
 787                              (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0))
 788                              (set rD (mnemonic WI rA rB))
 789                              )
 790                    (if (andif sys-sr-ov sys-sr-ove)
 791                        (raise-exception EXCEPT-RANGE))
 792                    )
 793          ()
 794          )
 795     )
 796   )
 797
 798 (alu-carry-insn add)
 799 (alu-carry-insn sub)
 800
 801 (dni (l-addc) "l.addc reg/reg/reg"
 802           ((MACH ORBIS-MACHS))
 803           ("l.addc $rD,$rA,$rB")
 804           (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC)
 805           (sequence ()
 806                     (sequence ((BI tmp-sys-sr-cy))
 807                               (set BI tmp-sys-sr-cy sys-sr-cy)
 808                               (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy))
 809                               (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy))
 810                               (set rD (addc WI rA rB tmp-sys-sr-cy))
 811                               )
 812                    (if (andif sys-sr-ov sys-sr-ove)
 813                        (raise-exception EXCEPT-RANGE))
 814                    )
 815           ()
 816 )
 817
 818 (dni (l-mul) "l.mul reg/reg/reg"
 819           ((MACH ORBIS-MACHS))
 820           ("l.mul $rD,$rA,$rB")
 821           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL)
 822           (sequence ()
 823                     (sequence ()
 824                               ; 2's complement overflow
 825                               (set BI sys-sr-ov (mul-o2flag WI rA rB))
 826                               ; 1's complement overflow
 827                               (set BI sys-sr-cy (mul-o1flag WI rA rB))
 828                               (set rD (mul WI rA rB))
 829                               )
 830                     (if (andif sys-sr-ov sys-sr-ove)
 831                         (raise-exception EXCEPT-RANGE))
 832                     )
 833           ()
 834 )
 835
 836 (dni (l-mulu) "l.mulu reg/reg/reg"
 837           ((MACH ORBIS-MACHS))
 838           ("l.mulu $rD,$rA,$rB")
 839           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU)
 840           (sequence ()
 841                     (sequence ()
 842                               ; 2's complement overflow
 843                               (set BI sys-sr-ov 0)
 844                               ; 1's complement overflow
 845                               (set BI sys-sr-cy (mul-o1flag UWI rA rB))
 846                               (set rD (mul UWI rA rB))
 847                               )
 848                     (if (andif sys-sr-ov sys-sr-ove)
 849                         (raise-exception EXCEPT-RANGE))
 850                     )
 851           ()
 852 )
 853
 854 (dni l-div "divide (signed)"
 855           ((MACH ORBIS-MACHS))
 856           "l.div $rD,$rA,$rB"
 857           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV)
 858           (sequence ()
 859                     (if (ne rB 0)
 860                         (sequence ()
 861                                   (set BI sys-sr-cy 0)
 862                                   (set WI rD (div WI rA rB))
 863                                   )
 864                         (set BI sys-sr-cy 1)
 865                         )
 866                     (set BI sys-sr-ov 0)
 867                     (if (andif sys-sr-cy sys-sr-ove)
 868                         (raise-exception EXCEPT-RANGE))
 869                     )
 870           ()
 871 )
 872
 873 (dni l-divu "divide (unsigned)"
 874           ((MACH ORBIS-MACHS))
 875           "l.divu $rD,$rA,$rB"
 876           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU)
 877           (sequence ()
 878                     (if (ne rB 0)
 879                         (sequence ()
 880                                   (set BI sys-sr-cy 0)
 881                                   (set rD (udiv UWI rA rB))
 882                                   )
 883                         (set BI sys-sr-cy 1)
 884                         )
 885                     (set BI sys-sr-ov 0)
 886                     (if (andif sys-sr-cy sys-sr-ove)
 887                         (raise-exception EXCEPT-RANGE))
 888                     )
 889           ()
 890 )
 891
 892 (dni l-ff1 "find first '1'"
 893           ((MACH ORBIS-MACHS))
 894           "l.ff1 $rD,$rA"
 895           (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1)
 896           (set rD (c-call UWI "@cpu@_ff1" rA))
 897           ()
 898 )
 899
 900 (dni l-fl1 "find last '1'"
 901           ((MACH ORBIS-MACHS))
 902           "l.fl1 $rD,$rA"
 903           (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1)
 904           (set rD (c-call UWI "@cpu@_fl1" rA))
 905           ()
 906 )
 907
 908
 909 (define-pmacro (alu-insn-simm  mnemonic)
 910   (begin
 911       (dni (.sym l- mnemonic "i")
 912           (.str "l." mnemonic " reg/reg/simm16")
 913           ((MACH ORBIS-MACHS))
 914           (.str "l." mnemonic "i $rD,$rA,$simm16")
 915           (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16)
 916           (set rD (mnemonic rA (ext WI simm16)))
 917           ()
 918      )
 919    )
 920 )
 921
 922 (define-pmacro (alu-insn-uimm  mnemonic)
 923   (begin
 924       (dni (.sym l- mnemonic "i")
 925           (.str "l." mnemonic " reg/reg/uimm16")
 926           ((MACH ORBIS-MACHS))
 927           (.str "l." mnemonic "i $rD,$rA,$uimm16")
 928           (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16)
 929           (set rD (mnemonic rA (zext UWI uimm16)))
 930           ()
 931      )
 932    )
 933 )
 934
 935 (alu-insn-uimm and)
 936 (alu-insn-uimm or)
 937 (alu-insn-simm xor)
 938
 939 (define-pmacro (alu-carry-insn-simm mnemonic)
 940   (begin
 941     (dni (.sym l- mnemonic "i")
 942          (.str "l." mnemonic "i reg/reg/simm16")
 943          ((MACH ORBIS-MACHS))
 944          (.str "l." mnemonic "i $rD,$rA,$simm16")
 945          (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16)
 946          (sequence ()
 947                    (sequence ()
 948                              (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0))
 949                              (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0))
 950                              (set rD (mnemonic WI rA (ext WI simm16)))
 951                              )
 952                    (if (andif sys-sr-ov sys-sr-ove)
 953                        (raise-exception EXCEPT-RANGE))
 954                    )
 955          ()
 956          )
 957     )
 958   )
 959
 960 (alu-carry-insn-simm add)
 961
 962 (dni (l-addic)
 963      ("l.addic reg/reg/simm16")
 964      ((MACH ORBIS-MACHS))
 965      ("l.addic $rD,$rA,$simm16")
 966      (+ OPC_ADDIC rD rA simm16)
 967      (sequence ()
 968                (sequence ((BI tmp-sys-sr-cy))
 969                          (set BI tmp-sys-sr-cy sys-sr-cy)
 970                          (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy))
 971                          (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy))
 972                          (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy))
 973                          )
 974                (if (andif sys-sr-ov sys-sr-ove)
 975                    (raise-exception EXCEPT-RANGE))
 976                )
 977      ()
 978 )
 979
 980 (dni (l-muli)
 981      "l.muli reg/reg/simm16"
 982      ((MACH ORBIS-MACHS))
 983      ("l.muli $rD,$rA,$simm16")
 984      (+ OPC_MULI rD rA simm16)
 985      (sequence ()
 986                (sequence ()
 987                          ; 2's complement overflow
 988                          (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16)))
 989                          ; 1's complement overflow
 990                          (set sys-sr-cy (mul-o1flag UWI rA (ext UWI simm16)))
 991                          (set rD (mul WI rA (ext WI simm16)))
 992                          )
 993                (if (andif sys-sr-ov sys-sr-ove)
 994                    (raise-exception EXCEPT-RANGE))
 995                )
 996      ()
 997      )
 998
 999 (define-pmacro (extbh-insn mnemonic extop extmode truncmode)
1000   (begin
1001     (dni (.sym l- mnemonic)
1002          (.str "l." mnemonic " reg/reg")
1003          ((MACH ORBIS-MACHS))
1004          (.str "l." mnemonic " $rD,$rA")
1005          (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH)
1006          (set rD (extop extmode (trunc truncmode rA)))
1007          ()
1008          )
1009     )
1010   )
1011
1012 (extbh-insn exths ext  WI  HI)
1013 (extbh-insn extbs ext  WI  QI)
1014 (extbh-insn exthz zext UWI UHI)
1015 (extbh-insn extbz zext UWI UQI)
1016
1017 (define-pmacro (extw-insn mnemonic extop extmode truncmode)
1018   (begin
1019     (dni (.sym l- mnemonic)
1020          (.str "l." mnemonic " reg/reg")
1021          ((MACH ORBIS-MACHS))
1022          (.str "l." mnemonic " $rD,$rA")
1023          (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW)
1024          (set rD (extop extmode (trunc truncmode rA)))
1025          ()
1026          )
1027     )
1028   )
1029
1030 (extw-insn extws ext  WI  SI)
1031 (extw-insn extwz zext USI USI)
1032
1033 (dni l-cmov
1034      "l.cmov reg/reg/reg"
1035      ((MACH ORBIS-MACHS))
1036      "l.cmov $rD,$rA,$rB"
1037      (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV)
1038      (if sys-sr-f
1039          (set UWI rD rA)
1040          (set UWI rD rB)
1041          )
1042      ()
1043      )
1044
1045 ; Compare instructions
1046
1047 ; Ordering compare
1048 (define-pmacro (sf-insn op)
1049   (begin
1050      (dni (.sym l- "sf" op "s")                                               ; l-sfgts
1051           (.str "l.sf" op "s reg/reg")                                        ; "l.sfgts reg/reg"
1052           ((MACH ORBIS-MACHS))
1053           (.str "l.sf" op "s $rA,$rB")                                        ; "l.sfgts $rA,$rB"
1054           (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0))
1055           (set sys-sr-f (op WI rA rB))                                        ; (set sys-sr-f (gt WI rA rB))
1056           ()
1057           )
1058      (dni (.sym l- "sf" op "si")                                              ; l-sfgtsi
1059           (.str "l.sf" op "si reg/simm16")                                    ; "l.sfgtsi reg/simm16"
1060           ((MACH ORBIS-MACHS))
1061           (.str "l.sf" op "si $rA,$simm16")                                   ; "l.sfgtsi $rA,$simm16"
1062           (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16)             ; (+ OPC_SFI OPC_SF_GTS rA simm16)
1063           (set sys-sr-f (op WI rA (ext WI simm16)))                           ; (set sys-sr-f (gt WI rA (ext WI simm16)))
1064           ()
1065           )
1066      (dni (.sym l- "sf" op "u")                                               ; l-sfgtu
1067           (.str "l.sf" op "u reg/reg")                                        ; "l.sfgtu reg/reg"
1068           ((MACH ORBIS-MACHS))
1069           (.str "l.sf" op "u $rA,$rB")                                        ; "l.sfgtu $rA,$rB"
1070           (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0))
1071           (set sys-sr-f ((.sym op "u") WI rA rB))                             ; (set sys-sr-f (gtu WI rA rB))
1072           ()
1073           )
1074      ; immediate is sign extended even for unsigned compare
1075      (dni (.sym l- "sf" op "ui")                                              ; l-sfgtui
1076           (.str "l.sf" op "ui reg/simm16")                                    ; "l.sfgtui reg/uimm16"
1077           ((MACH ORBIS-MACHS))
1078           (.str "l.sf" op "ui $rA,$simm16")                                   ; "l.sfgtui $rA,$simm16"
1079           (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16)             ; (+ OPC_SFI OPC_SF_GTU rA simm16)
1080           (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16)))                ; (set sys-sr-f (gtu WI rA (ext WI simm16)))
1081           ()
1082           )
1083      )
1084   )
1085
1086 (sf-insn gt)
1087 (sf-insn ge)
1088 (sf-insn lt)
1089 (sf-insn le)
1090
1091 ; Equality compare
1092 (define-pmacro (sf-insn-eq op)
1093   (begin
1094      (dni (.sym l- "sf" op)
1095           (.str "l." op " reg/reg")
1096           ((MACH ORBIS-MACHS))
1097           (.str "l.sf" op " $rA,$rB")
1098           (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0))
1099           (set sys-sr-f (op WI rA rB))
1100           ()
1101      )
1102      (dni (.sym l- "sf" op "i")
1103           (.str "l.sf" op "i reg/simm16")
1104           ((MACH ORBIS-MACHS))
1105           (.str "l.sf" op "i $rA,$simm16")
1106           (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16)
1107           (set sys-sr-f (op WI rA (ext WI simm16)))
1108           ()
1109      )
1110    )
1111 )
1112
1113 (sf-insn-eq eq)
1114 (sf-insn-eq ne)
1115
1116 (dni l-mac
1117      "l.mac reg/reg"
1118      ((MACH ORBIS-MACHS))
1119      "l.mac $rA,$rB"
1120      (+  OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC)
1121      (sequence ((WI prod) (DI result))
1122                (set WI prod (mul WI rA rB))
1123                (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
1124                (set SI mac-machi (subword SI result 0))
1125                (set SI mac-maclo (subword SI result 1))
1126                )
1127      ()
1128      )
1129
1130 (dni l-msb
1131      "l.msb reg/reg"
1132      ((MACH ORBIS-MACHS))
1133      "l.msb $rA,$rB"
1134      (+  OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB)
1135      (sequence ((WI prod) (DI result))
1136                (set WI prod (mul WI rA rB))
1137                (set DI result (sub (join DI SI mac-machi mac-maclo) (ext DI prod)))
1138                (set SI mac-machi (subword SI result 0))
1139                (set SI mac-maclo (subword SI result 1))
1140                )
1141      ()
1142      )
1143
1144 (dni l-maci
1145      "l.maci reg/simm16"
1146      ((MACH ORBIS-MACHS))
1147      "l.maci $rA,${simm16}"
1148      (+ OPC_MACI (f-resv-25-5 0) rA simm16)
1149      (sequence ((WI prod) (DI result))
1150                (set WI prod (mul WI (ext WI simm16) rA))
1151                (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
1152                (set SI mac-machi (subword SI result 0))
1153                (set SI mac-maclo (subword SI result 1))
1154                )
1155      ()
1156      )
1157
1158 (define-pmacro (cust-insn cust-num)
1159   (begin
1160     (dni (.sym l- "cust" cust-num)
1161          (.str "l.cust" cust-num)
1162          ((MACH ORBIS-MACHS))
1163          (.str "l.cust" cust-num)
1164          (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0))
1165          (nop)
1166          ()
1167          )
1168     )
1169   )
1170
1171 (cust-insn "1")
1172 (cust-insn "2")
1173 (cust-insn "3")
1174 (cust-insn "4")
1175 (cust-insn "5")
1176 (cust-insn "6")
1177 (cust-insn "7")
1178 (cust-insn "8")