cpu/or1korbis.cpu

   1 ; OpenRISC Basic Instruction Set 32-bit (ORBIS)  -*- Scheme -*-
   2 ; Copyright 2000-2014 Free Software Foundation, Inc.
   3 ; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
   4 ; Modified by Julius Baxter, juliusbaxter@gmail.com
   5 ; Modified by Peter Gavin, pgavin@gmail.com
   6 ;
   7 ; This program is free software; you can redistribute it and/or modify
   8 ; it under the terms of the GNU General Public License as published by
   9 ; the Free Software Foundation; either version 3 of the License, or
  10 ; (at your option) any later version.
  11 ;
  12 ; This program is distributed in the hope that it will be useful,
  13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ; GNU General Public License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with this program; if not, see <http://www.gnu.org/licenses/>
  19
  20 ; Instruction fields.
  21
  22 ; Hardware for immediate operands
  23 (dnh h-simm16      "16-bit signed immediate"   ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ())
  24 (dnh h-uimm16      "16-bit unsigned immediate" ()                   (immediate (UINT 16)) () () ())
  25 (dnh h-uimm6       "6-bit unsigned immediate"  ()                   (immediate (UINT 6)) () () ())
  26
  27 ; Instruction classes.
  28 (dnf f-opcode      "insn opcode"               ((MACH ORBIS-MACHS)) 31 6)
  29
  30 ; Register fields.
  31 (dnf f-r1          "r1"                        ((MACH ORBIS-MACHS)) 25 5)
  32 (dnf f-r2          "r2"                        ((MACH ORBIS-MACHS)) 20 5)
  33 (dnf f-r3          "r3"                        ((MACH ORBIS-MACHS)) 15 5)
  34
  35 ; Sub fields
  36 (dnf f-op-25-2     "op-25-2"                   ((MACH ORBIS-MACHS)) 25 2) ;; nop
  37 (dnf f-op-25-5     "op-25-5"                   ((MACH ORBIS-MACHS)) 25 5) ;; sys, trap, *sync, sf*
  38 (dnf f-op-16-1     "op-16-1"                   ((MACH ORBIS-MACHS)) 16 1) ;; movhi,macrc
  39 (dnf f-op-7-4      "op-7-4"                    ((MACH ORBIS-MACHS)) 7 4)
  40 (dnf f-op-3-4      "op-3-4"                    ((MACH ORBIS-MACHS)) 3 4)
  41 (dnf f-op-9-2      "op-9-2"                    ((MACH ORBIS-MACHS)) 9 2) ;; alu ops upper opcode
  42 (dnf f-op-9-4      "op-9-4"                    ((MACH ORBIS-MACHS)) 9 4) ;;
  43 (dnf f-op-7-8      "op-7-8"                    ((MACH ORBIS-MACHS)) 7 8)
  44 (dnf f-op-7-2      "op-7-2"                    ((MACH ORBIS-MACHS)) 7 2) ;; alu lower upper opc,shroti
  45
  46 ; Reserved fields
  47 (dnf f-resv-25-26  "resv-25-26"                ((MACH ORBIS-MACHS) RESERVED) 25 26)
  48 (dnf f-resv-25-10  "resv-25-10"                ((MACH ORBIS-MACHS) RESERVED) 25 10)
  49 (dnf f-resv-25-5   "resv-25-5"                 ((MACH ORBIS-MACHS) RESERVED) 25 5)
  50 (dnf f-resv-23-8   "resv-23-8"                 ((MACH ORBIS-MACHS) RESERVED) 23 8)
  51 (dnf f-resv-20-5   "resv-20-5"                 ((MACH ORBIS-MACHS) RESERVED) 20 5)
  52 (dnf f-resv-20-4   "resv-20-4"                 ((MACH ORBIS-MACHS) RESERVED) 20 4)
  53 (dnf f-resv-15-8   "resv-15-8"                 ((MACH ORBIS-MACHS) RESERVED) 15 8)
  54 (dnf f-resv-15-6   "resv-15-6"                 ((MACH ORBIS-MACHS) RESERVED) 15 6)
  55 (dnf f-resv-10-11  "resv-10-11"                ((MACH ORBIS-MACHS) RESERVED) 10 11)
  56 (dnf f-resv-10-7   "resv-10-7"                 ((MACH ORBIS-MACHS) RESERVED) 10 7)
  57 (dnf f-resv-10-3   "resv-10-3"                 ((MACH ORBIS-MACHS) RESERVED) 10 3)
  58 (dnf f-resv-10-1   "resv-10-1"                 ((MACH ORBIS-MACHS) RESERVED) 10 1)
  59 (dnf f-resv-7-4    "resv-7-4"                  ((MACH ORBIS-MACHS) RESERVED) 7 4)
  60 (dnf f-resv-5-2    "resv-5-2"                  ((MACH ORBIS-MACHS) RESERVED) 5 2)
  61
  62 (dnf f-imm16-25-5  "imm16-25-5"                ((MACH ORBIS-MACHS)) 25  5)
  63 (dnf f-imm16-10-11 "imm16-10-11"               ((MACH ORBIS-MACHS)) 10 11)
  64
  65 ; PC relative, 26-bit (2 shifted to right)
  66 (df f-disp26
  67     "disp26"
  68     ((MACH ORBIS-MACHS) PCREL-ADDR)
  69     25
  70     26
  71     INT
  72     ((value pc) (sra SI (sub IAI value pc) (const 2)))
  73     ((value pc) (add IAI (sll IAI value (const 2)) pc))
  74     )
  75
  76 ; Immediates.
  77 (dnf f-uimm16    "uimm16"                      ((MACH ORBIS-MACHS))          15 16)
  78 (df  f-simm16    "simm16"                      ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f)
  79 (dnf f-uimm6     "uimm6"                       ((MACH ORBIS-MACHS))          5  6) ;; shroti
  80
  81 (define-multi-ifield
  82   (name f-uimm16-split)
  83   (comment "16-bit split unsigned immediate")
  84   (attrs (MACH ORBIS-MACHS))
  85   (mode UINT)
  86   (subfields f-imm16-25-5 f-imm16-10-11)
  87   (insert (sequence ()
  88                     (set (ifield f-imm16-25-5)
  89                          (and (srl (ifield f-uimm16-split)
  90                                    (const 11))
  91                               (const #x1f)))
  92                     (set (ifield f-imm16-10-11)
  93                          (and (ifield f-uimm16-split)
  94                               (const #x7ff)))))
  95   (extract
  96            (set (ifield f-uimm16-split)
  97                 (trunc UHI
  98                        (or (sll (ifield f-imm16-25-5)
  99                                 (const 11))
 100                            (ifield f-imm16-10-11)))))
 101   )
 102
 103 (define-multi-ifield
 104   (name f-simm16-split)
 105   (comment "16-bit split signed immediate")
 106   (attrs (MACH ORBIS-MACHS) SIGN-OPT)
 107   (mode INT)
 108   (subfields f-imm16-25-5 f-imm16-10-11)
 109   (insert (sequence ()
 110                     (set (ifield f-imm16-25-5)
 111                          (and (sra (ifield f-simm16-split)
 112                                    (const 11))
 113                               (const #x1f)))
 114                     (set (ifield f-imm16-10-11)
 115                          (and (ifield f-simm16-split)
 116                               (const #x7ff)))))
 117   (extract
 118            (set (ifield f-simm16-split)
 119                 (trunc HI
 120                        (or (sll (ifield f-imm16-25-5)
 121                                 (const 11))
 122                            (ifield f-imm16-10-11)))))
 123   )
 124
 125 ; Enums.
 126
 127 ; insn-opcode: bits 31-26
 128 (define-normal-insn-enum
 129   insn-opcode "insn main opcode enums" ((MACH ORBIS-MACHS)) OPC_ f-opcode
 130   (("J"            #x00)
 131    ("JAL"          #x01)
 132    ("BNF"          #x03)
 133    ("BF"           #x04)
 134    ("NOP"          #x05)
 135    ("MOVHIMACRC"   #x06)
 136    ("SYSTRAPSYNCS" #x08)
 137    ("RFE"          #x09)
 138    ("VECTOR"       #x0a)
 139    ("JR"           #x11)
 140    ("JALR"         #x12)
 141    ("MACI"         #x13)
 142    ("CUST1"        #x1c)
 143    ("CUST2"        #x1d)
 144    ("CUST3"        #x1e)
 145    ("CUST4"        #x1f)
 146    ("LD"           #x20)
 147    ("LWZ"          #x21)
 148    ("LWS"          #x22)
 149    ("LBZ"          #x23)
 150    ("LBS"          #x24)
 151    ("LHZ"          #x25)
 152    ("LHS"          #x26)
 153    ("ADDI"         #x27)
 154    ("ADDIC"        #x28)
 155    ("ANDI"         #x29)
 156    ("ORI"          #x2a)
 157    ("XORI"         #x2b)
 158    ("MULI"         #x2c)
 159    ("MFSPR"        #x2d)
 160    ("SHROTI"       #x2e)
 161    ("SFI"          #x2f)
 162    ("MTSPR"        #x30)
 163    ("MAC"          #x31)
 164    ("FLOAT"        #x32)
 165    ("SD"           #x34)
 166    ("SW"           #x35)
 167    ("SB"           #x36)
 168    ("SH"           #x37)
 169    ("ALU"          #x38)
 170    ("SF"           #x39)
 171    ("CUST5"        #x3c)
 172    ("CUST6"        #x3d)
 173    ("CUST7"        #x3e)
 174    ("CUST8"        #x3f)
 175   )
 176 )
 177
 178 (define-normal-insn-enum insn-opcode-systrapsyncs
 179   "systrapsync insn opcode enums" ((MACH ORBIS-MACHS))
 180   OPC_SYSTRAPSYNCS_ f-op-25-5
 181     (("SYSCALL" #x00 )
 182      ("TRAP" #x08 )
 183      ("MSYNC" #x10 )
 184      ("PSYNC" #x14 )
 185      ("CSYNC" #x18 )
 186     )
 187 )
 188
 189 (define-normal-insn-enum insn-opcode-movehimacrc
 190   "movhi/macrc insn opcode enums" ((MACH ORBIS-MACHS))
 191   OPC_MOVHIMACRC_ f-op-16-1
 192   (("MOVHI" #x0)
 193    ("MACRC" #x1)
 194   )
 195 )
 196
 197 (define-normal-insn-enum insn-opcode-mac
 198   "multiply/accumulate insn opcode enums" ((MACH ORBIS-MACHS))
 199   OPC_MAC_ f-op-3-4
 200   (("MAC" #x1)
 201    ("MSB" #x2)
 202    )
 203   )
 204
 205 (define-normal-insn-enum insn-opcode-shorts
 206   "shift/rotate insn opcode enums" ((MACH ORBIS-MACHS))
 207   OPC_SHROTS_ f-op-7-2
 208     (("SLL" #x0 )
 209      ("SRL" #x1 )
 210      ("SRA" #x2 )
 211      ("ROR" #x3 )
 212     )
 213 )
 214
 215 (define-normal-insn-enum insn-opcode-extbhs
 216   "extend byte/half opcode enums" ((MACH ORBIS-MACHS))
 217   OPC_EXTBHS_ f-op-9-4
 218   (("EXTHS" #x0)
 219    ("EXTBS" #x1)
 220    ("EXTHZ" #x2)
 221    ("EXTBZ" #x3)
 222    )
 223 )
 224
 225 (define-normal-insn-enum insn-opcode-extws
 226   "extend word opcode enums" ((MACH ORBIS-MACHS))
 227   OPC_EXTWS_ f-op-9-4
 228   (("EXTWS" #x0)
 229    ("EXTWZ" #x1)
 230    )
 231 )
 232
 233 (define-normal-insn-enum insn-opcode-alu-regreg
 234   "alu reg/reg insn opcode enums" ((MACH ORBIS-MACHS))
 235   OPC_ALU_REGREG_ f-op-3-4
 236   (("ADD"   #x0)
 237    ("ADDC"  #x1)
 238    ("SUB"   #x2)
 239    ("AND"   #x3)
 240    ("OR"    #x4)
 241    ("XOR"   #x5)
 242    ("MUL"   #x6)
 243    ("SHROT" #x8)
 244    ("DIV"   #x9)
 245    ("DIVU"  #xA)
 246    ("MULU"  #xB)
 247    ("EXTBH" #xC)
 248    ("EXTW"  #xD)
 249    ("CMOV"  #xE)
 250    ("FFL1"  #xF)
 251    )
 252 )
 253
 254 (define-normal-insn-enum insn-opcode-setflag
 255   "setflag insn opcode enums" ((MACH ORBIS-MACHS))
 256   OPC_SF_ f-op-25-5
 257     (("EQ"  #x00)
 258      ("NE"  #x01)
 259      ("GTU" #x02)
 260      ("GEU" #x03)
 261      ("LTU" #x04)
 262      ("LEU" #x05)
 263      ("GTS" #x0A)
 264      ("GES" #x0B)
 265      ("LTS" #x0C)
 266      ("LES" #x0D)
 267     )
 268 )
 269
 270 \f
 271 ; Instruction operands.
 272
 273 (dnop sys-sr            "supervision register"             ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr            f-nil)
 274 (dnop sys-esr0          "exception supervision register 0" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-esr0          f-nil)
 275 (dnop sys-epcr0         "exception PC register 0"          ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-epcr0         f-nil)
 276
 277 (dnop sys-sr-lee        "SR little endian enable bit"      ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-lee        f-nil)
 278 (dnop sys-sr-f          "SR flag bit"                      ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-f          f-nil)
 279 (dnop sys-sr-cy         "SR carry bit"                     ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-cy         f-nil)
 280 (dnop sys-sr-ov         "SR overflow bit"                  ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ov         f-nil)
 281 (dnop sys-sr-ove        "SR overflow exception enable bit" ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-sr-ove        f-nil)
 282 (dnop sys-cpucfgr-ob64s "CPUCFGR ORBIS64 supported bit"    ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-ob64s f-nil)
 283 (dnop sys-cpucfgr-nd    "CPUCFGR no delay bit"             ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-cpucfgr-nd    f-nil)
 284 (dnop sys-fpcsr-rm      "floating point round mode"        ((MACH ORBIS-MACHS) SEM-ONLY) h-sys-fpcsr-rm      f-nil)
 285
 286 (dnop mac-machi         "MAC HI result register"           ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-machi         f-nil)
 287 (dnop mac-maclo         "MAC LO result register"           ((MACH ORBIS-MACHS) SEM-ONLY) h-mac-maclo         f-nil)
 288
 289 (dnop uimm6             "uimm6"                            ((MACH ORBIS-MACHS))          h-uimm6             f-uimm6)
 290
 291 (dnop rD                "destination register"             ((MACH ORBIS-MACHS))          h-gpr               f-r1)
 292 (dnop rA                "source register A"                ((MACH ORBIS-MACHS))          h-gpr               f-r2)
 293 (dnop rB                "source register B"                ((MACH ORBIS-MACHS))          h-gpr               f-r3)
 294
 295 (define-operand
 296   (name disp26)
 297   (comment "pc-rel 26 bit")
 298   (attrs (MACH ORBIS-MACHS))
 299   (type h-iaddr)
 300   (index f-disp26)
 301   (handlers (parse "disp26"))
 302   )
 303
 304 (define-operand
 305   (name simm16)
 306   (comment "16-bit signed immediate")
 307   (attrs (MACH ORBIS-MACHS) SIGN-OPT)
 308   (type h-simm16)
 309   (index f-simm16)
 310   (handlers (parse "simm16"))
 311   )
 312
 313 (define-operand
 314   (name uimm16)
 315   (comment "16-bit unsigned immediate")
 316   (attrs (MACH ORBIS-MACHS))
 317   (type h-uimm16)
 318   (index f-uimm16)
 319   (handlers (parse "uimm16"))
 320   )
 321
 322 (define-operand
 323   (name simm16-split)
 324   (comment "split 16-bit signed immediate")
 325   (attrs (MACH ORBIS-MACHS) SIGN-OPT)
 326   (type h-simm16)
 327   (index f-simm16-split)
 328   (handlers (parse "simm16"))
 329 )
 330
 331 (define-operand
 332   (name uimm16-split)
 333   (comment "split 16-bit unsigned immediate")
 334   (attrs (MACH ORBIS-MACHS))
 335   (type h-uimm16)
 336   (index f-uimm16-split)
 337   (handlers (parse "uimm16"))
 338 )
 339
 340 ; Instructions.
 341
 342 ; Branch releated instructions
 343
 344 (define-pmacro (cti-link-return)
 345   (set IAI (reg h-gpr 9) (add pc (if sys-cpucfgr-nd 4 8)))
 346   )
 347 (define-pmacro (cti-transfer-control condition target)
 348   ;; this mess is necessary because we're
 349   ;; skipping the delay slot, but it's
 350   ;; actually the start of the next basic
 351   ;; block
 352   (sequence ()
 353             (if condition
 354                 (delay 1 (set IAI pc target))
 355                 (if sys-cpucfgr-nd
 356                     (delay 1 (set IAI pc (add pc 4))))
 357                 )
 358             (if sys-cpucfgr-nd
 359                 (skip 1)
 360                 )
 361             )
 362   )
 363
 364 (define-pmacro
 365   (define-cti
 366     cti-name
 367     cti-comment
 368     cti-attrs
 369     cti-syntax
 370     cti-format
 371     cti-semantics)
 372   (begin
 373     (dni
 374       cti-name
 375       cti-comment
 376       (.splice (MACH ORBIS-MACHS) DELAYED-CTI NOT-IN-DELAY-SLOT (.unsplice cti-attrs))
 377       cti-syntax
 378       cti-format
 379       (cti-semantics)
 380       ()
 381       )
 382     )
 383   )
 384
 385 (define-cti
 386   l-j
 387   "jump (pc-relative iaddr)"
 388   (!COND-CTI UNCOND-CTI)
 389   "l.j ${disp26}"
 390   (+ OPC_J disp26)
 391   (.pmacro ()
 392            (cti-transfer-control 1 disp26)
 393            )
 394   )
 395
 396 (define-cti
 397   l-jal
 398   "jump and link (pc-relative iaddr)"
 399   (!COND-CTI UNCOND-CTI)
 400   "l.jal ${disp26}"
 401   (+ OPC_JAL disp26)
 402   (.pmacro ()
 403            (sequence ()
 404                      (cti-link-return)
 405                      (cti-transfer-control 1 disp26)
 406                      )
 407            )
 408   )
 409
 410 (define-cti
 411   l-jr
 412   "jump register (absolute iaddr)"
 413   (!COND-CTI UNCOND-CTI)
 414   "l.jr $rB"
 415   (+ OPC_JR (f-resv-25-10 0) rB (f-resv-10-11 0))
 416   (.pmacro ()
 417            (cti-transfer-control 1 rB)
 418            )
 419   )
 420
 421 (define-cti
 422   l-jalr
 423   "jump register and link (absolute iaddr)"
 424   (!COND-CTI UNCOND-CTI)
 425   "l.jalr $rB"
 426   (+ OPC_JALR (f-resv-25-10 0) rB (f-resv-10-11 0) )
 427   (.pmacro ()
 428            (sequence ()
 429                      (cti-link-return)
 430                      (cti-transfer-control 1 rB)
 431                      )
 432            )
 433   )
 434
 435 (define-cti
 436   l-bnf
 437   "branch if condition bit not set (pc relative iaddr)"
 438   (COND-CTI !UNCOND-CTI)
 439   "l.bnf ${disp26}"
 440   (+ OPC_BNF disp26)
 441   (.pmacro ()
 442            (cti-transfer-control (not sys-sr-f) disp26)
 443            )
 444   )
 445
 446 (define-cti
 447   l-bf
 448   "branch if condition bit set (pc relative iaddr)"
 449   (COND-CTI !UNCOND-CTI)
 450   "l.bf ${disp26}"
 451   (+ OPC_BF disp26)
 452   (.pmacro ()
 453            (cti-transfer-control sys-sr-f disp26)
 454            )
 455   )
 456
 457 (dni l-trap "trap (exception)"
 458      ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT)
 459      "l.trap ${uimm16}"
 460      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_TRAP (f-resv-20-5 0) uimm16)
 461      ; Do exception entry handling in C function, PC set based on SR state
 462      (raise-exception EXCEPT-TRAP)
 463      ()
 464 )
 465
 466
 467 (dni l-sys "syscall (exception)"
 468      ; This function may not be in delay slot
 469      ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT)
 470
 471      "l.sys ${uimm16}"
 472      (+ OPC_SYSTRAPSYNCS OPC_SYSTRAPSYNCS_SYSCALL (f-resv-20-5 0) uimm16)
 473      ; Do exception entry handling in C function, PC set based on SR state
 474      (raise-exception EXCEPT-SYSCALL)
 475      ()
 476 )
 477
 478
 479 (dni l-rfe "return from exception"
 480      ; This function may not be in delay slot
 481      ((MACH ORBIS-MACHS) NOT-IN-DELAY-SLOT FORCED-CTI)
 482
 483      "l.rfe"
 484      (+ OPC_RFE (f-resv-25-26 0))
 485      (c-call VOID "@cpu@_rfe")
 486      ()
 487 )
 488
 489 \f
 490 ; Misc instructions
 491
 492 ; l.nop with immediate must be first so it handles all l.nops in sim
 493 (dni l-nop-imm "nop uimm16"
 494      ((MACH ORBIS-MACHS))
 495      "l.nop ${uimm16}"
 496      (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16)
 497      (c-call VOID "@cpu@_nop" (zext UWI uimm16))
 498      ()
 499      )
 500
 501 (if (application-is? SIMULATOR)
 502     (begin)
 503     (begin
 504       (dni l-nop "nop"
 505            ((MACH ORBIS-MACHS))
 506            "l.nop"
 507            (+ OPC_NOP (f-op-25-2 #x1) (f-resv-23-8 0) uimm16)
 508            (nop)
 509            ()
 510            )
 511       )
 512 )
 513
 514 (dni l-movhi "movhi reg/uimm16"
 515      ((MACH ORBIS-MACHS))
 516      "l.movhi $rD,$uimm16"
 517      (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MOVHI uimm16)
 518      (set UWI rD (sll UWI (zext UWI uimm16) (const 16)))
 519      ()
 520 )
 521
 522 (dni l-macrc "macrc reg"
 523      ((MACH ORBIS-MACHS))
 524      "l.macrc $rD"
 525      (+ OPC_MOVHIMACRC rD (f-resv-20-4 0) OPC_MOVHIMACRC_MACRC (f-uimm16 0))
 526      (sequence ()
 527                (set UWI rD mac-maclo)
 528                (set UWI mac-maclo 0)
 529                (set UWI mac-machi 0)
 530                )
 531      ()
 532      )
 533
 534 \f
 535 ; System releated instructions
 536
 537 (dni l-mfspr "mfspr"
 538      ((MACH ORBIS-MACHS))
 539      "l.mfspr $rD,$rA,${uimm16}"
 540      (+ OPC_MFSPR rD rA uimm16)
 541      (set UWI rD (c-call UWI "@cpu@_mfspr" (or rA (zext UWI uimm16))))
 542      ()
 543 )
 544
 545 (dni l-mtspr "mtspr"
 546      ((MACH ORBIS-MACHS))
 547      "l.mtspr $rA,$rB,${uimm16-split}"
 548      (+ OPC_MTSPR rA rB uimm16-split )
 549      (c-call VOID "@cpu@_mtspr" (or rA (zext WI uimm16-split)) rB)
 550      ()
 551 )
 552
 553 \f
 554 ; Load instructions
 555 (define-pmacro (load-store-addr base offset size)
 556   (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size))
 557
 558 (dni l-lwz "l.lwz reg/simm16(reg)"
 559      ((MACH ORBIS-MACHS))
 560      "l.lwz $rD,${simm16}($rA)"
 561      (+ OPC_LWZ rD rA simm16)
 562      (set UWI rD (zext UWI (mem USI (load-store-addr rA simm16 4))))
 563      ()
 564 )
 565
 566
 567 (dni l-lws "l.lws reg/simm16(reg)"
 568      ((MACH ORBIS-MACHS))
 569      "l.lws $rD,${simm16}($rA)"
 570      (+ OPC_LWS rD rA simm16)
 571      (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4))))
 572      ()
 573 )
 574
 575 (dni l-lbz "l.lbz reg/simm16(reg)"
 576      ((MACH ORBIS-MACHS))
 577      "l.lbz $rD,${simm16}($rA)"
 578      (+ OPC_LBZ rD rA simm16)
 579      (set UWI rD (zext UWI (mem UQI (load-store-addr rA simm16 1))))
 580      ()
 581 )
 582
 583 (dni l-lbs "l.lbz reg/simm16(reg)"
 584      ((MACH ORBIS-MACHS))
 585      "l.lbs $rD,${simm16}($rA)"
 586      (+ OPC_LBS rD rA simm16)
 587      (set WI rD (ext WI (mem QI (load-store-addr rA simm16 1))))
 588      ()
 589 )
 590
 591 (dni l-lhz "l.lhz reg/simm16(reg)"
 592      ((MACH ORBIS-MACHS))
 593      "l.lhz $rD,${simm16}($rA)"
 594      (+ OPC_LHZ rD simm16 rA)
 595      (set UWI rD (zext UWI (mem UHI (load-store-addr rA simm16 2))))
 596      ()
 597 )
 598
 599 (dni l-lhs "l.lhs reg/simm16(reg)"
 600      ((MACH ORBIS-MACHS))
 601      "l.lhs $rD,${simm16}($rA)"
 602      (+ OPC_LHS rD rA simm16)
 603      (set WI rD (ext WI (mem HI (load-store-addr rA simm16 2))))
 604      ()
 605 )
 606
 607 \f
 608 ; Store instructions
 609
 610 (define-pmacro (store-insn mnemonic opc-op mode size)
 611   (begin
 612      (dni (.sym l- mnemonic)
 613           (.str "l." mnemonic " simm16(reg)/reg")
 614           ((MACH ORBIS-MACHS))
 615           (.str "l." mnemonic " ${simm16-split}($rA),$rB")
 616           (+ opc-op rB rD simm16-split)
 617           (set mode (mem mode (load-store-addr rA simm16-split size)) (trunc mode rB))
 618           ()
 619      )
 620    )
 621 )
 622
 623 (store-insn sw OPC_SW USI 4)
 624 (store-insn sb OPC_SB UQI 1)
 625 (store-insn sh OPC_SH UHI 2)
 626
 627
 628 \f
 629 ; Shift and rotate instructions
 630
 631 (define-pmacro (shift-insn mnemonic)
 632   (begin
 633      (dni (.sym l- mnemonic)
 634           (.str "l." mnemonic " reg/reg/reg")
 635           ((MACH ORBIS-MACHS))
 636           (.str "l." mnemonic " $rD,$rA,$rB")
 637           (+ OPC_ALU rD rA rB (f-resv-10-3 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) (f-resv-5-2 0)
 638              OPC_ALU_REGREG_SHROT )
 639           (set UWI rD (mnemonic rA rB))
 640           ()
 641      )
 642      (dni (.sym l- mnemonic "i")
 643           (.str "l." mnemonic " reg/reg/uimm6")
 644           ((MACH ORBIS-MACHS))
 645           (.str "l." mnemonic "i $rD,$rA,${uimm6}")
 646           (+ OPC_SHROTI rD rA (f-resv-15-8 0) (.sym OPC_SHROTS_ (.upcase mnemonic)) uimm6)
 647           (set rD (mnemonic rA uimm6))
 648           ()
 649      )
 650    )
 651 )
 652
 653 (shift-insn sll)
 654 (shift-insn srl)
 655 (shift-insn sra)
 656 (shift-insn ror)
 657
 658 \f
 659 ; Arithmetic insns
 660
 661 ; ALU op macro
 662 (define-pmacro (alu-insn mnemonic)
 663   (begin
 664      (dni (.sym l- mnemonic)
 665           (.str "l." mnemonic " reg/reg/reg")
 666           ((MACH ORBIS-MACHS))
 667           (.str "l." mnemonic " $rD,$rA,$rB")
 668           (+ OPC_ALU rD rA rB (f-resv-10-7 0) (.sym OPC_ALU_REGREG_ (.upcase mnemonic)))
 669           (set rD (mnemonic rA rB))
 670           ()
 671      )
 672   )
 673 )
 674
 675 (alu-insn and)
 676 (alu-insn or)
 677 (alu-insn xor)
 678
 679 (define-pmacro (alu-carry-insn mnemonic)
 680   (begin
 681     (dni (.sym l- mnemonic)
 682          (.str "l." mnemonic " reg/reg/reg")
 683          ((MACH ORBIS-MACHS))
 684          (.str "l." mnemonic " $rD,$rA,$rB")
 685          (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) (.sym OPC_ALU_REGREG_ (.upcase mnemonic)))
 686          (sequence ()
 687                    (sequence ()
 688                              (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA rB 0))
 689                              (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA rB 0))
 690                              (set rD (mnemonic WI rA rB))
 691                              )
 692                    (if (andif sys-sr-ov sys-sr-ove)
 693                        (raise-exception EXCEPT-RANGE))
 694                    )
 695          ()
 696          )
 697     )
 698   )
 699
 700 (alu-carry-insn add)
 701 (alu-carry-insn sub)
 702
 703 (dni (l-addc) "l.addc reg/reg/reg"
 704           ((MACH ORBIS-MACHS))
 705           ("l.addc $rD,$rA,$rB")
 706           (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_ADDC)
 707           (sequence ()
 708                     (sequence ((BI tmp-sys-sr-cy))
 709                               (set BI tmp-sys-sr-cy sys-sr-cy)
 710                               (set BI sys-sr-cy (addc-cflag WI rA rB tmp-sys-sr-cy))
 711                               (set BI sys-sr-ov (addc-oflag WI rA rB tmp-sys-sr-cy))
 712                               (set rD (addc WI rA rB tmp-sys-sr-cy))
 713                               )
 714                    (if (andif sys-sr-ov sys-sr-ove)
 715                        (raise-exception EXCEPT-RANGE))
 716                    )
 717           ()
 718 )
 719
 720 (dni (l-mul) "l.mul reg/reg/reg"
 721           ((MACH ORBIS-MACHS))
 722           ("l.mul $rD,$rA,$rB")
 723           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MUL)
 724           (sequence ()
 725                     (sequence ()
 726                               ; 2's complement overflow
 727                               (set BI sys-sr-ov (mul-o2flag WI rA rB))
 728                               ; 1's complement overflow
 729                               (set BI sys-sr-cy (mul-o1flag WI rA rB))
 730                               (set rD (mul WI rA rB))
 731                               )
 732                     (if (andif sys-sr-ov sys-sr-ove)
 733                         (raise-exception EXCEPT-RANGE))
 734                     )
 735           ()
 736 )
 737
 738 (dni (l-mulu) "l.mulu reg/reg/reg"
 739           ((MACH ORBIS-MACHS))
 740           ("l.mulu $rD,$rA,$rB")
 741           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_MULU)
 742           (sequence ()
 743                     (sequence ()
 744                               ; 2's complement overflow
 745                               (set BI sys-sr-ov 0)
 746                               ; 1's complement overflow
 747                               (set BI sys-sr-cy (mul-o1flag UWI rA rB))
 748                               (set rD (mul UWI rA rB))
 749                               )
 750                     (if (andif sys-sr-ov sys-sr-ove)
 751                         (raise-exception EXCEPT-RANGE))
 752                     )
 753           ()
 754 )
 755
 756 (dni l-div "divide (signed)"
 757           ((MACH ORBIS-MACHS))
 758           "l.div $rD,$rA,$rB"
 759           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIV)
 760           (sequence ()
 761                     (if (ne rB 0)
 762                         (sequence ()
 763                                   (set BI sys-sr-cy 0)
 764                                   (set WI rD (div WI rA rB))
 765                                   )
 766                         (set BI sys-sr-cy 1)
 767                         )
 768                     (set BI sys-sr-ov 0)
 769                     (if (andif sys-sr-cy sys-sr-ove)
 770                         (raise-exception EXCEPT-RANGE))
 771                     )
 772           ()
 773 )
 774
 775 (dni l-divu "divide (unsigned)"
 776           ((MACH ORBIS-MACHS))
 777           "l.divu $rD,$rA,$rB"
 778           (+ OPC_ALU rD rA rB (f-resv-10-7 #x30) OPC_ALU_REGREG_DIVU)
 779           (sequence ()
 780                     (if (ne rB 0)
 781                         (sequence ()
 782                                   (set BI sys-sr-cy 0)
 783                                   (set rD (udiv UWI rA rB))
 784                                   )
 785                         (set BI sys-sr-cy 1)
 786                         )
 787                     (set BI sys-sr-ov 0)
 788                     (if (andif sys-sr-cy sys-sr-ove)
 789                         (raise-exception EXCEPT-RANGE))
 790                     )
 791           ()
 792 )
 793
 794 (dni l-ff1 "find first '1'"
 795           ((MACH ORBIS-MACHS))
 796           "l.ff1 $rD,$rA"
 797           (+ OPC_ALU rD rA rB (f-resv-10-7 #x00) OPC_ALU_REGREG_FFL1)
 798           (set rD (c-call UWI "@cpu@_ff1" rA))
 799           ()
 800 )
 801
 802 (dni l-fl1 "find last '1'"
 803           ((MACH ORBIS-MACHS))
 804           "l.fl1 $rD,$rA"
 805           (+ OPC_ALU rD rA rB (f-resv-10-7 #x10) OPC_ALU_REGREG_FFL1)
 806           (set rD (c-call UWI "@cpu@_fl1" rA))
 807           ()
 808 )
 809
 810
 811 (define-pmacro (alu-insn-simm  mnemonic)
 812   (begin
 813       (dni (.sym l- mnemonic "i")
 814           (.str "l." mnemonic " reg/reg/simm16")
 815           ((MACH ORBIS-MACHS))
 816           (.str "l." mnemonic "i $rD,$rA,$simm16")
 817           (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16)
 818           (set rD (mnemonic rA (ext WI simm16)))
 819           ()
 820      )
 821    )
 822 )
 823
 824 (define-pmacro (alu-insn-uimm  mnemonic)
 825   (begin
 826       (dni (.sym l- mnemonic "i")
 827           (.str "l." mnemonic " reg/reg/uimm16")
 828           ((MACH ORBIS-MACHS))
 829           (.str "l." mnemonic "i $rD,$rA,$uimm16")
 830           (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA uimm16)
 831           (set rD (mnemonic rA (zext UWI uimm16)))
 832           ()
 833      )
 834    )
 835 )
 836
 837 (alu-insn-uimm and)
 838 (alu-insn-uimm or)
 839 (alu-insn-simm xor)
 840
 841 (define-pmacro (alu-carry-insn-simm mnemonic)
 842   (begin
 843     (dni (.sym l- mnemonic "i")
 844          (.str "l." mnemonic "i reg/reg/simm16")
 845          ((MACH ORBIS-MACHS))
 846          (.str "l." mnemonic "i $rD,$rA,$simm16")
 847          (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16)
 848          (sequence ()
 849                    (sequence ()
 850                              (set BI sys-sr-cy ((.sym mnemonic "c-cflag") WI rA (ext WI simm16) 0))
 851                              (set BI sys-sr-ov ((.sym mnemonic "c-oflag") WI rA (ext WI simm16) 0))
 852                              (set rD (mnemonic WI rA (ext WI simm16)))
 853                              )
 854                    (if (andif sys-sr-ov sys-sr-ove)
 855                        (raise-exception EXCEPT-RANGE))
 856                    )
 857          ()
 858          )
 859     )
 860   )
 861
 862 (alu-carry-insn-simm add)
 863
 864 (dni (l-addic)
 865      ("l.addic reg/reg/simm16")
 866      ((MACH ORBIS-MACHS))
 867      ("l.addic $rD,$rA,$simm16")
 868      (+ OPC_ADDIC rD rA simm16)
 869      (sequence ()
 870                (sequence ((BI tmp-sys-sr-cy))
 871                          (set BI tmp-sys-sr-cy sys-sr-cy)
 872                          (set BI sys-sr-cy (addc-cflag WI rA (ext WI simm16) tmp-sys-sr-cy))
 873                          (set BI sys-sr-ov (addc-oflag WI rA (ext WI simm16) tmp-sys-sr-cy))
 874                          (set WI rD (addc WI rA (ext WI simm16) tmp-sys-sr-cy))
 875                          )
 876                (if (andif sys-sr-ov sys-sr-ove)
 877                    (raise-exception EXCEPT-RANGE))
 878                )
 879      ()
 880 )
 881
 882 (dni (l-muli)
 883      "l.muli reg/reg/simm16"
 884      ((MACH ORBIS-MACHS))
 885      ("l.muli $rD,$rA,$simm16")
 886      (+ OPC_MULI rD rA simm16)
 887      (sequence ()
 888                (sequence ()
 889                          ; 2's complement overflow
 890                          (set sys-sr-ov (mul-o2flag WI rA (ext WI simm16)))
 891                          ; 1's complement overflow
 892                          (set sys-sr-cy (mul-o1flag UWI rA (ext UWI simm16)))
 893                          (set rD (mul WI rA (ext WI simm16)))
 894                          )
 895                (if (andif sys-sr-ov sys-sr-ove)
 896                    (raise-exception EXCEPT-RANGE))
 897                )
 898      ()
 899      )
 900
 901 (define-pmacro (extbh-insn mnemonic extop extmode truncmode)
 902   (begin
 903     (dni (.sym l- mnemonic)
 904          (.str "l." mnemonic " reg/reg")
 905          ((MACH ORBIS-MACHS))
 906          (.str "l." mnemonic " $rD,$rA")
 907          (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTBHS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTBH)
 908          (set rD (extop extmode (trunc truncmode rA)))
 909          ()
 910          )
 911     )
 912   )
 913
 914 (extbh-insn exths ext  WI  HI)
 915 (extbh-insn extbs ext  WI  QI)
 916 (extbh-insn exthz zext UWI UHI)
 917 (extbh-insn extbz zext UWI UQI)
 918
 919 (define-pmacro (extw-insn mnemonic extop extmode truncmode)
 920   (begin
 921     (dni (.sym l- mnemonic)
 922          (.str "l." mnemonic " reg/reg")
 923          ((MACH ORBIS-MACHS))
 924          (.str "l." mnemonic " $rD,$rA")
 925          (+ OPC_ALU rD rA (f-resv-15-6 0) (.sym OPC_EXTWS_ (.upcase mnemonic)) (f-resv-5-2 0) OPC_ALU_REGREG_EXTW)
 926          (set rD (extop extmode (trunc truncmode rA)))
 927          ()
 928          )
 929     )
 930   )
 931
 932 (extw-insn extws ext  WI  SI)
 933 (extw-insn extwz zext USI USI)
 934
 935 (dni l-cmov
 936      "l.cmov reg/reg/reg"
 937      ((MACH ORBIS-MACHS))
 938      "l.cmov $rD,$rA,$rB"
 939      (+ OPC_ALU rD rA rB (f-resv-10-1 0) (f-op-9-2 0) (f-resv-7-4 0) OPC_ALU_REGREG_CMOV)
 940      (if sys-sr-f
 941          (set UWI rD rA)
 942          (set UWI rD rB)
 943          )
 944      ()
 945      )
 946
 947 ; Compare instructions
 948
 949 ; Ordering compare
 950 (define-pmacro (sf-insn op)
 951   (begin
 952      (dni (.sym l- "sf" op "s")                                               ; l-sfgts
 953           (.str "l.sf" op "s reg/reg")                                        ; "l.sfgts reg/reg"
 954           ((MACH ORBIS-MACHS))
 955           (.str "l.sf" op "s $rA,$rB")                                        ; "l.sfgts $rA,$rB"
 956           (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "S") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTS rA rB (f-resv-10-11 0))
 957           (set sys-sr-f (op WI rA rB))                                        ; (set sys-sr-f (gt WI rA rB))
 958           ()
 959           )
 960      (dni (.sym l- "sf" op "si")                                              ; l-sfgtsi
 961           (.str "l.sf" op "si reg/simm16")                                    ; "l.sfgtsi reg/simm16"
 962           ((MACH ORBIS-MACHS))
 963           (.str "l.sf" op "si $rA,$simm16")                                   ; "l.sfgtsi $rA,$simm16"
 964           (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "S") rA simm16)             ; (+ OPC_SFI OPC_SF_GTS rA simm16)
 965           (set sys-sr-f (op WI rA (ext WI simm16)))                           ; (set sys-sr-f (gt WI rA (ext WI simm16)))
 966           ()
 967           )
 968      (dni (.sym l- "sf" op "u")                                               ; l-sfgtu
 969           (.str "l.sf" op "u reg/reg")                                        ; "l.sfgtu reg/reg"
 970           ((MACH ORBIS-MACHS))
 971           (.str "l.sf" op "u $rA,$rB")                                        ; "l.sfgtu $rA,$rB"
 972           (+ OPC_SF (.sym "OPC_SF_" (.upcase op) "U") rA rB (f-resv-10-11 0)) ; (+ OPC_SF OPC_SF_GTU rA rB (f-resv-10-11 0))
 973           (set sys-sr-f ((.sym op "u") WI rA rB))                             ; (set sys-sr-f (gtu WI rA rB))
 974           ()
 975           )
 976      ; immediate is sign extended even for unsigned compare
 977      (dni (.sym l- "sf" op "ui")                                              ; l-sfgtui
 978           (.str "l.sf" op "ui reg/simm16")                                    ; "l.sfgtui reg/uimm16"
 979           ((MACH ORBIS-MACHS))
 980           (.str "l.sf" op "ui $rA,$simm16")                                   ; "l.sfgtui $rA,$simm16"
 981           (+ OPC_SFI (.sym "OPC_SF_" (.upcase op) "U") rA simm16)             ; (+ OPC_SFI OPC_SF_GTU rA simm16)
 982           (set sys-sr-f ((.sym op "u") WI rA (ext WI simm16)))                ; (set sys-sr-f (gtu WI rA (ext WI simm16)))
 983           ()
 984           )
 985      )
 986   )
 987
 988 (sf-insn gt)
 989 (sf-insn ge)
 990 (sf-insn lt)
 991 (sf-insn le)
 992
 993 ; Equality compare
 994 (define-pmacro (sf-insn-eq op)
 995   (begin
 996      (dni (.sym l- "sf" op)
 997           (.str "l." op " reg/reg")
 998           ((MACH ORBIS-MACHS))
 999           (.str "l.sf" op " $rA,$rB")
1000           (+ OPC_SF (.sym "OPC_SF_" (.upcase op)) rA rB (f-resv-10-11 0))
1001           (set sys-sr-f (op WI rA rB))
1002           ()
1003      )
1004      (dni (.sym l- "sf" op "i")
1005           (.str "l.sf" op "i reg/simm16")
1006           ((MACH ORBIS-MACHS))
1007           (.str "l.sf" op "i $rA,$simm16")
1008           (+ OPC_SFI (.sym "OPC_SF_" (.upcase op)) rA simm16)
1009           (set sys-sr-f (op WI rA (ext WI simm16)))
1010           ()
1011      )
1012    )
1013 )
1014
1015 (sf-insn-eq eq)
1016 (sf-insn-eq ne)
1017
1018 (dni l-mac
1019      "l.mac reg/reg"
1020      ((MACH ORBIS-MACHS))
1021      "l.mac $rA,$rB"
1022      (+  OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MAC)
1023      (sequence ((WI prod) (DI result))
1024                (set WI prod (mul WI rA rB))
1025                (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
1026                (set SI mac-machi (subword SI result 0))
1027                (set SI mac-maclo (subword SI result 1))
1028                )
1029      ()
1030      )
1031
1032 (dni l-msb
1033      "l.msb reg/reg"
1034      ((MACH ORBIS-MACHS))
1035      "l.msb $rA,$rB"
1036      (+  OPC_MAC (f-op-25-5 0) rA rB (f-resv-10-7 0) OPC_MAC_MSB)
1037      (sequence ((WI prod) (DI result))
1038                (set WI prod (mul WI rA rB))
1039                (set DI result (sub (join DI SI mac-machi mac-maclo) (ext DI prod)))
1040                (set SI mac-machi (subword SI result 0))
1041                (set SI mac-maclo (subword SI result 1))
1042                )
1043      ()
1044      )
1045
1046 (dni l-maci
1047      "l.maci reg/simm16"
1048      ((MACH ORBIS-MACHS))
1049      "l.maci $rA,${simm16}"
1050      (+ OPC_MACI (f-resv-25-5 0) rA simm16)
1051      (sequence ((WI prod) (DI result))
1052                (set WI prod (mul WI (ext WI simm16) rA))
1053                (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
1054                (set SI mac-machi (subword SI result 0))
1055                (set SI mac-maclo (subword SI result 1))
1056                )
1057      ()
1058      )
1059
1060 (define-pmacro (cust-insn cust-num)
1061   (begin
1062     (dni (.sym l- "cust" cust-num)
1063          (.str "l.cust" cust-num)
1064          ((MACH ORBIS-MACHS))
1065          (.str "l.cust" cust-num)
1066          (+ (.sym OPC_CUST cust-num) (f-resv-25-26 0))
1067          (nop)
1068          ()
1069          )
1070     )
1071   )
1072
1073 (cust-insn "1")
1074 (cust-insn "2")
1075 (cust-insn "3")
1076 (cust-insn "4")
1077 (cust-insn "5")
1078 (cust-insn "6")
1079 (cust-insn "7")
1080 (cust-insn "8")