cpu/or1korfpx.cpu

   1 ; OpenRISC 1000 architecture.  -*- Scheme -*-
   2 ; Copyright 2000-2019 Free Software Foundation, Inc.
   3 ; Contributed by Peter Gavin, pgavin@gmail.com
   4 ; Modified by Andrey Bacherov, avbacherov@opencores.org
   5 ;
   6 ; This program is free software; you can redistribute it and/or modify
   7 ; it under the terms of the GNU General Public License as published by
   8 ; the Free Software Foundation; either version 3 of the License, or
   9 ; (at your option) any later version.
  10 ;
  11 ; This program is distributed in the hope that it will be useful,
  12 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ; GNU General Public License for more details.
  15 ;
  16 ; You should have received a copy of the GNU General Public License
  17 ; along with this program; if not, see <http://www.gnu.org/licenses/>
  18
  19 ; Initial ORFPX32 instruction set
  20
  21 ; I'm not sure how CGEN handles rounding in FP operations, except for
  22 ; in conversions to/from integers.  So lf.add, lf.sub, lf.mul, and
  23 ; lf.div do not round according to the FPCSR RM field.
  24 ; NaN, overflow, and underflow are not yet handled either.
  25
  26 (define-normal-insn-enum insn-opcode-float-regreg
  27   "floating point reg/reg insn opcode enums" ()
  28   OPC_FLOAT_REGREG_ f-op-7-8
  29   (("ADD_S"  #x00)
  30    ("SUB_S"  #x01)
  31    ("MUL_S"  #x02)
  32    ("DIV_S"  #x03)
  33    ("ITOF_S" #x04)
  34    ("FTOI_S" #x05)
  35    ("REM_S"  #x06)
  36    ("MADD_S" #x07)
  37    ("SFEQ_S" #x08)
  38    ("SFNE_S" #x09)
  39    ("SFGT_S" #x0a)
  40    ("SFGE_S" #x0b)
  41    ("SFLT_S" #x0c)
  42    ("SFLE_S" #x0d)
  43    ("ADD_D"  #x10)
  44    ("SUB_D"  #x11)
  45    ("MUL_D"  #x12)
  46    ("DIV_D"  #x13)
  47    ("ITOF_D" #x14)
  48    ("FTOI_D" #x15)
  49    ("REM_D"  #x16)
  50    ("MADD_D" #x17)
  51    ("SFEQ_D" #x18)
  52    ("SFNE_D" #x19)
  53    ("SFGT_D" #x1a)
  54    ("SFGE_D" #x1b)
  55    ("SFLT_D" #x1c)
  56    ("SFLE_D" #x1d)
  57    ("CUST1_S" #xd0)
  58    ("CUST1_D" #xe0)
  59    )
  60   )
  61
  62 ; Register offset flags, if set offset is 2 otherwise offset is 1
  63 (dnf f-rdoff-10-1   "destination register pair offset flag" ((MACH ORFPX64A32-MACHS)) 10 1)
  64 (dnf f-raoff-9-1    "source register A pair offset flag"    ((MACH ORFPX64A32-MACHS)) 9 1)
  65 (dnf f-rboff-8-1    "source register B pair offset flag"    ((MACH ORFPX64A32-MACHS)) 8 1)
  66
  67 (dsh h-roff1        "1-bit offset flag"                     () (register BI))
  68
  69 (dnop rDSF "destination register (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r1)
  70 (dnop rASF "source register A (single floating point mode)"    ((MACH ORFPX32-MACHS)) h-fsr f-r2)
  71 (dnop rBSF "source register B (single floating point mode)"    ((MACH ORFPX32-MACHS)) h-fsr f-r3)
  72
  73 (dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
  74 (dnop rADF "or64 source register A (double floating point mode)"    ((MACH ORFPX64-MACHS)) h-fdr f-r2)
  75 (dnop rBDF "or64 source register B (double floating point mode)"    ((MACH ORFPX64-MACHS)) h-fdr f-r3)
  76
  77 (define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
  78   (begin
  79     (define-multi-ifield
  80       (name (.sym "f-r" (.downcase mnemonic) "d32"))
  81       (comment op-comment)
  82       (attrs (MACH ORFPX64A32-MACHS))
  83       (mode SI)
  84       (subfields reg offbit)
  85       ; From the multi-ifield insert the bits into subfields
  86       (insert (sequence
  87                 ()
  88                 (set (ifield reg)
  89                   (and (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
  90                        (const #x1f))
  91                   )
  92                 (set (ifield offbit)
  93                   (and (sra (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
  94                             (const 5))
  95                        (const 1))
  96                   )
  97                 )
  98         )
  99       ; Extract the multi-ifield from the subfield bits
 100       (extract
 101                (set (ifield (.sym "f-r" (.downcase mnemonic) "d32"))
 102                     (or (ifield reg)
 103                         (sll (ifield offbit)
 104                              (const 5)))
 105                  )
 106         )
 107       )
 108     (define-operand
 109       (name (.sym "r" (.upcase mnemonic) "D32F"))
 110       (comment (.str op-comment " (double floating point pair)"))
 111       (attrs (MACH ORFPX64A32-MACHS))
 112       (type h-fd32r)
 113       (index (.sym "f-r" (.downcase mnemonic) "d32"))
 114       (handlers (parse "regpair") (print "regpair"))
 115       )
 116     (define-operand
 117       (name (.sym "r" (.upcase mnemonic) "DI"))
 118       (comment (.str op-comment " (double integer pair)"))
 119       (attrs (MACH ORFPX64A32-MACHS))
 120       (type h-i64r)
 121       (index (.sym "f-r" (.downcase mnemonic) "d32"))
 122       (handlers (parse "regpair") (print "regpair"))
 123       )
 124     )
 125   )
 126
 127 (double-field-and-ops D f-r1 f-rdoff-10-1 "destination register")
 128 (double-field-and-ops A f-r2 f-raoff-9-1  "source register A")
 129 (double-field-and-ops B f-r3 f-rboff-8-1  "source register B")
 130
 131 (define-pmacro (float-regreg-insn mnemonic)
 132   (begin
 133     (dni (.sym lf- mnemonic -s)
 134          (.str "lf." mnemonic ".s reg/reg/reg")
 135          ((MACH ORFPX32-MACHS))
 136          (.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
 137          (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
 138          (set SF rDSF (mnemonic SF rASF rBSF))
 139          ()
 140          )
 141     (dni (.sym lf- mnemonic -d)
 142          (.str "lf." mnemonic ".d reg/reg/reg")
 143          ((MACH ORFPX64-MACHS))
 144          (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
 145          (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
 146          (set DF rDDF (mnemonic DF rADF rBDF))
 147          ()
 148          )
 149     (dni (.sym lf- mnemonic -d32)
 150          (.str "lf." mnemonic ".d regpair/regpair/regpair")
 151          ((MACH ORFPX64A32-MACHS))
 152          (.str "lf." mnemonic ".d $rDD32F,$rAD32F,$rBD32F")
 153          (+ OPC_FLOAT rDD32F rAD32F rBD32F (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
 154          (set DF rDD32F (mnemonic DF rAD32F rBD32F))
 155          ()
 156          )
 157     )
 158   )
 159
 160 (float-regreg-insn add)
 161 (float-regreg-insn sub)
 162 (float-regreg-insn mul)
 163 (float-regreg-insn div)
 164
 165 (dni lf-rem-s
 166      "lf.rem.s reg/reg/reg"
 167      ((MACH ORFPX32-MACHS))
 168      "lf.rem.s $rDSF,$rASF,$rBSF"
 169      (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
 170      (set SF rDSF (rem SF rASF rBSF))
 171      ()
 172      )
 173
 174 (dni lf-rem-d
 175      "lf.rem.d reg/reg/reg"
 176      ((MACH ORFPX64-MACHS))
 177      "lf.rem.d $rDDF,$rADF,$rBDF"
 178      (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
 179      (set DF rDDF (rem DF rADF rBDF))
 180      ()
 181      )
 182
 183 (dni lf-rem-d32
 184      "lf.rem.d regpair/regpair/regpair"
 185      ((MACH ORFPX64A32-MACHS))
 186      "lf.rem.d $rDD32F,$rAD32F,$rBD32F"
 187      (+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_REM_D)
 188      (set DF rDD32F (rem DF rAD32F rBD32F))
 189      ()
 190      )
 191
 192 (define-pmacro (get-rounding-mode)
 193   (case INT sys-fpcsr-rm
 194         ((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
 195         ((1) 3) ; TOWARD-ZERO
 196         ((2) 4) ; TOWARD-POSITIVE
 197         (else 5) ; TOWARD-NEGATIVE
 198         )
 199   )
 200
 201 (dni lf-itof-s
 202      "lf.itof.s reg/reg"
 203      ((MACH ORFPX32-MACHS))
 204      "lf.itof.s $rDSF,$rA"
 205      (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
 206      (set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
 207      ()
 208      )
 209
 210 (dni lf-itof-d
 211      "lf.itof.d reg/reg"
 212      ((MACH ORFPX64-MACHS))
 213      "lf.itof.d $rDDF,$rA"
 214      (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
 215      (set DF rDDF (float DF (get-rounding-mode) rA))
 216      ()
 217      )
 218
 219 (dni lf-itof-d32
 220      "lf.itof.d regpair/regpair"
 221      ((MACH ORFPX64A32-MACHS))
 222      "lf.itof.d $rDD32F,$rADI"
 223      (+ OPC_FLOAT rDD32F rADI (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_ITOF_D)
 224      (set DF rDD32F (float DF (get-rounding-mode) rADI))
 225      ()
 226      )
 227
 228 (dni lf-ftoi-s
 229      "lf.ftoi.s reg/reg"
 230      ((MACH ORFPX32-MACHS))
 231      "lf.ftoi.s $rD,$rASF"
 232      (+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
 233      (set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
 234      ()
 235      )
 236
 237 (dni lf-ftoi-d
 238      "lf.ftoi.d reg/reg"
 239      ((MACH ORFPX64-MACHS))
 240      "lf.ftoi.d $rD,$rADF"
 241      (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
 242      (set WI rD (fix WI (get-rounding-mode) rADF))
 243      ()
 244      )
 245
 246 (dni lf-ftoi-d32
 247      "lf.ftoi.d regpair/regpair"
 248      ((MACH ORFPX64A32-MACHS))
 249      "lf.ftoi.d $rDDI,$rAD32F"
 250      (+ OPC_FLOAT rDDI rAD32F (f-r3 0) (f-resv-8-1 0) OPC_FLOAT_REGREG_FTOI_D)
 251      (set DI rDDI (fix DI (get-rounding-mode) rAD32F))
 252      ()
 253      )
 254
 255 (define-pmacro (float-setflag-insn mnemonic)
 256   (begin
 257     (dni (.sym lf- mnemonic -s)
 258          (.str "lf.sf" mnemonic ".s reg/reg")
 259          ((MACH ORFPX32-MACHS))
 260          (.str "lf.sf" mnemonic ".s $rASF,$rBSF")
 261          (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
 262          (set BI sys-sr-f (mnemonic SF rASF rBSF))
 263          ()
 264          )
 265     (dni (.sym lf- mnemonic -d)
 266          (.str "lf.sf" mnemonic ".d reg/reg")
 267          ((MACH ORFPX64-MACHS))
 268          (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
 269          (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
 270          (set BI sys-sr-f (mnemonic DF rADF rBDF))
 271          ()
 272          )
 273     (dni (.sym lf- mnemonic -d32)
 274          (.str "lf.sf" mnemonic ".d regpair/regpair")
 275          ((MACH ORFPX64A32-MACHS))
 276          (.str "lf.sf" mnemonic ".d $rAD32F,$rBD32F")
 277          (+ OPC_FLOAT (f-r1 0) rAD32F rBD32F (f-resv-10-1 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
 278          (set BI sys-sr-f (mnemonic DF rAD32F rBD32F))
 279          ()
 280          )
 281     )
 282   )
 283
 284 (float-setflag-insn eq)
 285 (float-setflag-insn ne)
 286 (float-setflag-insn ge)
 287 (float-setflag-insn gt)
 288 (float-setflag-insn lt)
 289 (float-setflag-insn le)
 290
 291 (dni lf-madd-s
 292      "lf.madd.s reg/reg/reg"
 293      ((MACH ORFPX32-MACHS))
 294      "lf.madd.s $rDSF,$rASF,$rBSF"
 295      (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
 296      (set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
 297      ()
 298      )
 299
 300 (dni lf-madd-d
 301      "lf.madd.d reg/reg/reg"
 302      ((MACH ORFPX64-MACHS))
 303      "lf.madd.d $rDDF,$rADF,$rBDF"
 304      (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
 305      (set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
 306      ()
 307      )
 308
 309 (dni lf-madd-d32
 310      "lf.madd.d regpair/regpair/regpair"
 311      ((MACH ORFPX64A32-MACHS))
 312      "lf.madd.d $rDD32F,$rAD32F,$rBD32F"
 313      (+ OPC_FLOAT rDD32F rAD32F rBD32F OPC_FLOAT_REGREG_MADD_D)
 314      (set DF rDD32F (add DF (mul DF rAD32F rBD32F) rDD32F))
 315      ()
 316      )
 317
 318 (define-pmacro (float-cust-insn cust-num)
 319   (begin
 320     (dni (.sym "lf-cust" cust-num "-s")
 321          (.str "lf.cust" cust-num ".s")
 322          ((MACH ORFPX32-MACHS))
 323          (.str "lf.cust" cust-num ".s $rASF,$rBSF")
 324          (+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
 325          (nop)
 326          ()
 327          )
 328     (dni (.sym "lf-cust" cust-num "-d")
 329          (.str "lf.cust" cust-num ".d")
 330          ((MACH ORFPX64-MACHS))
 331          (.str "lf.cust" cust-num ".d")
 332          (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
 333          (nop)
 334          ()
 335          )
 336     (dni (.sym "lf-cust" cust-num "-d32")
 337          (.str "lf.cust" cust-num ".d")
 338          ((MACH ORFPX64A32-MACHS))
 339          (.str "lf.cust" cust-num ".d")
 340          (+ OPC_FLOAT (f-resv-25-5 0) rAD32F rBD32F (f-resv-10-1 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
 341          (nop)
 342          ()
 343          )
 344     )
 345   )
 346
 347 (float-cust-insn "1")