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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / drivers / acpi / acpi_lpss.c
1 /*
2 * ACPI support for Intel Lynxpoint LPSS.
3 *
4 * Copyright (C) 2013, Intel Corporation
5 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/acpi.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/mutex.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/clk-lpss.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/delay.h>
24
25 #include "internal.h"
26
27 ACPI_MODULE_NAME("acpi_lpss");
28
29 #ifdef CONFIG_X86_INTEL_LPSS
30
31 #include <asm/cpu_device_id.h>
32 #include <asm/intel-family.h>
33 #include <asm/iosf_mbi.h>
34 #include <asm/pmc_atom.h>
35
36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
37
38 #define LPSS_CLK_SIZE 0x04
39 #define LPSS_LTR_SIZE 0x18
40
41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
42 #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16))
43 #define LPSS_RESETS 0x04
44 #define LPSS_RESETS_RESET_FUNC BIT(0)
45 #define LPSS_RESETS_RESET_APB BIT(1)
46 #define LPSS_GENERAL 0x08
47 #define LPSS_GENERAL_LTR_MODE_SW BIT(2)
48 #define LPSS_GENERAL_UART_RTS_OVRD BIT(3)
49 #define LPSS_SW_LTR 0x10
50 #define LPSS_AUTO_LTR 0x14
51 #define LPSS_LTR_SNOOP_REQ BIT(15)
52 #define LPSS_LTR_SNOOP_MASK 0x0000FFFF
53 #define LPSS_LTR_SNOOP_LAT_1US 0x800
54 #define LPSS_LTR_SNOOP_LAT_32US 0xC00
55 #define LPSS_LTR_SNOOP_LAT_SHIFT 5
56 #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000
57 #define LPSS_LTR_MAX_VAL 0x3FF
58 #define LPSS_TX_INT 0x20
59 #define LPSS_TX_INT_MASK BIT(1)
60
61 #define LPSS_PRV_REG_COUNT 9
62
63 /* LPSS Flags */
64 #define LPSS_CLK BIT(0)
65 #define LPSS_CLK_GATE BIT(1)
66 #define LPSS_CLK_DIVIDER BIT(2)
67 #define LPSS_LTR BIT(3)
68 #define LPSS_SAVE_CTX BIT(4)
69 #define LPSS_NO_D3_DELAY BIT(5)
70
71 struct lpss_private_data;
72
73 struct lpss_device_desc {
74 unsigned int flags;
75 const char *clk_con_id;
76 unsigned int prv_offset;
77 size_t prv_size_override;
78 struct property_entry *properties;
79 void (*setup)(struct lpss_private_data *pdata);
80 };
81
82 static const struct lpss_device_desc lpss_dma_desc = {
83 .flags = LPSS_CLK,
84 };
85
86 struct lpss_private_data {
87 void __iomem *mmio_base;
88 resource_size_t mmio_size;
89 unsigned int fixed_clk_rate;
90 struct clk *clk;
91 const struct lpss_device_desc *dev_desc;
92 u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
93 };
94
95 /* LPSS run time quirks */
96 static unsigned int lpss_quirks;
97
98 /*
99 * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
100 *
101 * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
102 * it can be powered off automatically whenever the last LPSS device goes down.
103 * In case of no power any access to the DMA controller will hang the system.
104 * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
105 * well as on ASuS T100TA transformer.
106 *
107 * This quirk overrides power state of entire LPSS island to keep DMA powered
108 * on whenever we have at least one other device in use.
109 */
110 #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0)
111
112 /* UART Component Parameter Register */
113 #define LPSS_UART_CPR 0xF4
114 #define LPSS_UART_CPR_AFCE BIT(4)
115
116 static void lpss_uart_setup(struct lpss_private_data *pdata)
117 {
118 unsigned int offset;
119 u32 val;
120
121 offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
122 val = readl(pdata->mmio_base + offset);
123 writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
124
125 val = readl(pdata->mmio_base + LPSS_UART_CPR);
126 if (!(val & LPSS_UART_CPR_AFCE)) {
127 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
128 val = readl(pdata->mmio_base + offset);
129 val |= LPSS_GENERAL_UART_RTS_OVRD;
130 writel(val, pdata->mmio_base + offset);
131 }
132 }
133
134 static void lpss_deassert_reset(struct lpss_private_data *pdata)
135 {
136 unsigned int offset;
137 u32 val;
138
139 offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
140 val = readl(pdata->mmio_base + offset);
141 val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
142 writel(val, pdata->mmio_base + offset);
143 }
144
145 #define LPSS_I2C_ENABLE 0x6c
146
147 static void byt_i2c_setup(struct lpss_private_data *pdata)
148 {
149 lpss_deassert_reset(pdata);
150
151 if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
152 pdata->fixed_clk_rate = 133000000;
153
154 writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
155 }
156
157 static const struct lpss_device_desc lpt_dev_desc = {
158 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
159 .prv_offset = 0x800,
160 };
161
162 static const struct lpss_device_desc lpt_i2c_dev_desc = {
163 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
164 .prv_offset = 0x800,
165 };
166
167 static struct property_entry uart_properties[] = {
168 PROPERTY_ENTRY_U32("reg-io-width", 4),
169 PROPERTY_ENTRY_U32("reg-shift", 2),
170 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
171 { },
172 };
173
174 static const struct lpss_device_desc lpt_uart_dev_desc = {
175 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
176 .clk_con_id = "baudclk",
177 .prv_offset = 0x800,
178 .setup = lpss_uart_setup,
179 .properties = uart_properties,
180 };
181
182 static const struct lpss_device_desc lpt_sdio_dev_desc = {
183 .flags = LPSS_LTR,
184 .prv_offset = 0x1000,
185 .prv_size_override = 0x1018,
186 };
187
188 static const struct lpss_device_desc byt_pwm_dev_desc = {
189 .flags = LPSS_SAVE_CTX,
190 };
191
192 static const struct lpss_device_desc bsw_pwm_dev_desc = {
193 .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
194 };
195
196 static const struct lpss_device_desc byt_uart_dev_desc = {
197 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
198 .clk_con_id = "baudclk",
199 .prv_offset = 0x800,
200 .setup = lpss_uart_setup,
201 .properties = uart_properties,
202 };
203
204 static const struct lpss_device_desc bsw_uart_dev_desc = {
205 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
206 | LPSS_NO_D3_DELAY,
207 .clk_con_id = "baudclk",
208 .prv_offset = 0x800,
209 .setup = lpss_uart_setup,
210 .properties = uart_properties,
211 };
212
213 static const struct lpss_device_desc byt_spi_dev_desc = {
214 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
215 .prv_offset = 0x400,
216 };
217
218 static const struct lpss_device_desc byt_sdio_dev_desc = {
219 .flags = LPSS_CLK,
220 };
221
222 static const struct lpss_device_desc byt_i2c_dev_desc = {
223 .flags = LPSS_CLK | LPSS_SAVE_CTX,
224 .prv_offset = 0x800,
225 .setup = byt_i2c_setup,
226 };
227
228 static const struct lpss_device_desc bsw_i2c_dev_desc = {
229 .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
230 .prv_offset = 0x800,
231 .setup = byt_i2c_setup,
232 };
233
234 static const struct lpss_device_desc bsw_spi_dev_desc = {
235 .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
236 | LPSS_NO_D3_DELAY,
237 .prv_offset = 0x400,
238 .setup = lpss_deassert_reset,
239 };
240
241 #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
242
243 static const struct x86_cpu_id lpss_cpu_ids[] = {
244 ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */
245 ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */
246 {}
247 };
248
249 #else
250
251 #define LPSS_ADDR(desc) (0UL)
252
253 #endif /* CONFIG_X86_INTEL_LPSS */
254
255 static const struct acpi_device_id acpi_lpss_device_ids[] = {
256 /* Generic LPSS devices */
257 { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
258
259 /* Lynxpoint LPSS devices */
260 { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
261 { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
262 { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
263 { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
264 { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
265 { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
266 { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
267 { "INT33C7", },
268
269 /* BayTrail LPSS devices */
270 { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
271 { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
272 { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
273 { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
274 { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
275 { "INT33B2", },
276 { "INT33FC", },
277
278 /* Braswell LPSS devices */
279 { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
280 { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
281 { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
282 { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
283
284 /* Broadwell LPSS devices */
285 { "INT3430", LPSS_ADDR(lpt_dev_desc) },
286 { "INT3431", LPSS_ADDR(lpt_dev_desc) },
287 { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
288 { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
289 { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
290 { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
291 { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
292 { "INT3437", },
293
294 /* Wildcat Point LPSS devices */
295 { "INT3438", LPSS_ADDR(lpt_dev_desc) },
296
297 { }
298 };
299
300 #ifdef CONFIG_X86_INTEL_LPSS
301
302 static int is_memory(struct acpi_resource *res, void *not_used)
303 {
304 struct resource r;
305 return !acpi_dev_resource_memory(res, &r);
306 }
307
308 /* LPSS main clock device. */
309 static struct platform_device *lpss_clk_dev;
310
311 static inline void lpt_register_clock_device(void)
312 {
313 lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
314 }
315
316 static int register_device_clock(struct acpi_device *adev,
317 struct lpss_private_data *pdata)
318 {
319 const struct lpss_device_desc *dev_desc = pdata->dev_desc;
320 const char *devname = dev_name(&adev->dev);
321 struct clk *clk = ERR_PTR(-ENODEV);
322 struct lpss_clk_data *clk_data;
323 const char *parent, *clk_name;
324 void __iomem *prv_base;
325
326 if (!lpss_clk_dev)
327 lpt_register_clock_device();
328
329 clk_data = platform_get_drvdata(lpss_clk_dev);
330 if (!clk_data)
331 return -ENODEV;
332 clk = clk_data->clk;
333
334 if (!pdata->mmio_base
335 || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
336 return -ENODATA;
337
338 parent = clk_data->name;
339 prv_base = pdata->mmio_base + dev_desc->prv_offset;
340
341 if (pdata->fixed_clk_rate) {
342 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
343 pdata->fixed_clk_rate);
344 goto out;
345 }
346
347 if (dev_desc->flags & LPSS_CLK_GATE) {
348 clk = clk_register_gate(NULL, devname, parent, 0,
349 prv_base, 0, 0, NULL);
350 parent = devname;
351 }
352
353 if (dev_desc->flags & LPSS_CLK_DIVIDER) {
354 /* Prevent division by zero */
355 if (!readl(prv_base))
356 writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
357
358 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
359 if (!clk_name)
360 return -ENOMEM;
361 clk = clk_register_fractional_divider(NULL, clk_name, parent,
362 0, prv_base,
363 1, 15, 16, 15, 0, NULL);
364 parent = clk_name;
365
366 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
367 if (!clk_name) {
368 kfree(parent);
369 return -ENOMEM;
370 }
371 clk = clk_register_gate(NULL, clk_name, parent,
372 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
373 prv_base, 31, 0, NULL);
374 kfree(parent);
375 kfree(clk_name);
376 }
377 out:
378 if (IS_ERR(clk))
379 return PTR_ERR(clk);
380
381 pdata->clk = clk;
382 clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
383 return 0;
384 }
385
386 static int acpi_lpss_create_device(struct acpi_device *adev,
387 const struct acpi_device_id *id)
388 {
389 const struct lpss_device_desc *dev_desc;
390 struct lpss_private_data *pdata;
391 struct resource_entry *rentry;
392 struct list_head resource_list;
393 struct platform_device *pdev;
394 int ret;
395
396 dev_desc = (const struct lpss_device_desc *)id->driver_data;
397 if (!dev_desc) {
398 pdev = acpi_create_platform_device(adev);
399 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
400 }
401 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
402 if (!pdata)
403 return -ENOMEM;
404
405 INIT_LIST_HEAD(&resource_list);
406 ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
407 if (ret < 0)
408 goto err_out;
409
410 list_for_each_entry(rentry, &resource_list, node)
411 if (resource_type(rentry->res) == IORESOURCE_MEM) {
412 if (dev_desc->prv_size_override)
413 pdata->mmio_size = dev_desc->prv_size_override;
414 else
415 pdata->mmio_size = resource_size(rentry->res);
416 pdata->mmio_base = ioremap(rentry->res->start,
417 pdata->mmio_size);
418 break;
419 }
420
421 acpi_dev_free_resource_list(&resource_list);
422
423 if (!pdata->mmio_base) {
424 ret = -ENOMEM;
425 goto err_out;
426 }
427
428 pdata->dev_desc = dev_desc;
429
430 if (dev_desc->setup)
431 dev_desc->setup(pdata);
432
433 if (dev_desc->flags & LPSS_CLK) {
434 ret = register_device_clock(adev, pdata);
435 if (ret) {
436 /* Skip the device, but continue the namespace scan. */
437 ret = 0;
438 goto err_out;
439 }
440 }
441
442 /*
443 * This works around a known issue in ACPI tables where LPSS devices
444 * have _PS0 and _PS3 without _PSC (and no power resources), so
445 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
446 */
447 ret = acpi_device_fix_up_power(adev);
448 if (ret) {
449 /* Skip the device, but continue the namespace scan. */
450 ret = 0;
451 goto err_out;
452 }
453
454 if (dev_desc->properties) {
455 ret = device_add_properties(&adev->dev, dev_desc->properties);
456 if (ret)
457 goto err_out;
458 }
459
460 adev->driver_data = pdata;
461 pdev = acpi_create_platform_device(adev);
462 if (!IS_ERR_OR_NULL(pdev)) {
463 return 1;
464 }
465
466 ret = PTR_ERR(pdev);
467 adev->driver_data = NULL;
468
469 err_out:
470 kfree(pdata);
471 return ret;
472 }
473
474 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
475 {
476 return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
477 }
478
479 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
480 unsigned int reg)
481 {
482 writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
483 }
484
485 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
486 {
487 struct acpi_device *adev;
488 struct lpss_private_data *pdata;
489 unsigned long flags;
490 int ret;
491
492 ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
493 if (WARN_ON(ret))
494 return ret;
495
496 spin_lock_irqsave(&dev->power.lock, flags);
497 if (pm_runtime_suspended(dev)) {
498 ret = -EAGAIN;
499 goto out;
500 }
501 pdata = acpi_driver_data(adev);
502 if (WARN_ON(!pdata || !pdata->mmio_base)) {
503 ret = -ENODEV;
504 goto out;
505 }
506 *val = __lpss_reg_read(pdata, reg);
507
508 out:
509 spin_unlock_irqrestore(&dev->power.lock, flags);
510 return ret;
511 }
512
513 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
514 char *buf)
515 {
516 u32 ltr_value = 0;
517 unsigned int reg;
518 int ret;
519
520 reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
521 ret = lpss_reg_read(dev, reg, &ltr_value);
522 if (ret)
523 return ret;
524
525 return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
526 }
527
528 static ssize_t lpss_ltr_mode_show(struct device *dev,
529 struct device_attribute *attr, char *buf)
530 {
531 u32 ltr_mode = 0;
532 char *outstr;
533 int ret;
534
535 ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
536 if (ret)
537 return ret;
538
539 outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
540 return sprintf(buf, "%s\n", outstr);
541 }
542
543 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
544 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
545 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
546
547 static struct attribute *lpss_attrs[] = {
548 &dev_attr_auto_ltr.attr,
549 &dev_attr_sw_ltr.attr,
550 &dev_attr_ltr_mode.attr,
551 NULL,
552 };
553
554 static struct attribute_group lpss_attr_group = {
555 .attrs = lpss_attrs,
556 .name = "lpss_ltr",
557 };
558
559 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
560 {
561 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
562 u32 ltr_mode, ltr_val;
563
564 ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
565 if (val < 0) {
566 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
567 ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
568 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
569 }
570 return;
571 }
572 ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
573 if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
574 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
575 val = LPSS_LTR_MAX_VAL;
576 } else if (val > LPSS_LTR_MAX_VAL) {
577 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
578 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
579 } else {
580 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
581 }
582 ltr_val |= val;
583 __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
584 if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
585 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
586 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
587 }
588 }
589
590 #ifdef CONFIG_PM
591 /**
592 * acpi_lpss_save_ctx() - Save the private registers of LPSS device
593 * @dev: LPSS device
594 * @pdata: pointer to the private data of the LPSS device
595 *
596 * Most LPSS devices have private registers which may loose their context when
597 * the device is powered down. acpi_lpss_save_ctx() saves those registers into
598 * prv_reg_ctx array.
599 */
600 static void acpi_lpss_save_ctx(struct device *dev,
601 struct lpss_private_data *pdata)
602 {
603 unsigned int i;
604
605 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
606 unsigned long offset = i * sizeof(u32);
607
608 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
609 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
610 pdata->prv_reg_ctx[i], offset);
611 }
612 }
613
614 /**
615 * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
616 * @dev: LPSS device
617 * @pdata: pointer to the private data of the LPSS device
618 *
619 * Restores the registers that were previously stored with acpi_lpss_save_ctx().
620 */
621 static void acpi_lpss_restore_ctx(struct device *dev,
622 struct lpss_private_data *pdata)
623 {
624 unsigned int i;
625
626 for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
627 unsigned long offset = i * sizeof(u32);
628
629 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
630 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
631 pdata->prv_reg_ctx[i], offset);
632 }
633 }
634
635 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
636 {
637 /*
638 * The following delay is needed or the subsequent write operations may
639 * fail. The LPSS devices are actually PCI devices and the PCI spec
640 * expects 10ms delay before the device can be accessed after D3 to D0
641 * transition. However some platforms like BSW does not need this delay.
642 */
643 unsigned int delay = 10; /* default 10ms delay */
644
645 if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
646 delay = 0;
647
648 msleep(delay);
649 }
650
651 static int acpi_lpss_activate(struct device *dev)
652 {
653 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
654 int ret;
655
656 ret = acpi_dev_runtime_resume(dev);
657 if (ret)
658 return ret;
659
660 acpi_lpss_d3_to_d0_delay(pdata);
661
662 /*
663 * This is called only on ->probe() stage where a device is either in
664 * known state defined by BIOS or most likely powered off. Due to this
665 * we have to deassert reset line to be sure that ->probe() will
666 * recognize the device.
667 */
668 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
669 lpss_deassert_reset(pdata);
670
671 return 0;
672 }
673
674 static void acpi_lpss_dismiss(struct device *dev)
675 {
676 acpi_dev_runtime_suspend(dev);
677 }
678
679 #ifdef CONFIG_PM_SLEEP
680 static int acpi_lpss_suspend_late(struct device *dev)
681 {
682 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
683 int ret;
684
685 ret = pm_generic_suspend_late(dev);
686 if (ret)
687 return ret;
688
689 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
690 acpi_lpss_save_ctx(dev, pdata);
691
692 return acpi_dev_suspend_late(dev);
693 }
694
695 static int acpi_lpss_resume_early(struct device *dev)
696 {
697 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
698 int ret;
699
700 ret = acpi_dev_resume_early(dev);
701 if (ret)
702 return ret;
703
704 acpi_lpss_d3_to_d0_delay(pdata);
705
706 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
707 acpi_lpss_restore_ctx(dev, pdata);
708
709 return pm_generic_resume_early(dev);
710 }
711 #endif /* CONFIG_PM_SLEEP */
712
713 /* IOSF SB for LPSS island */
714 #define LPSS_IOSF_UNIT_LPIOEP 0xA0
715 #define LPSS_IOSF_UNIT_LPIO1 0xAB
716 #define LPSS_IOSF_UNIT_LPIO2 0xAC
717
718 #define LPSS_IOSF_PMCSR 0x84
719 #define LPSS_PMCSR_D0 0
720 #define LPSS_PMCSR_D3hot 3
721 #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0)
722
723 #define LPSS_IOSF_GPIODEF0 0x154
724 #define LPSS_GPIODEF0_DMA1_D3 BIT(2)
725 #define LPSS_GPIODEF0_DMA2_D3 BIT(3)
726 #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2)
727
728 static DEFINE_MUTEX(lpss_iosf_mutex);
729
730 static void lpss_iosf_enter_d3_state(void)
731 {
732 u32 value1 = 0;
733 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
734 u32 value2 = LPSS_PMCSR_D3hot;
735 u32 mask2 = LPSS_PMCSR_Dx_MASK;
736 /*
737 * PMC provides an information about actual status of the LPSS devices.
738 * Here we read the values related to LPSS power island, i.e. LPSS
739 * devices, excluding both LPSS DMA controllers, along with SCC domain.
740 */
741 u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe;
742 int ret;
743
744 ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
745 if (ret)
746 return;
747
748 mutex_lock(&lpss_iosf_mutex);
749
750 ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
751 if (ret)
752 goto exit;
753
754 /*
755 * Get the status of entire LPSS power island per device basis.
756 * Shutdown both LPSS DMA controllers if and only if all other devices
757 * are already in D3hot.
758 */
759 pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask;
760 if (pmc_status)
761 goto exit;
762
763 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
764 LPSS_IOSF_PMCSR, value2, mask2);
765
766 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
767 LPSS_IOSF_PMCSR, value2, mask2);
768
769 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
770 LPSS_IOSF_GPIODEF0, value1, mask1);
771 exit:
772 mutex_unlock(&lpss_iosf_mutex);
773 }
774
775 static void lpss_iosf_exit_d3_state(void)
776 {
777 u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3;
778 u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
779 u32 value2 = LPSS_PMCSR_D0;
780 u32 mask2 = LPSS_PMCSR_Dx_MASK;
781
782 mutex_lock(&lpss_iosf_mutex);
783
784 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
785 LPSS_IOSF_GPIODEF0, value1, mask1);
786
787 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
788 LPSS_IOSF_PMCSR, value2, mask2);
789
790 iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
791 LPSS_IOSF_PMCSR, value2, mask2);
792
793 mutex_unlock(&lpss_iosf_mutex);
794 }
795
796 static int acpi_lpss_runtime_suspend(struct device *dev)
797 {
798 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
799 int ret;
800
801 ret = pm_generic_runtime_suspend(dev);
802 if (ret)
803 return ret;
804
805 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
806 acpi_lpss_save_ctx(dev, pdata);
807
808 ret = acpi_dev_runtime_suspend(dev);
809
810 /*
811 * This call must be last in the sequence, otherwise PMC will return
812 * wrong status for devices being about to be powered off. See
813 * lpss_iosf_enter_d3_state() for further information.
814 */
815 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
816 lpss_iosf_enter_d3_state();
817
818 return ret;
819 }
820
821 static int acpi_lpss_runtime_resume(struct device *dev)
822 {
823 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
824 int ret;
825
826 /*
827 * This call is kept first to be in symmetry with
828 * acpi_lpss_runtime_suspend() one.
829 */
830 if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
831 lpss_iosf_exit_d3_state();
832
833 ret = acpi_dev_runtime_resume(dev);
834 if (ret)
835 return ret;
836
837 acpi_lpss_d3_to_d0_delay(pdata);
838
839 if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
840 acpi_lpss_restore_ctx(dev, pdata);
841
842 return pm_generic_runtime_resume(dev);
843 }
844 #endif /* CONFIG_PM */
845
846 static struct dev_pm_domain acpi_lpss_pm_domain = {
847 #ifdef CONFIG_PM
848 .activate = acpi_lpss_activate,
849 .dismiss = acpi_lpss_dismiss,
850 #endif
851 .ops = {
852 #ifdef CONFIG_PM
853 #ifdef CONFIG_PM_SLEEP
854 .prepare = acpi_subsys_prepare,
855 .complete = pm_complete_with_resume_check,
856 .suspend = acpi_subsys_suspend,
857 .suspend_late = acpi_lpss_suspend_late,
858 .resume_early = acpi_lpss_resume_early,
859 .freeze = acpi_subsys_freeze,
860 .poweroff = acpi_subsys_suspend,
861 .poweroff_late = acpi_lpss_suspend_late,
862 .restore_early = acpi_lpss_resume_early,
863 #endif
864 .runtime_suspend = acpi_lpss_runtime_suspend,
865 .runtime_resume = acpi_lpss_runtime_resume,
866 #endif
867 },
868 };
869
870 static int acpi_lpss_platform_notify(struct notifier_block *nb,
871 unsigned long action, void *data)
872 {
873 struct platform_device *pdev = to_platform_device(data);
874 struct lpss_private_data *pdata;
875 struct acpi_device *adev;
876 const struct acpi_device_id *id;
877
878 id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
879 if (!id || !id->driver_data)
880 return 0;
881
882 if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
883 return 0;
884
885 pdata = acpi_driver_data(adev);
886 if (!pdata)
887 return 0;
888
889 if (pdata->mmio_base &&
890 pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
891 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
892 return 0;
893 }
894
895 switch (action) {
896 case BUS_NOTIFY_BIND_DRIVER:
897 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
898 break;
899 case BUS_NOTIFY_DRIVER_NOT_BOUND:
900 case BUS_NOTIFY_UNBOUND_DRIVER:
901 dev_pm_domain_set(&pdev->dev, NULL);
902 break;
903 case BUS_NOTIFY_ADD_DEVICE:
904 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
905 if (pdata->dev_desc->flags & LPSS_LTR)
906 return sysfs_create_group(&pdev->dev.kobj,
907 &lpss_attr_group);
908 break;
909 case BUS_NOTIFY_DEL_DEVICE:
910 if (pdata->dev_desc->flags & LPSS_LTR)
911 sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
912 dev_pm_domain_set(&pdev->dev, NULL);
913 break;
914 default:
915 break;
916 }
917
918 return 0;
919 }
920
921 static struct notifier_block acpi_lpss_nb = {
922 .notifier_call = acpi_lpss_platform_notify,
923 };
924
925 static void acpi_lpss_bind(struct device *dev)
926 {
927 struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
928
929 if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
930 return;
931
932 if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
933 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
934 else
935 dev_err(dev, "MMIO size insufficient to access LTR\n");
936 }
937
938 static void acpi_lpss_unbind(struct device *dev)
939 {
940 dev->power.set_latency_tolerance = NULL;
941 }
942
943 static struct acpi_scan_handler lpss_handler = {
944 .ids = acpi_lpss_device_ids,
945 .attach = acpi_lpss_create_device,
946 .bind = acpi_lpss_bind,
947 .unbind = acpi_lpss_unbind,
948 };
949
950 void __init acpi_lpss_init(void)
951 {
952 const struct x86_cpu_id *id;
953 int ret;
954
955 ret = lpt_clk_init();
956 if (ret)
957 return;
958
959 id = x86_match_cpu(lpss_cpu_ids);
960 if (id)
961 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
962
963 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
964 acpi_scan_add_handler(&lpss_handler);
965 }
966
967 #else
968
969 static struct acpi_scan_handler lpss_handler = {
970 .ids = acpi_lpss_device_ids,
971 };
972
973 void __init acpi_lpss_init(void)
974 {
975 acpi_scan_add_handler(&lpss_handler);
976 }
977
978 #endif /* CONFIG_X86_INTEL_LPSS */
Linux kernel - Deliverables
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