projects / deliverable / linux.git / blob
? search:


4ac1bb39a9dfef1e37b11a0c18fa12bce28b6894
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <linux/msi.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_CAVIUM = 0,
57 AHCI_PCI_BAR_ENMOTUS = 2,
58 AHCI_PCI_BAR_STANDARD = 5,
59 };
60
61 enum board_ids {
62 /* board IDs by feature in alphabetical order */
63 board_ahci,
64 board_ahci_ign_iferr,
65 board_ahci_nomsi,
66 board_ahci_noncq,
67 board_ahci_nosntf,
68 board_ahci_yes_fbs,
69
70 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_avn,
72 board_ahci_mcp65,
73 board_ahci_mcp77,
74 board_ahci_mcp89,
75 board_ahci_mv,
76 board_ahci_sb600,
77 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_vt8251,
79
80 /* aliases */
81 board_ahci_mcp_linux = board_ahci_mcp65,
82 board_ahci_mcp67 = board_ahci_mcp65,
83 board_ahci_mcp73 = board_ahci_mcp65,
84 board_ahci_mcp79 = board_ahci_mcp77,
85 };
86
87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
96 #ifdef CONFIG_PM_SLEEP
97 static int ahci_pci_device_suspend(struct device *dev);
98 static int ahci_pci_device_resume(struct device *dev);
99 #endif
100
101 static struct scsi_host_template ahci_sht = {
102 AHCI_SHT("ahci"),
103 };
104
105 static struct ata_port_operations ahci_vt8251_ops = {
106 .inherits = &ahci_ops,
107 .hardreset = ahci_vt8251_hardreset,
108 };
109
110 static struct ata_port_operations ahci_p5wdh_ops = {
111 .inherits = &ahci_ops,
112 .hardreset = ahci_p5wdh_hardreset,
113 };
114
115 static struct ata_port_operations ahci_avn_ops = {
116 .inherits = &ahci_ops,
117 .hardreset = ahci_avn_hardreset,
118 };
119
120 static const struct ata_port_info ahci_port_info[] = {
121 /* by features */
122 [board_ahci] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
127 },
128 [board_ahci_ign_iferr] = {
129 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
135 [board_ahci_nomsi] = {
136 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
141 },
142 [board_ahci_noncq] = {
143 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_nosntf] = {
150 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
151 .flags = AHCI_FLAG_COMMON,
152 .pio_mask = ATA_PIO4,
153 .udma_mask = ATA_UDMA6,
154 .port_ops = &ahci_ops,
155 },
156 [board_ahci_yes_fbs] = {
157 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
158 .flags = AHCI_FLAG_COMMON,
159 .pio_mask = ATA_PIO4,
160 .udma_mask = ATA_UDMA6,
161 .port_ops = &ahci_ops,
162 },
163 /* by chipsets */
164 [board_ahci_avn] = {
165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_avn_ops,
169 },
170 [board_ahci_mcp65] = {
171 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
172 AHCI_HFLAG_YES_NCQ),
173 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_mcp77] = {
179 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 [board_ahci_mcp89] = {
186 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_ops,
191 },
192 [board_ahci_mv] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
194 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
195 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_sb600] = {
201 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
202 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
203 AHCI_HFLAG_32BIT_ONLY),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_pmp_retry_srst_ops,
208 },
209 [board_ahci_sb700] = { /* for SB700 and SB800 */
210 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_pmp_retry_srst_ops,
215 },
216 [board_ahci_vt8251] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
218 .flags = AHCI_FLAG_COMMON,
219 .pio_mask = ATA_PIO4,
220 .udma_mask = ATA_UDMA6,
221 .port_ops = &ahci_vt8251_ops,
222 },
223 };
224
225 static const struct pci_device_id ahci_pci_tbl[] = {
226 /* Intel */
227 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
228 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
229 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
230 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
231 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
232 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
233 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
235 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
236 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
237 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
239 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
240 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
241 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
242 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
246 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
247 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
251 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
254 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
255 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
256 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
258 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
259 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
260 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
261 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
262 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
264 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
265 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
266 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
288 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
289 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
291 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
292 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
293 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
294 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
296 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
297 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
299 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
300 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
304 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
305 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
306 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
307 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
309 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
311 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
312 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
313 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
319 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
320 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
321 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
322 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
323 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
328 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
329 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
330 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
331 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
338 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
340 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
341 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
342 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
344 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
346 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
347 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
348 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
349 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
352 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
353 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
354 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
355 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
356 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
357 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
358 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
359 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
360 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
361 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
363 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
364 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
365 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
366 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
367 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
368 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
369 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
370 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
371 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
372 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
374 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
375 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
376 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
377 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
379
380 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
381 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
382 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
383 /* JMicron 362B and 362C have an AHCI function with IDE class code */
384 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
385 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
386 /* May need to update quirk_jmicron_async_suspend() for additions */
387
388 /* ATI */
389 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
390 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
391 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
392 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
393 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
394 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
395 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
396
397 /* AMD */
398 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
399 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
400 /* AMD is using RAID class only for ahci controllers */
401 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
402 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
403
404 /* VIA */
405 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
406 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
407
408 /* NVIDIA */
409 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
430 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
431 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
432 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
433 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
434 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
435 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
436 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
437 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
438 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
446 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
447 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
458 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
470 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
471 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
472 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
473 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
474 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
475 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
476 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
477 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
478 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
482 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
483 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
484 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
485 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
486 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
487 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
488 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
489 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
490 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
493
494 /* SiS */
495 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
496 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
497 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
498
499 /* ST Microelectronics */
500 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
501
502 /* Marvell */
503 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
504 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
505 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
506 .class = PCI_CLASS_STORAGE_SATA_AHCI,
507 .class_mask = 0xffffff,
508 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
509 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
510 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
511 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
512 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
513 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
515 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
516 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
517 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
521 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
522 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
523 .driver_data = board_ahci_yes_fbs },
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
525 .driver_data = board_ahci_yes_fbs },
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
527 .driver_data = board_ahci_yes_fbs },
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
529 .driver_data = board_ahci_yes_fbs },
530 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
531 .driver_data = board_ahci_yes_fbs },
532
533 /* Promise */
534 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
535 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
536
537 /* Asmedia */
538 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
539 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
540 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
541 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
542
543 /*
544 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
545 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
546 */
547 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
548 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
549
550 /* Enmotus */
551 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
552
553 /* Generic, PCI class code for AHCI */
554 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
555 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
556
557 { } /* terminate list */
558 };
559
560 static const struct dev_pm_ops ahci_pci_pm_ops = {
561 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
562 };
563
564 static struct pci_driver ahci_pci_driver = {
565 .name = DRV_NAME,
566 .id_table = ahci_pci_tbl,
567 .probe = ahci_init_one,
568 .remove = ata_pci_remove_one,
569 .driver = {
570 .pm = &ahci_pci_pm_ops,
571 },
572 };
573
574 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
575 static int marvell_enable;
576 #else
577 static int marvell_enable = 1;
578 #endif
579 module_param(marvell_enable, int, 0644);
580 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
581
582
583 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
584 struct ahci_host_priv *hpriv)
585 {
586 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
587 dev_info(&pdev->dev, "JMB361 has only one port\n");
588 hpriv->force_port_map = 1;
589 }
590
591 /*
592 * Temporary Marvell 6145 hack: PATA port presence
593 * is asserted through the standard AHCI port
594 * presence register, as bit 4 (counting from 0)
595 */
596 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
597 if (pdev->device == 0x6121)
598 hpriv->mask_port_map = 0x3;
599 else
600 hpriv->mask_port_map = 0xf;
601 dev_info(&pdev->dev,
602 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
603 }
604
605 ahci_save_initial_config(&pdev->dev, hpriv);
606 }
607
608 static int ahci_pci_reset_controller(struct ata_host *host)
609 {
610 struct pci_dev *pdev = to_pci_dev(host->dev);
611
612 ahci_reset_controller(host);
613
614 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
615 struct ahci_host_priv *hpriv = host->private_data;
616 u16 tmp16;
617
618 /* configure PCS */
619 pci_read_config_word(pdev, 0x92, &tmp16);
620 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
621 tmp16 |= hpriv->port_map;
622 pci_write_config_word(pdev, 0x92, tmp16);
623 }
624 }
625
626 return 0;
627 }
628
629 static void ahci_pci_init_controller(struct ata_host *host)
630 {
631 struct ahci_host_priv *hpriv = host->private_data;
632 struct pci_dev *pdev = to_pci_dev(host->dev);
633 void __iomem *port_mmio;
634 u32 tmp;
635 int mv;
636
637 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
638 if (pdev->device == 0x6121)
639 mv = 2;
640 else
641 mv = 4;
642 port_mmio = __ahci_port_base(host, mv);
643
644 writel(0, port_mmio + PORT_IRQ_MASK);
645
646 /* clear port IRQ */
647 tmp = readl(port_mmio + PORT_IRQ_STAT);
648 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
649 if (tmp)
650 writel(tmp, port_mmio + PORT_IRQ_STAT);
651 }
652
653 ahci_init_controller(host);
654 }
655
656 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
657 unsigned long deadline)
658 {
659 struct ata_port *ap = link->ap;
660 struct ahci_host_priv *hpriv = ap->host->private_data;
661 bool online;
662 int rc;
663
664 DPRINTK("ENTER\n");
665
666 ahci_stop_engine(ap);
667
668 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
669 deadline, &online, NULL);
670
671 hpriv->start_engine(ap);
672
673 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
674
675 /* vt8251 doesn't clear BSY on signature FIS reception,
676 * request follow-up softreset.
677 */
678 return online ? -EAGAIN : rc;
679 }
680
681 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
682 unsigned long deadline)
683 {
684 struct ata_port *ap = link->ap;
685 struct ahci_port_priv *pp = ap->private_data;
686 struct ahci_host_priv *hpriv = ap->host->private_data;
687 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
688 struct ata_taskfile tf;
689 bool online;
690 int rc;
691
692 ahci_stop_engine(ap);
693
694 /* clear D2H reception area to properly wait for D2H FIS */
695 ata_tf_init(link->device, &tf);
696 tf.command = ATA_BUSY;
697 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
698
699 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
700 deadline, &online, NULL);
701
702 hpriv->start_engine(ap);
703
704 /* The pseudo configuration device on SIMG4726 attached to
705 * ASUS P5W-DH Deluxe doesn't send signature FIS after
706 * hardreset if no device is attached to the first downstream
707 * port && the pseudo device locks up on SRST w/ PMP==0. To
708 * work around this, wait for !BSY only briefly. If BSY isn't
709 * cleared, perform CLO and proceed to IDENTIFY (achieved by
710 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
711 *
712 * Wait for two seconds. Devices attached to downstream port
713 * which can't process the following IDENTIFY after this will
714 * have to be reset again. For most cases, this should
715 * suffice while making probing snappish enough.
716 */
717 if (online) {
718 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
719 ahci_check_ready);
720 if (rc)
721 ahci_kick_engine(ap);
722 }
723 return rc;
724 }
725
726 /*
727 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
728 *
729 * It has been observed with some SSDs that the timing of events in the
730 * link synchronization phase can leave the port in a state that can not
731 * be recovered by a SATA-hard-reset alone. The failing signature is
732 * SStatus.DET stuck at 1 ("Device presence detected but Phy
733 * communication not established"). It was found that unloading and
734 * reloading the driver when this problem occurs allows the drive
735 * connection to be recovered (DET advanced to 0x3). The critical
736 * component of reloading the driver is that the port state machines are
737 * reset by bouncing "port enable" in the AHCI PCS configuration
738 * register. So, reproduce that effect by bouncing a port whenever we
739 * see DET==1 after a reset.
740 */
741 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
742 unsigned long deadline)
743 {
744 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
745 struct ata_port *ap = link->ap;
746 struct ahci_port_priv *pp = ap->private_data;
747 struct ahci_host_priv *hpriv = ap->host->private_data;
748 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
749 unsigned long tmo = deadline - jiffies;
750 struct ata_taskfile tf;
751 bool online;
752 int rc, i;
753
754 DPRINTK("ENTER\n");
755
756 ahci_stop_engine(ap);
757
758 for (i = 0; i < 2; i++) {
759 u16 val;
760 u32 sstatus;
761 int port = ap->port_no;
762 struct ata_host *host = ap->host;
763 struct pci_dev *pdev = to_pci_dev(host->dev);
764
765 /* clear D2H reception area to properly wait for D2H FIS */
766 ata_tf_init(link->device, &tf);
767 tf.command = ATA_BUSY;
768 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
769
770 rc = sata_link_hardreset(link, timing, deadline, &online,
771 ahci_check_ready);
772
773 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
774 (sstatus & 0xf) != 1)
775 break;
776
777 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
778 port);
779
780 pci_read_config_word(pdev, 0x92, &val);
781 val &= ~(1 << port);
782 pci_write_config_word(pdev, 0x92, val);
783 ata_msleep(ap, 1000);
784 val |= 1 << port;
785 pci_write_config_word(pdev, 0x92, val);
786 deadline += tmo;
787 }
788
789 hpriv->start_engine(ap);
790
791 if (online)
792 *class = ahci_dev_classify(ap);
793
794 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
795 return rc;
796 }
797
798
799 #ifdef CONFIG_PM_SLEEP
800 static int ahci_pci_device_suspend(struct device *dev)
801 {
802 struct pci_dev *pdev = to_pci_dev(dev);
803 struct ata_host *host = pci_get_drvdata(pdev);
804 struct ahci_host_priv *hpriv = host->private_data;
805 void __iomem *mmio = hpriv->mmio;
806 u32 ctl;
807
808 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
809 dev_err(&pdev->dev,
810 "BIOS update required for suspend/resume\n");
811 return -EIO;
812 }
813
814 /* AHCI spec rev1.1 section 8.3.3:
815 * Software must disable interrupts prior to requesting a
816 * transition of the HBA to D3 state.
817 */
818 ctl = readl(mmio + HOST_CTL);
819 ctl &= ~HOST_IRQ_EN;
820 writel(ctl, mmio + HOST_CTL);
821 readl(mmio + HOST_CTL); /* flush */
822
823 return ata_host_suspend(host, PMSG_SUSPEND);
824 }
825
826 static int ahci_pci_device_resume(struct device *dev)
827 {
828 struct pci_dev *pdev = to_pci_dev(dev);
829 struct ata_host *host = pci_get_drvdata(pdev);
830 int rc;
831
832 /* Apple BIOS helpfully mangles the registers on resume */
833 if (is_mcp89_apple(pdev))
834 ahci_mcp89_apple_enable(pdev);
835
836 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
837 rc = ahci_pci_reset_controller(host);
838 if (rc)
839 return rc;
840
841 ahci_pci_init_controller(host);
842 }
843
844 ata_host_resume(host);
845
846 return 0;
847 }
848 #endif
849
850 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
851 {
852 int rc;
853
854 /*
855 * If the device fixup already set the dma_mask to some non-standard
856 * value, don't extend it here. This happens on STA2X11, for example.
857 */
858 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
859 return 0;
860
861 if (using_dac &&
862 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
863 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
864 if (rc) {
865 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
866 if (rc) {
867 dev_err(&pdev->dev,
868 "64-bit DMA enable failed\n");
869 return rc;
870 }
871 }
872 } else {
873 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
874 if (rc) {
875 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
876 return rc;
877 }
878 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
879 if (rc) {
880 dev_err(&pdev->dev,
881 "32-bit consistent DMA enable failed\n");
882 return rc;
883 }
884 }
885 return 0;
886 }
887
888 static void ahci_pci_print_info(struct ata_host *host)
889 {
890 struct pci_dev *pdev = to_pci_dev(host->dev);
891 u16 cc;
892 const char *scc_s;
893
894 pci_read_config_word(pdev, 0x0a, &cc);
895 if (cc == PCI_CLASS_STORAGE_IDE)
896 scc_s = "IDE";
897 else if (cc == PCI_CLASS_STORAGE_SATA)
898 scc_s = "SATA";
899 else if (cc == PCI_CLASS_STORAGE_RAID)
900 scc_s = "RAID";
901 else
902 scc_s = "unknown";
903
904 ahci_print_info(host, scc_s);
905 }
906
907 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
908 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
909 * support PMP and the 4726 either directly exports the device
910 * attached to the first downstream port or acts as a hardware storage
911 * controller and emulate a single ATA device (can be RAID 0/1 or some
912 * other configuration).
913 *
914 * When there's no device attached to the first downstream port of the
915 * 4726, "Config Disk" appears, which is a pseudo ATA device to
916 * configure the 4726. However, ATA emulation of the device is very
917 * lame. It doesn't send signature D2H Reg FIS after the initial
918 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
919 *
920 * The following function works around the problem by always using
921 * hardreset on the port and not depending on receiving signature FIS
922 * afterward. If signature FIS isn't received soon, ATA class is
923 * assumed without follow-up softreset.
924 */
925 static void ahci_p5wdh_workaround(struct ata_host *host)
926 {
927 static const struct dmi_system_id sysids[] = {
928 {
929 .ident = "P5W DH Deluxe",
930 .matches = {
931 DMI_MATCH(DMI_SYS_VENDOR,
932 "ASUSTEK COMPUTER INC"),
933 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
934 },
935 },
936 { }
937 };
938 struct pci_dev *pdev = to_pci_dev(host->dev);
939
940 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
941 dmi_check_system(sysids)) {
942 struct ata_port *ap = host->ports[1];
943
944 dev_info(&pdev->dev,
945 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
946
947 ap->ops = &ahci_p5wdh_ops;
948 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
949 }
950 }
951
952 /*
953 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
954 * booting in BIOS compatibility mode. We restore the registers but not ID.
955 */
956 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
957 {
958 u32 val;
959
960 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
961
962 pci_read_config_dword(pdev, 0xf8, &val);
963 val |= 1 << 0x1b;
964 /* the following changes the device ID, but appears not to affect function */
965 /* val = (val & ~0xf0000000) | 0x80000000; */
966 pci_write_config_dword(pdev, 0xf8, val);
967
968 pci_read_config_dword(pdev, 0x54c, &val);
969 val |= 1 << 0xc;
970 pci_write_config_dword(pdev, 0x54c, val);
971
972 pci_read_config_dword(pdev, 0x4a4, &val);
973 val &= 0xff;
974 val |= 0x01060100;
975 pci_write_config_dword(pdev, 0x4a4, val);
976
977 pci_read_config_dword(pdev, 0x54c, &val);
978 val &= ~(1 << 0xc);
979 pci_write_config_dword(pdev, 0x54c, val);
980
981 pci_read_config_dword(pdev, 0xf8, &val);
982 val &= ~(1 << 0x1b);
983 pci_write_config_dword(pdev, 0xf8, val);
984 }
985
986 static bool is_mcp89_apple(struct pci_dev *pdev)
987 {
988 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
989 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
990 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
991 pdev->subsystem_device == 0xcb89;
992 }
993
994 /* only some SB600 ahci controllers can do 64bit DMA */
995 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
996 {
997 static const struct dmi_system_id sysids[] = {
998 /*
999 * The oldest version known to be broken is 0901 and
1000 * working is 1501 which was released on 2007-10-26.
1001 * Enable 64bit DMA on 1501 and anything newer.
1002 *
1003 * Please read bko#9412 for more info.
1004 */
1005 {
1006 .ident = "ASUS M2A-VM",
1007 .matches = {
1008 DMI_MATCH(DMI_BOARD_VENDOR,
1009 "ASUSTeK Computer INC."),
1010 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1011 },
1012 .driver_data = "20071026", /* yyyymmdd */
1013 },
1014 /*
1015 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1016 * support 64bit DMA.
1017 *
1018 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1019 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1020 * This spelling mistake was fixed in BIOS version 1.5, so
1021 * 1.5 and later have the Manufacturer as
1022 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1023 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1024 *
1025 * BIOS versions earlier than 1.9 had a Board Product Name
1026 * DMI field of "MS-7376". This was changed to be
1027 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1028 * match on DMI_BOARD_NAME of "MS-7376".
1029 */
1030 {
1031 .ident = "MSI K9A2 Platinum",
1032 .matches = {
1033 DMI_MATCH(DMI_BOARD_VENDOR,
1034 "MICRO-STAR INTER"),
1035 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1036 },
1037 },
1038 /*
1039 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1040 * 64bit DMA.
1041 *
1042 * This board also had the typo mentioned above in the
1043 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1044 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1045 */
1046 {
1047 .ident = "MSI K9AGM2",
1048 .matches = {
1049 DMI_MATCH(DMI_BOARD_VENDOR,
1050 "MICRO-STAR INTER"),
1051 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1052 },
1053 },
1054 /*
1055 * All BIOS versions for the Asus M3A support 64bit DMA.
1056 * (all release versions from 0301 to 1206 were tested)
1057 */
1058 {
1059 .ident = "ASUS M3A",
1060 .matches = {
1061 DMI_MATCH(DMI_BOARD_VENDOR,
1062 "ASUSTeK Computer INC."),
1063 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1064 },
1065 },
1066 { }
1067 };
1068 const struct dmi_system_id *match;
1069 int year, month, date;
1070 char buf[9];
1071
1072 match = dmi_first_match(sysids);
1073 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1074 !match)
1075 return false;
1076
1077 if (!match->driver_data)
1078 goto enable_64bit;
1079
1080 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1081 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1082
1083 if (strcmp(buf, match->driver_data) >= 0)
1084 goto enable_64bit;
1085 else {
1086 dev_warn(&pdev->dev,
1087 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1088 match->ident);
1089 return false;
1090 }
1091
1092 enable_64bit:
1093 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1094 return true;
1095 }
1096
1097 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1098 {
1099 static const struct dmi_system_id broken_systems[] = {
1100 {
1101 .ident = "HP Compaq nx6310",
1102 .matches = {
1103 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1104 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1105 },
1106 /* PCI slot number of the controller */
1107 .driver_data = (void *)0x1FUL,
1108 },
1109 {
1110 .ident = "HP Compaq 6720s",
1111 .matches = {
1112 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1113 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1114 },
1115 /* PCI slot number of the controller */
1116 .driver_data = (void *)0x1FUL,
1117 },
1118
1119 { } /* terminate list */
1120 };
1121 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1122
1123 if (dmi) {
1124 unsigned long slot = (unsigned long)dmi->driver_data;
1125 /* apply the quirk only to on-board controllers */
1126 return slot == PCI_SLOT(pdev->devfn);
1127 }
1128
1129 return false;
1130 }
1131
1132 static bool ahci_broken_suspend(struct pci_dev *pdev)
1133 {
1134 static const struct dmi_system_id sysids[] = {
1135 /*
1136 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1137 * to the harddisk doesn't become online after
1138 * resuming from STR. Warn and fail suspend.
1139 *
1140 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1141 *
1142 * Use dates instead of versions to match as HP is
1143 * apparently recycling both product and version
1144 * strings.
1145 *
1146 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1147 */
1148 {
1149 .ident = "dv4",
1150 .matches = {
1151 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1152 DMI_MATCH(DMI_PRODUCT_NAME,
1153 "HP Pavilion dv4 Notebook PC"),
1154 },
1155 .driver_data = "20090105", /* F.30 */
1156 },
1157 {
1158 .ident = "dv5",
1159 .matches = {
1160 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1161 DMI_MATCH(DMI_PRODUCT_NAME,
1162 "HP Pavilion dv5 Notebook PC"),
1163 },
1164 .driver_data = "20090506", /* F.16 */
1165 },
1166 {
1167 .ident = "dv6",
1168 .matches = {
1169 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1170 DMI_MATCH(DMI_PRODUCT_NAME,
1171 "HP Pavilion dv6 Notebook PC"),
1172 },
1173 .driver_data = "20090423", /* F.21 */
1174 },
1175 {
1176 .ident = "HDX18",
1177 .matches = {
1178 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1179 DMI_MATCH(DMI_PRODUCT_NAME,
1180 "HP HDX18 Notebook PC"),
1181 },
1182 .driver_data = "20090430", /* F.23 */
1183 },
1184 /*
1185 * Acer eMachines G725 has the same problem. BIOS
1186 * V1.03 is known to be broken. V3.04 is known to
1187 * work. Between, there are V1.06, V2.06 and V3.03
1188 * that we don't have much idea about. For now,
1189 * blacklist anything older than V3.04.
1190 *
1191 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1192 */
1193 {
1194 .ident = "G725",
1195 .matches = {
1196 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1197 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1198 },
1199 .driver_data = "20091216", /* V3.04 */
1200 },
1201 { } /* terminate list */
1202 };
1203 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1204 int year, month, date;
1205 char buf[9];
1206
1207 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1208 return false;
1209
1210 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1211 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1212
1213 return strcmp(buf, dmi->driver_data) < 0;
1214 }
1215
1216 static bool ahci_broken_online(struct pci_dev *pdev)
1217 {
1218 #define ENCODE_BUSDEVFN(bus, slot, func) \
1219 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1220 static const struct dmi_system_id sysids[] = {
1221 /*
1222 * There are several gigabyte boards which use
1223 * SIMG5723s configured as hardware RAID. Certain
1224 * 5723 firmware revisions shipped there keep the link
1225 * online but fail to answer properly to SRST or
1226 * IDENTIFY when no device is attached downstream
1227 * causing libata to retry quite a few times leading
1228 * to excessive detection delay.
1229 *
1230 * As these firmwares respond to the second reset try
1231 * with invalid device signature, considering unknown
1232 * sig as offline works around the problem acceptably.
1233 */
1234 {
1235 .ident = "EP45-DQ6",
1236 .matches = {
1237 DMI_MATCH(DMI_BOARD_VENDOR,
1238 "Gigabyte Technology Co., Ltd."),
1239 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1240 },
1241 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1242 },
1243 {
1244 .ident = "EP45-DS5",
1245 .matches = {
1246 DMI_MATCH(DMI_BOARD_VENDOR,
1247 "Gigabyte Technology Co., Ltd."),
1248 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1249 },
1250 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1251 },
1252 { } /* terminate list */
1253 };
1254 #undef ENCODE_BUSDEVFN
1255 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1256 unsigned int val;
1257
1258 if (!dmi)
1259 return false;
1260
1261 val = (unsigned long)dmi->driver_data;
1262
1263 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1264 }
1265
1266 static bool ahci_broken_devslp(struct pci_dev *pdev)
1267 {
1268 /* device with broken DEVSLP but still showing SDS capability */
1269 static const struct pci_device_id ids[] = {
1270 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1271 {}
1272 };
1273
1274 return pci_match_id(ids, pdev);
1275 }
1276
1277 #ifdef CONFIG_ATA_ACPI
1278 static void ahci_gtf_filter_workaround(struct ata_host *host)
1279 {
1280 static const struct dmi_system_id sysids[] = {
1281 /*
1282 * Aspire 3810T issues a bunch of SATA enable commands
1283 * via _GTF including an invalid one and one which is
1284 * rejected by the device. Among the successful ones
1285 * is FPDMA non-zero offset enable which when enabled
1286 * only on the drive side leads to NCQ command
1287 * failures. Filter it out.
1288 */
1289 {
1290 .ident = "Aspire 3810T",
1291 .matches = {
1292 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1293 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1294 },
1295 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1296 },
1297 { }
1298 };
1299 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1300 unsigned int filter;
1301 int i;
1302
1303 if (!dmi)
1304 return;
1305
1306 filter = (unsigned long)dmi->driver_data;
1307 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1308 filter, dmi->ident);
1309
1310 for (i = 0; i < host->n_ports; i++) {
1311 struct ata_port *ap = host->ports[i];
1312 struct ata_link *link;
1313 struct ata_device *dev;
1314
1315 ata_for_each_link(link, ap, EDGE)
1316 ata_for_each_dev(dev, link, ALL)
1317 dev->gtf_filter |= filter;
1318 }
1319 }
1320 #else
1321 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1322 {}
1323 #endif
1324
1325 /*
1326 * ahci_init_msix() - optionally enable per-port MSI-X otherwise defer
1327 * to single msi.
1328 */
1329 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1330 struct ahci_host_priv *hpriv, unsigned long flags)
1331 {
1332 int nvec, i, rc;
1333
1334 /* Do not init MSI-X if MSI is disabled for the device */
1335 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1336 return -ENODEV;
1337
1338 nvec = pci_msix_vec_count(pdev);
1339 if (nvec < 0)
1340 return nvec;
1341
1342 /*
1343 * Proper MSI-X implementations will have a vector per-port.
1344 * Barring that, we prefer single-MSI over single-MSIX. If this
1345 * check fails (not enough MSI-X vectors for all ports) we will
1346 * be called again with the flag clear iff ahci_init_msi()
1347 * fails.
1348 */
1349 if (flags & AHCI_HFLAG_MULTI_MSIX) {
1350 if (nvec < n_ports)
1351 return -ENODEV;
1352 nvec = n_ports;
1353 } else if (nvec) {
1354 nvec = 1;
1355 } else {
1356 /*
1357 * Emit dev_err() since this was the non-legacy irq
1358 * method of last resort.
1359 */
1360 rc = -ENODEV;
1361 goto fail;
1362 }
1363
1364 for (i = 0; i < nvec; i++)
1365 hpriv->msix[i].entry = i;
1366 rc = pci_enable_msix_exact(pdev, hpriv->msix, nvec);
1367 if (rc < 0)
1368 goto fail;
1369
1370 if (nvec > 1)
1371 hpriv->flags |= AHCI_HFLAG_MULTI_MSIX;
1372 hpriv->irq = hpriv->msix[0].vector; /* for single msi-x */
1373
1374 return nvec;
1375 fail:
1376 dev_err(&pdev->dev,
1377 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1378 rc, nvec);
1379
1380 return rc;
1381 }
1382
1383 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1384 struct ahci_host_priv *hpriv)
1385 {
1386 int rc, nvec;
1387
1388 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1389 return -ENODEV;
1390
1391 nvec = pci_msi_vec_count(pdev);
1392 if (nvec < 0)
1393 return nvec;
1394
1395 /*
1396 * If number of MSIs is less than number of ports then Sharing Last
1397 * Message mode could be enforced. In this case assume that advantage
1398 * of multipe MSIs is negated and use single MSI mode instead.
1399 */
1400 if (nvec < n_ports)
1401 goto single_msi;
1402
1403 rc = pci_enable_msi_exact(pdev, nvec);
1404 if (rc == -ENOSPC)
1405 goto single_msi;
1406 if (rc < 0)
1407 return rc;
1408
1409 /* fallback to single MSI mode if the controller enforced MRSM mode */
1410 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1411 pci_disable_msi(pdev);
1412 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1413 goto single_msi;
1414 }
1415
1416 if (nvec > 1)
1417 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1418
1419 goto out;
1420
1421 single_msi:
1422 nvec = 1;
1423
1424 rc = pci_enable_msi(pdev);
1425 if (rc < 0)
1426 return rc;
1427 out:
1428 hpriv->irq = pdev->irq;
1429
1430 return nvec;
1431 }
1432
1433 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1434 struct ahci_host_priv *hpriv)
1435 {
1436 int nvec;
1437
1438 /*
1439 * Try to enable per-port MSI-X. If the host is not capable
1440 * fall back to single MSI before finally attempting single
1441 * MSI-X.
1442 */
1443 nvec = ahci_init_msix(pdev, n_ports, hpriv, AHCI_HFLAG_MULTI_MSIX);
1444 if (nvec >= 0)
1445 return nvec;
1446
1447 nvec = ahci_init_msi(pdev, n_ports, hpriv);
1448 if (nvec >= 0)
1449 return nvec;
1450
1451 /* try single-msix */
1452 nvec = ahci_init_msix(pdev, n_ports, hpriv, 0);
1453 if (nvec >= 0)
1454 return nvec;
1455
1456 /* legacy intx interrupts */
1457 pci_intx(pdev, 1);
1458 hpriv->irq = pdev->irq;
1459
1460 return 0;
1461 }
1462
1463 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1464 {
1465 unsigned int board_id = ent->driver_data;
1466 struct ata_port_info pi = ahci_port_info[board_id];
1467 const struct ata_port_info *ppi[] = { &pi, NULL };
1468 struct device *dev = &pdev->dev;
1469 struct ahci_host_priv *hpriv;
1470 struct ata_host *host;
1471 int n_ports, i, rc;
1472 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1473
1474 VPRINTK("ENTER\n");
1475
1476 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1477
1478 ata_print_version_once(&pdev->dev, DRV_VERSION);
1479
1480 /* The AHCI driver can only drive the SATA ports, the PATA driver
1481 can drive them all so if both drivers are selected make sure
1482 AHCI stays out of the way */
1483 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1484 return -ENODEV;
1485
1486 /* Apple BIOS on MCP89 prevents us using AHCI */
1487 if (is_mcp89_apple(pdev))
1488 ahci_mcp89_apple_enable(pdev);
1489
1490 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1491 * At the moment, we can only use the AHCI mode. Let the users know
1492 * that for SAS drives they're out of luck.
1493 */
1494 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1495 dev_info(&pdev->dev,
1496 "PDC42819 can only drive SATA devices with this driver\n");
1497
1498 /* Some devices use non-standard BARs */
1499 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1500 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1501 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1502 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1503 else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1504 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1505
1506 /* acquire resources */
1507 rc = pcim_enable_device(pdev);
1508 if (rc)
1509 return rc;
1510
1511 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1512 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1513 u8 map;
1514
1515 /* ICH6s share the same PCI ID for both piix and ahci
1516 * modes. Enabling ahci mode while MAP indicates
1517 * combined mode is a bad idea. Yield to ata_piix.
1518 */
1519 pci_read_config_byte(pdev, ICH_MAP, &map);
1520 if (map & 0x3) {
1521 dev_info(&pdev->dev,
1522 "controller is in combined mode, can't enable AHCI mode\n");
1523 return -ENODEV;
1524 }
1525 }
1526
1527 /* AHCI controllers often implement SFF compatible interface.
1528 * Grab all PCI BARs just in case.
1529 */
1530 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1531 if (rc == -EBUSY)
1532 pcim_pin_device(pdev);
1533 if (rc)
1534 return rc;
1535
1536 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1537 if (!hpriv)
1538 return -ENOMEM;
1539 hpriv->flags |= (unsigned long)pi.private_data;
1540
1541 /* MCP65 revision A1 and A2 can't do MSI */
1542 if (board_id == board_ahci_mcp65 &&
1543 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1544 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1545
1546 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1547 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1548 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1549
1550 /* only some SB600s can do 64bit DMA */
1551 if (ahci_sb600_enable_64bit(pdev))
1552 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1553
1554 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1555
1556 /* must set flag prior to save config in order to take effect */
1557 if (ahci_broken_devslp(pdev))
1558 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1559
1560 /* save initial config */
1561 ahci_pci_save_initial_config(pdev, hpriv);
1562
1563 /* prepare host */
1564 if (hpriv->cap & HOST_CAP_NCQ) {
1565 pi.flags |= ATA_FLAG_NCQ;
1566 /*
1567 * Auto-activate optimization is supposed to be
1568 * supported on all AHCI controllers indicating NCQ
1569 * capability, but it seems to be broken on some
1570 * chipsets including NVIDIAs.
1571 */
1572 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1573 pi.flags |= ATA_FLAG_FPDMA_AA;
1574
1575 /*
1576 * All AHCI controllers should be forward-compatible
1577 * with the new auxiliary field. This code should be
1578 * conditionalized if any buggy AHCI controllers are
1579 * encountered.
1580 */
1581 pi.flags |= ATA_FLAG_FPDMA_AUX;
1582 }
1583
1584 if (hpriv->cap & HOST_CAP_PMP)
1585 pi.flags |= ATA_FLAG_PMP;
1586
1587 ahci_set_em_messages(hpriv, &pi);
1588
1589 if (ahci_broken_system_poweroff(pdev)) {
1590 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1591 dev_info(&pdev->dev,
1592 "quirky BIOS, skipping spindown on poweroff\n");
1593 }
1594
1595 if (ahci_broken_suspend(pdev)) {
1596 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1597 dev_warn(&pdev->dev,
1598 "BIOS update required for suspend/resume\n");
1599 }
1600
1601 if (ahci_broken_online(pdev)) {
1602 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1603 dev_info(&pdev->dev,
1604 "online status unreliable, applying workaround\n");
1605 }
1606
1607 /* CAP.NP sometimes indicate the index of the last enabled
1608 * port, at other times, that of the last possible port, so
1609 * determining the maximum port number requires looking at
1610 * both CAP.NP and port_map.
1611 */
1612 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1613
1614 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1615 if (!host)
1616 return -ENOMEM;
1617 host->private_data = hpriv;
1618 hpriv->msix = devm_kzalloc(&pdev->dev,
1619 sizeof(struct msix_entry) * n_ports, GFP_KERNEL);
1620 if (!hpriv->msix)
1621 return -ENOMEM;
1622 ahci_init_interrupts(pdev, n_ports, hpriv);
1623
1624 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1625 host->flags |= ATA_HOST_PARALLEL_SCAN;
1626 else
1627 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1628
1629 if (pi.flags & ATA_FLAG_EM)
1630 ahci_reset_em(host);
1631
1632 for (i = 0; i < host->n_ports; i++) {
1633 struct ata_port *ap = host->ports[i];
1634
1635 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1636 ata_port_pbar_desc(ap, ahci_pci_bar,
1637 0x100 + ap->port_no * 0x80, "port");
1638
1639 /* set enclosure management message type */
1640 if (ap->flags & ATA_FLAG_EM)
1641 ap->em_message_type = hpriv->em_msg_type;
1642
1643
1644 /* disabled/not-implemented port */
1645 if (!(hpriv->port_map & (1 << i)))
1646 ap->ops = &ata_dummy_port_ops;
1647 }
1648
1649 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1650 ahci_p5wdh_workaround(host);
1651
1652 /* apply gtf filter quirk */
1653 ahci_gtf_filter_workaround(host);
1654
1655 /* initialize adapter */
1656 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1657 if (rc)
1658 return rc;
1659
1660 rc = ahci_pci_reset_controller(host);
1661 if (rc)
1662 return rc;
1663
1664 ahci_pci_init_controller(host);
1665 ahci_pci_print_info(host);
1666
1667 pci_set_master(pdev);
1668
1669 return ahci_host_activate(host, &ahci_sht);
1670 }
1671
1672 module_pci_driver(ahci_pci_driver);
1673
1674 MODULE_AUTHOR("Jeff Garzik");
1675 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1676 MODULE_LICENSE("GPL");
1677 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1678 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
This page took 0.084457 seconds and 4 git commands to generate.