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Merge branches 'pm-avs', 'pm-clk', 'pm-devfreq' and 'pm-sleep'
[deliverable/linux.git] / drivers / ata / libahci.c
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include <linux/pci.h>
47 #include "ahci.h"
48 #include "libata.h"
49
50 static int ahci_skip_host_reset;
51 int ahci_ignore_sss;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73 static int ahci_port_start(struct ata_port *ap);
74 static void ahci_port_stop(struct ata_port *ap);
75 static void ahci_qc_prep(struct ata_queued_cmd *qc);
76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77 static void ahci_freeze(struct ata_port *ap);
78 static void ahci_thaw(struct ata_port *ap);
79 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_postreset(struct ata_link *link, unsigned int *class);
91 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
92 static void ahci_dev_config(struct ata_device *dev);
93 #ifdef CONFIG_PM
94 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95 #endif
96 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97 static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99 static void ahci_init_sw_activity(struct ata_link *link);
100
101 static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103 static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
114 static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
116 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
117
118 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
122 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
124 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
125
126 struct device_attribute *ahci_shost_attrs[] = {
127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
134 &dev_attr_em_buffer,
135 &dev_attr_em_message_supported,
136 NULL
137 };
138 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
139
140 struct device_attribute *ahci_sdev_attrs[] = {
141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 NULL
144 };
145 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
146
147 struct ata_port_operations ahci_ops = {
148 .inherits = &sata_pmp_port_ops,
149
150 .qc_defer = ahci_pmp_qc_defer,
151 .qc_prep = ahci_qc_prep,
152 .qc_issue = ahci_qc_issue,
153 .qc_fill_rtf = ahci_qc_fill_rtf,
154
155 .freeze = ahci_freeze,
156 .thaw = ahci_thaw,
157 .softreset = ahci_softreset,
158 .hardreset = ahci_hardreset,
159 .postreset = ahci_postreset,
160 .pmp_softreset = ahci_softreset,
161 .error_handler = ahci_error_handler,
162 .post_internal_cmd = ahci_post_internal_cmd,
163 .dev_config = ahci_dev_config,
164
165 .scr_read = ahci_scr_read,
166 .scr_write = ahci_scr_write,
167 .pmp_attach = ahci_pmp_attach,
168 .pmp_detach = ahci_pmp_detach,
169
170 .set_lpm = ahci_set_lpm,
171 .em_show = ahci_led_show,
172 .em_store = ahci_led_store,
173 .sw_activity_show = ahci_activity_show,
174 .sw_activity_store = ahci_activity_store,
175 .transmit_led_message = ahci_transmit_led_message,
176 #ifdef CONFIG_PM
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
179 #endif
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
182 };
183 EXPORT_SYMBOL_GPL(ahci_ops);
184
185 struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
188 };
189 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
190
191 static bool ahci_em_messages __read_mostly = true;
192 EXPORT_SYMBOL_GPL(ahci_em_messages);
193 module_param(ahci_em_messages, bool, 0444);
194 /* add other LED protocol types when they become supported */
195 MODULE_PARM_DESC(ahci_em_messages,
196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
197
198 /* device sleep idle timeout in ms */
199 static int devslp_idle_timeout __read_mostly = 1000;
200 module_param(devslp_idle_timeout, int, 0644);
201 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
202
203 static void ahci_enable_ahci(void __iomem *mmio)
204 {
205 int i;
206 u32 tmp;
207
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
211 return;
212
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
215 */
216 for (i = 0; i < 5; i++) {
217 tmp |= HOST_AHCI_EN;
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
221 return;
222 msleep(10);
223 }
224
225 WARN_ON(1);
226 }
227
228 static ssize_t ahci_show_host_caps(struct device *dev,
229 struct device_attribute *attr, char *buf)
230 {
231 struct Scsi_Host *shost = class_to_shost(dev);
232 struct ata_port *ap = ata_shost_to_port(shost);
233 struct ahci_host_priv *hpriv = ap->host->private_data;
234
235 return sprintf(buf, "%x\n", hpriv->cap);
236 }
237
238 static ssize_t ahci_show_host_cap2(struct device *dev,
239 struct device_attribute *attr, char *buf)
240 {
241 struct Scsi_Host *shost = class_to_shost(dev);
242 struct ata_port *ap = ata_shost_to_port(shost);
243 struct ahci_host_priv *hpriv = ap->host->private_data;
244
245 return sprintf(buf, "%x\n", hpriv->cap2);
246 }
247
248 static ssize_t ahci_show_host_version(struct device *dev,
249 struct device_attribute *attr, char *buf)
250 {
251 struct Scsi_Host *shost = class_to_shost(dev);
252 struct ata_port *ap = ata_shost_to_port(shost);
253 struct ahci_host_priv *hpriv = ap->host->private_data;
254 void __iomem *mmio = hpriv->mmio;
255
256 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
257 }
258
259 static ssize_t ahci_show_port_cmd(struct device *dev,
260 struct device_attribute *attr, char *buf)
261 {
262 struct Scsi_Host *shost = class_to_shost(dev);
263 struct ata_port *ap = ata_shost_to_port(shost);
264 void __iomem *port_mmio = ahci_port_base(ap);
265
266 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
267 }
268
269 static ssize_t ahci_read_em_buffer(struct device *dev,
270 struct device_attribute *attr, char *buf)
271 {
272 struct Scsi_Host *shost = class_to_shost(dev);
273 struct ata_port *ap = ata_shost_to_port(shost);
274 struct ahci_host_priv *hpriv = ap->host->private_data;
275 void __iomem *mmio = hpriv->mmio;
276 void __iomem *em_mmio = mmio + hpriv->em_loc;
277 u32 em_ctl, msg;
278 unsigned long flags;
279 size_t count;
280 int i;
281
282 spin_lock_irqsave(ap->lock, flags);
283
284 em_ctl = readl(mmio + HOST_EM_CTL);
285 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
286 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
287 spin_unlock_irqrestore(ap->lock, flags);
288 return -EINVAL;
289 }
290
291 if (!(em_ctl & EM_CTL_MR)) {
292 spin_unlock_irqrestore(ap->lock, flags);
293 return -EAGAIN;
294 }
295
296 if (!(em_ctl & EM_CTL_SMB))
297 em_mmio += hpriv->em_buf_sz;
298
299 count = hpriv->em_buf_sz;
300
301 /* the count should not be larger than PAGE_SIZE */
302 if (count > PAGE_SIZE) {
303 if (printk_ratelimit())
304 ata_port_warn(ap,
305 "EM read buffer size too large: "
306 "buffer size %u, page size %lu\n",
307 hpriv->em_buf_sz, PAGE_SIZE);
308 count = PAGE_SIZE;
309 }
310
311 for (i = 0; i < count; i += 4) {
312 msg = readl(em_mmio + i);
313 buf[i] = msg & 0xff;
314 buf[i + 1] = (msg >> 8) & 0xff;
315 buf[i + 2] = (msg >> 16) & 0xff;
316 buf[i + 3] = (msg >> 24) & 0xff;
317 }
318
319 spin_unlock_irqrestore(ap->lock, flags);
320
321 return i;
322 }
323
324 static ssize_t ahci_store_em_buffer(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t size)
327 {
328 struct Scsi_Host *shost = class_to_shost(dev);
329 struct ata_port *ap = ata_shost_to_port(shost);
330 struct ahci_host_priv *hpriv = ap->host->private_data;
331 void __iomem *mmio = hpriv->mmio;
332 void __iomem *em_mmio = mmio + hpriv->em_loc;
333 const unsigned char *msg_buf = buf;
334 u32 em_ctl, msg;
335 unsigned long flags;
336 int i;
337
338 /* check size validity */
339 if (!(ap->flags & ATA_FLAG_EM) ||
340 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
341 size % 4 || size > hpriv->em_buf_sz)
342 return -EINVAL;
343
344 spin_lock_irqsave(ap->lock, flags);
345
346 em_ctl = readl(mmio + HOST_EM_CTL);
347 if (em_ctl & EM_CTL_TM) {
348 spin_unlock_irqrestore(ap->lock, flags);
349 return -EBUSY;
350 }
351
352 for (i = 0; i < size; i += 4) {
353 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
354 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
355 writel(msg, em_mmio + i);
356 }
357
358 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
359
360 spin_unlock_irqrestore(ap->lock, flags);
361
362 return size;
363 }
364
365 static ssize_t ahci_show_em_supported(struct device *dev,
366 struct device_attribute *attr, char *buf)
367 {
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 u32 em_ctl;
373
374 em_ctl = readl(mmio + HOST_EM_CTL);
375
376 return sprintf(buf, "%s%s%s%s\n",
377 em_ctl & EM_CTL_LED ? "led " : "",
378 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
379 em_ctl & EM_CTL_SES ? "ses-2 " : "",
380 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
381 }
382
383 /**
384 * ahci_save_initial_config - Save and fixup initial config values
385 * @dev: target AHCI device
386 * @hpriv: host private area to store config values
387 *
388 * Some registers containing configuration info might be setup by
389 * BIOS and might be cleared on reset. This function saves the
390 * initial values of those registers into @hpriv such that they
391 * can be restored after controller reset.
392 *
393 * If inconsistent, config values are fixed up by this function.
394 *
395 * If it is not set already this function sets hpriv->start_engine to
396 * ahci_start_engine.
397 *
398 * LOCKING:
399 * None.
400 */
401 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
402 {
403 void __iomem *mmio = hpriv->mmio;
404 u32 cap, cap2, vers, port_map;
405 int i;
406
407 /* make sure AHCI mode is enabled before accessing CAP */
408 ahci_enable_ahci(mmio);
409
410 /* Values prefixed with saved_ are written back to host after
411 * reset. Values without are used for driver operation.
412 */
413 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
414 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
415
416 /* CAP2 register is only defined for AHCI 1.2 and later */
417 vers = readl(mmio + HOST_VERSION);
418 if ((vers >> 16) > 1 ||
419 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
420 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
421 else
422 hpriv->saved_cap2 = cap2 = 0;
423
424 /* some chips have errata preventing 64bit use */
425 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
426 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
427 cap &= ~HOST_CAP_64;
428 }
429
430 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
431 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
432 cap &= ~HOST_CAP_NCQ;
433 }
434
435 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
436 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
437 cap |= HOST_CAP_NCQ;
438 }
439
440 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
441 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
442 cap &= ~HOST_CAP_PMP;
443 }
444
445 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
446 dev_info(dev,
447 "controller can't do SNTF, turning off CAP_SNTF\n");
448 cap &= ~HOST_CAP_SNTF;
449 }
450
451 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
452 dev_info(dev,
453 "controller can't do DEVSLP, turning off\n");
454 cap2 &= ~HOST_CAP2_SDS;
455 cap2 &= ~HOST_CAP2_SADM;
456 }
457
458 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
459 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
460 cap |= HOST_CAP_FBS;
461 }
462
463 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
464 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
465 cap &= ~HOST_CAP_FBS;
466 }
467
468 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
469 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
470 port_map, hpriv->force_port_map);
471 port_map = hpriv->force_port_map;
472 }
473
474 if (hpriv->mask_port_map) {
475 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
476 port_map,
477 port_map & hpriv->mask_port_map);
478 port_map &= hpriv->mask_port_map;
479 }
480
481 /* cross check port_map and cap.n_ports */
482 if (port_map) {
483 int map_ports = 0;
484
485 for (i = 0; i < AHCI_MAX_PORTS; i++)
486 if (port_map & (1 << i))
487 map_ports++;
488
489 /* If PI has more ports than n_ports, whine, clear
490 * port_map and let it be generated from n_ports.
491 */
492 if (map_ports > ahci_nr_ports(cap)) {
493 dev_warn(dev,
494 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
495 port_map, ahci_nr_ports(cap));
496 port_map = 0;
497 }
498 }
499
500 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
501 if (!port_map && vers < 0x10300) {
502 port_map = (1 << ahci_nr_ports(cap)) - 1;
503 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
504
505 /* write the fixed up value to the PI register */
506 hpriv->saved_port_map = port_map;
507 }
508
509 /* record values to use during operation */
510 hpriv->cap = cap;
511 hpriv->cap2 = cap2;
512 hpriv->port_map = port_map;
513
514 if (!hpriv->start_engine)
515 hpriv->start_engine = ahci_start_engine;
516
517 if (!hpriv->irq_handler)
518 hpriv->irq_handler = ahci_single_level_irq_intr;
519 }
520 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
521
522 /**
523 * ahci_restore_initial_config - Restore initial config
524 * @host: target ATA host
525 *
526 * Restore initial config stored by ahci_save_initial_config().
527 *
528 * LOCKING:
529 * None.
530 */
531 static void ahci_restore_initial_config(struct ata_host *host)
532 {
533 struct ahci_host_priv *hpriv = host->private_data;
534 void __iomem *mmio = hpriv->mmio;
535
536 writel(hpriv->saved_cap, mmio + HOST_CAP);
537 if (hpriv->saved_cap2)
538 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
539 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
540 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
541 }
542
543 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
544 {
545 static const int offset[] = {
546 [SCR_STATUS] = PORT_SCR_STAT,
547 [SCR_CONTROL] = PORT_SCR_CTL,
548 [SCR_ERROR] = PORT_SCR_ERR,
549 [SCR_ACTIVE] = PORT_SCR_ACT,
550 [SCR_NOTIFICATION] = PORT_SCR_NTF,
551 };
552 struct ahci_host_priv *hpriv = ap->host->private_data;
553
554 if (sc_reg < ARRAY_SIZE(offset) &&
555 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
556 return offset[sc_reg];
557 return 0;
558 }
559
560 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
561 {
562 void __iomem *port_mmio = ahci_port_base(link->ap);
563 int offset = ahci_scr_offset(link->ap, sc_reg);
564
565 if (offset) {
566 *val = readl(port_mmio + offset);
567 return 0;
568 }
569 return -EINVAL;
570 }
571
572 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
573 {
574 void __iomem *port_mmio = ahci_port_base(link->ap);
575 int offset = ahci_scr_offset(link->ap, sc_reg);
576
577 if (offset) {
578 writel(val, port_mmio + offset);
579 return 0;
580 }
581 return -EINVAL;
582 }
583
584 void ahci_start_engine(struct ata_port *ap)
585 {
586 void __iomem *port_mmio = ahci_port_base(ap);
587 u32 tmp;
588
589 /* start DMA */
590 tmp = readl(port_mmio + PORT_CMD);
591 tmp |= PORT_CMD_START;
592 writel(tmp, port_mmio + PORT_CMD);
593 readl(port_mmio + PORT_CMD); /* flush */
594 }
595 EXPORT_SYMBOL_GPL(ahci_start_engine);
596
597 int ahci_stop_engine(struct ata_port *ap)
598 {
599 void __iomem *port_mmio = ahci_port_base(ap);
600 struct ahci_host_priv *hpriv = ap->host->private_data;
601 u32 tmp;
602
603 /*
604 * On some controllers, stopping a port's DMA engine while the port
605 * is in ALPM state (partial or slumber) results in failures on
606 * subsequent DMA engine starts. For those controllers, put the
607 * port back in active state before stopping its DMA engine.
608 */
609 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
610 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
611 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
612 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
613 return -EIO;
614 }
615
616 tmp = readl(port_mmio + PORT_CMD);
617
618 /* check if the HBA is idle */
619 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
620 return 0;
621
622 /* setting HBA to idle */
623 tmp &= ~PORT_CMD_START;
624 writel(tmp, port_mmio + PORT_CMD);
625
626 /* wait for engine to stop. This could be as long as 500 msec */
627 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
628 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
629 if (tmp & PORT_CMD_LIST_ON)
630 return -EIO;
631
632 return 0;
633 }
634 EXPORT_SYMBOL_GPL(ahci_stop_engine);
635
636 void ahci_start_fis_rx(struct ata_port *ap)
637 {
638 void __iomem *port_mmio = ahci_port_base(ap);
639 struct ahci_host_priv *hpriv = ap->host->private_data;
640 struct ahci_port_priv *pp = ap->private_data;
641 u32 tmp;
642
643 /* set FIS registers */
644 if (hpriv->cap & HOST_CAP_64)
645 writel((pp->cmd_slot_dma >> 16) >> 16,
646 port_mmio + PORT_LST_ADDR_HI);
647 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
648
649 if (hpriv->cap & HOST_CAP_64)
650 writel((pp->rx_fis_dma >> 16) >> 16,
651 port_mmio + PORT_FIS_ADDR_HI);
652 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
653
654 /* enable FIS reception */
655 tmp = readl(port_mmio + PORT_CMD);
656 tmp |= PORT_CMD_FIS_RX;
657 writel(tmp, port_mmio + PORT_CMD);
658
659 /* flush */
660 readl(port_mmio + PORT_CMD);
661 }
662 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
663
664 static int ahci_stop_fis_rx(struct ata_port *ap)
665 {
666 void __iomem *port_mmio = ahci_port_base(ap);
667 u32 tmp;
668
669 /* disable FIS reception */
670 tmp = readl(port_mmio + PORT_CMD);
671 tmp &= ~PORT_CMD_FIS_RX;
672 writel(tmp, port_mmio + PORT_CMD);
673
674 /* wait for completion, spec says 500ms, give it 1000 */
675 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
676 PORT_CMD_FIS_ON, 10, 1000);
677 if (tmp & PORT_CMD_FIS_ON)
678 return -EBUSY;
679
680 return 0;
681 }
682
683 static void ahci_power_up(struct ata_port *ap)
684 {
685 struct ahci_host_priv *hpriv = ap->host->private_data;
686 void __iomem *port_mmio = ahci_port_base(ap);
687 u32 cmd;
688
689 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
690
691 /* spin up device */
692 if (hpriv->cap & HOST_CAP_SSS) {
693 cmd |= PORT_CMD_SPIN_UP;
694 writel(cmd, port_mmio + PORT_CMD);
695 }
696
697 /* wake up link */
698 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
699 }
700
701 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
702 unsigned int hints)
703 {
704 struct ata_port *ap = link->ap;
705 struct ahci_host_priv *hpriv = ap->host->private_data;
706 struct ahci_port_priv *pp = ap->private_data;
707 void __iomem *port_mmio = ahci_port_base(ap);
708
709 if (policy != ATA_LPM_MAX_POWER) {
710 /* wakeup flag only applies to the max power policy */
711 hints &= ~ATA_LPM_WAKE_ONLY;
712
713 /*
714 * Disable interrupts on Phy Ready. This keeps us from
715 * getting woken up due to spurious phy ready
716 * interrupts.
717 */
718 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
719 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
720
721 sata_link_scr_lpm(link, policy, false);
722 }
723
724 if (hpriv->cap & HOST_CAP_ALPM) {
725 u32 cmd = readl(port_mmio + PORT_CMD);
726
727 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
728 if (!(hints & ATA_LPM_WAKE_ONLY))
729 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
730 cmd |= PORT_CMD_ICC_ACTIVE;
731
732 writel(cmd, port_mmio + PORT_CMD);
733 readl(port_mmio + PORT_CMD);
734
735 /* wait 10ms to be sure we've come out of LPM state */
736 ata_msleep(ap, 10);
737
738 if (hints & ATA_LPM_WAKE_ONLY)
739 return 0;
740 } else {
741 cmd |= PORT_CMD_ALPE;
742 if (policy == ATA_LPM_MIN_POWER)
743 cmd |= PORT_CMD_ASP;
744
745 /* write out new cmd value */
746 writel(cmd, port_mmio + PORT_CMD);
747 }
748 }
749
750 /* set aggressive device sleep */
751 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
752 (hpriv->cap2 & HOST_CAP2_SADM) &&
753 (link->device->flags & ATA_DFLAG_DEVSLP)) {
754 if (policy == ATA_LPM_MIN_POWER)
755 ahci_set_aggressive_devslp(ap, true);
756 else
757 ahci_set_aggressive_devslp(ap, false);
758 }
759
760 if (policy == ATA_LPM_MAX_POWER) {
761 sata_link_scr_lpm(link, policy, false);
762
763 /* turn PHYRDY IRQ back on */
764 pp->intr_mask |= PORT_IRQ_PHYRDY;
765 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
766 }
767
768 return 0;
769 }
770
771 #ifdef CONFIG_PM
772 static void ahci_power_down(struct ata_port *ap)
773 {
774 struct ahci_host_priv *hpriv = ap->host->private_data;
775 void __iomem *port_mmio = ahci_port_base(ap);
776 u32 cmd, scontrol;
777
778 if (!(hpriv->cap & HOST_CAP_SSS))
779 return;
780
781 /* put device into listen mode, first set PxSCTL.DET to 0 */
782 scontrol = readl(port_mmio + PORT_SCR_CTL);
783 scontrol &= ~0xf;
784 writel(scontrol, port_mmio + PORT_SCR_CTL);
785
786 /* then set PxCMD.SUD to 0 */
787 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
788 cmd &= ~PORT_CMD_SPIN_UP;
789 writel(cmd, port_mmio + PORT_CMD);
790 }
791 #endif
792
793 static void ahci_start_port(struct ata_port *ap)
794 {
795 struct ahci_host_priv *hpriv = ap->host->private_data;
796 struct ahci_port_priv *pp = ap->private_data;
797 struct ata_link *link;
798 struct ahci_em_priv *emp;
799 ssize_t rc;
800 int i;
801
802 /* enable FIS reception */
803 ahci_start_fis_rx(ap);
804
805 /* enable DMA */
806 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
807 hpriv->start_engine(ap);
808
809 /* turn on LEDs */
810 if (ap->flags & ATA_FLAG_EM) {
811 ata_for_each_link(link, ap, EDGE) {
812 emp = &pp->em_priv[link->pmp];
813
814 /* EM Transmit bit maybe busy during init */
815 for (i = 0; i < EM_MAX_RETRY; i++) {
816 rc = ap->ops->transmit_led_message(ap,
817 emp->led_state,
818 4);
819 /*
820 * If busy, give a breather but do not
821 * release EH ownership by using msleep()
822 * instead of ata_msleep(). EM Transmit
823 * bit is busy for the whole host and
824 * releasing ownership will cause other
825 * ports to fail the same way.
826 */
827 if (rc == -EBUSY)
828 msleep(1);
829 else
830 break;
831 }
832 }
833 }
834
835 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
836 ata_for_each_link(link, ap, EDGE)
837 ahci_init_sw_activity(link);
838
839 }
840
841 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
842 {
843 int rc;
844
845 /* disable DMA */
846 rc = ahci_stop_engine(ap);
847 if (rc) {
848 *emsg = "failed to stop engine";
849 return rc;
850 }
851
852 /* disable FIS reception */
853 rc = ahci_stop_fis_rx(ap);
854 if (rc) {
855 *emsg = "failed stop FIS RX";
856 return rc;
857 }
858
859 return 0;
860 }
861
862 int ahci_reset_controller(struct ata_host *host)
863 {
864 struct ahci_host_priv *hpriv = host->private_data;
865 void __iomem *mmio = hpriv->mmio;
866 u32 tmp;
867
868 /* we must be in AHCI mode, before using anything
869 * AHCI-specific, such as HOST_RESET.
870 */
871 ahci_enable_ahci(mmio);
872
873 /* global controller reset */
874 if (!ahci_skip_host_reset) {
875 tmp = readl(mmio + HOST_CTL);
876 if ((tmp & HOST_RESET) == 0) {
877 writel(tmp | HOST_RESET, mmio + HOST_CTL);
878 readl(mmio + HOST_CTL); /* flush */
879 }
880
881 /*
882 * to perform host reset, OS should set HOST_RESET
883 * and poll until this bit is read to be "0".
884 * reset must complete within 1 second, or
885 * the hardware should be considered fried.
886 */
887 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
888 HOST_RESET, 10, 1000);
889
890 if (tmp & HOST_RESET) {
891 dev_err(host->dev, "controller reset failed (0x%x)\n",
892 tmp);
893 return -EIO;
894 }
895
896 /* turn on AHCI mode */
897 ahci_enable_ahci(mmio);
898
899 /* Some registers might be cleared on reset. Restore
900 * initial values.
901 */
902 ahci_restore_initial_config(host);
903 } else
904 dev_info(host->dev, "skipping global host reset\n");
905
906 return 0;
907 }
908 EXPORT_SYMBOL_GPL(ahci_reset_controller);
909
910 static void ahci_sw_activity(struct ata_link *link)
911 {
912 struct ata_port *ap = link->ap;
913 struct ahci_port_priv *pp = ap->private_data;
914 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
915
916 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
917 return;
918
919 emp->activity++;
920 if (!timer_pending(&emp->timer))
921 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
922 }
923
924 static void ahci_sw_activity_blink(unsigned long arg)
925 {
926 struct ata_link *link = (struct ata_link *)arg;
927 struct ata_port *ap = link->ap;
928 struct ahci_port_priv *pp = ap->private_data;
929 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
930 unsigned long led_message = emp->led_state;
931 u32 activity_led_state;
932 unsigned long flags;
933
934 led_message &= EM_MSG_LED_VALUE;
935 led_message |= ap->port_no | (link->pmp << 8);
936
937 /* check to see if we've had activity. If so,
938 * toggle state of LED and reset timer. If not,
939 * turn LED to desired idle state.
940 */
941 spin_lock_irqsave(ap->lock, flags);
942 if (emp->saved_activity != emp->activity) {
943 emp->saved_activity = emp->activity;
944 /* get the current LED state */
945 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
946
947 if (activity_led_state)
948 activity_led_state = 0;
949 else
950 activity_led_state = 1;
951
952 /* clear old state */
953 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
954
955 /* toggle state */
956 led_message |= (activity_led_state << 16);
957 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
958 } else {
959 /* switch to idle */
960 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
961 if (emp->blink_policy == BLINK_OFF)
962 led_message |= (1 << 16);
963 }
964 spin_unlock_irqrestore(ap->lock, flags);
965 ap->ops->transmit_led_message(ap, led_message, 4);
966 }
967
968 static void ahci_init_sw_activity(struct ata_link *link)
969 {
970 struct ata_port *ap = link->ap;
971 struct ahci_port_priv *pp = ap->private_data;
972 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
973
974 /* init activity stats, setup timer */
975 emp->saved_activity = emp->activity = 0;
976 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
977
978 /* check our blink policy and set flag for link if it's enabled */
979 if (emp->blink_policy)
980 link->flags |= ATA_LFLAG_SW_ACTIVITY;
981 }
982
983 int ahci_reset_em(struct ata_host *host)
984 {
985 struct ahci_host_priv *hpriv = host->private_data;
986 void __iomem *mmio = hpriv->mmio;
987 u32 em_ctl;
988
989 em_ctl = readl(mmio + HOST_EM_CTL);
990 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
991 return -EINVAL;
992
993 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
994 return 0;
995 }
996 EXPORT_SYMBOL_GPL(ahci_reset_em);
997
998 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
999 ssize_t size)
1000 {
1001 struct ahci_host_priv *hpriv = ap->host->private_data;
1002 struct ahci_port_priv *pp = ap->private_data;
1003 void __iomem *mmio = hpriv->mmio;
1004 u32 em_ctl;
1005 u32 message[] = {0, 0};
1006 unsigned long flags;
1007 int pmp;
1008 struct ahci_em_priv *emp;
1009
1010 /* get the slot number from the message */
1011 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1012 if (pmp < EM_MAX_SLOTS)
1013 emp = &pp->em_priv[pmp];
1014 else
1015 return -EINVAL;
1016
1017 spin_lock_irqsave(ap->lock, flags);
1018
1019 /*
1020 * if we are still busy transmitting a previous message,
1021 * do not allow
1022 */
1023 em_ctl = readl(mmio + HOST_EM_CTL);
1024 if (em_ctl & EM_CTL_TM) {
1025 spin_unlock_irqrestore(ap->lock, flags);
1026 return -EBUSY;
1027 }
1028
1029 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1030 /*
1031 * create message header - this is all zero except for
1032 * the message size, which is 4 bytes.
1033 */
1034 message[0] |= (4 << 8);
1035
1036 /* ignore 0:4 of byte zero, fill in port info yourself */
1037 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1038
1039 /* write message to EM_LOC */
1040 writel(message[0], mmio + hpriv->em_loc);
1041 writel(message[1], mmio + hpriv->em_loc+4);
1042
1043 /*
1044 * tell hardware to transmit the message
1045 */
1046 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1047 }
1048
1049 /* save off new led state for port/slot */
1050 emp->led_state = state;
1051
1052 spin_unlock_irqrestore(ap->lock, flags);
1053 return size;
1054 }
1055
1056 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1057 {
1058 struct ahci_port_priv *pp = ap->private_data;
1059 struct ata_link *link;
1060 struct ahci_em_priv *emp;
1061 int rc = 0;
1062
1063 ata_for_each_link(link, ap, EDGE) {
1064 emp = &pp->em_priv[link->pmp];
1065 rc += sprintf(buf, "%lx\n", emp->led_state);
1066 }
1067 return rc;
1068 }
1069
1070 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1071 size_t size)
1072 {
1073 unsigned int state;
1074 int pmp;
1075 struct ahci_port_priv *pp = ap->private_data;
1076 struct ahci_em_priv *emp;
1077
1078 if (kstrtouint(buf, 0, &state) < 0)
1079 return -EINVAL;
1080
1081 /* get the slot number from the message */
1082 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1083 if (pmp < EM_MAX_SLOTS)
1084 emp = &pp->em_priv[pmp];
1085 else
1086 return -EINVAL;
1087
1088 /* mask off the activity bits if we are in sw_activity
1089 * mode, user should turn off sw_activity before setting
1090 * activity led through em_message
1091 */
1092 if (emp->blink_policy)
1093 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1094
1095 return ap->ops->transmit_led_message(ap, state, size);
1096 }
1097
1098 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1099 {
1100 struct ata_link *link = dev->link;
1101 struct ata_port *ap = link->ap;
1102 struct ahci_port_priv *pp = ap->private_data;
1103 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1104 u32 port_led_state = emp->led_state;
1105
1106 /* save the desired Activity LED behavior */
1107 if (val == OFF) {
1108 /* clear LFLAG */
1109 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1110
1111 /* set the LED to OFF */
1112 port_led_state &= EM_MSG_LED_VALUE_OFF;
1113 port_led_state |= (ap->port_no | (link->pmp << 8));
1114 ap->ops->transmit_led_message(ap, port_led_state, 4);
1115 } else {
1116 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1117 if (val == BLINK_OFF) {
1118 /* set LED to ON for idle */
1119 port_led_state &= EM_MSG_LED_VALUE_OFF;
1120 port_led_state |= (ap->port_no | (link->pmp << 8));
1121 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1122 ap->ops->transmit_led_message(ap, port_led_state, 4);
1123 }
1124 }
1125 emp->blink_policy = val;
1126 return 0;
1127 }
1128
1129 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1130 {
1131 struct ata_link *link = dev->link;
1132 struct ata_port *ap = link->ap;
1133 struct ahci_port_priv *pp = ap->private_data;
1134 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1135
1136 /* display the saved value of activity behavior for this
1137 * disk.
1138 */
1139 return sprintf(buf, "%d\n", emp->blink_policy);
1140 }
1141
1142 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1143 int port_no, void __iomem *mmio,
1144 void __iomem *port_mmio)
1145 {
1146 struct ahci_host_priv *hpriv = ap->host->private_data;
1147 const char *emsg = NULL;
1148 int rc;
1149 u32 tmp;
1150
1151 /* make sure port is not active */
1152 rc = ahci_deinit_port(ap, &emsg);
1153 if (rc)
1154 dev_warn(dev, "%s (%d)\n", emsg, rc);
1155
1156 /* clear SError */
1157 tmp = readl(port_mmio + PORT_SCR_ERR);
1158 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1159 writel(tmp, port_mmio + PORT_SCR_ERR);
1160
1161 /* clear port IRQ */
1162 tmp = readl(port_mmio + PORT_IRQ_STAT);
1163 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1164 if (tmp)
1165 writel(tmp, port_mmio + PORT_IRQ_STAT);
1166
1167 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1168
1169 /* mark esata ports */
1170 tmp = readl(port_mmio + PORT_CMD);
1171 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1172 ap->pflags |= ATA_PFLAG_EXTERNAL;
1173 }
1174
1175 void ahci_init_controller(struct ata_host *host)
1176 {
1177 struct ahci_host_priv *hpriv = host->private_data;
1178 void __iomem *mmio = hpriv->mmio;
1179 int i;
1180 void __iomem *port_mmio;
1181 u32 tmp;
1182
1183 for (i = 0; i < host->n_ports; i++) {
1184 struct ata_port *ap = host->ports[i];
1185
1186 port_mmio = ahci_port_base(ap);
1187 if (ata_port_is_dummy(ap))
1188 continue;
1189
1190 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1191 }
1192
1193 tmp = readl(mmio + HOST_CTL);
1194 VPRINTK("HOST_CTL 0x%x\n", tmp);
1195 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1196 tmp = readl(mmio + HOST_CTL);
1197 VPRINTK("HOST_CTL 0x%x\n", tmp);
1198 }
1199 EXPORT_SYMBOL_GPL(ahci_init_controller);
1200
1201 static void ahci_dev_config(struct ata_device *dev)
1202 {
1203 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1204
1205 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1206 dev->max_sectors = 255;
1207 ata_dev_info(dev,
1208 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1209 }
1210 }
1211
1212 unsigned int ahci_dev_classify(struct ata_port *ap)
1213 {
1214 void __iomem *port_mmio = ahci_port_base(ap);
1215 struct ata_taskfile tf;
1216 u32 tmp;
1217
1218 tmp = readl(port_mmio + PORT_SIG);
1219 tf.lbah = (tmp >> 24) & 0xff;
1220 tf.lbam = (tmp >> 16) & 0xff;
1221 tf.lbal = (tmp >> 8) & 0xff;
1222 tf.nsect = (tmp) & 0xff;
1223
1224 return ata_dev_classify(&tf);
1225 }
1226 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1227
1228 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1229 u32 opts)
1230 {
1231 dma_addr_t cmd_tbl_dma;
1232
1233 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1234
1235 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1236 pp->cmd_slot[tag].status = 0;
1237 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1238 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1239 }
1240 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1241
1242 int ahci_kick_engine(struct ata_port *ap)
1243 {
1244 void __iomem *port_mmio = ahci_port_base(ap);
1245 struct ahci_host_priv *hpriv = ap->host->private_data;
1246 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1247 u32 tmp;
1248 int busy, rc;
1249
1250 /* stop engine */
1251 rc = ahci_stop_engine(ap);
1252 if (rc)
1253 goto out_restart;
1254
1255 /* need to do CLO?
1256 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1257 */
1258 busy = status & (ATA_BUSY | ATA_DRQ);
1259 if (!busy && !sata_pmp_attached(ap)) {
1260 rc = 0;
1261 goto out_restart;
1262 }
1263
1264 if (!(hpriv->cap & HOST_CAP_CLO)) {
1265 rc = -EOPNOTSUPP;
1266 goto out_restart;
1267 }
1268
1269 /* perform CLO */
1270 tmp = readl(port_mmio + PORT_CMD);
1271 tmp |= PORT_CMD_CLO;
1272 writel(tmp, port_mmio + PORT_CMD);
1273
1274 rc = 0;
1275 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1276 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1277 if (tmp & PORT_CMD_CLO)
1278 rc = -EIO;
1279
1280 /* restart engine */
1281 out_restart:
1282 hpriv->start_engine(ap);
1283 return rc;
1284 }
1285 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1286
1287 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1288 struct ata_taskfile *tf, int is_cmd, u16 flags,
1289 unsigned long timeout_msec)
1290 {
1291 const u32 cmd_fis_len = 5; /* five dwords */
1292 struct ahci_port_priv *pp = ap->private_data;
1293 void __iomem *port_mmio = ahci_port_base(ap);
1294 u8 *fis = pp->cmd_tbl;
1295 u32 tmp;
1296
1297 /* prep the command */
1298 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1299 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1300
1301 /* set port value for softreset of Port Multiplier */
1302 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1303 tmp = readl(port_mmio + PORT_FBS);
1304 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1305 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1306 writel(tmp, port_mmio + PORT_FBS);
1307 pp->fbs_last_dev = pmp;
1308 }
1309
1310 /* issue & wait */
1311 writel(1, port_mmio + PORT_CMD_ISSUE);
1312
1313 if (timeout_msec) {
1314 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1315 0x1, 0x1, 1, timeout_msec);
1316 if (tmp & 0x1) {
1317 ahci_kick_engine(ap);
1318 return -EBUSY;
1319 }
1320 } else
1321 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1322
1323 return 0;
1324 }
1325
1326 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1327 int pmp, unsigned long deadline,
1328 int (*check_ready)(struct ata_link *link))
1329 {
1330 struct ata_port *ap = link->ap;
1331 struct ahci_host_priv *hpriv = ap->host->private_data;
1332 struct ahci_port_priv *pp = ap->private_data;
1333 const char *reason = NULL;
1334 unsigned long now, msecs;
1335 struct ata_taskfile tf;
1336 bool fbs_disabled = false;
1337 int rc;
1338
1339 DPRINTK("ENTER\n");
1340
1341 /* prepare for SRST (AHCI-1.1 10.4.1) */
1342 rc = ahci_kick_engine(ap);
1343 if (rc && rc != -EOPNOTSUPP)
1344 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1345
1346 /*
1347 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1348 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1349 * that is attached to port multiplier.
1350 */
1351 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1352 ahci_disable_fbs(ap);
1353 fbs_disabled = true;
1354 }
1355
1356 ata_tf_init(link->device, &tf);
1357
1358 /* issue the first D2H Register FIS */
1359 msecs = 0;
1360 now = jiffies;
1361 if (time_after(deadline, now))
1362 msecs = jiffies_to_msecs(deadline - now);
1363
1364 tf.ctl |= ATA_SRST;
1365 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1366 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1367 rc = -EIO;
1368 reason = "1st FIS failed";
1369 goto fail;
1370 }
1371
1372 /* spec says at least 5us, but be generous and sleep for 1ms */
1373 ata_msleep(ap, 1);
1374
1375 /* issue the second D2H Register FIS */
1376 tf.ctl &= ~ATA_SRST;
1377 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1378
1379 /* wait for link to become ready */
1380 rc = ata_wait_after_reset(link, deadline, check_ready);
1381 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1382 /*
1383 * Workaround for cases where link online status can't
1384 * be trusted. Treat device readiness timeout as link
1385 * offline.
1386 */
1387 ata_link_info(link, "device not ready, treating as offline\n");
1388 *class = ATA_DEV_NONE;
1389 } else if (rc) {
1390 /* link occupied, -ENODEV too is an error */
1391 reason = "device not ready";
1392 goto fail;
1393 } else
1394 *class = ahci_dev_classify(ap);
1395
1396 /* re-enable FBS if disabled before */
1397 if (fbs_disabled)
1398 ahci_enable_fbs(ap);
1399
1400 DPRINTK("EXIT, class=%u\n", *class);
1401 return 0;
1402
1403 fail:
1404 ata_link_err(link, "softreset failed (%s)\n", reason);
1405 return rc;
1406 }
1407
1408 int ahci_check_ready(struct ata_link *link)
1409 {
1410 void __iomem *port_mmio = ahci_port_base(link->ap);
1411 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1412
1413 return ata_check_ready(status);
1414 }
1415 EXPORT_SYMBOL_GPL(ahci_check_ready);
1416
1417 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1418 unsigned long deadline)
1419 {
1420 int pmp = sata_srst_pmp(link);
1421
1422 DPRINTK("ENTER\n");
1423
1424 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1425 }
1426 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1427
1428 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1429 {
1430 void __iomem *port_mmio = ahci_port_base(link->ap);
1431 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1432 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1433
1434 /*
1435 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1436 * which can save timeout delay.
1437 */
1438 if (irq_status & PORT_IRQ_BAD_PMP)
1439 return -EIO;
1440
1441 return ata_check_ready(status);
1442 }
1443
1444 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1445 unsigned long deadline)
1446 {
1447 struct ata_port *ap = link->ap;
1448 void __iomem *port_mmio = ahci_port_base(ap);
1449 int pmp = sata_srst_pmp(link);
1450 int rc;
1451 u32 irq_sts;
1452
1453 DPRINTK("ENTER\n");
1454
1455 rc = ahci_do_softreset(link, class, pmp, deadline,
1456 ahci_bad_pmp_check_ready);
1457
1458 /*
1459 * Soft reset fails with IPMS set when PMP is enabled but
1460 * SATA HDD/ODD is connected to SATA port, do soft reset
1461 * again to port 0.
1462 */
1463 if (rc == -EIO) {
1464 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1465 if (irq_sts & PORT_IRQ_BAD_PMP) {
1466 ata_link_warn(link,
1467 "applying PMP SRST workaround "
1468 "and retrying\n");
1469 rc = ahci_do_softreset(link, class, 0, deadline,
1470 ahci_check_ready);
1471 }
1472 }
1473
1474 return rc;
1475 }
1476
1477 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1478 unsigned long deadline)
1479 {
1480 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1481 struct ata_port *ap = link->ap;
1482 struct ahci_port_priv *pp = ap->private_data;
1483 struct ahci_host_priv *hpriv = ap->host->private_data;
1484 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1485 struct ata_taskfile tf;
1486 bool online;
1487 int rc;
1488
1489 DPRINTK("ENTER\n");
1490
1491 ahci_stop_engine(ap);
1492
1493 /* clear D2H reception area to properly wait for D2H FIS */
1494 ata_tf_init(link->device, &tf);
1495 tf.command = ATA_BUSY;
1496 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1497
1498 rc = sata_link_hardreset(link, timing, deadline, &online,
1499 ahci_check_ready);
1500
1501 hpriv->start_engine(ap);
1502
1503 if (online)
1504 *class = ahci_dev_classify(ap);
1505
1506 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1507 return rc;
1508 }
1509
1510 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1511 {
1512 struct ata_port *ap = link->ap;
1513 void __iomem *port_mmio = ahci_port_base(ap);
1514 u32 new_tmp, tmp;
1515
1516 ata_std_postreset(link, class);
1517
1518 /* Make sure port's ATAPI bit is set appropriately */
1519 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1520 if (*class == ATA_DEV_ATAPI)
1521 new_tmp |= PORT_CMD_ATAPI;
1522 else
1523 new_tmp &= ~PORT_CMD_ATAPI;
1524 if (new_tmp != tmp) {
1525 writel(new_tmp, port_mmio + PORT_CMD);
1526 readl(port_mmio + PORT_CMD); /* flush */
1527 }
1528 }
1529
1530 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1531 {
1532 struct scatterlist *sg;
1533 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1534 unsigned int si;
1535
1536 VPRINTK("ENTER\n");
1537
1538 /*
1539 * Next, the S/G list.
1540 */
1541 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1542 dma_addr_t addr = sg_dma_address(sg);
1543 u32 sg_len = sg_dma_len(sg);
1544
1545 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1546 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1547 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1548 }
1549
1550 return si;
1551 }
1552
1553 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1554 {
1555 struct ata_port *ap = qc->ap;
1556 struct ahci_port_priv *pp = ap->private_data;
1557
1558 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1559 return ata_std_qc_defer(qc);
1560 else
1561 return sata_pmp_qc_defer_cmd_switch(qc);
1562 }
1563
1564 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1565 {
1566 struct ata_port *ap = qc->ap;
1567 struct ahci_port_priv *pp = ap->private_data;
1568 int is_atapi = ata_is_atapi(qc->tf.protocol);
1569 void *cmd_tbl;
1570 u32 opts;
1571 const u32 cmd_fis_len = 5; /* five dwords */
1572 unsigned int n_elem;
1573
1574 /*
1575 * Fill in command table information. First, the header,
1576 * a SATA Register - Host to Device command FIS.
1577 */
1578 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1579
1580 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1581 if (is_atapi) {
1582 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1583 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1584 }
1585
1586 n_elem = 0;
1587 if (qc->flags & ATA_QCFLAG_DMAMAP)
1588 n_elem = ahci_fill_sg(qc, cmd_tbl);
1589
1590 /*
1591 * Fill in command slot information.
1592 */
1593 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1594 if (qc->tf.flags & ATA_TFLAG_WRITE)
1595 opts |= AHCI_CMD_WRITE;
1596 if (is_atapi)
1597 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1598
1599 ahci_fill_cmd_slot(pp, qc->tag, opts);
1600 }
1601
1602 static void ahci_fbs_dec_intr(struct ata_port *ap)
1603 {
1604 struct ahci_port_priv *pp = ap->private_data;
1605 void __iomem *port_mmio = ahci_port_base(ap);
1606 u32 fbs = readl(port_mmio + PORT_FBS);
1607 int retries = 3;
1608
1609 DPRINTK("ENTER\n");
1610 BUG_ON(!pp->fbs_enabled);
1611
1612 /* time to wait for DEC is not specified by AHCI spec,
1613 * add a retry loop for safety.
1614 */
1615 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1616 fbs = readl(port_mmio + PORT_FBS);
1617 while ((fbs & PORT_FBS_DEC) && retries--) {
1618 udelay(1);
1619 fbs = readl(port_mmio + PORT_FBS);
1620 }
1621
1622 if (fbs & PORT_FBS_DEC)
1623 dev_err(ap->host->dev, "failed to clear device error\n");
1624 }
1625
1626 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1627 {
1628 struct ahci_host_priv *hpriv = ap->host->private_data;
1629 struct ahci_port_priv *pp = ap->private_data;
1630 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1631 struct ata_link *link = NULL;
1632 struct ata_queued_cmd *active_qc;
1633 struct ata_eh_info *active_ehi;
1634 bool fbs_need_dec = false;
1635 u32 serror;
1636
1637 /* determine active link with error */
1638 if (pp->fbs_enabled) {
1639 void __iomem *port_mmio = ahci_port_base(ap);
1640 u32 fbs = readl(port_mmio + PORT_FBS);
1641 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1642
1643 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1644 link = &ap->pmp_link[pmp];
1645 fbs_need_dec = true;
1646 }
1647
1648 } else
1649 ata_for_each_link(link, ap, EDGE)
1650 if (ata_link_active(link))
1651 break;
1652
1653 if (!link)
1654 link = &ap->link;
1655
1656 active_qc = ata_qc_from_tag(ap, link->active_tag);
1657 active_ehi = &link->eh_info;
1658
1659 /* record irq stat */
1660 ata_ehi_clear_desc(host_ehi);
1661 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1662
1663 /* AHCI needs SError cleared; otherwise, it might lock up */
1664 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1665 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1666 host_ehi->serror |= serror;
1667
1668 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1669 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1670 irq_stat &= ~PORT_IRQ_IF_ERR;
1671
1672 if (irq_stat & PORT_IRQ_TF_ERR) {
1673 /* If qc is active, charge it; otherwise, the active
1674 * link. There's no active qc on NCQ errors. It will
1675 * be determined by EH by reading log page 10h.
1676 */
1677 if (active_qc)
1678 active_qc->err_mask |= AC_ERR_DEV;
1679 else
1680 active_ehi->err_mask |= AC_ERR_DEV;
1681
1682 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1683 host_ehi->serror &= ~SERR_INTERNAL;
1684 }
1685
1686 if (irq_stat & PORT_IRQ_UNK_FIS) {
1687 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1688
1689 active_ehi->err_mask |= AC_ERR_HSM;
1690 active_ehi->action |= ATA_EH_RESET;
1691 ata_ehi_push_desc(active_ehi,
1692 "unknown FIS %08x %08x %08x %08x" ,
1693 unk[0], unk[1], unk[2], unk[3]);
1694 }
1695
1696 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1697 active_ehi->err_mask |= AC_ERR_HSM;
1698 active_ehi->action |= ATA_EH_RESET;
1699 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1700 }
1701
1702 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1703 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1704 host_ehi->action |= ATA_EH_RESET;
1705 ata_ehi_push_desc(host_ehi, "host bus error");
1706 }
1707
1708 if (irq_stat & PORT_IRQ_IF_ERR) {
1709 if (fbs_need_dec)
1710 active_ehi->err_mask |= AC_ERR_DEV;
1711 else {
1712 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1713 host_ehi->action |= ATA_EH_RESET;
1714 }
1715
1716 ata_ehi_push_desc(host_ehi, "interface fatal error");
1717 }
1718
1719 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1720 ata_ehi_hotplugged(host_ehi);
1721 ata_ehi_push_desc(host_ehi, "%s",
1722 irq_stat & PORT_IRQ_CONNECT ?
1723 "connection status changed" : "PHY RDY changed");
1724 }
1725
1726 /* okay, let's hand over to EH */
1727
1728 if (irq_stat & PORT_IRQ_FREEZE)
1729 ata_port_freeze(ap);
1730 else if (fbs_need_dec) {
1731 ata_link_abort(link);
1732 ahci_fbs_dec_intr(ap);
1733 } else
1734 ata_port_abort(ap);
1735 }
1736
1737 static void ahci_handle_port_interrupt(struct ata_port *ap,
1738 void __iomem *port_mmio, u32 status)
1739 {
1740 struct ata_eh_info *ehi = &ap->link.eh_info;
1741 struct ahci_port_priv *pp = ap->private_data;
1742 struct ahci_host_priv *hpriv = ap->host->private_data;
1743 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1744 u32 qc_active = 0;
1745 int rc;
1746
1747 /* ignore BAD_PMP while resetting */
1748 if (unlikely(resetting))
1749 status &= ~PORT_IRQ_BAD_PMP;
1750
1751 if (sata_lpm_ignore_phy_events(&ap->link)) {
1752 status &= ~PORT_IRQ_PHYRDY;
1753 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1754 }
1755
1756 if (unlikely(status & PORT_IRQ_ERROR)) {
1757 ahci_error_intr(ap, status);
1758 return;
1759 }
1760
1761 if (status & PORT_IRQ_SDB_FIS) {
1762 /* If SNotification is available, leave notification
1763 * handling to sata_async_notification(). If not,
1764 * emulate it by snooping SDB FIS RX area.
1765 *
1766 * Snooping FIS RX area is probably cheaper than
1767 * poking SNotification but some constrollers which
1768 * implement SNotification, ICH9 for example, don't
1769 * store AN SDB FIS into receive area.
1770 */
1771 if (hpriv->cap & HOST_CAP_SNTF)
1772 sata_async_notification(ap);
1773 else {
1774 /* If the 'N' bit in word 0 of the FIS is set,
1775 * we just received asynchronous notification.
1776 * Tell libata about it.
1777 *
1778 * Lack of SNotification should not appear in
1779 * ahci 1.2, so the workaround is unnecessary
1780 * when FBS is enabled.
1781 */
1782 if (pp->fbs_enabled)
1783 WARN_ON_ONCE(1);
1784 else {
1785 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1786 u32 f0 = le32_to_cpu(f[0]);
1787 if (f0 & (1 << 15))
1788 sata_async_notification(ap);
1789 }
1790 }
1791 }
1792
1793 /* pp->active_link is not reliable once FBS is enabled, both
1794 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1795 * NCQ and non-NCQ commands may be in flight at the same time.
1796 */
1797 if (pp->fbs_enabled) {
1798 if (ap->qc_active) {
1799 qc_active = readl(port_mmio + PORT_SCR_ACT);
1800 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1801 }
1802 } else {
1803 /* pp->active_link is valid iff any command is in flight */
1804 if (ap->qc_active && pp->active_link->sactive)
1805 qc_active = readl(port_mmio + PORT_SCR_ACT);
1806 else
1807 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1808 }
1809
1810
1811 rc = ata_qc_complete_multiple(ap, qc_active);
1812
1813 /* while resetting, invalid completions are expected */
1814 if (unlikely(rc < 0 && !resetting)) {
1815 ehi->err_mask |= AC_ERR_HSM;
1816 ehi->action |= ATA_EH_RESET;
1817 ata_port_freeze(ap);
1818 }
1819 }
1820
1821 static void ahci_port_intr(struct ata_port *ap)
1822 {
1823 void __iomem *port_mmio = ahci_port_base(ap);
1824 u32 status;
1825
1826 status = readl(port_mmio + PORT_IRQ_STAT);
1827 writel(status, port_mmio + PORT_IRQ_STAT);
1828
1829 ahci_handle_port_interrupt(ap, port_mmio, status);
1830 }
1831
1832 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1833 {
1834 struct ata_port *ap = dev_instance;
1835 void __iomem *port_mmio = ahci_port_base(ap);
1836 u32 status;
1837
1838 VPRINTK("ENTER\n");
1839
1840 status = readl(port_mmio + PORT_IRQ_STAT);
1841 writel(status, port_mmio + PORT_IRQ_STAT);
1842
1843 spin_lock(ap->lock);
1844 ahci_handle_port_interrupt(ap, port_mmio, status);
1845 spin_unlock(ap->lock);
1846
1847 VPRINTK("EXIT\n");
1848
1849 return IRQ_HANDLED;
1850 }
1851
1852 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1853 {
1854 unsigned int i, handled = 0;
1855
1856 for (i = 0; i < host->n_ports; i++) {
1857 struct ata_port *ap;
1858
1859 if (!(irq_masked & (1 << i)))
1860 continue;
1861
1862 ap = host->ports[i];
1863 if (ap) {
1864 ahci_port_intr(ap);
1865 VPRINTK("port %u\n", i);
1866 } else {
1867 VPRINTK("port %u (no irq)\n", i);
1868 if (ata_ratelimit())
1869 dev_warn(host->dev,
1870 "interrupt on disabled port %u\n", i);
1871 }
1872
1873 handled = 1;
1874 }
1875
1876 return handled;
1877 }
1878 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1879
1880 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1881 {
1882 struct ata_host *host = dev_instance;
1883 struct ahci_host_priv *hpriv;
1884 unsigned int rc = 0;
1885 void __iomem *mmio;
1886 u32 irq_stat, irq_masked;
1887
1888 VPRINTK("ENTER\n");
1889
1890 hpriv = host->private_data;
1891 mmio = hpriv->mmio;
1892
1893 /* sigh. 0xffffffff is a valid return from h/w */
1894 irq_stat = readl(mmio + HOST_IRQ_STAT);
1895 if (!irq_stat)
1896 return IRQ_NONE;
1897
1898 irq_masked = irq_stat & hpriv->port_map;
1899
1900 spin_lock(&host->lock);
1901
1902 rc = ahci_handle_port_intr(host, irq_masked);
1903
1904 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1905 * it should be cleared after all the port events are cleared;
1906 * otherwise, it will raise a spurious interrupt after each
1907 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1908 * information.
1909 *
1910 * Also, use the unmasked value to clear interrupt as spurious
1911 * pending event on a dummy port might cause screaming IRQ.
1912 */
1913 writel(irq_stat, mmio + HOST_IRQ_STAT);
1914
1915 spin_unlock(&host->lock);
1916
1917 VPRINTK("EXIT\n");
1918
1919 return IRQ_RETVAL(rc);
1920 }
1921
1922 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1923 {
1924 struct ata_port *ap = qc->ap;
1925 void __iomem *port_mmio = ahci_port_base(ap);
1926 struct ahci_port_priv *pp = ap->private_data;
1927
1928 /* Keep track of the currently active link. It will be used
1929 * in completion path to determine whether NCQ phase is in
1930 * progress.
1931 */
1932 pp->active_link = qc->dev->link;
1933
1934 if (qc->tf.protocol == ATA_PROT_NCQ)
1935 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1936
1937 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1938 u32 fbs = readl(port_mmio + PORT_FBS);
1939 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1940 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1941 writel(fbs, port_mmio + PORT_FBS);
1942 pp->fbs_last_dev = qc->dev->link->pmp;
1943 }
1944
1945 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1946
1947 ahci_sw_activity(qc->dev->link);
1948
1949 return 0;
1950 }
1951 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1952
1953 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1954 {
1955 struct ahci_port_priv *pp = qc->ap->private_data;
1956 u8 *rx_fis = pp->rx_fis;
1957
1958 if (pp->fbs_enabled)
1959 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1960
1961 /*
1962 * After a successful execution of an ATA PIO data-in command,
1963 * the device doesn't send D2H Reg FIS to update the TF and
1964 * the host should take TF and E_Status from the preceding PIO
1965 * Setup FIS.
1966 */
1967 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1968 !(qc->flags & ATA_QCFLAG_FAILED)) {
1969 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1970 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1971 } else
1972 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1973
1974 return true;
1975 }
1976
1977 static void ahci_freeze(struct ata_port *ap)
1978 {
1979 void __iomem *port_mmio = ahci_port_base(ap);
1980
1981 /* turn IRQ off */
1982 writel(0, port_mmio + PORT_IRQ_MASK);
1983 }
1984
1985 static void ahci_thaw(struct ata_port *ap)
1986 {
1987 struct ahci_host_priv *hpriv = ap->host->private_data;
1988 void __iomem *mmio = hpriv->mmio;
1989 void __iomem *port_mmio = ahci_port_base(ap);
1990 u32 tmp;
1991 struct ahci_port_priv *pp = ap->private_data;
1992
1993 /* clear IRQ */
1994 tmp = readl(port_mmio + PORT_IRQ_STAT);
1995 writel(tmp, port_mmio + PORT_IRQ_STAT);
1996 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1997
1998 /* turn IRQ back on */
1999 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2000 }
2001
2002 void ahci_error_handler(struct ata_port *ap)
2003 {
2004 struct ahci_host_priv *hpriv = ap->host->private_data;
2005
2006 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2007 /* restart engine */
2008 ahci_stop_engine(ap);
2009 hpriv->start_engine(ap);
2010 }
2011
2012 sata_pmp_error_handler(ap);
2013
2014 if (!ata_dev_enabled(ap->link.device))
2015 ahci_stop_engine(ap);
2016 }
2017 EXPORT_SYMBOL_GPL(ahci_error_handler);
2018
2019 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2020 {
2021 struct ata_port *ap = qc->ap;
2022
2023 /* make DMA engine forget about the failed command */
2024 if (qc->flags & ATA_QCFLAG_FAILED)
2025 ahci_kick_engine(ap);
2026 }
2027
2028 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2029 {
2030 struct ahci_host_priv *hpriv = ap->host->private_data;
2031 void __iomem *port_mmio = ahci_port_base(ap);
2032 struct ata_device *dev = ap->link.device;
2033 u32 devslp, dm, dito, mdat, deto;
2034 int rc;
2035 unsigned int err_mask;
2036
2037 devslp = readl(port_mmio + PORT_DEVSLP);
2038 if (!(devslp & PORT_DEVSLP_DSP)) {
2039 dev_info(ap->host->dev, "port does not support device sleep\n");
2040 return;
2041 }
2042
2043 /* disable device sleep */
2044 if (!sleep) {
2045 if (devslp & PORT_DEVSLP_ADSE) {
2046 writel(devslp & ~PORT_DEVSLP_ADSE,
2047 port_mmio + PORT_DEVSLP);
2048 err_mask = ata_dev_set_feature(dev,
2049 SETFEATURES_SATA_DISABLE,
2050 SATA_DEVSLP);
2051 if (err_mask && err_mask != AC_ERR_DEV)
2052 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2053 }
2054 return;
2055 }
2056
2057 /* device sleep was already enabled */
2058 if (devslp & PORT_DEVSLP_ADSE)
2059 return;
2060
2061 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2062 rc = ahci_stop_engine(ap);
2063 if (rc)
2064 return;
2065
2066 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2067 dito = devslp_idle_timeout / (dm + 1);
2068 if (dito > 0x3ff)
2069 dito = 0x3ff;
2070
2071 /* Use the nominal value 10 ms if the read MDAT is zero,
2072 * the nominal value of DETO is 20 ms.
2073 */
2074 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2075 ATA_LOG_DEVSLP_VALID_MASK) {
2076 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2077 ATA_LOG_DEVSLP_MDAT_MASK;
2078 if (!mdat)
2079 mdat = 10;
2080 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2081 if (!deto)
2082 deto = 20;
2083 } else {
2084 mdat = 10;
2085 deto = 20;
2086 }
2087
2088 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2089 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2090 (deto << PORT_DEVSLP_DETO_OFFSET) |
2091 PORT_DEVSLP_ADSE);
2092 writel(devslp, port_mmio + PORT_DEVSLP);
2093
2094 hpriv->start_engine(ap);
2095
2096 /* enable device sleep feature for the drive */
2097 err_mask = ata_dev_set_feature(dev,
2098 SETFEATURES_SATA_ENABLE,
2099 SATA_DEVSLP);
2100 if (err_mask && err_mask != AC_ERR_DEV)
2101 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2102 }
2103
2104 static void ahci_enable_fbs(struct ata_port *ap)
2105 {
2106 struct ahci_host_priv *hpriv = ap->host->private_data;
2107 struct ahci_port_priv *pp = ap->private_data;
2108 void __iomem *port_mmio = ahci_port_base(ap);
2109 u32 fbs;
2110 int rc;
2111
2112 if (!pp->fbs_supported)
2113 return;
2114
2115 fbs = readl(port_mmio + PORT_FBS);
2116 if (fbs & PORT_FBS_EN) {
2117 pp->fbs_enabled = true;
2118 pp->fbs_last_dev = -1; /* initialization */
2119 return;
2120 }
2121
2122 rc = ahci_stop_engine(ap);
2123 if (rc)
2124 return;
2125
2126 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2127 fbs = readl(port_mmio + PORT_FBS);
2128 if (fbs & PORT_FBS_EN) {
2129 dev_info(ap->host->dev, "FBS is enabled\n");
2130 pp->fbs_enabled = true;
2131 pp->fbs_last_dev = -1; /* initialization */
2132 } else
2133 dev_err(ap->host->dev, "Failed to enable FBS\n");
2134
2135 hpriv->start_engine(ap);
2136 }
2137
2138 static void ahci_disable_fbs(struct ata_port *ap)
2139 {
2140 struct ahci_host_priv *hpriv = ap->host->private_data;
2141 struct ahci_port_priv *pp = ap->private_data;
2142 void __iomem *port_mmio = ahci_port_base(ap);
2143 u32 fbs;
2144 int rc;
2145
2146 if (!pp->fbs_supported)
2147 return;
2148
2149 fbs = readl(port_mmio + PORT_FBS);
2150 if ((fbs & PORT_FBS_EN) == 0) {
2151 pp->fbs_enabled = false;
2152 return;
2153 }
2154
2155 rc = ahci_stop_engine(ap);
2156 if (rc)
2157 return;
2158
2159 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2160 fbs = readl(port_mmio + PORT_FBS);
2161 if (fbs & PORT_FBS_EN)
2162 dev_err(ap->host->dev, "Failed to disable FBS\n");
2163 else {
2164 dev_info(ap->host->dev, "FBS is disabled\n");
2165 pp->fbs_enabled = false;
2166 }
2167
2168 hpriv->start_engine(ap);
2169 }
2170
2171 static void ahci_pmp_attach(struct ata_port *ap)
2172 {
2173 void __iomem *port_mmio = ahci_port_base(ap);
2174 struct ahci_port_priv *pp = ap->private_data;
2175 u32 cmd;
2176
2177 cmd = readl(port_mmio + PORT_CMD);
2178 cmd |= PORT_CMD_PMP;
2179 writel(cmd, port_mmio + PORT_CMD);
2180
2181 ahci_enable_fbs(ap);
2182
2183 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2184
2185 /*
2186 * We must not change the port interrupt mask register if the
2187 * port is marked frozen, the value in pp->intr_mask will be
2188 * restored later when the port is thawed.
2189 *
2190 * Note that during initialization, the port is marked as
2191 * frozen since the irq handler is not yet registered.
2192 */
2193 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2194 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2195 }
2196
2197 static void ahci_pmp_detach(struct ata_port *ap)
2198 {
2199 void __iomem *port_mmio = ahci_port_base(ap);
2200 struct ahci_port_priv *pp = ap->private_data;
2201 u32 cmd;
2202
2203 ahci_disable_fbs(ap);
2204
2205 cmd = readl(port_mmio + PORT_CMD);
2206 cmd &= ~PORT_CMD_PMP;
2207 writel(cmd, port_mmio + PORT_CMD);
2208
2209 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2210
2211 /* see comment above in ahci_pmp_attach() */
2212 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2213 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2214 }
2215
2216 int ahci_port_resume(struct ata_port *ap)
2217 {
2218 ahci_power_up(ap);
2219 ahci_start_port(ap);
2220
2221 if (sata_pmp_attached(ap))
2222 ahci_pmp_attach(ap);
2223 else
2224 ahci_pmp_detach(ap);
2225
2226 return 0;
2227 }
2228 EXPORT_SYMBOL_GPL(ahci_port_resume);
2229
2230 #ifdef CONFIG_PM
2231 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2232 {
2233 const char *emsg = NULL;
2234 int rc;
2235
2236 rc = ahci_deinit_port(ap, &emsg);
2237 if (rc == 0)
2238 ahci_power_down(ap);
2239 else {
2240 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2241 ata_port_freeze(ap);
2242 }
2243
2244 return rc;
2245 }
2246 #endif
2247
2248 static int ahci_port_start(struct ata_port *ap)
2249 {
2250 struct ahci_host_priv *hpriv = ap->host->private_data;
2251 struct device *dev = ap->host->dev;
2252 struct ahci_port_priv *pp;
2253 void *mem;
2254 dma_addr_t mem_dma;
2255 size_t dma_sz, rx_fis_sz;
2256
2257 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2258 if (!pp)
2259 return -ENOMEM;
2260
2261 if (ap->host->n_ports > 1) {
2262 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2263 if (!pp->irq_desc) {
2264 devm_kfree(dev, pp);
2265 return -ENOMEM;
2266 }
2267 snprintf(pp->irq_desc, 8,
2268 "%s%d", dev_driver_string(dev), ap->port_no);
2269 }
2270
2271 /* check FBS capability */
2272 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2273 void __iomem *port_mmio = ahci_port_base(ap);
2274 u32 cmd = readl(port_mmio + PORT_CMD);
2275 if (cmd & PORT_CMD_FBSCP)
2276 pp->fbs_supported = true;
2277 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2278 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2279 ap->port_no);
2280 pp->fbs_supported = true;
2281 } else
2282 dev_warn(dev, "port %d is not capable of FBS\n",
2283 ap->port_no);
2284 }
2285
2286 if (pp->fbs_supported) {
2287 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2288 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2289 } else {
2290 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2291 rx_fis_sz = AHCI_RX_FIS_SZ;
2292 }
2293
2294 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2295 if (!mem)
2296 return -ENOMEM;
2297 memset(mem, 0, dma_sz);
2298
2299 /*
2300 * First item in chunk of DMA memory: 32-slot command table,
2301 * 32 bytes each in size
2302 */
2303 pp->cmd_slot = mem;
2304 pp->cmd_slot_dma = mem_dma;
2305
2306 mem += AHCI_CMD_SLOT_SZ;
2307 mem_dma += AHCI_CMD_SLOT_SZ;
2308
2309 /*
2310 * Second item: Received-FIS area
2311 */
2312 pp->rx_fis = mem;
2313 pp->rx_fis_dma = mem_dma;
2314
2315 mem += rx_fis_sz;
2316 mem_dma += rx_fis_sz;
2317
2318 /*
2319 * Third item: data area for storing a single command
2320 * and its scatter-gather table
2321 */
2322 pp->cmd_tbl = mem;
2323 pp->cmd_tbl_dma = mem_dma;
2324
2325 /*
2326 * Save off initial list of interrupts to be enabled.
2327 * This could be changed later
2328 */
2329 pp->intr_mask = DEF_PORT_IRQ;
2330
2331 /*
2332 * Switch to per-port locking in case each port has its own MSI vector.
2333 */
2334 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2335 spin_lock_init(&pp->lock);
2336 ap->lock = &pp->lock;
2337 }
2338
2339 ap->private_data = pp;
2340
2341 /* engage engines, captain */
2342 return ahci_port_resume(ap);
2343 }
2344
2345 static void ahci_port_stop(struct ata_port *ap)
2346 {
2347 const char *emsg = NULL;
2348 int rc;
2349
2350 /* de-initialize port */
2351 rc = ahci_deinit_port(ap, &emsg);
2352 if (rc)
2353 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2354 }
2355
2356 void ahci_print_info(struct ata_host *host, const char *scc_s)
2357 {
2358 struct ahci_host_priv *hpriv = host->private_data;
2359 void __iomem *mmio = hpriv->mmio;
2360 u32 vers, cap, cap2, impl, speed;
2361 const char *speed_s;
2362
2363 vers = readl(mmio + HOST_VERSION);
2364 cap = hpriv->cap;
2365 cap2 = hpriv->cap2;
2366 impl = hpriv->port_map;
2367
2368 speed = (cap >> 20) & 0xf;
2369 if (speed == 1)
2370 speed_s = "1.5";
2371 else if (speed == 2)
2372 speed_s = "3";
2373 else if (speed == 3)
2374 speed_s = "6";
2375 else
2376 speed_s = "?";
2377
2378 dev_info(host->dev,
2379 "AHCI %02x%02x.%02x%02x "
2380 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2381 ,
2382
2383 (vers >> 24) & 0xff,
2384 (vers >> 16) & 0xff,
2385 (vers >> 8) & 0xff,
2386 vers & 0xff,
2387
2388 ((cap >> 8) & 0x1f) + 1,
2389 (cap & 0x1f) + 1,
2390 speed_s,
2391 impl,
2392 scc_s);
2393
2394 dev_info(host->dev,
2395 "flags: "
2396 "%s%s%s%s%s%s%s"
2397 "%s%s%s%s%s%s%s"
2398 "%s%s%s%s%s%s%s"
2399 "%s%s\n"
2400 ,
2401
2402 cap & HOST_CAP_64 ? "64bit " : "",
2403 cap & HOST_CAP_NCQ ? "ncq " : "",
2404 cap & HOST_CAP_SNTF ? "sntf " : "",
2405 cap & HOST_CAP_MPS ? "ilck " : "",
2406 cap & HOST_CAP_SSS ? "stag " : "",
2407 cap & HOST_CAP_ALPM ? "pm " : "",
2408 cap & HOST_CAP_LED ? "led " : "",
2409 cap & HOST_CAP_CLO ? "clo " : "",
2410 cap & HOST_CAP_ONLY ? "only " : "",
2411 cap & HOST_CAP_PMP ? "pmp " : "",
2412 cap & HOST_CAP_FBS ? "fbs " : "",
2413 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2414 cap & HOST_CAP_SSC ? "slum " : "",
2415 cap & HOST_CAP_PART ? "part " : "",
2416 cap & HOST_CAP_CCC ? "ccc " : "",
2417 cap & HOST_CAP_EMS ? "ems " : "",
2418 cap & HOST_CAP_SXS ? "sxs " : "",
2419 cap2 & HOST_CAP2_DESO ? "deso " : "",
2420 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2421 cap2 & HOST_CAP2_SDS ? "sds " : "",
2422 cap2 & HOST_CAP2_APST ? "apst " : "",
2423 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2424 cap2 & HOST_CAP2_BOH ? "boh " : ""
2425 );
2426 }
2427 EXPORT_SYMBOL_GPL(ahci_print_info);
2428
2429 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2430 struct ata_port_info *pi)
2431 {
2432 u8 messages;
2433 void __iomem *mmio = hpriv->mmio;
2434 u32 em_loc = readl(mmio + HOST_EM_LOC);
2435 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2436
2437 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2438 return;
2439
2440 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2441
2442 if (messages) {
2443 /* store em_loc */
2444 hpriv->em_loc = ((em_loc >> 16) * 4);
2445 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2446 hpriv->em_msg_type = messages;
2447 pi->flags |= ATA_FLAG_EM;
2448 if (!(em_ctl & EM_CTL_ALHD))
2449 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2450 }
2451 }
2452 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2453
2454 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2455 struct scsi_host_template *sht)
2456 {
2457 struct ahci_host_priv *hpriv = host->private_data;
2458 int i, rc;
2459
2460 rc = ata_host_start(host);
2461 if (rc)
2462 return rc;
2463 /*
2464 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2465 * allocated. That is one MSI per port, starting from @irq.
2466 */
2467 for (i = 0; i < host->n_ports; i++) {
2468 struct ahci_port_priv *pp = host->ports[i]->private_data;
2469 int irq = ahci_irq_vector(hpriv, i);
2470
2471 /* Do not receive interrupts sent by dummy ports */
2472 if (!pp) {
2473 disable_irq(irq + i);
2474 continue;
2475 }
2476
2477 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2478 0, pp->irq_desc, host->ports[i]);
2479
2480 if (rc)
2481 return rc;
2482 ata_port_desc(host->ports[i], "irq %d", irq);
2483 }
2484
2485 return ata_host_register(host, sht);
2486 }
2487
2488 /**
2489 * ahci_host_activate - start AHCI host, request IRQs and register it
2490 * @host: target ATA host
2491 * @sht: scsi_host_template to use when registering the host
2492 *
2493 * LOCKING:
2494 * Inherited from calling layer (may sleep).
2495 *
2496 * RETURNS:
2497 * 0 on success, -errno otherwise.
2498 */
2499 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2500 {
2501 struct ahci_host_priv *hpriv = host->private_data;
2502 int irq = hpriv->irq;
2503 int rc;
2504
2505 if (hpriv->flags & (AHCI_HFLAG_MULTI_MSI | AHCI_HFLAG_MULTI_MSIX)) {
2506 if (hpriv->irq_handler)
2507 dev_warn(host->dev, "both AHCI_HFLAG_MULTI_MSI flag set \
2508 and custom irq handler implemented\n");
2509
2510 rc = ahci_host_activate_multi_irqs(host, sht);
2511 } else {
2512 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2513 IRQF_SHARED, sht);
2514 }
2515
2516
2517 return rc;
2518 }
2519 EXPORT_SYMBOL_GPL(ahci_host_activate);
2520
2521 MODULE_AUTHOR("Jeff Garzik");
2522 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2523 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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