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[deliverable/linux.git] / drivers / ata / sata_dwc_460ex.c
1 /*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21 #ifdef CONFIG_SATA_DWC_DEBUG
22 #define DEBUG
23 #endif
24
25 #ifdef CONFIG_SATA_DWC_VDEBUG
26 #define VERBOSE_DEBUG
27 #define DEBUG_NCQ
28 #endif
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/device.h>
33 #include <linux/dmaengine.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_platform.h>
37 #include <linux/platform_device.h>
38 #include <linux/phy/phy.h>
39 #include <linux/libata.h>
40 #include <linux/slab.h>
41
42 #include "libata.h"
43
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46
47 /* These two are defined in "libata.h" */
48 #undef DRV_NAME
49 #undef DRV_VERSION
50
51 #define DRV_NAME "sata-dwc"
52 #define DRV_VERSION "1.3"
53
54 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
55 #define sata_dwc_readl(a) readl_relaxed(a)
56
57 #ifndef NO_IRQ
58 #define NO_IRQ 0
59 #endif
60
61 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
62
63 enum {
64 SATA_DWC_MAX_PORTS = 1,
65
66 SATA_DWC_SCR_OFFSET = 0x24,
67 SATA_DWC_REG_OFFSET = 0x64,
68 };
69
70 /* DWC SATA Registers */
71 struct sata_dwc_regs {
72 u32 fptagr; /* 1st party DMA tag */
73 u32 fpbor; /* 1st party DMA buffer offset */
74 u32 fptcr; /* 1st party DMA Xfr count */
75 u32 dmacr; /* DMA Control */
76 u32 dbtsr; /* DMA Burst Transac size */
77 u32 intpr; /* Interrupt Pending */
78 u32 intmr; /* Interrupt Mask */
79 u32 errmr; /* Error Mask */
80 u32 llcr; /* Link Layer Control */
81 u32 phycr; /* PHY Control */
82 u32 physr; /* PHY Status */
83 u32 rxbistpd; /* Recvd BIST pattern def register */
84 u32 rxbistpd1; /* Recvd BIST data dword1 */
85 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
86 u32 txbistpd; /* Trans BIST pattern def register */
87 u32 txbistpd1; /* Trans BIST data dword1 */
88 u32 txbistpd2; /* Trans BIST data dword2 */
89 u32 bistcr; /* BIST Control Register */
90 u32 bistfctr; /* BIST FIS Count Register */
91 u32 bistsr; /* BIST Status Register */
92 u32 bistdecr; /* BIST Dword Error count register */
93 u32 res[15]; /* Reserved locations */
94 u32 testr; /* Test Register */
95 u32 versionr; /* Version Register */
96 u32 idr; /* ID Register */
97 u32 unimpl[192]; /* Unimplemented */
98 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
99 };
100
101 enum {
102 SCR_SCONTROL_DET_ENABLE = 0x00000001,
103 SCR_SSTATUS_DET_PRESENT = 0x00000001,
104 SCR_SERROR_DIAG_X = 0x04000000,
105 /* DWC SATA Register Operations */
106 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
107 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
108 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
109 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
110 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
111 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
112 SATA_DWC_INTPR_DMAT = 0x00000001,
113 SATA_DWC_INTPR_NEWFP = 0x00000002,
114 SATA_DWC_INTPR_PMABRT = 0x00000004,
115 SATA_DWC_INTPR_ERR = 0x00000008,
116 SATA_DWC_INTPR_NEWBIST = 0x00000010,
117 SATA_DWC_INTPR_IPF = 0x10000000,
118 SATA_DWC_INTMR_DMATM = 0x00000001,
119 SATA_DWC_INTMR_NEWFPM = 0x00000002,
120 SATA_DWC_INTMR_PMABRTM = 0x00000004,
121 SATA_DWC_INTMR_ERRM = 0x00000008,
122 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
123 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
124 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
125 SATA_DWC_LLCR_RPDEN = 0x00000004,
126 /* This is all error bits, zero's are reserved fields. */
127 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
128 };
129
130 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
131 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
132 SATA_DWC_DMACR_TMOD_TXCHEN)
133 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
134 SATA_DWC_DMACR_TMOD_TXCHEN)
135 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
136 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
137 << 16)
138 struct sata_dwc_device {
139 struct device *dev; /* generic device struct */
140 struct ata_probe_ent *pe; /* ptr to probe-ent */
141 struct ata_host *host;
142 u8 __iomem *reg_base;
143 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
144 u32 sactive_issued;
145 u32 sactive_queued;
146 struct phy *phy;
147 #ifdef CONFIG_SATA_DWC_OLD_DMA
148 struct dw_dma_chip *dma;
149 #endif
150 };
151
152 #define SATA_DWC_QCMD_MAX 32
153
154 struct sata_dwc_device_port {
155 struct sata_dwc_device *hsdev;
156 int cmd_issued[SATA_DWC_QCMD_MAX];
157 int dma_pending[SATA_DWC_QCMD_MAX];
158
159 /* DMA info */
160 struct dma_chan *chan;
161 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
162 u32 dma_interrupt_count;
163 };
164
165 /*
166 * Commonly used DWC SATA driver macros
167 */
168 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
169 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
170 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
171 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
173
174 enum {
175 SATA_DWC_CMD_ISSUED_NOT = 0,
176 SATA_DWC_CMD_ISSUED_PEND = 1,
177 SATA_DWC_CMD_ISSUED_EXEC = 2,
178 SATA_DWC_CMD_ISSUED_NODATA = 3,
179
180 SATA_DWC_DMA_PENDING_NONE = 0,
181 SATA_DWC_DMA_PENDING_TX = 1,
182 SATA_DWC_DMA_PENDING_RX = 2,
183 };
184
185 /*
186 * Prototypes
187 */
188 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
189 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
190 u32 check_status);
191 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
192 static void sata_dwc_port_stop(struct ata_port *ap);
193 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
194
195 #ifdef CONFIG_SATA_DWC_OLD_DMA
196
197 #include <linux/platform_data/dma-dw.h>
198 #include <linux/dma/dw.h>
199
200 static struct dw_dma_slave sata_dwc_dma_dws = {
201 .src_id = 0,
202 .dst_id = 0,
203 .m_master = 1,
204 .p_master = 0,
205 };
206
207 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
208 {
209 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
210
211 if (dws->dma_dev != chan->device->dev)
212 return false;
213
214 chan->private = dws;
215 return true;
216 }
217
218 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
219 {
220 struct sata_dwc_device *hsdev = hsdevp->hsdev;
221 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
222 dma_cap_mask_t mask;
223
224 dws->dma_dev = hsdev->dev;
225
226 dma_cap_zero(mask);
227 dma_cap_set(DMA_SLAVE, mask);
228
229 /* Acquire DMA channel */
230 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
231 if (!hsdevp->chan) {
232 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
233 __func__);
234 return -EAGAIN;
235 }
236
237 return 0;
238 }
239
240 static int sata_dwc_dma_init_old(struct platform_device *pdev,
241 struct sata_dwc_device *hsdev)
242 {
243 struct device_node *np = pdev->dev.of_node;
244 int err;
245
246 hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
247 if (!hsdev->dma)
248 return -ENOMEM;
249
250 hsdev->dma->dev = &pdev->dev;
251
252 /* Get SATA DMA interrupt number */
253 hsdev->dma->irq = irq_of_parse_and_map(np, 1);
254 if (hsdev->dma->irq == NO_IRQ) {
255 dev_err(&pdev->dev, "no SATA DMA irq\n");
256 return -ENODEV;
257 }
258
259 /* Get physical SATA DMA register base address */
260 hsdev->dma->regs = of_iomap(np, 1);
261 if (!hsdev->dma->regs) {
262 dev_err(&pdev->dev,
263 "ioremap failed for AHBDMA register address\n");
264 return -ENODEV;
265 }
266
267 /* Initialize AHB DMAC */
268 err = dw_dma_probe(hsdev->dma);
269 if (err) {
270 iounmap(hsdev->dma->regs);
271 return err;
272 }
273
274 return 0;
275 }
276
277 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
278 {
279 if (!hsdev->dma)
280 return;
281
282 dw_dma_remove(hsdev->dma);
283 iounmap(hsdev->dma->regs);
284 }
285
286 #endif
287
288 static const char *get_prot_descript(u8 protocol)
289 {
290 switch ((enum ata_tf_protocols)protocol) {
291 case ATA_PROT_NODATA:
292 return "ATA no data";
293 case ATA_PROT_PIO:
294 return "ATA PIO";
295 case ATA_PROT_DMA:
296 return "ATA DMA";
297 case ATA_PROT_NCQ:
298 return "ATA NCQ";
299 case ATAPI_PROT_NODATA:
300 return "ATAPI no data";
301 case ATAPI_PROT_PIO:
302 return "ATAPI PIO";
303 case ATAPI_PROT_DMA:
304 return "ATAPI DMA";
305 default:
306 return "unknown";
307 }
308 }
309
310 static const char *get_dma_dir_descript(int dma_dir)
311 {
312 switch ((enum dma_data_direction)dma_dir) {
313 case DMA_BIDIRECTIONAL:
314 return "bidirectional";
315 case DMA_TO_DEVICE:
316 return "to device";
317 case DMA_FROM_DEVICE:
318 return "from device";
319 default:
320 return "none";
321 }
322 }
323
324 static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
325 {
326 dev_vdbg(ap->dev,
327 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
328 tf->command, get_prot_descript(tf->protocol), tf->flags,
329 tf->device);
330 dev_vdbg(ap->dev,
331 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
332 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
333 dev_vdbg(ap->dev,
334 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
335 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
336 tf->hob_lbah);
337 }
338
339 static void dma_dwc_xfer_done(void *hsdev_instance)
340 {
341 unsigned long flags;
342 struct sata_dwc_device *hsdev = hsdev_instance;
343 struct ata_host *host = (struct ata_host *)hsdev->host;
344 struct ata_port *ap;
345 struct sata_dwc_device_port *hsdevp;
346 u8 tag = 0;
347 unsigned int port = 0;
348
349 spin_lock_irqsave(&host->lock, flags);
350 ap = host->ports[port];
351 hsdevp = HSDEVP_FROM_AP(ap);
352 tag = ap->link.active_tag;
353
354 /*
355 * Each DMA command produces 2 interrupts. Only
356 * complete the command after both interrupts have been
357 * seen. (See sata_dwc_isr())
358 */
359 hsdevp->dma_interrupt_count++;
360 sata_dwc_clear_dmacr(hsdevp, tag);
361
362 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
363 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
364 tag, hsdevp->dma_pending[tag]);
365 }
366
367 if ((hsdevp->dma_interrupt_count % 2) == 0)
368 sata_dwc_dma_xfer_complete(ap, 1);
369
370 spin_unlock_irqrestore(&host->lock, flags);
371 }
372
373 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
374 {
375 struct ata_port *ap = qc->ap;
376 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
377 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
378 dma_addr_t addr = (dma_addr_t)&hsdev->sata_dwc_regs->dmadr;
379 struct dma_slave_config sconf;
380 struct dma_async_tx_descriptor *desc;
381
382 if (qc->dma_dir == DMA_DEV_TO_MEM) {
383 sconf.src_addr = addr;
384 sconf.device_fc = false;
385 } else { /* DMA_MEM_TO_DEV */
386 sconf.dst_addr = addr;
387 sconf.device_fc = false;
388 }
389
390 sconf.direction = qc->dma_dir;
391 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
392 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
393 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
394 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
395
396 dmaengine_slave_config(hsdevp->chan, &sconf);
397
398 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
399 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
400 qc->dma_dir,
401 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
402
403 if (!desc)
404 return NULL;
405
406 desc->callback = dma_dwc_xfer_done;
407 desc->callback_param = hsdev;
408
409 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pad\n",
410 __func__, qc->sg, qc->n_elem, &addr);
411
412 return desc;
413 }
414
415 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
416 {
417 if (scr > SCR_NOTIFICATION) {
418 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
419 __func__, scr);
420 return -EINVAL;
421 }
422
423 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
424 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
425 __func__, link->ap->print_id, scr, *val);
426
427 return 0;
428 }
429
430 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
431 {
432 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
433 __func__, link->ap->print_id, scr, val);
434 if (scr > SCR_NOTIFICATION) {
435 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
436 __func__, scr);
437 return -EINVAL;
438 }
439 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
440
441 return 0;
442 }
443
444 static void clear_serror(struct ata_port *ap)
445 {
446 u32 val;
447 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
448 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
449 }
450
451 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
452 {
453 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
454 sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
455 }
456
457 static u32 qcmd_tag_to_mask(u8 tag)
458 {
459 return 0x00000001 << (tag & 0x1f);
460 }
461
462 /* See ahci.c */
463 static void sata_dwc_error_intr(struct ata_port *ap,
464 struct sata_dwc_device *hsdev, uint intpr)
465 {
466 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
467 struct ata_eh_info *ehi = &ap->link.eh_info;
468 unsigned int err_mask = 0, action = 0;
469 struct ata_queued_cmd *qc;
470 u32 serror;
471 u8 status, tag;
472
473 ata_ehi_clear_desc(ehi);
474
475 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
476 status = ap->ops->sff_check_status(ap);
477
478 tag = ap->link.active_tag;
479
480 dev_err(ap->dev,
481 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
482 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
483 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
484
485 /* Clear error register and interrupt bit */
486 clear_serror(ap);
487 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
488
489 /* This is the only error happening now. TODO check for exact error */
490
491 err_mask |= AC_ERR_HOST_BUS;
492 action |= ATA_EH_RESET;
493
494 /* Pass this on to EH */
495 ehi->serror |= serror;
496 ehi->action |= action;
497
498 qc = ata_qc_from_tag(ap, tag);
499 if (qc)
500 qc->err_mask |= err_mask;
501 else
502 ehi->err_mask |= err_mask;
503
504 ata_port_abort(ap);
505 }
506
507 /*
508 * Function : sata_dwc_isr
509 * arguments : irq, void *dev_instance, struct pt_regs *regs
510 * Return value : irqreturn_t - status of IRQ
511 * This Interrupt handler called via port ops registered function.
512 * .irq_handler = sata_dwc_isr
513 */
514 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
515 {
516 struct ata_host *host = (struct ata_host *)dev_instance;
517 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
518 struct ata_port *ap;
519 struct ata_queued_cmd *qc;
520 unsigned long flags;
521 u8 status, tag;
522 int handled, num_processed, port = 0;
523 uint intpr, sactive, sactive2, tag_mask;
524 struct sata_dwc_device_port *hsdevp;
525 hsdev->sactive_issued = 0;
526
527 spin_lock_irqsave(&host->lock, flags);
528
529 /* Read the interrupt register */
530 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
531
532 ap = host->ports[port];
533 hsdevp = HSDEVP_FROM_AP(ap);
534
535 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
536 ap->link.active_tag);
537
538 /* Check for error interrupt */
539 if (intpr & SATA_DWC_INTPR_ERR) {
540 sata_dwc_error_intr(ap, hsdev, intpr);
541 handled = 1;
542 goto DONE;
543 }
544
545 /* Check for DMA SETUP FIS (FP DMA) interrupt */
546 if (intpr & SATA_DWC_INTPR_NEWFP) {
547 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
548
549 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
550 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
551 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
552 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
553
554 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
555
556 qc = ata_qc_from_tag(ap, tag);
557 /*
558 * Start FP DMA for NCQ command. At this point the tag is the
559 * active tag. It is the tag that matches the command about to
560 * be completed.
561 */
562 qc->ap->link.active_tag = tag;
563 sata_dwc_bmdma_start_by_tag(qc, tag);
564
565 handled = 1;
566 goto DONE;
567 }
568 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
569 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
570
571 /* If no sactive issued and tag_mask is zero then this is not NCQ */
572 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
573 if (ap->link.active_tag == ATA_TAG_POISON)
574 tag = 0;
575 else
576 tag = ap->link.active_tag;
577 qc = ata_qc_from_tag(ap, tag);
578
579 /* DEV interrupt w/ no active qc? */
580 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
581 dev_err(ap->dev,
582 "%s interrupt with no active qc qc=%p\n",
583 __func__, qc);
584 ap->ops->sff_check_status(ap);
585 handled = 1;
586 goto DONE;
587 }
588 status = ap->ops->sff_check_status(ap);
589
590 qc->ap->link.active_tag = tag;
591 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
592
593 if (status & ATA_ERR) {
594 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
595 sata_dwc_qc_complete(ap, qc, 1);
596 handled = 1;
597 goto DONE;
598 }
599
600 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
601 __func__, get_prot_descript(qc->tf.protocol));
602 DRVSTILLBUSY:
603 if (ata_is_dma(qc->tf.protocol)) {
604 /*
605 * Each DMA transaction produces 2 interrupts. The DMAC
606 * transfer complete interrupt and the SATA controller
607 * operation done interrupt. The command should be
608 * completed only after both interrupts are seen.
609 */
610 hsdevp->dma_interrupt_count++;
611 if (hsdevp->dma_pending[tag] == \
612 SATA_DWC_DMA_PENDING_NONE) {
613 dev_err(ap->dev,
614 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
615 __func__, intpr, status,
616 hsdevp->dma_pending[tag]);
617 }
618
619 if ((hsdevp->dma_interrupt_count % 2) == 0)
620 sata_dwc_dma_xfer_complete(ap, 1);
621 } else if (ata_is_pio(qc->tf.protocol)) {
622 ata_sff_hsm_move(ap, qc, status, 0);
623 handled = 1;
624 goto DONE;
625 } else {
626 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
627 goto DRVSTILLBUSY;
628 }
629
630 handled = 1;
631 goto DONE;
632 }
633
634 /*
635 * This is a NCQ command. At this point we need to figure out for which
636 * tags we have gotten a completion interrupt. One interrupt may serve
637 * as completion for more than one operation when commands are queued
638 * (NCQ). We need to process each completed command.
639 */
640
641 /* process completed commands */
642 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
643 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
644
645 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
646 dev_dbg(ap->dev,
647 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
648 __func__, sactive, hsdev->sactive_issued, tag_mask);
649 }
650
651 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
652 dev_warn(ap->dev,
653 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
654 sactive, hsdev->sactive_issued, tag_mask);
655 }
656
657 /* read just to clear ... not bad if currently still busy */
658 status = ap->ops->sff_check_status(ap);
659 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
660
661 tag = 0;
662 num_processed = 0;
663 while (tag_mask) {
664 num_processed++;
665 while (!(tag_mask & 0x00000001)) {
666 tag++;
667 tag_mask <<= 1;
668 }
669
670 tag_mask &= (~0x00000001);
671 qc = ata_qc_from_tag(ap, tag);
672
673 /* To be picked up by completion functions */
674 qc->ap->link.active_tag = tag;
675 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
676
677 /* Let libata/scsi layers handle error */
678 if (status & ATA_ERR) {
679 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
680 status);
681 sata_dwc_qc_complete(ap, qc, 1);
682 handled = 1;
683 goto DONE;
684 }
685
686 /* Process completed command */
687 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
688 get_prot_descript(qc->tf.protocol));
689 if (ata_is_dma(qc->tf.protocol)) {
690 hsdevp->dma_interrupt_count++;
691 if (hsdevp->dma_pending[tag] == \
692 SATA_DWC_DMA_PENDING_NONE)
693 dev_warn(ap->dev, "%s: DMA not pending?\n",
694 __func__);
695 if ((hsdevp->dma_interrupt_count % 2) == 0)
696 sata_dwc_dma_xfer_complete(ap, 1);
697 } else {
698 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
699 goto STILLBUSY;
700 }
701 continue;
702
703 STILLBUSY:
704 ap->stats.idle_irq++;
705 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
706 ap->print_id);
707 } /* while tag_mask */
708
709 /*
710 * Check to see if any commands completed while we were processing our
711 * initial set of completed commands (read status clears interrupts,
712 * so we might miss a completed command interrupt if one came in while
713 * we were processing --we read status as part of processing a completed
714 * command).
715 */
716 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
717 if (sactive2 != sactive) {
718 dev_dbg(ap->dev,
719 "More completed - sactive=0x%x sactive2=0x%x\n",
720 sactive, sactive2);
721 }
722 handled = 1;
723
724 DONE:
725 spin_unlock_irqrestore(&host->lock, flags);
726 return IRQ_RETVAL(handled);
727 }
728
729 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
730 {
731 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
732 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
733
734 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
735 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
736 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
737 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
738 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
739 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
740 } else {
741 /*
742 * This should not happen, it indicates the driver is out of
743 * sync. If it does happen, clear dmacr anyway.
744 */
745 dev_err(hsdev->dev,
746 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
747 __func__, tag, hsdevp->dma_pending[tag], dmacr);
748 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
749 SATA_DWC_DMACR_TXRXCH_CLEAR);
750 }
751 }
752
753 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
754 {
755 struct ata_queued_cmd *qc;
756 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
757 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
758 u8 tag = 0;
759
760 tag = ap->link.active_tag;
761 qc = ata_qc_from_tag(ap, tag);
762 if (!qc) {
763 dev_err(ap->dev, "failed to get qc");
764 return;
765 }
766
767 #ifdef DEBUG_NCQ
768 if (tag > 0) {
769 dev_info(ap->dev,
770 "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
771 __func__, qc->tag, qc->tf.command,
772 get_dma_dir_descript(qc->dma_dir),
773 get_prot_descript(qc->tf.protocol),
774 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
775 }
776 #endif
777
778 if (ata_is_dma(qc->tf.protocol)) {
779 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
780 dev_err(ap->dev,
781 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
782 __func__,
783 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
784 }
785
786 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
787 sata_dwc_qc_complete(ap, qc, check_status);
788 ap->link.active_tag = ATA_TAG_POISON;
789 } else {
790 sata_dwc_qc_complete(ap, qc, check_status);
791 }
792 }
793
794 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
795 u32 check_status)
796 {
797 u8 status = 0;
798 u32 mask = 0x0;
799 u8 tag = qc->tag;
800 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
801 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
802 hsdev->sactive_queued = 0;
803 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
804
805 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
806 dev_err(ap->dev, "TX DMA PENDING\n");
807 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
808 dev_err(ap->dev, "RX DMA PENDING\n");
809 dev_dbg(ap->dev,
810 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
811 qc->tf.command, status, ap->print_id, qc->tf.protocol);
812
813 /* clear active bit */
814 mask = (~(qcmd_tag_to_mask(tag)));
815 hsdev->sactive_queued = hsdev->sactive_queued & mask;
816 hsdev->sactive_issued = hsdev->sactive_issued & mask;
817 ata_qc_complete(qc);
818 return 0;
819 }
820
821 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
822 {
823 /* Enable selective interrupts by setting the interrupt maskregister*/
824 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
825 SATA_DWC_INTMR_ERRM |
826 SATA_DWC_INTMR_NEWFPM |
827 SATA_DWC_INTMR_PMABRTM |
828 SATA_DWC_INTMR_DMATM);
829 /*
830 * Unmask the error bits that should trigger an error interrupt by
831 * setting the error mask register.
832 */
833 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
834
835 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
836 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
837 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
838 }
839
840 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
841 {
842 port->cmd_addr = base + 0x00;
843 port->data_addr = base + 0x00;
844
845 port->error_addr = base + 0x04;
846 port->feature_addr = base + 0x04;
847
848 port->nsect_addr = base + 0x08;
849
850 port->lbal_addr = base + 0x0c;
851 port->lbam_addr = base + 0x10;
852 port->lbah_addr = base + 0x14;
853
854 port->device_addr = base + 0x18;
855 port->command_addr = base + 0x1c;
856 port->status_addr = base + 0x1c;
857
858 port->altstatus_addr = base + 0x20;
859 port->ctl_addr = base + 0x20;
860 }
861
862 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
863 {
864 struct sata_dwc_device *hsdev = hsdevp->hsdev;
865 struct device *dev = hsdev->dev;
866
867 #ifdef CONFIG_SATA_DWC_OLD_DMA
868 if (!of_find_property(dev->of_node, "dmas", NULL))
869 return sata_dwc_dma_get_channel_old(hsdevp);
870 #endif
871
872 hsdevp->chan = dma_request_chan(dev, "sata-dma");
873 if (IS_ERR(hsdevp->chan)) {
874 dev_err(dev, "failed to allocate dma channel: %ld\n",
875 PTR_ERR(hsdevp->chan));
876 return PTR_ERR(hsdevp->chan);
877 }
878
879 return 0;
880 }
881
882 /*
883 * Function : sata_dwc_port_start
884 * arguments : struct ata_ioports *port
885 * Return value : returns 0 if success, error code otherwise
886 * This function allocates the scatter gather LLI table for AHB DMA
887 */
888 static int sata_dwc_port_start(struct ata_port *ap)
889 {
890 int err = 0;
891 struct sata_dwc_device *hsdev;
892 struct sata_dwc_device_port *hsdevp = NULL;
893 struct device *pdev;
894 int i;
895
896 hsdev = HSDEV_FROM_AP(ap);
897
898 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
899
900 hsdev->host = ap->host;
901 pdev = ap->host->dev;
902 if (!pdev) {
903 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
904 err = -ENODEV;
905 goto CLEANUP;
906 }
907
908 /* Allocate Port Struct */
909 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
910 if (!hsdevp) {
911 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
912 err = -ENOMEM;
913 goto CLEANUP;
914 }
915 hsdevp->hsdev = hsdev;
916
917 err = sata_dwc_dma_get_channel(hsdevp);
918 if (err)
919 goto CLEANUP_ALLOC;
920
921 err = phy_power_on(hsdev->phy);
922 if (err)
923 goto CLEANUP_ALLOC;
924
925 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
926 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
927
928 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
929 ap->bmdma_prd_dma = 0;
930
931 if (ap->port_no == 0) {
932 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
933 __func__);
934 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
935 SATA_DWC_DMACR_TXRXCH_CLEAR);
936
937 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
938 __func__);
939 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
940 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
941 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
942 }
943
944 /* Clear any error bits before libata starts issuing commands */
945 clear_serror(ap);
946 ap->private_data = hsdevp;
947 dev_dbg(ap->dev, "%s: done\n", __func__);
948 return 0;
949
950 CLEANUP_ALLOC:
951 kfree(hsdevp);
952 CLEANUP:
953 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
954 return err;
955 }
956
957 static void sata_dwc_port_stop(struct ata_port *ap)
958 {
959 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
960 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
961
962 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
963
964 dmaengine_terminate_sync(hsdevp->chan);
965 dma_release_channel(hsdevp->chan);
966 phy_power_off(hsdev->phy);
967
968 kfree(hsdevp);
969 ap->private_data = NULL;
970 }
971
972 /*
973 * Function : sata_dwc_exec_command_by_tag
974 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
975 * Return value : None
976 * This function keeps track of individual command tag ids and calls
977 * ata_exec_command in libata
978 */
979 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
980 struct ata_taskfile *tf,
981 u8 tag, u32 cmd_issued)
982 {
983 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
984
985 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
986 ata_get_cmd_descript(tf->command), tag);
987
988 hsdevp->cmd_issued[tag] = cmd_issued;
989
990 /*
991 * Clear SError before executing a new command.
992 * sata_dwc_scr_write and read can not be used here. Clearing the PM
993 * managed SError register for the disk needs to be done before the
994 * task file is loaded.
995 */
996 clear_serror(ap);
997 ata_sff_exec_command(ap, tf);
998 }
999
1000 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1001 {
1002 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1003 SATA_DWC_CMD_ISSUED_PEND);
1004 }
1005
1006 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1007 {
1008 u8 tag = qc->tag;
1009
1010 if (ata_is_ncq(qc->tf.protocol)) {
1011 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1012 __func__, qc->ap->link.sactive, tag);
1013 } else {
1014 tag = 0;
1015 }
1016 sata_dwc_bmdma_setup_by_tag(qc, tag);
1017 }
1018
1019 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1020 {
1021 int start_dma;
1022 u32 reg;
1023 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1024 struct ata_port *ap = qc->ap;
1025 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1026 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
1027 int dir = qc->dma_dir;
1028
1029 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1030 start_dma = 1;
1031 if (dir == DMA_TO_DEVICE)
1032 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1033 else
1034 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1035 } else {
1036 dev_err(ap->dev,
1037 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1038 __func__, hsdevp->cmd_issued[tag], tag);
1039 start_dma = 0;
1040 }
1041
1042 dev_dbg(ap->dev,
1043 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1044 __func__, qc, tag, qc->tf.command,
1045 get_dma_dir_descript(qc->dma_dir), start_dma);
1046 sata_dwc_tf_dump(ap, &qc->tf);
1047
1048 if (start_dma) {
1049 sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
1050 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1051 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1052 __func__, reg);
1053 }
1054
1055 if (dir == DMA_TO_DEVICE)
1056 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1057 SATA_DWC_DMACR_TXCHEN);
1058 else
1059 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1060 SATA_DWC_DMACR_RXCHEN);
1061
1062 /* Enable AHB DMA transfer on the specified channel */
1063 dmaengine_submit(desc);
1064 dma_async_issue_pending(hsdevp->chan);
1065 }
1066 }
1067
1068 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1069 {
1070 u8 tag = qc->tag;
1071
1072 if (ata_is_ncq(qc->tf.protocol)) {
1073 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1074 __func__, qc->ap->link.sactive, tag);
1075 } else {
1076 tag = 0;
1077 }
1078 dev_dbg(qc->ap->dev, "%s\n", __func__);
1079 sata_dwc_bmdma_start_by_tag(qc, tag);
1080 }
1081
1082 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1083 {
1084 u32 sactive;
1085 u8 tag = qc->tag;
1086 struct ata_port *ap = qc->ap;
1087 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1088
1089 #ifdef DEBUG_NCQ
1090 if (qc->tag > 0 || ap->link.sactive > 1)
1091 dev_info(ap->dev,
1092 "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1093 __func__, ap->print_id, qc->tf.command,
1094 ata_get_cmd_descript(qc->tf.command),
1095 qc->tag, get_prot_descript(qc->tf.protocol),
1096 ap->link.active_tag, ap->link.sactive);
1097 #endif
1098
1099 if (!ata_is_ncq(qc->tf.protocol))
1100 tag = 0;
1101
1102 if (ata_is_dma(qc->tf.protocol)) {
1103 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1104 if (!hsdevp->desc[tag])
1105 return AC_ERR_SYSTEM;
1106 } else {
1107 hsdevp->desc[tag] = NULL;
1108 }
1109
1110 if (ata_is_ncq(qc->tf.protocol)) {
1111 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1112 sactive |= (0x00000001 << tag);
1113 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1114
1115 dev_dbg(qc->ap->dev,
1116 "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1117 __func__, tag, qc->ap->link.sactive, sactive);
1118
1119 ap->ops->sff_tf_load(ap, &qc->tf);
1120 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1121 SATA_DWC_CMD_ISSUED_PEND);
1122 } else {
1123 return ata_bmdma_qc_issue(qc);
1124 }
1125 return 0;
1126 }
1127
1128 static void sata_dwc_error_handler(struct ata_port *ap)
1129 {
1130 ata_sff_error_handler(ap);
1131 }
1132
1133 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1134 unsigned long deadline)
1135 {
1136 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1137 int ret;
1138
1139 ret = sata_sff_hardreset(link, class, deadline);
1140
1141 sata_dwc_enable_interrupts(hsdev);
1142
1143 /* Reconfigure the DMA control register */
1144 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1145 SATA_DWC_DMACR_TXRXCH_CLEAR);
1146
1147 /* Reconfigure the DMA Burst Transaction Size register */
1148 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1149 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1150 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1151
1152 return ret;
1153 }
1154
1155 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1156 {
1157 /* SATA DWC is master only */
1158 }
1159
1160 /*
1161 * scsi mid-layer and libata interface structures
1162 */
1163 static struct scsi_host_template sata_dwc_sht = {
1164 ATA_NCQ_SHT(DRV_NAME),
1165 /*
1166 * test-only: Currently this driver doesn't handle NCQ
1167 * correctly. We enable NCQ but set the queue depth to a
1168 * max of 1. This will get fixed in in a future release.
1169 */
1170 .sg_tablesize = LIBATA_MAX_PRD,
1171 /* .can_queue = ATA_MAX_QUEUE, */
1172 /*
1173 * Make sure a LLI block is not created that will span 8K max FIS
1174 * boundary. If the block spans such a FIS boundary, there is a chance
1175 * that a DMA burst will cross that boundary -- this results in an
1176 * error in the host controller.
1177 */
1178 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
1179 };
1180
1181 static struct ata_port_operations sata_dwc_ops = {
1182 .inherits = &ata_sff_port_ops,
1183
1184 .error_handler = sata_dwc_error_handler,
1185 .hardreset = sata_dwc_hardreset,
1186
1187 .qc_issue = sata_dwc_qc_issue,
1188
1189 .scr_read = sata_dwc_scr_read,
1190 .scr_write = sata_dwc_scr_write,
1191
1192 .port_start = sata_dwc_port_start,
1193 .port_stop = sata_dwc_port_stop,
1194
1195 .sff_dev_select = sata_dwc_dev_select,
1196
1197 .bmdma_setup = sata_dwc_bmdma_setup,
1198 .bmdma_start = sata_dwc_bmdma_start,
1199 };
1200
1201 static const struct ata_port_info sata_dwc_port_info[] = {
1202 {
1203 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1204 .pio_mask = ATA_PIO4,
1205 .udma_mask = ATA_UDMA6,
1206 .port_ops = &sata_dwc_ops,
1207 },
1208 };
1209
1210 static int sata_dwc_probe(struct platform_device *ofdev)
1211 {
1212 struct sata_dwc_device *hsdev;
1213 u32 idr, versionr;
1214 char *ver = (char *)&versionr;
1215 void __iomem *base;
1216 int err = 0;
1217 int irq;
1218 struct ata_host *host;
1219 struct ata_port_info pi = sata_dwc_port_info[0];
1220 const struct ata_port_info *ppi[] = { &pi, NULL };
1221 struct device_node *np = ofdev->dev.of_node;
1222
1223 /* Allocate DWC SATA device */
1224 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1225 hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1226 if (!host || !hsdev)
1227 return -ENOMEM;
1228
1229 host->private_data = hsdev;
1230
1231 /* Ioremap SATA registers */
1232 base = of_iomap(np, 0);
1233 if (!base) {
1234 dev_err(&ofdev->dev,
1235 "ioremap failed for SATA register address\n");
1236 return -ENODEV;
1237 }
1238 hsdev->reg_base = base;
1239 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1240
1241 /* Synopsys DWC SATA specific Registers */
1242 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1243
1244 /* Setup port */
1245 host->ports[0]->ioaddr.cmd_addr = base;
1246 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1247 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1248
1249 /* Read the ID and Version Registers */
1250 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1251 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1252 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1253 idr, ver[0], ver[1], ver[2]);
1254
1255 /* Save dev for later use in dev_xxx() routines */
1256 hsdev->dev = &ofdev->dev;
1257
1258 /* Enable SATA Interrupts */
1259 sata_dwc_enable_interrupts(hsdev);
1260
1261 /* Get SATA interrupt number */
1262 irq = irq_of_parse_and_map(np, 0);
1263 if (irq == NO_IRQ) {
1264 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1265 err = -ENODEV;
1266 goto error_out;
1267 }
1268
1269 #ifdef CONFIG_SATA_DWC_OLD_DMA
1270 if (!of_find_property(np, "dmas", NULL)) {
1271 err = sata_dwc_dma_init_old(ofdev, hsdev);
1272 if (err)
1273 goto error_out;
1274 }
1275 #endif
1276
1277 hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1278 if (IS_ERR(hsdev->phy)) {
1279 err = PTR_ERR(hsdev->phy);
1280 hsdev->phy = NULL;
1281 goto error_out;
1282 }
1283
1284 err = phy_init(hsdev->phy);
1285 if (err)
1286 goto error_out;
1287
1288 /*
1289 * Now, register with libATA core, this will also initiate the
1290 * device discovery process, invoking our port_start() handler &
1291 * error_handler() to execute a dummy Softreset EH session
1292 */
1293 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1294 if (err)
1295 dev_err(&ofdev->dev, "failed to activate host");
1296
1297 dev_set_drvdata(&ofdev->dev, host);
1298 return 0;
1299
1300 error_out:
1301 phy_exit(hsdev->phy);
1302 iounmap(base);
1303 return err;
1304 }
1305
1306 static int sata_dwc_remove(struct platform_device *ofdev)
1307 {
1308 struct device *dev = &ofdev->dev;
1309 struct ata_host *host = dev_get_drvdata(dev);
1310 struct sata_dwc_device *hsdev = host->private_data;
1311
1312 ata_host_detach(host);
1313
1314 phy_exit(hsdev->phy);
1315
1316 #ifdef CONFIG_SATA_DWC_OLD_DMA
1317 /* Free SATA DMA resources */
1318 sata_dwc_dma_exit_old(hsdev);
1319 #endif
1320
1321 iounmap(hsdev->reg_base);
1322 dev_dbg(&ofdev->dev, "done\n");
1323 return 0;
1324 }
1325
1326 static const struct of_device_id sata_dwc_match[] = {
1327 { .compatible = "amcc,sata-460ex", },
1328 {}
1329 };
1330 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1331
1332 static struct platform_driver sata_dwc_driver = {
1333 .driver = {
1334 .name = DRV_NAME,
1335 .of_match_table = sata_dwc_match,
1336 },
1337 .probe = sata_dwc_probe,
1338 .remove = sata_dwc_remove,
1339 };
1340
1341 module_platform_driver(sata_dwc_driver);
1342
1343 MODULE_LICENSE("GPL");
1344 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1345 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1346 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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