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bus: arm-ccn: make event groups reliable
[deliverable/linux.git] / drivers / bus / arm-ccn.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2014 ARM Limited
12 */
13
14 #include <linux/ctype.h>
15 #include <linux/hrtimer.h>
16 #include <linux/idr.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define CCN_NUM_XP_PORTS 2
25 #define CCN_NUM_VCS 4
26 #define CCN_NUM_REGIONS 256
27 #define CCN_REGION_SIZE 0x10000
28
29 #define CCN_ALL_OLY_ID 0xff00
30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT 0
31 #define CCN_ALL_OLY_ID__OLY_ID__MASK 0x1f
32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT 8
33 #define CCN_ALL_OLY_ID__NODE_ID__MASK 0x3f
34
35 #define CCN_MN_ERRINT_STATUS 0x0008
36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT 0x11
37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE 0x02
38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED 0x20
39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE 0x22
40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE 0x04
41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE 0x44
43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE 0x08
44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED 0x80
45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE 0x88
46 #define CCN_MN_OLY_COMP_LIST_63_0 0x01e0
47 #define CCN_MN_ERR_SIG_VAL_63_0 0x0300
48 #define CCN_MN_ERR_SIG_VAL_63_0__DT (1 << 1)
49
50 #define CCN_DT_ACTIVE_DSM 0x0000
51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n) ((n) * 8)
52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK 0xff
53 #define CCN_DT_CTL 0x0028
54 #define CCN_DT_CTL__DT_EN (1 << 0)
55 #define CCN_DT_PMEVCNT(n) (0x0100 + (n) * 0x8)
56 #define CCN_DT_PMCCNTR 0x0140
57 #define CCN_DT_PMCCNTRSR 0x0190
58 #define CCN_DT_PMOVSR 0x0198
59 #define CCN_DT_PMOVSR_CLR 0x01a0
60 #define CCN_DT_PMOVSR_CLR__MASK 0x1f
61 #define CCN_DT_PMCR 0x01a8
62 #define CCN_DT_PMCR__OVFL_INTR_EN (1 << 6)
63 #define CCN_DT_PMCR__PMU_EN (1 << 0)
64 #define CCN_DT_PMSR 0x01b0
65 #define CCN_DT_PMSR_REQ 0x01b8
66 #define CCN_DT_PMSR_CLR 0x01c0
67
68 #define CCN_HNF_PMU_EVENT_SEL 0x0600
69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK 0xf
71
72 #define CCN_XP_DT_CONFIG 0x0300
73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n) ((n) * 4)
74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK 0xf
75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH 0x0
76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n) (0x2 + (n))
78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n) (0x4 + (n))
79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
80 #define CCN_XP_DT_INTERFACE_SEL 0x0308
81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n) (0 + (n) * 8)
82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK 0x1
83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n) (1 + (n) * 8)
84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK 0x1
85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n) (2 + (n) * 8)
86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK 0x3
87 #define CCN_XP_DT_CMP_VAL_L(n) (0x0310 + (n) * 0x40)
88 #define CCN_XP_DT_CMP_VAL_H(n) (0x0318 + (n) * 0x40)
89 #define CCN_XP_DT_CMP_MASK_L(n) (0x0320 + (n) * 0x40)
90 #define CCN_XP_DT_CMP_MASK_H(n) (0x0328 + (n) * 0x40)
91 #define CCN_XP_DT_CONTROL 0x0370
92 #define CCN_XP_DT_CONTROL__DT_ENABLE (1 << 0)
93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n) (12 + (n) * 4)
94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK 0xf
95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS 0xf
96 #define CCN_XP_PMU_EVENT_SEL 0x0600
97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 7)
98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK 0x3f
99
100 #define CCN_SBAS_PMU_EVENT_SEL 0x0600
101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK 0xf
103
104 #define CCN_RNI_PMU_EVENT_SEL 0x0600
105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n) ((n) * 4)
106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK 0xf
107
108 #define CCN_TYPE_MN 0x01
109 #define CCN_TYPE_DT 0x02
110 #define CCN_TYPE_HNF 0x04
111 #define CCN_TYPE_HNI 0x05
112 #define CCN_TYPE_XP 0x08
113 #define CCN_TYPE_SBSX 0x0c
114 #define CCN_TYPE_SBAS 0x10
115 #define CCN_TYPE_RNI_1P 0x14
116 #define CCN_TYPE_RNI_2P 0x15
117 #define CCN_TYPE_RNI_3P 0x16
118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
119 #define CCN_TYPE_RND_2P 0x19
120 #define CCN_TYPE_RND_3P 0x1a
121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
122
123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
124
125 #define CCN_NUM_PMU_EVENTS 4
126 #define CCN_NUM_XP_WATCHPOINTS 2 /* See DT.dbg_id.num_watchpoints */
127 #define CCN_NUM_PMU_EVENT_COUNTERS 8 /* See DT.dbg_id.num_pmucntr */
128 #define CCN_IDX_PMU_CYCLE_COUNTER CCN_NUM_PMU_EVENT_COUNTERS
129
130 #define CCN_NUM_PREDEFINED_MASKS 4
131 #define CCN_IDX_MASK_ANY (CCN_NUM_PMU_EVENT_COUNTERS + 0)
132 #define CCN_IDX_MASK_EXACT (CCN_NUM_PMU_EVENT_COUNTERS + 1)
133 #define CCN_IDX_MASK_ORDER (CCN_NUM_PMU_EVENT_COUNTERS + 2)
134 #define CCN_IDX_MASK_OPCODE (CCN_NUM_PMU_EVENT_COUNTERS + 3)
135
136 struct arm_ccn_component {
137 void __iomem *base;
138 u32 type;
139
140 DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
141 union {
142 struct {
143 DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
144 } xp;
145 };
146 };
147
148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
149 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
150
151 struct arm_ccn_dt {
152 int id;
153 void __iomem *base;
154
155 spinlock_t config_lock;
156
157 DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
158 struct {
159 struct arm_ccn_component *source;
160 struct perf_event *event;
161 } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
162
163 struct {
164 u64 l, h;
165 } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
166
167 struct hrtimer hrtimer;
168
169 cpumask_t cpu;
170 struct list_head entry;
171
172 struct pmu pmu;
173 };
174
175 struct arm_ccn {
176 struct device *dev;
177 void __iomem *base;
178 unsigned int irq;
179
180 unsigned sbas_present:1;
181 unsigned sbsx_present:1;
182
183 int num_nodes;
184 struct arm_ccn_component *node;
185
186 int num_xps;
187 struct arm_ccn_component *xp;
188
189 struct arm_ccn_dt dt;
190 int mn_id;
191 };
192
193 static DEFINE_MUTEX(arm_ccn_mutex);
194 static LIST_HEAD(arm_ccn_list);
195
196 static int arm_ccn_node_to_xp(int node)
197 {
198 return node / CCN_NUM_XP_PORTS;
199 }
200
201 static int arm_ccn_node_to_xp_port(int node)
202 {
203 return node % CCN_NUM_XP_PORTS;
204 }
205
206
207 /*
208 * Bit shifts and masks in these defines must be kept in sync with
209 * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
210 */
211 #define CCN_CONFIG_NODE(_config) (((_config) >> 0) & 0xff)
212 #define CCN_CONFIG_XP(_config) (((_config) >> 0) & 0xff)
213 #define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
214 #define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
215 #define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
216 #define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
217 #define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
218 #define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
219 #define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
220
221 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
222 {
223 *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
224 *config |= (node_xp << 0) | (type << 8) | (port << 24);
225 }
226
227 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
228 struct device_attribute *attr, char *buf)
229 {
230 struct dev_ext_attribute *ea = container_of(attr,
231 struct dev_ext_attribute, attr);
232
233 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
234 }
235
236 #define CCN_FORMAT_ATTR(_name, _config) \
237 struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
238 { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
239 NULL), _config }
240
241 static CCN_FORMAT_ATTR(node, "config:0-7");
242 static CCN_FORMAT_ATTR(xp, "config:0-7");
243 static CCN_FORMAT_ATTR(type, "config:8-15");
244 static CCN_FORMAT_ATTR(event, "config:16-23");
245 static CCN_FORMAT_ATTR(port, "config:24-25");
246 static CCN_FORMAT_ATTR(bus, "config:24-25");
247 static CCN_FORMAT_ATTR(vc, "config:26-28");
248 static CCN_FORMAT_ATTR(dir, "config:29-29");
249 static CCN_FORMAT_ATTR(mask, "config:30-33");
250 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
251 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
252
253 static struct attribute *arm_ccn_pmu_format_attrs[] = {
254 &arm_ccn_pmu_format_attr_node.attr.attr,
255 &arm_ccn_pmu_format_attr_xp.attr.attr,
256 &arm_ccn_pmu_format_attr_type.attr.attr,
257 &arm_ccn_pmu_format_attr_event.attr.attr,
258 &arm_ccn_pmu_format_attr_port.attr.attr,
259 &arm_ccn_pmu_format_attr_bus.attr.attr,
260 &arm_ccn_pmu_format_attr_vc.attr.attr,
261 &arm_ccn_pmu_format_attr_dir.attr.attr,
262 &arm_ccn_pmu_format_attr_mask.attr.attr,
263 &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
264 &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
265 NULL
266 };
267
268 static struct attribute_group arm_ccn_pmu_format_attr_group = {
269 .name = "format",
270 .attrs = arm_ccn_pmu_format_attrs,
271 };
272
273
274 struct arm_ccn_pmu_event {
275 struct device_attribute attr;
276 u32 type;
277 u32 event;
278 int num_ports;
279 int num_vcs;
280 const char *def;
281 int mask;
282 };
283
284 #define CCN_EVENT_ATTR(_name) \
285 __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
286
287 /*
288 * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
289 * their ports in XP they are connected to. For the sake of usability they are
290 * explicitly defined here (and translated into a relevant watchpoint in
291 * arm_ccn_pmu_event_init()) so the user can easily request them without deep
292 * knowledge of the flit format.
293 */
294
295 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
296 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
297 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
298 .def = _def, .mask = _mask, }
299
300 #define CCN_EVENT_HNI(_name, _def, _mask) { \
301 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
302 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
303 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
304
305 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
306 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
307 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
308 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
309
310 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
311 .type = CCN_TYPE_HNF, .event = _event, }
312
313 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
314 .type = CCN_TYPE_XP, .event = _event, \
315 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
316
317 /*
318 * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
319 * on configuration. One of them is picked to represent the whole group,
320 * as they all share the same event types.
321 */
322 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
323 .type = CCN_TYPE_RNI_3P, .event = _event, }
324
325 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
326 .type = CCN_TYPE_SBAS, .event = _event, }
327
328 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
329 .type = CCN_TYPE_CYCLES }
330
331
332 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
333 struct device_attribute *attr, char *buf)
334 {
335 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
336 struct arm_ccn_pmu_event *event = container_of(attr,
337 struct arm_ccn_pmu_event, attr);
338 ssize_t res;
339
340 res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
341 if (event->event)
342 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
343 event->event);
344 if (event->def)
345 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
346 event->def);
347 if (event->mask)
348 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
349 event->mask);
350
351 /* Arguments required by an event */
352 switch (event->type) {
353 case CCN_TYPE_CYCLES:
354 break;
355 case CCN_TYPE_XP:
356 res += snprintf(buf + res, PAGE_SIZE - res,
357 ",xp=?,vc=?");
358 if (event->event == CCN_EVENT_WATCHPOINT)
359 res += snprintf(buf + res, PAGE_SIZE - res,
360 ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
361 else
362 res += snprintf(buf + res, PAGE_SIZE - res,
363 ",bus=?");
364
365 break;
366 case CCN_TYPE_MN:
367 res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
368 break;
369 default:
370 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
371 break;
372 }
373
374 res += snprintf(buf + res, PAGE_SIZE - res, "\n");
375
376 return res;
377 }
378
379 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
380 struct attribute *attr, int index)
381 {
382 struct device *dev = kobj_to_dev(kobj);
383 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
384 struct device_attribute *dev_attr = container_of(attr,
385 struct device_attribute, attr);
386 struct arm_ccn_pmu_event *event = container_of(dev_attr,
387 struct arm_ccn_pmu_event, attr);
388
389 if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
390 return 0;
391 if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
392 return 0;
393
394 return attr->mode;
395 }
396
397 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
398 CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
399 CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
400 CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
401 CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
402 CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
403 CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
404 CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
405 CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
406 CCN_IDX_MASK_ORDER),
407 CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
408 CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
409 CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
410 CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
411 CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
412 CCN_IDX_MASK_ORDER),
413 CCN_EVENT_HNF(cache_miss, 0x1),
414 CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
415 CCN_EVENT_HNF(cache_fill, 0x3),
416 CCN_EVENT_HNF(pocq_retry, 0x4),
417 CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
418 CCN_EVENT_HNF(sf_hit, 0x6),
419 CCN_EVENT_HNF(sf_evictions, 0x7),
420 CCN_EVENT_HNF(snoops_sent, 0x8),
421 CCN_EVENT_HNF(snoops_broadcast, 0x9),
422 CCN_EVENT_HNF(l3_eviction, 0xa),
423 CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
424 CCN_EVENT_HNF(mc_retries, 0xc),
425 CCN_EVENT_HNF(mc_reqs, 0xd),
426 CCN_EVENT_HNF(qos_hh_retry, 0xe),
427 CCN_EVENT_RNI(rdata_beats_p0, 0x1),
428 CCN_EVENT_RNI(rdata_beats_p1, 0x2),
429 CCN_EVENT_RNI(rdata_beats_p2, 0x3),
430 CCN_EVENT_RNI(rxdat_flits, 0x4),
431 CCN_EVENT_RNI(txdat_flits, 0x5),
432 CCN_EVENT_RNI(txreq_flits, 0x6),
433 CCN_EVENT_RNI(txreq_flits_retried, 0x7),
434 CCN_EVENT_RNI(rrt_full, 0x8),
435 CCN_EVENT_RNI(wrt_full, 0x9),
436 CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
437 CCN_EVENT_XP(upload_starvation, 0x1),
438 CCN_EVENT_XP(download_starvation, 0x2),
439 CCN_EVENT_XP(respin, 0x3),
440 CCN_EVENT_XP(valid_flit, 0x4),
441 CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
442 CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
443 CCN_EVENT_SBAS(rxdat_flits, 0x4),
444 CCN_EVENT_SBAS(txdat_flits, 0x5),
445 CCN_EVENT_SBAS(txreq_flits, 0x6),
446 CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
447 CCN_EVENT_SBAS(rrt_full, 0x8),
448 CCN_EVENT_SBAS(wrt_full, 0x9),
449 CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
450 CCN_EVENT_CYCLES(cycles),
451 };
452
453 /* Populated in arm_ccn_init() */
454 static struct attribute
455 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
456
457 static struct attribute_group arm_ccn_pmu_events_attr_group = {
458 .name = "events",
459 .is_visible = arm_ccn_pmu_events_is_visible,
460 .attrs = arm_ccn_pmu_events_attrs,
461 };
462
463
464 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
465 {
466 unsigned long i;
467
468 if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
469 return NULL;
470 i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
471
472 switch (name[1]) {
473 case 'l':
474 return &ccn->dt.cmp_mask[i].l;
475 case 'h':
476 return &ccn->dt.cmp_mask[i].h;
477 default:
478 return NULL;
479 }
480 }
481
482 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
483 struct device_attribute *attr, char *buf)
484 {
485 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
486 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
487
488 return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
489 }
490
491 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
492 struct device_attribute *attr, const char *buf, size_t count)
493 {
494 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
495 u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
496 int err = -EINVAL;
497
498 if (mask)
499 err = kstrtoull(buf, 0, mask);
500
501 return err ? err : count;
502 }
503
504 #define CCN_CMP_MASK_ATTR(_name) \
505 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
506 __ATTR(_name, S_IRUGO | S_IWUSR, \
507 arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
508
509 #define CCN_CMP_MASK_ATTR_RO(_name) \
510 struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
511 __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
512
513 static CCN_CMP_MASK_ATTR(0l);
514 static CCN_CMP_MASK_ATTR(0h);
515 static CCN_CMP_MASK_ATTR(1l);
516 static CCN_CMP_MASK_ATTR(1h);
517 static CCN_CMP_MASK_ATTR(2l);
518 static CCN_CMP_MASK_ATTR(2h);
519 static CCN_CMP_MASK_ATTR(3l);
520 static CCN_CMP_MASK_ATTR(3h);
521 static CCN_CMP_MASK_ATTR(4l);
522 static CCN_CMP_MASK_ATTR(4h);
523 static CCN_CMP_MASK_ATTR(5l);
524 static CCN_CMP_MASK_ATTR(5h);
525 static CCN_CMP_MASK_ATTR(6l);
526 static CCN_CMP_MASK_ATTR(6h);
527 static CCN_CMP_MASK_ATTR(7l);
528 static CCN_CMP_MASK_ATTR(7h);
529 static CCN_CMP_MASK_ATTR_RO(8l);
530 static CCN_CMP_MASK_ATTR_RO(8h);
531 static CCN_CMP_MASK_ATTR_RO(9l);
532 static CCN_CMP_MASK_ATTR_RO(9h);
533 static CCN_CMP_MASK_ATTR_RO(al);
534 static CCN_CMP_MASK_ATTR_RO(ah);
535 static CCN_CMP_MASK_ATTR_RO(bl);
536 static CCN_CMP_MASK_ATTR_RO(bh);
537
538 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
539 &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
540 &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
541 &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
542 &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
543 &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
544 &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
545 &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
546 &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
547 &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
548 &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
549 &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
550 &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
551 NULL
552 };
553
554 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
555 .name = "cmp_mask",
556 .attrs = arm_ccn_pmu_cmp_mask_attrs,
557 };
558
559 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
560 struct device_attribute *attr, char *buf)
561 {
562 struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
563
564 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
565 }
566
567 static struct device_attribute arm_ccn_pmu_cpumask_attr =
568 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
569
570 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
571 &arm_ccn_pmu_cpumask_attr.attr,
572 NULL,
573 };
574
575 static struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
576 .attrs = arm_ccn_pmu_cpumask_attrs,
577 };
578
579 /*
580 * Default poll period is 10ms, which is way over the top anyway,
581 * as in the worst case scenario (an event every cycle), with 1GHz
582 * clocked bus, the smallest, 32 bit counter will overflow in
583 * more than 4s.
584 */
585 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
586 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
587 S_IRUGO | S_IWUSR);
588
589 static ktime_t arm_ccn_pmu_timer_period(void)
590 {
591 return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
592 }
593
594
595 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
596 &arm_ccn_pmu_events_attr_group,
597 &arm_ccn_pmu_format_attr_group,
598 &arm_ccn_pmu_cmp_mask_attr_group,
599 &arm_ccn_pmu_cpumask_attr_group,
600 NULL
601 };
602
603
604 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
605 {
606 int bit;
607
608 do {
609 bit = find_first_zero_bit(bitmap, size);
610 if (bit >= size)
611 return -EAGAIN;
612 } while (test_and_set_bit(bit, bitmap));
613
614 return bit;
615 }
616
617 /* All RN-I and RN-D nodes have identical PMUs */
618 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
619 {
620 if (a == b)
621 return 1;
622
623 switch (a) {
624 case CCN_TYPE_RNI_1P:
625 case CCN_TYPE_RNI_2P:
626 case CCN_TYPE_RNI_3P:
627 case CCN_TYPE_RND_1P:
628 case CCN_TYPE_RND_2P:
629 case CCN_TYPE_RND_3P:
630 switch (b) {
631 case CCN_TYPE_RNI_1P:
632 case CCN_TYPE_RNI_2P:
633 case CCN_TYPE_RNI_3P:
634 case CCN_TYPE_RND_1P:
635 case CCN_TYPE_RND_2P:
636 case CCN_TYPE_RND_3P:
637 return 1;
638 }
639 break;
640 }
641
642 return 0;
643 }
644
645 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
646 {
647 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
648 struct hw_perf_event *hw = &event->hw;
649 u32 node_xp, type, event_id;
650 struct arm_ccn_component *source;
651 int bit;
652
653 node_xp = CCN_CONFIG_NODE(event->attr.config);
654 type = CCN_CONFIG_TYPE(event->attr.config);
655 event_id = CCN_CONFIG_EVENT(event->attr.config);
656
657 /* Allocate the cycle counter */
658 if (type == CCN_TYPE_CYCLES) {
659 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
660 ccn->dt.pmu_counters_mask))
661 return -EAGAIN;
662
663 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
664 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
665
666 return 0;
667 }
668
669 /* Allocate an event counter */
670 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
671 CCN_NUM_PMU_EVENT_COUNTERS);
672 if (hw->idx < 0) {
673 dev_dbg(ccn->dev, "No more counters available!\n");
674 return -EAGAIN;
675 }
676
677 if (type == CCN_TYPE_XP)
678 source = &ccn->xp[node_xp];
679 else
680 source = &ccn->node[node_xp];
681 ccn->dt.pmu_counters[hw->idx].source = source;
682
683 /* Allocate an event source or a watchpoint */
684 if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
685 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
686 CCN_NUM_XP_WATCHPOINTS);
687 else
688 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
689 CCN_NUM_PMU_EVENTS);
690 if (bit < 0) {
691 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
692 node_xp);
693 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
694 return -EAGAIN;
695 }
696 hw->config_base = bit;
697
698 ccn->dt.pmu_counters[hw->idx].event = event;
699
700 return 0;
701 }
702
703 static void arm_ccn_pmu_event_release(struct perf_event *event)
704 {
705 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
706 struct hw_perf_event *hw = &event->hw;
707
708 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
709 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
710 } else {
711 struct arm_ccn_component *source =
712 ccn->dt.pmu_counters[hw->idx].source;
713
714 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
715 CCN_CONFIG_EVENT(event->attr.config) ==
716 CCN_EVENT_WATCHPOINT)
717 clear_bit(hw->config_base, source->xp.dt_cmp_mask);
718 else
719 clear_bit(hw->config_base, source->pmu_events_mask);
720 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
721 }
722
723 ccn->dt.pmu_counters[hw->idx].source = NULL;
724 ccn->dt.pmu_counters[hw->idx].event = NULL;
725 }
726
727 static int arm_ccn_pmu_event_init(struct perf_event *event)
728 {
729 struct arm_ccn *ccn;
730 struct hw_perf_event *hw = &event->hw;
731 u32 node_xp, type, event_id;
732 int valid;
733 int i;
734 struct perf_event *sibling;
735
736 if (event->attr.type != event->pmu->type)
737 return -ENOENT;
738
739 ccn = pmu_to_arm_ccn(event->pmu);
740
741 if (hw->sample_period) {
742 dev_warn(ccn->dev, "Sampling not supported!\n");
743 return -EOPNOTSUPP;
744 }
745
746 if (has_branch_stack(event) || event->attr.exclude_user ||
747 event->attr.exclude_kernel || event->attr.exclude_hv ||
748 event->attr.exclude_idle || event->attr.exclude_host ||
749 event->attr.exclude_guest) {
750 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
751 return -EINVAL;
752 }
753
754 if (event->cpu < 0) {
755 dev_warn(ccn->dev, "Can't provide per-task data!\n");
756 return -EOPNOTSUPP;
757 }
758 /*
759 * Many perf core operations (eg. events rotation) operate on a
760 * single CPU context. This is obvious for CPU PMUs, where one
761 * expects the same sets of events being observed on all CPUs,
762 * but can lead to issues for off-core PMUs, like CCN, where each
763 * event could be theoretically assigned to a different CPU. To
764 * mitigate this, we enforce CPU assignment to one, selected
765 * processor (the one described in the "cpumask" attribute).
766 */
767 event->cpu = cpumask_first(&ccn->dt.cpu);
768
769 node_xp = CCN_CONFIG_NODE(event->attr.config);
770 type = CCN_CONFIG_TYPE(event->attr.config);
771 event_id = CCN_CONFIG_EVENT(event->attr.config);
772
773 /* Validate node/xp vs topology */
774 switch (type) {
775 case CCN_TYPE_MN:
776 if (node_xp != ccn->mn_id) {
777 dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
778 return -EINVAL;
779 }
780 break;
781 case CCN_TYPE_XP:
782 if (node_xp >= ccn->num_xps) {
783 dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
784 return -EINVAL;
785 }
786 break;
787 case CCN_TYPE_CYCLES:
788 break;
789 default:
790 if (node_xp >= ccn->num_nodes) {
791 dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
792 return -EINVAL;
793 }
794 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
795 dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
796 type, node_xp);
797 return -EINVAL;
798 }
799 break;
800 }
801
802 /* Validate event ID vs available for the type */
803 for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
804 i++) {
805 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
806 u32 port = CCN_CONFIG_PORT(event->attr.config);
807 u32 vc = CCN_CONFIG_VC(event->attr.config);
808
809 if (!arm_ccn_pmu_type_eq(type, e->type))
810 continue;
811 if (event_id != e->event)
812 continue;
813 if (e->num_ports && port >= e->num_ports) {
814 dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
815 port, node_xp);
816 return -EINVAL;
817 }
818 if (e->num_vcs && vc >= e->num_vcs) {
819 dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
820 vc, node_xp);
821 return -EINVAL;
822 }
823 valid = 1;
824 }
825 if (!valid) {
826 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
827 event_id, node_xp);
828 return -EINVAL;
829 }
830
831 /* Watchpoint-based event for a node is actually set on XP */
832 if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
833 u32 port;
834
835 type = CCN_TYPE_XP;
836 port = arm_ccn_node_to_xp_port(node_xp);
837 node_xp = arm_ccn_node_to_xp(node_xp);
838
839 arm_ccn_pmu_config_set(&event->attr.config,
840 node_xp, type, port);
841 }
842
843 /*
844 * We must NOT create groups containing mixed PMUs, although software
845 * events are acceptable (for example to create a CCN group
846 * periodically read when a hrtimer aka cpu-clock leader triggers).
847 */
848 if (event->group_leader->pmu != event->pmu &&
849 !is_software_event(event->group_leader))
850 return -EINVAL;
851
852 list_for_each_entry(sibling, &event->group_leader->sibling_list,
853 group_entry)
854 if (sibling->pmu != event->pmu &&
855 !is_software_event(sibling))
856 return -EINVAL;
857
858 return 0;
859 }
860
861 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
862 {
863 u64 res;
864
865 if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
866 #ifdef readq
867 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
868 #else
869 /* 40 bit counter, can do snapshot and read in two parts */
870 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
871 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
872 ;
873 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
874 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
875 res <<= 32;
876 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
877 #endif
878 } else {
879 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
880 }
881
882 return res;
883 }
884
885 static void arm_ccn_pmu_event_update(struct perf_event *event)
886 {
887 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
888 struct hw_perf_event *hw = &event->hw;
889 u64 prev_count, new_count, mask;
890
891 do {
892 prev_count = local64_read(&hw->prev_count);
893 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
894 } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
895
896 mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
897
898 local64_add((new_count - prev_count) & mask, &event->count);
899 }
900
901 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
902 {
903 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
904 struct hw_perf_event *hw = &event->hw;
905 struct arm_ccn_component *xp;
906 u32 val, dt_cfg;
907
908 /* Nothing to do for cycle counter */
909 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
910 return;
911
912 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
913 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
914 else
915 xp = &ccn->xp[arm_ccn_node_to_xp(
916 CCN_CONFIG_NODE(event->attr.config))];
917
918 if (enable)
919 dt_cfg = hw->event_base;
920 else
921 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
922
923 spin_lock(&ccn->dt.config_lock);
924
925 val = readl(xp->base + CCN_XP_DT_CONFIG);
926 val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
927 CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
928 val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
929 writel(val, xp->base + CCN_XP_DT_CONFIG);
930
931 spin_unlock(&ccn->dt.config_lock);
932 }
933
934 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
935 {
936 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
937 struct hw_perf_event *hw = &event->hw;
938
939 local64_set(&event->hw.prev_count,
940 arm_ccn_pmu_read_counter(ccn, hw->idx));
941 hw->state = 0;
942
943 /* Set the DT bus input, engaging the counter */
944 arm_ccn_pmu_xp_dt_config(event, 1);
945 }
946
947 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
948 {
949 struct hw_perf_event *hw = &event->hw;
950
951 /* Disable counting, setting the DT bus to pass-through mode */
952 arm_ccn_pmu_xp_dt_config(event, 0);
953
954 if (flags & PERF_EF_UPDATE)
955 arm_ccn_pmu_event_update(event);
956
957 hw->state |= PERF_HES_STOPPED;
958 }
959
960 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
961 {
962 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
963 struct hw_perf_event *hw = &event->hw;
964 struct arm_ccn_component *source =
965 ccn->dt.pmu_counters[hw->idx].source;
966 unsigned long wp = hw->config_base;
967 u32 val;
968 u64 cmp_l = event->attr.config1;
969 u64 cmp_h = event->attr.config2;
970 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
971 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
972
973 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
974
975 /* Direction (RX/TX), device (port) & virtual channel */
976 val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
977 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
978 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
979 val |= CCN_CONFIG_DIR(event->attr.config) <<
980 CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
981 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
982 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
983 val |= CCN_CONFIG_PORT(event->attr.config) <<
984 CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
985 val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
986 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
987 val |= CCN_CONFIG_VC(event->attr.config) <<
988 CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
989 writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
990
991 /* Comparison values */
992 writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
993 writel((cmp_l >> 32) & 0x7fffffff,
994 source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
995 writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
996 writel((cmp_h >> 32) & 0x0fffffff,
997 source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
998
999 /* Mask */
1000 writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
1001 writel((mask_l >> 32) & 0x7fffffff,
1002 source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
1003 writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
1004 writel((mask_h >> 32) & 0x0fffffff,
1005 source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1006 }
1007
1008 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1009 {
1010 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1011 struct hw_perf_event *hw = &event->hw;
1012 struct arm_ccn_component *source =
1013 ccn->dt.pmu_counters[hw->idx].source;
1014 u32 val, id;
1015
1016 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1017
1018 id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1019 (CCN_CONFIG_BUS(event->attr.config) << 3) |
1020 (CCN_CONFIG_EVENT(event->attr.config) << 0);
1021
1022 val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1023 val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1024 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1025 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1026 writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1027 }
1028
1029 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1030 {
1031 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1032 struct hw_perf_event *hw = &event->hw;
1033 struct arm_ccn_component *source =
1034 ccn->dt.pmu_counters[hw->idx].source;
1035 u32 type = CCN_CONFIG_TYPE(event->attr.config);
1036 u32 val, port;
1037
1038 port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1039 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1040 hw->config_base);
1041
1042 /* These *_event_sel regs should be identical, but let's make sure... */
1043 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1044 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1045 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1046 CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1047 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1048 CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1049 BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1050 CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1051 BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1052 CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1053 if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1054 !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1055 return;
1056
1057 /* Set the event id for the pre-allocated counter */
1058 val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1059 val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1060 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1061 val |= CCN_CONFIG_EVENT(event->attr.config) <<
1062 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1063 writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1064 }
1065
1066 static void arm_ccn_pmu_event_config(struct perf_event *event)
1067 {
1068 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1069 struct hw_perf_event *hw = &event->hw;
1070 u32 xp, offset, val;
1071
1072 /* Cycle counter requires no setup */
1073 if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1074 return;
1075
1076 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1077 xp = CCN_CONFIG_XP(event->attr.config);
1078 else
1079 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1080
1081 spin_lock(&ccn->dt.config_lock);
1082
1083 /* Set the DT bus "distance" register */
1084 offset = (hw->idx / 4) * 4;
1085 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1086 val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1087 CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1088 val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1089 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1090
1091 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1092 if (CCN_CONFIG_EVENT(event->attr.config) ==
1093 CCN_EVENT_WATCHPOINT)
1094 arm_ccn_pmu_xp_watchpoint_config(event);
1095 else
1096 arm_ccn_pmu_xp_event_config(event);
1097 } else {
1098 arm_ccn_pmu_node_event_config(event);
1099 }
1100
1101 spin_unlock(&ccn->dt.config_lock);
1102 }
1103
1104 static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1105 {
1106 return bitmap_weight(ccn->dt.pmu_counters_mask,
1107 CCN_NUM_PMU_EVENT_COUNTERS + 1);
1108 }
1109
1110 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1111 {
1112 int err;
1113 struct hw_perf_event *hw = &event->hw;
1114 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1115
1116 err = arm_ccn_pmu_event_alloc(event);
1117 if (err)
1118 return err;
1119
1120 /*
1121 * Pin the timer, so that the overflows are handled by the chosen
1122 * event->cpu (this is the same one as presented in "cpumask"
1123 * attribute).
1124 */
1125 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1126 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1127 HRTIMER_MODE_REL_PINNED);
1128
1129 arm_ccn_pmu_event_config(event);
1130
1131 hw->state = PERF_HES_STOPPED;
1132
1133 if (flags & PERF_EF_START)
1134 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1135
1136 return 0;
1137 }
1138
1139 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1140 {
1141 struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1142
1143 arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1144
1145 arm_ccn_pmu_event_release(event);
1146
1147 if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1148 hrtimer_cancel(&ccn->dt.hrtimer);
1149 }
1150
1151 static void arm_ccn_pmu_event_read(struct perf_event *event)
1152 {
1153 arm_ccn_pmu_event_update(event);
1154 }
1155
1156 static void arm_ccn_pmu_enable(struct pmu *pmu)
1157 {
1158 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1159
1160 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1161 val |= CCN_DT_PMCR__PMU_EN;
1162 writel(val, ccn->dt.base + CCN_DT_PMCR);
1163 }
1164
1165 static void arm_ccn_pmu_disable(struct pmu *pmu)
1166 {
1167 struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1168
1169 u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1170 val &= ~CCN_DT_PMCR__PMU_EN;
1171 writel(val, ccn->dt.base + CCN_DT_PMCR);
1172 }
1173
1174 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1175 {
1176 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1177 int idx;
1178
1179 if (!pmovsr)
1180 return IRQ_NONE;
1181
1182 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1183
1184 BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1185
1186 for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1187 struct perf_event *event = dt->pmu_counters[idx].event;
1188 int overflowed = pmovsr & BIT(idx);
1189
1190 WARN_ON_ONCE(overflowed && !event &&
1191 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1192
1193 if (!event || !overflowed)
1194 continue;
1195
1196 arm_ccn_pmu_event_update(event);
1197 }
1198
1199 return IRQ_HANDLED;
1200 }
1201
1202 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1203 {
1204 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1205 hrtimer);
1206 unsigned long flags;
1207
1208 local_irq_save(flags);
1209 arm_ccn_pmu_overflow_handler(dt);
1210 local_irq_restore(flags);
1211
1212 hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1213 return HRTIMER_RESTART;
1214 }
1215
1216
1217 static int arm_ccn_pmu_offline_cpu(unsigned int cpu)
1218 {
1219 struct arm_ccn_dt *dt;
1220 unsigned int target;
1221
1222 mutex_lock(&arm_ccn_mutex);
1223 list_for_each_entry(dt, &arm_ccn_list, entry) {
1224 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1225
1226 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1227 continue;
1228 target = cpumask_any_but(cpu_online_mask, cpu);
1229 if (target >= nr_cpu_ids)
1230 continue;
1231 perf_pmu_migrate_context(&dt->pmu, cpu, target);
1232 cpumask_set_cpu(target, &dt->cpu);
1233 if (ccn->irq)
1234 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0);
1235 }
1236 mutex_unlock(&arm_ccn_mutex);
1237 return 0;
1238 }
1239
1240
1241 static DEFINE_IDA(arm_ccn_pmu_ida);
1242
1243 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1244 {
1245 int i;
1246 char *name;
1247 int err;
1248
1249 /* Initialize DT subsystem */
1250 ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1251 spin_lock_init(&ccn->dt.config_lock);
1252 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1253 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1254 writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1255 ccn->dt.base + CCN_DT_PMCR);
1256 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1257 for (i = 0; i < ccn->num_xps; i++) {
1258 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1259 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1260 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1261 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1262 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1263 CCN_XP_DT_CONTROL__DT_ENABLE,
1264 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1265 }
1266 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1267 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1268 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1269 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1270 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1271 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1272 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1273 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1274
1275 /* Get a convenient /sys/event_source/devices/ name */
1276 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1277 if (ccn->dt.id == 0) {
1278 name = "ccn";
1279 } else {
1280 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1281
1282 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1283 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1284 }
1285
1286 /* Perf driver registration */
1287 ccn->dt.pmu = (struct pmu) {
1288 .attr_groups = arm_ccn_pmu_attr_groups,
1289 .task_ctx_nr = perf_invalid_context,
1290 .event_init = arm_ccn_pmu_event_init,
1291 .add = arm_ccn_pmu_event_add,
1292 .del = arm_ccn_pmu_event_del,
1293 .start = arm_ccn_pmu_event_start,
1294 .stop = arm_ccn_pmu_event_stop,
1295 .read = arm_ccn_pmu_event_read,
1296 .pmu_enable = arm_ccn_pmu_enable,
1297 .pmu_disable = arm_ccn_pmu_disable,
1298 };
1299
1300 /* No overflow interrupt? Have to use a timer instead. */
1301 if (!ccn->irq) {
1302 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1303 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1304 HRTIMER_MODE_REL);
1305 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1306 }
1307
1308 /* Pick one CPU which we will use to collect data from CCN... */
1309 cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);
1310
1311 /* Also make sure that the overflow interrupt is handled by this CPU */
1312 if (ccn->irq) {
1313 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu);
1314 if (err) {
1315 dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1316 goto error_set_affinity;
1317 }
1318 }
1319
1320 err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1321 if (err)
1322 goto error_pmu_register;
1323
1324 mutex_lock(&arm_ccn_mutex);
1325 list_add(&ccn->dt.entry, &arm_ccn_list);
1326 mutex_unlock(&arm_ccn_mutex);
1327 return 0;
1328
1329 error_pmu_register:
1330 error_set_affinity:
1331 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1332 for (i = 0; i < ccn->num_xps; i++)
1333 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1334 writel(0, ccn->dt.base + CCN_DT_PMCR);
1335 return err;
1336 }
1337
1338 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1339 {
1340 int i;
1341
1342 mutex_lock(&arm_ccn_mutex);
1343 list_del(&ccn->dt.entry);
1344 mutex_unlock(&arm_ccn_mutex);
1345
1346 if (ccn->irq)
1347 irq_set_affinity_hint(ccn->irq, NULL);
1348 for (i = 0; i < ccn->num_xps; i++)
1349 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1350 writel(0, ccn->dt.base + CCN_DT_PMCR);
1351 perf_pmu_unregister(&ccn->dt.pmu);
1352 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1353 }
1354
1355 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1356 int (*callback)(struct arm_ccn *ccn, int region,
1357 void __iomem *base, u32 type, u32 id))
1358 {
1359 int region;
1360
1361 for (region = 0; region < CCN_NUM_REGIONS; region++) {
1362 u32 val, type, id;
1363 void __iomem *base;
1364 int err;
1365
1366 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1367 4 * (region / 32));
1368 if (!(val & (1 << (region % 32))))
1369 continue;
1370
1371 base = ccn->base + region * CCN_REGION_SIZE;
1372 val = readl(base + CCN_ALL_OLY_ID);
1373 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1374 CCN_ALL_OLY_ID__OLY_ID__MASK;
1375 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1376 CCN_ALL_OLY_ID__NODE_ID__MASK;
1377
1378 err = callback(ccn, region, base, type, id);
1379 if (err)
1380 return err;
1381 }
1382
1383 return 0;
1384 }
1385
1386 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1387 void __iomem *base, u32 type, u32 id)
1388 {
1389
1390 if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1391 ccn->num_xps = id + 1;
1392 else if (id >= ccn->num_nodes)
1393 ccn->num_nodes = id + 1;
1394
1395 return 0;
1396 }
1397
1398 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1399 void __iomem *base, u32 type, u32 id)
1400 {
1401 struct arm_ccn_component *component;
1402
1403 dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1404
1405 switch (type) {
1406 case CCN_TYPE_MN:
1407 ccn->mn_id = id;
1408 return 0;
1409 case CCN_TYPE_DT:
1410 return 0;
1411 case CCN_TYPE_XP:
1412 component = &ccn->xp[id];
1413 break;
1414 case CCN_TYPE_SBSX:
1415 ccn->sbsx_present = 1;
1416 component = &ccn->node[id];
1417 break;
1418 case CCN_TYPE_SBAS:
1419 ccn->sbas_present = 1;
1420 /* Fall-through */
1421 default:
1422 component = &ccn->node[id];
1423 break;
1424 }
1425
1426 component->base = base;
1427 component->type = type;
1428
1429 return 0;
1430 }
1431
1432
1433 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1434 const u32 *err_sig_val)
1435 {
1436 /* This should be really handled by firmware... */
1437 dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1438 err_sig_val[5], err_sig_val[4], err_sig_val[3],
1439 err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1440 dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1441 writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1442 ccn->base + CCN_MN_ERRINT_STATUS);
1443
1444 return IRQ_HANDLED;
1445 }
1446
1447
1448 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1449 {
1450 irqreturn_t res = IRQ_NONE;
1451 struct arm_ccn *ccn = dev_id;
1452 u32 err_sig_val[6];
1453 u32 err_or;
1454 int i;
1455
1456 /* PMU overflow is a special case */
1457 err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1458 if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1459 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1460 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1461 }
1462
1463 /* Have to read all err_sig_vals to clear them */
1464 for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1465 err_sig_val[i] = readl(ccn->base +
1466 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1467 err_or |= err_sig_val[i];
1468 }
1469 if (err_or)
1470 res |= arm_ccn_error_handler(ccn, err_sig_val);
1471
1472 if (res != IRQ_NONE)
1473 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1474 ccn->base + CCN_MN_ERRINT_STATUS);
1475
1476 return res;
1477 }
1478
1479
1480 static int arm_ccn_probe(struct platform_device *pdev)
1481 {
1482 struct arm_ccn *ccn;
1483 struct resource *res;
1484 unsigned int irq;
1485 int err;
1486
1487 ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1488 if (!ccn)
1489 return -ENOMEM;
1490 ccn->dev = &pdev->dev;
1491 platform_set_drvdata(pdev, ccn);
1492
1493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 if (!res)
1495 return -EINVAL;
1496
1497 if (!devm_request_mem_region(ccn->dev, res->start,
1498 resource_size(res), pdev->name))
1499 return -EBUSY;
1500
1501 ccn->base = devm_ioremap(ccn->dev, res->start,
1502 resource_size(res));
1503 if (!ccn->base)
1504 return -EFAULT;
1505
1506 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1507 if (!res)
1508 return -EINVAL;
1509 irq = res->start;
1510
1511 /* Check if we can use the interrupt */
1512 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1513 ccn->base + CCN_MN_ERRINT_STATUS);
1514 if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1515 CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1516 /* Can set 'disable' bits, so can acknowledge interrupts */
1517 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1518 ccn->base + CCN_MN_ERRINT_STATUS);
1519 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1520 IRQF_NOBALANCING | IRQF_NO_THREAD,
1521 dev_name(ccn->dev), ccn);
1522 if (err)
1523 return err;
1524
1525 ccn->irq = irq;
1526 }
1527
1528
1529 /* Build topology */
1530
1531 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1532 if (err)
1533 return err;
1534
1535 ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1536 GFP_KERNEL);
1537 ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1538 GFP_KERNEL);
1539 if (!ccn->node || !ccn->xp)
1540 return -ENOMEM;
1541
1542 err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1543 if (err)
1544 return err;
1545
1546 return arm_ccn_pmu_init(ccn);
1547 }
1548
1549 static int arm_ccn_remove(struct platform_device *pdev)
1550 {
1551 struct arm_ccn *ccn = platform_get_drvdata(pdev);
1552
1553 arm_ccn_pmu_cleanup(ccn);
1554
1555 return 0;
1556 }
1557
1558 static const struct of_device_id arm_ccn_match[] = {
1559 { .compatible = "arm,ccn-504", },
1560 {},
1561 };
1562
1563 static struct platform_driver arm_ccn_driver = {
1564 .driver = {
1565 .name = "arm-ccn",
1566 .of_match_table = arm_ccn_match,
1567 },
1568 .probe = arm_ccn_probe,
1569 .remove = arm_ccn_remove,
1570 };
1571
1572 static int __init arm_ccn_init(void)
1573 {
1574 int i, ret;
1575
1576 ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1577 "AP_PERF_ARM_CCN_ONLINE", NULL,
1578 arm_ccn_pmu_offline_cpu);
1579 if (ret)
1580 return ret;
1581
1582 for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1583 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1584
1585 return platform_driver_register(&arm_ccn_driver);
1586 }
1587
1588 static void __exit arm_ccn_exit(void)
1589 {
1590 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1591 platform_driver_unregister(&arm_ccn_driver);
1592 }
1593
1594 module_init(arm_ccn_init);
1595 module_exit(arm_ccn_exit);
1596
1597 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1598 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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