drivers/clk/meson/clkc.h

   1 /*
   2  * Copyright (c) 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __CLKC_H
  19 #define __CLKC_H
  20
  21 #define PMASK(width)                    GENMASK(width - 1, 0)
  22 #define SETPMASK(width, shift)          GENMASK(shift + width - 1, shift)
  23 #define CLRPMASK(width, shift)          (~SETPMASK(width, shift))
  24
  25 #define PARM_GET(width, shift, reg)                                     \
  26         (((reg) & SETPMASK(width, shift)) >> (shift))
  27 #define PARM_SET(width, shift, reg, val)                                \
  28         (((reg) & CLRPMASK(width, shift)) | (val << (shift)))
  29
  30 #define MESON_PARM_APPLICABLE(p)                (!!((p)->width))
  31
  32 struct parm {
  33         u16     reg_off;
  34         u8      shift;
  35         u8      width;
  36 };
  37
  38 struct pll_rate_table {
  39         unsigned long   rate;
  40         u16             m;
  41         u16             n;
  42         u16             od;
  43         u16             od2;
  44         u16             frac;
  45 };
  46
  47 #define PLL_RATE(_r, _m, _n, _od)                                       \
  48         {                                                               \
  49                 .rate           = (_r),                                 \
  50                 .m              = (_m),                                 \
  51                 .n              = (_n),                                 \
  52                 .od             = (_od),                                \
  53         }                                                               \
  54
  55 #define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac)                     \
  56         {                                                               \
  57                 .rate           = (_r),                                 \
  58                 .m              = (_m),                                 \
  59                 .n              = (_n),                                 \
  60                 .od             = (_od),                                \
  61                 .od2            = (_od2),                               \
  62                 .frac           = (_frac),                              \
  63         }                                                               \
  64
  65 struct meson_clk_pll {
  66         struct clk_hw hw;
  67         void __iomem *base;
  68         struct parm m;
  69         struct parm n;
  70         struct parm frac;
  71         struct parm od;
  72         struct parm od2;
  73         const struct pll_rate_table *rate_table;
  74         unsigned int rate_count;
  75         spinlock_t *lock;
  76 };
  77
  78 #define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
  79
  80 struct meson_clk_cpu {
  81         struct clk_hw hw;
  82         void __iomem *base;
  83         u16 reg_off;
  84         struct notifier_block clk_nb;
  85         const struct clk_div_table *div_table;
  86 };
  87
  88 int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event,
  89                 void *data);
  90
  91 struct meson_clk_mpll {
  92         struct clk_hw hw;
  93         void __iomem *base;
  94         struct parm sdm;
  95         struct parm n2;
  96         /* FIXME ssen gate control? */
  97         spinlock_t *lock;
  98 };
  99
 100 #define MESON_GATE(_name, _reg, _bit)                                   \
 101 struct clk_gate gxbb_##_name = {                                                \
 102         .reg = (void __iomem *) _reg,                                   \
 103         .bit_idx = (_bit),                                              \
 104         .lock = &clk_lock,                                              \
 105         .hw.init = &(struct clk_init_data) {                            \
 106                 .name = #_name,                                 \
 107                 .ops = &clk_gate_ops,                                   \
 108                 .parent_names = (const char *[]){ "clk81" },            \
 109                 .num_parents = 1,                                       \
 110                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),     \
 111         },                                                              \
 112 };
 113
 114 /* clk_ops */
 115 extern const struct clk_ops meson_clk_pll_ro_ops;
 116 extern const struct clk_ops meson_clk_pll_ops;
 117 extern const struct clk_ops meson_clk_cpu_ops;
 118 extern const struct clk_ops meson_clk_mpll_ro_ops;
 119
 120 #endif /* __CLKC_H */