drivers/clk/sunxi-ng/ccu_mp.c

   1 /*
   2  * Copyright (C) 2016 Maxime Ripard
   3  * Maxime Ripard <maxime.ripard@free-electrons.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/clk-provider.h>
  12
  13 #include "ccu_gate.h"
  14 #include "ccu_mp.h"
  15
  16 static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
  17                              unsigned int max_m, unsigned int max_p,
  18                              unsigned int *m, unsigned int *p)
  19 {
  20         unsigned long best_rate = 0;
  21         unsigned int best_m = 0, best_p = 0;
  22         unsigned int _m, _p;
  23
  24         for (_p = 0; _p <= max_p; _p++) {
  25                 for (_m = 1; _m <= max_m; _m++) {
  26                         unsigned long tmp_rate = (parent >> _p) / _m;
  27
  28                         if (tmp_rate > rate)
  29                                 continue;
  30
  31                         if ((rate - tmp_rate) < (rate - best_rate)) {
  32                                 best_rate = tmp_rate;
  33                                 best_m = _m;
  34                                 best_p = _p;
  35                         }
  36                 }
  37         }
  38
  39         *m = best_m;
  40         *p = best_p;
  41 }
  42
  43 static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
  44                                        unsigned long parent_rate,
  45                                        unsigned long rate,
  46                                        void *data)
  47 {
  48         struct ccu_mp *cmp = data;
  49         unsigned int m, p;
  50
  51         ccu_mp_find_best(parent_rate, rate,
  52                          1 << cmp->m.width, (1 << cmp->p.width) - 1,
  53                          &m, &p);
  54
  55         return (parent_rate >> p) / m;
  56 }
  57
  58 static void ccu_mp_disable(struct clk_hw *hw)
  59 {
  60         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  61
  62         return ccu_gate_helper_disable(&cmp->common, cmp->enable);
  63 }
  64
  65 static int ccu_mp_enable(struct clk_hw *hw)
  66 {
  67         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  68
  69         return ccu_gate_helper_enable(&cmp->common, cmp->enable);
  70 }
  71
  72 static int ccu_mp_is_enabled(struct clk_hw *hw)
  73 {
  74         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  75
  76         return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);
  77 }
  78
  79 static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
  80                                         unsigned long parent_rate)
  81 {
  82         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
  83         unsigned int m, p;
  84         u32 reg;
  85
  86         reg = readl(cmp->common.base + cmp->common.reg);
  87
  88         m = reg >> cmp->m.shift;
  89         m &= (1 << cmp->m.width) - 1;
  90
  91         p = reg >> cmp->p.shift;
  92         p &= (1 << cmp->p.width) - 1;
  93
  94         return (parent_rate >> p) / (m + 1);
  95 }
  96
  97 static int ccu_mp_determine_rate(struct clk_hw *hw,
  98                                  struct clk_rate_request *req)
  99 {
 100         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
 101
 102         return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,
 103                                              req, ccu_mp_round_rate, cmp);
 104 }
 105
 106 static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
 107                            unsigned long parent_rate)
 108 {
 109         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
 110         unsigned long flags;
 111         unsigned int m, p;
 112         u32 reg;
 113
 114         ccu_mp_find_best(parent_rate, rate,
 115                          1 << cmp->m.width, (1 << cmp->p.width) - 1,
 116                          &m, &p);
 117
 118
 119         spin_lock_irqsave(cmp->common.lock, flags);
 120
 121         reg = readl(cmp->common.base + cmp->common.reg);
 122         reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
 123         reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
 124
 125         writel(reg | (p << cmp->p.shift) | ((m - 1) << cmp->m.shift),
 126                cmp->common.base + cmp->common.reg);
 127
 128         spin_unlock_irqrestore(cmp->common.lock, flags);
 129
 130         return 0;
 131 }
 132
 133 static u8 ccu_mp_get_parent(struct clk_hw *hw)
 134 {
 135         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
 136
 137         return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);
 138 }
 139
 140 static int ccu_mp_set_parent(struct clk_hw *hw, u8 index)
 141 {
 142         struct ccu_mp *cmp = hw_to_ccu_mp(hw);
 143
 144         return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);
 145 }
 146
 147 const struct clk_ops ccu_mp_ops = {
 148         .disable        = ccu_mp_disable,
 149         .enable         = ccu_mp_enable,
 150         .is_enabled     = ccu_mp_is_enabled,
 151
 152         .get_parent     = ccu_mp_get_parent,
 153         .set_parent     = ccu_mp_set_parent,
 154
 155         .determine_rate = ccu_mp_determine_rate,
 156         .recalc_rate    = ccu_mp_recalc_rate,
 157         .set_rate       = ccu_mp_set_rate,
 158 };