2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
39 #define ATOM_RATIOS 0x66a
40 #define ATOM_VIDS 0x66b
41 #define ATOM_TURBO_RATIOS 0x66c
42 #define ATOM_TURBO_VIDS 0x66d
45 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
46 #define fp_toint(X) ((X) >> FRAC_BITS)
48 static inline int32_t mul_fp(int32_t x
, int32_t y
)
50 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
53 static inline int32_t div_fp(s64 x
, s64 y
)
55 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
58 static inline int ceiling_fp(int32_t x
)
63 mask
= (1 << FRAC_BITS
) - 1;
70 * struct sample - Store performance sample
71 * @core_pct_busy: Ratio of APERF/MPERF in percent, which is actual
72 * performance during last sample period
73 * @busy_scaled: Scaled busy value which is used to calculate next
74 * P state. This can be different than core_pct_busy
75 * to account for cpu idle period
76 * @aperf: Difference of actual performance frequency clock count
77 * read from APERF MSR between last and current sample
78 * @mperf: Difference of maximum performance frequency clock count
79 * read from MPERF MSR between last and current sample
80 * @tsc: Difference of time stamp counter between last and
82 * @freq: Effective frequency calculated from APERF/MPERF
83 * @time: Current time from scheduler
85 * This structure is used in the cpudata structure to store performance sample
86 * data for choosing next P State.
89 int32_t core_pct_busy
;
99 * struct pstate_data - Store P state data
100 * @current_pstate: Current requested P state
101 * @min_pstate: Min P state possible for this platform
102 * @max_pstate: Max P state possible for this platform
103 * @max_pstate_physical:This is physical Max P state for a processor
104 * This can be higher than the max_pstate which can
105 * be limited by platform thermal design power limits
106 * @scaling: Scaling factor to convert frequency to cpufreq
108 * @turbo_pstate: Max Turbo P state possible for this platform
110 * Stores the per cpu model P state limits and current P state.
116 int max_pstate_physical
;
122 * struct vid_data - Stores voltage information data
123 * @min: VID data for this platform corresponding to
125 * @max: VID data corresponding to the highest P State.
126 * @turbo: VID data for turbo P state
127 * @ratio: Ratio of (vid max - vid min) /
128 * (max P state - Min P State)
130 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
131 * This data is used in Atom platforms, where in addition to target P state,
132 * the voltage data needs to be specified to select next P State.
142 * struct _pid - Stores PID data
143 * @setpoint: Target set point for busyness or performance
144 * @integral: Storage for accumulated error values
145 * @p_gain: PID proportional gain
146 * @i_gain: PID integral gain
147 * @d_gain: PID derivative gain
148 * @deadband: PID deadband
149 * @last_err: Last error storage for integral part of PID calculation
151 * Stores PID coefficients and last error for PID controller.
164 * struct cpudata - Per CPU instance data storage
165 * @cpu: CPU number for this instance data
166 * @update_util: CPUFreq utility callback information
167 * @pstate: Stores P state limits for this CPU
168 * @vid: Stores VID limits for this CPU
169 * @pid: Stores PID parameters for this CPU
170 * @last_sample_time: Last Sample time
171 * @prev_aperf: Last APERF value read from APERF MSR
172 * @prev_mperf: Last MPERF value read from MPERF MSR
173 * @prev_tsc: Last timestamp counter (TSC) value
174 * @prev_cummulative_iowait: IO Wait time difference from last and
176 * @sample: Storage for storing last Sample data
178 * This structure stores per CPU instance data for all CPUs.
183 struct update_util_data update_util
;
185 struct pstate_data pstate
;
189 u64 last_sample_time
;
193 u64 prev_cummulative_iowait
;
194 struct sample sample
;
197 static struct cpudata
**all_cpu_data
;
200 * struct pid_adjust_policy - Stores static PID configuration data
201 * @sample_rate_ms: PID calculation sample rate in ms
202 * @sample_rate_ns: Sample rate calculation in ns
203 * @deadband: PID deadband
204 * @setpoint: PID Setpoint
205 * @p_gain_pct: PID proportional gain
206 * @i_gain_pct: PID integral gain
207 * @d_gain_pct: PID derivative gain
209 * Stores per CPU model static PID configuration data.
211 struct pstate_adjust_policy
{
222 * struct pstate_funcs - Per CPU model specific callbacks
223 * @get_max: Callback to get maximum non turbo effective P state
224 * @get_max_physical: Callback to get maximum non turbo physical P state
225 * @get_min: Callback to get minimum P state
226 * @get_turbo: Callback to get turbo P state
227 * @get_scaling: Callback to get frequency scaling factor
228 * @get_val: Callback to convert P state to actual MSR write value
229 * @get_vid: Callback to get VID data for Atom platforms
230 * @get_target_pstate: Callback to a function to calculate next P state to use
232 * Core and Atom CPU models have different way to get P State limits. This
233 * structure is used to store those callbacks.
235 struct pstate_funcs
{
236 int (*get_max
)(void);
237 int (*get_max_physical
)(void);
238 int (*get_min
)(void);
239 int (*get_turbo
)(void);
240 int (*get_scaling
)(void);
241 u64 (*get_val
)(struct cpudata
*, int pstate
);
242 void (*get_vid
)(struct cpudata
*);
243 int32_t (*get_target_pstate
)(struct cpudata
*);
247 * struct cpu_defaults- Per CPU model default config data
248 * @pid_policy: PID config data
249 * @funcs: Callback function data
251 struct cpu_defaults
{
252 struct pstate_adjust_policy pid_policy
;
253 struct pstate_funcs funcs
;
256 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
257 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
259 static struct pstate_adjust_policy pid_params
;
260 static struct pstate_funcs pstate_funcs
;
261 static int hwp_active
;
265 * struct perf_limits - Store user and policy limits
266 * @no_turbo: User requested turbo state from intel_pstate sysfs
267 * @turbo_disabled: Platform turbo status either from msr
268 * MSR_IA32_MISC_ENABLE or when maximum available pstate
269 * matches the maximum turbo pstate
270 * @max_perf_pct: Effective maximum performance limit in percentage, this
271 * is minimum of either limits enforced by cpufreq policy
272 * or limits from user set limits via intel_pstate sysfs
273 * @min_perf_pct: Effective minimum performance limit in percentage, this
274 * is maximum of either limits enforced by cpufreq policy
275 * or limits from user set limits via intel_pstate sysfs
276 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
277 * This value is used to limit max pstate
278 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
279 * This value is used to limit min pstate
280 * @max_policy_pct: The maximum performance in percentage enforced by
281 * cpufreq setpolicy interface
282 * @max_sysfs_pct: The maximum performance in percentage enforced by
283 * intel pstate sysfs interface
284 * @min_policy_pct: The minimum performance in percentage enforced by
285 * cpufreq setpolicy interface
286 * @min_sysfs_pct: The minimum performance in percentage enforced by
287 * intel pstate sysfs interface
289 * Storage for user and policy defined limits.
304 static struct perf_limits performance_limits
= {
308 .max_perf
= int_tofp(1),
310 .min_perf
= int_tofp(1),
311 .max_policy_pct
= 100,
312 .max_sysfs_pct
= 100,
317 static struct perf_limits powersave_limits
= {
321 .max_perf
= int_tofp(1),
324 .max_policy_pct
= 100,
325 .max_sysfs_pct
= 100,
330 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
331 static struct perf_limits
*limits
= &performance_limits
;
333 static struct perf_limits
*limits
= &powersave_limits
;
336 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
337 int deadband
, int integral
) {
338 pid
->setpoint
= int_tofp(setpoint
);
339 pid
->deadband
= int_tofp(deadband
);
340 pid
->integral
= int_tofp(integral
);
341 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
344 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
346 pid
->p_gain
= div_fp(percent
, 100);
349 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
351 pid
->i_gain
= div_fp(percent
, 100);
354 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
356 pid
->d_gain
= div_fp(percent
, 100);
359 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
362 int32_t pterm
, dterm
, fp_error
;
363 int32_t integral_limit
;
365 fp_error
= pid
->setpoint
- busy
;
367 if (abs(fp_error
) <= pid
->deadband
)
370 pterm
= mul_fp(pid
->p_gain
, fp_error
);
372 pid
->integral
+= fp_error
;
375 * We limit the integral here so that it will never
376 * get higher than 30. This prevents it from becoming
377 * too large an input over long periods of time and allows
378 * it to get factored out sooner.
380 * The value of 30 was chosen through experimentation.
382 integral_limit
= int_tofp(30);
383 if (pid
->integral
> integral_limit
)
384 pid
->integral
= integral_limit
;
385 if (pid
->integral
< -integral_limit
)
386 pid
->integral
= -integral_limit
;
388 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
389 pid
->last_err
= fp_error
;
391 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
392 result
= result
+ (1 << (FRAC_BITS
-1));
393 return (signed int)fp_toint(result
);
396 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
398 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
399 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
400 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
402 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
405 static inline void intel_pstate_reset_all_pid(void)
409 for_each_online_cpu(cpu
) {
410 if (all_cpu_data
[cpu
])
411 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
415 static inline void update_turbo_state(void)
420 cpu
= all_cpu_data
[0];
421 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
422 limits
->turbo_disabled
=
423 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
424 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
427 static void intel_pstate_hwp_set(const struct cpumask
*cpumask
)
429 int min
, hw_min
, max
, hw_max
, cpu
, range
, adj_range
;
432 rdmsrl(MSR_HWP_CAPABILITIES
, cap
);
433 hw_min
= HWP_LOWEST_PERF(cap
);
434 hw_max
= HWP_HIGHEST_PERF(cap
);
435 range
= hw_max
- hw_min
;
437 for_each_cpu(cpu
, cpumask
) {
438 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
439 adj_range
= limits
->min_perf_pct
* range
/ 100;
440 min
= hw_min
+ adj_range
;
441 value
&= ~HWP_MIN_PERF(~0L);
442 value
|= HWP_MIN_PERF(min
);
444 adj_range
= limits
->max_perf_pct
* range
/ 100;
445 max
= hw_min
+ adj_range
;
446 if (limits
->no_turbo
) {
447 hw_max
= HWP_GUARANTEED_PERF(cap
);
452 value
&= ~HWP_MAX_PERF(~0L);
453 value
|= HWP_MAX_PERF(max
);
454 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
458 static void intel_pstate_hwp_set_online_cpus(void)
461 intel_pstate_hwp_set(cpu_online_mask
);
465 /************************** debugfs begin ************************/
466 static int pid_param_set(void *data
, u64 val
)
469 intel_pstate_reset_all_pid();
473 static int pid_param_get(void *data
, u64
*val
)
478 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
485 static struct pid_param pid_files
[] = {
486 {"sample_rate_ms", &pid_params
.sample_rate_ms
},
487 {"d_gain_pct", &pid_params
.d_gain_pct
},
488 {"i_gain_pct", &pid_params
.i_gain_pct
},
489 {"deadband", &pid_params
.deadband
},
490 {"setpoint", &pid_params
.setpoint
},
491 {"p_gain_pct", &pid_params
.p_gain_pct
},
495 static void __init
intel_pstate_debug_expose_params(void)
497 struct dentry
*debugfs_parent
;
502 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
503 if (IS_ERR_OR_NULL(debugfs_parent
))
505 while (pid_files
[i
].name
) {
506 debugfs_create_file(pid_files
[i
].name
, 0660,
507 debugfs_parent
, pid_files
[i
].value
,
513 /************************** debugfs end ************************/
515 /************************** sysfs begin ************************/
516 #define show_one(file_name, object) \
517 static ssize_t show_##file_name \
518 (struct kobject *kobj, struct attribute *attr, char *buf) \
520 return sprintf(buf, "%u\n", limits->object); \
523 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
524 struct attribute
*attr
, char *buf
)
527 int total
, no_turbo
, turbo_pct
;
530 cpu
= all_cpu_data
[0];
532 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
533 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
534 turbo_fp
= div_fp(no_turbo
, total
);
535 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
536 return sprintf(buf
, "%u\n", turbo_pct
);
539 static ssize_t
show_num_pstates(struct kobject
*kobj
,
540 struct attribute
*attr
, char *buf
)
545 cpu
= all_cpu_data
[0];
546 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
547 return sprintf(buf
, "%u\n", total
);
550 static ssize_t
show_no_turbo(struct kobject
*kobj
,
551 struct attribute
*attr
, char *buf
)
555 update_turbo_state();
556 if (limits
->turbo_disabled
)
557 ret
= sprintf(buf
, "%u\n", limits
->turbo_disabled
);
559 ret
= sprintf(buf
, "%u\n", limits
->no_turbo
);
564 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
565 const char *buf
, size_t count
)
570 ret
= sscanf(buf
, "%u", &input
);
574 update_turbo_state();
575 if (limits
->turbo_disabled
) {
576 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
580 limits
->no_turbo
= clamp_t(int, input
, 0, 1);
583 intel_pstate_hwp_set_online_cpus();
588 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
589 const char *buf
, size_t count
)
594 ret
= sscanf(buf
, "%u", &input
);
598 limits
->max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
599 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
600 limits
->max_sysfs_pct
);
601 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
602 limits
->max_perf_pct
);
603 limits
->max_perf_pct
= max(limits
->min_perf_pct
,
604 limits
->max_perf_pct
);
605 limits
->max_perf
= div_fp(limits
->max_perf_pct
, 100);
608 intel_pstate_hwp_set_online_cpus();
612 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
613 const char *buf
, size_t count
)
618 ret
= sscanf(buf
, "%u", &input
);
622 limits
->min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
623 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
624 limits
->min_sysfs_pct
);
625 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
626 limits
->min_perf_pct
);
627 limits
->min_perf_pct
= min(limits
->max_perf_pct
,
628 limits
->min_perf_pct
);
629 limits
->min_perf
= div_fp(limits
->min_perf_pct
, 100);
632 intel_pstate_hwp_set_online_cpus();
636 show_one(max_perf_pct
, max_perf_pct
);
637 show_one(min_perf_pct
, min_perf_pct
);
639 define_one_global_rw(no_turbo
);
640 define_one_global_rw(max_perf_pct
);
641 define_one_global_rw(min_perf_pct
);
642 define_one_global_ro(turbo_pct
);
643 define_one_global_ro(num_pstates
);
645 static struct attribute
*intel_pstate_attributes
[] = {
654 static struct attribute_group intel_pstate_attr_group
= {
655 .attrs
= intel_pstate_attributes
,
658 static void __init
intel_pstate_sysfs_expose_params(void)
660 struct kobject
*intel_pstate_kobject
;
663 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
664 &cpu_subsys
.dev_root
->kobj
);
665 BUG_ON(!intel_pstate_kobject
);
666 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
669 /************************** sysfs end ************************/
671 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
673 /* First disable HWP notification interrupt as we don't process them */
674 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
676 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
679 static int atom_get_min_pstate(void)
683 rdmsrl(ATOM_RATIOS
, value
);
684 return (value
>> 8) & 0x7F;
687 static int atom_get_max_pstate(void)
691 rdmsrl(ATOM_RATIOS
, value
);
692 return (value
>> 16) & 0x7F;
695 static int atom_get_turbo_pstate(void)
699 rdmsrl(ATOM_TURBO_RATIOS
, value
);
703 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
709 val
= (u64
)pstate
<< 8;
710 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
713 vid_fp
= cpudata
->vid
.min
+ mul_fp(
714 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
717 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
718 vid
= ceiling_fp(vid_fp
);
720 if (pstate
> cpudata
->pstate
.max_pstate
)
721 vid
= cpudata
->vid
.turbo
;
726 static int silvermont_get_scaling(void)
730 /* Defined in Table 35-6 from SDM (Sept 2015) */
731 static int silvermont_freq_table
[] = {
732 83300, 100000, 133300, 116700, 80000};
734 rdmsrl(MSR_FSB_FREQ
, value
);
738 return silvermont_freq_table
[i
];
741 static int airmont_get_scaling(void)
745 /* Defined in Table 35-10 from SDM (Sept 2015) */
746 static int airmont_freq_table
[] = {
747 83300, 100000, 133300, 116700, 80000,
748 93300, 90000, 88900, 87500};
750 rdmsrl(MSR_FSB_FREQ
, value
);
754 return airmont_freq_table
[i
];
757 static void atom_get_vid(struct cpudata
*cpudata
)
761 rdmsrl(ATOM_VIDS
, value
);
762 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
763 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
764 cpudata
->vid
.ratio
= div_fp(
765 cpudata
->vid
.max
- cpudata
->vid
.min
,
766 int_tofp(cpudata
->pstate
.max_pstate
-
767 cpudata
->pstate
.min_pstate
));
769 rdmsrl(ATOM_TURBO_VIDS
, value
);
770 cpudata
->vid
.turbo
= value
& 0x7f;
773 static int core_get_min_pstate(void)
777 rdmsrl(MSR_PLATFORM_INFO
, value
);
778 return (value
>> 40) & 0xFF;
781 static int core_get_max_pstate_physical(void)
785 rdmsrl(MSR_PLATFORM_INFO
, value
);
786 return (value
>> 8) & 0xFF;
789 static int core_get_max_pstate(void)
796 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
797 max_pstate
= (plat_info
>> 8) & 0xFF;
799 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
801 /* Do some sanity checking for safety */
802 if (plat_info
& 0x600000000) {
807 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
811 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ tdp_ctrl
;
812 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
816 if (tdp_ratio
- 1 == tar
) {
818 pr_debug("max_pstate=TAC %x\n", max_pstate
);
829 static int core_get_turbo_pstate(void)
834 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
835 nont
= core_get_max_pstate();
842 static inline int core_get_scaling(void)
847 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
851 val
= (u64
)pstate
<< 8;
852 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
858 static int knl_get_turbo_pstate(void)
863 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
864 nont
= core_get_max_pstate();
865 ret
= (((value
) >> 8) & 0xFF);
871 static struct cpu_defaults core_params
= {
873 .sample_rate_ms
= 10,
881 .get_max
= core_get_max_pstate
,
882 .get_max_physical
= core_get_max_pstate_physical
,
883 .get_min
= core_get_min_pstate
,
884 .get_turbo
= core_get_turbo_pstate
,
885 .get_scaling
= core_get_scaling
,
886 .get_val
= core_get_val
,
887 .get_target_pstate
= get_target_pstate_use_performance
,
891 static struct cpu_defaults silvermont_params
= {
893 .sample_rate_ms
= 10,
901 .get_max
= atom_get_max_pstate
,
902 .get_max_physical
= atom_get_max_pstate
,
903 .get_min
= atom_get_min_pstate
,
904 .get_turbo
= atom_get_turbo_pstate
,
905 .get_val
= atom_get_val
,
906 .get_scaling
= silvermont_get_scaling
,
907 .get_vid
= atom_get_vid
,
908 .get_target_pstate
= get_target_pstate_use_cpu_load
,
912 static struct cpu_defaults airmont_params
= {
914 .sample_rate_ms
= 10,
922 .get_max
= atom_get_max_pstate
,
923 .get_max_physical
= atom_get_max_pstate
,
924 .get_min
= atom_get_min_pstate
,
925 .get_turbo
= atom_get_turbo_pstate
,
926 .get_val
= atom_get_val
,
927 .get_scaling
= airmont_get_scaling
,
928 .get_vid
= atom_get_vid
,
929 .get_target_pstate
= get_target_pstate_use_cpu_load
,
933 static struct cpu_defaults knl_params
= {
935 .sample_rate_ms
= 10,
943 .get_max
= core_get_max_pstate
,
944 .get_max_physical
= core_get_max_pstate_physical
,
945 .get_min
= core_get_min_pstate
,
946 .get_turbo
= knl_get_turbo_pstate
,
947 .get_scaling
= core_get_scaling
,
948 .get_val
= core_get_val
,
949 .get_target_pstate
= get_target_pstate_use_performance
,
953 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
955 int max_perf
= cpu
->pstate
.turbo_pstate
;
959 if (limits
->no_turbo
|| limits
->turbo_disabled
)
960 max_perf
= cpu
->pstate
.max_pstate
;
963 * performance can be limited by user through sysfs, by cpufreq
964 * policy, or by cpu specific default values determined through
967 max_perf_adj
= fp_toint(max_perf
* limits
->max_perf
);
968 *max
= clamp_t(int, max_perf_adj
,
969 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
971 min_perf
= fp_toint(max_perf
* limits
->min_perf
);
972 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
975 static inline void intel_pstate_record_pstate(struct cpudata
*cpu
, int pstate
)
977 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
978 cpu
->pstate
.current_pstate
= pstate
;
981 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
983 int pstate
= cpu
->pstate
.min_pstate
;
985 intel_pstate_record_pstate(cpu
, pstate
);
987 * Generally, there is no guarantee that this code will always run on
988 * the CPU being updated, so force the register update to run on the
991 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
992 pstate_funcs
.get_val(cpu
, pstate
));
995 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
997 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
998 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
999 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1000 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1001 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1003 if (pstate_funcs
.get_vid
)
1004 pstate_funcs
.get_vid(cpu
);
1006 intel_pstate_set_min_pstate(cpu
);
1009 static inline void intel_pstate_calc_busy(struct cpudata
*cpu
)
1011 struct sample
*sample
= &cpu
->sample
;
1014 core_pct
= sample
->aperf
* int_tofp(100);
1015 core_pct
= div64_u64(core_pct
, sample
->mperf
);
1017 sample
->core_pct_busy
= (int32_t)core_pct
;
1020 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1023 unsigned long flags
;
1026 local_irq_save(flags
);
1027 rdmsrl(MSR_IA32_APERF
, aperf
);
1028 rdmsrl(MSR_IA32_MPERF
, mperf
);
1030 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1031 local_irq_restore(flags
);
1034 local_irq_restore(flags
);
1036 cpu
->last_sample_time
= cpu
->sample
.time
;
1037 cpu
->sample
.time
= time
;
1038 cpu
->sample
.aperf
= aperf
;
1039 cpu
->sample
.mperf
= mperf
;
1040 cpu
->sample
.tsc
= tsc
;
1041 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1042 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1043 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1045 cpu
->prev_aperf
= aperf
;
1046 cpu
->prev_mperf
= mperf
;
1047 cpu
->prev_tsc
= tsc
;
1049 * First time this function is invoked in a given cycle, all of the
1050 * previous sample data fields are equal to zero or stale and they must
1051 * be populated with meaningful numbers for things to work, so assume
1052 * that sample.time will always be reset before setting the utilization
1053 * update hook and make the caller skip the sample then.
1055 return !!cpu
->last_sample_time
;
1058 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1060 return div64_u64(cpu
->pstate
.max_pstate_physical
* cpu
->sample
.aperf
*
1061 cpu
->pstate
.scaling
, cpu
->sample
.mperf
);
1064 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1066 struct sample
*sample
= &cpu
->sample
;
1067 u64 cummulative_iowait
, delta_iowait_us
;
1068 u64 delta_iowait_mperf
;
1072 cummulative_iowait
= get_cpu_iowait_time_us(cpu
->cpu
, &now
);
1075 * Convert iowait time into number of IO cycles spent at max_freq.
1076 * IO is considered as busy only for the cpu_load algorithm. For
1077 * performance this is not needed since we always try to reach the
1078 * maximum P-State, so we are already boosting the IOs.
1080 delta_iowait_us
= cummulative_iowait
- cpu
->prev_cummulative_iowait
;
1081 delta_iowait_mperf
= div64_u64(delta_iowait_us
* cpu
->pstate
.scaling
*
1082 cpu
->pstate
.max_pstate
, MSEC_PER_SEC
);
1084 mperf
= cpu
->sample
.mperf
+ delta_iowait_mperf
;
1085 cpu
->prev_cummulative_iowait
= cummulative_iowait
;
1088 * The load can be estimated as the ratio of the mperf counter
1089 * running at a constant frequency during active periods
1090 * (C0) and the time stamp counter running at the same frequency
1091 * also during C-states.
1093 cpu_load
= div64_u64(int_tofp(100) * mperf
, sample
->tsc
);
1094 cpu
->sample
.busy_scaled
= cpu_load
;
1096 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, cpu_load
);
1099 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1101 int32_t core_busy
, max_pstate
, current_pstate
, sample_ratio
;
1104 intel_pstate_calc_busy(cpu
);
1107 * core_busy is the ratio of actual performance to max
1108 * max_pstate is the max non turbo pstate available
1109 * current_pstate was the pstate that was requested during
1110 * the last sample period.
1112 * We normalize core_busy, which was our actual percent
1113 * performance to what we requested during the last sample
1114 * period. The result will be a percentage of busy at a
1117 core_busy
= cpu
->sample
.core_pct_busy
;
1118 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1119 current_pstate
= cpu
->pstate
.current_pstate
;
1120 core_busy
= mul_fp(core_busy
, div_fp(max_pstate
, current_pstate
));
1123 * Since our utilization update callback will not run unless we are
1124 * in C0, check if the actual elapsed time is significantly greater (3x)
1125 * than our sample interval. If it is, then we were idle for a long
1126 * enough period of time to adjust our busyness.
1128 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1129 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1130 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1131 core_busy
= mul_fp(core_busy
, sample_ratio
);
1134 cpu
->sample
.busy_scaled
= core_busy
;
1135 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, core_busy
);
1138 static inline void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1140 int max_perf
, min_perf
;
1142 update_turbo_state();
1144 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
1145 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
1146 if (pstate
== cpu
->pstate
.current_pstate
)
1149 intel_pstate_record_pstate(cpu
, pstate
);
1150 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1153 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1155 int from
, target_pstate
;
1156 struct sample
*sample
;
1158 from
= cpu
->pstate
.current_pstate
;
1160 target_pstate
= pstate_funcs
.get_target_pstate(cpu
);
1162 intel_pstate_update_pstate(cpu
, target_pstate
);
1164 sample
= &cpu
->sample
;
1165 trace_pstate_sample(fp_toint(sample
->core_pct_busy
),
1166 fp_toint(sample
->busy_scaled
),
1168 cpu
->pstate
.current_pstate
,
1172 get_avg_frequency(cpu
));
1175 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1176 unsigned long util
, unsigned long max
)
1178 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1179 u64 delta_ns
= time
- cpu
->sample
.time
;
1181 if ((s64
)delta_ns
>= pid_params
.sample_rate_ns
) {
1182 bool sample_taken
= intel_pstate_sample(cpu
, time
);
1184 if (sample_taken
&& !hwp_active
)
1185 intel_pstate_adjust_busy_pstate(cpu
);
1189 #define ICPU(model, policy) \
1190 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1191 (unsigned long)&policy }
1193 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1194 ICPU(0x2a, core_params
),
1195 ICPU(0x2d, core_params
),
1196 ICPU(0x37, silvermont_params
),
1197 ICPU(0x3a, core_params
),
1198 ICPU(0x3c, core_params
),
1199 ICPU(0x3d, core_params
),
1200 ICPU(0x3e, core_params
),
1201 ICPU(0x3f, core_params
),
1202 ICPU(0x45, core_params
),
1203 ICPU(0x46, core_params
),
1204 ICPU(0x47, core_params
),
1205 ICPU(0x4c, airmont_params
),
1206 ICPU(0x4e, core_params
),
1207 ICPU(0x4f, core_params
),
1208 ICPU(0x5e, core_params
),
1209 ICPU(0x56, core_params
),
1210 ICPU(0x57, knl_params
),
1213 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1215 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] = {
1216 ICPU(0x56, core_params
),
1220 static int intel_pstate_init_cpu(unsigned int cpunum
)
1222 struct cpudata
*cpu
;
1224 if (!all_cpu_data
[cpunum
])
1225 all_cpu_data
[cpunum
] = kzalloc(sizeof(struct cpudata
),
1227 if (!all_cpu_data
[cpunum
])
1230 cpu
= all_cpu_data
[cpunum
];
1235 intel_pstate_hwp_enable(cpu
);
1236 pid_params
.sample_rate_ms
= 50;
1237 pid_params
.sample_rate_ns
= 50 * NSEC_PER_MSEC
;
1240 intel_pstate_get_cpu_pstates(cpu
);
1242 intel_pstate_busy_pid_reset(cpu
);
1244 pr_debug("controlling: cpu %d\n", cpunum
);
1249 static unsigned int intel_pstate_get(unsigned int cpu_num
)
1251 struct sample
*sample
;
1252 struct cpudata
*cpu
;
1254 cpu
= all_cpu_data
[cpu_num
];
1257 sample
= &cpu
->sample
;
1258 return get_avg_frequency(cpu
);
1261 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
1263 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1265 /* Prevent intel_pstate_update_util() from using stale data. */
1266 cpu
->sample
.time
= 0;
1267 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
1268 intel_pstate_update_util
);
1271 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
1273 cpufreq_remove_update_util_hook(cpu
);
1274 synchronize_sched();
1277 static void intel_pstate_set_performance_limits(struct perf_limits
*limits
)
1279 limits
->no_turbo
= 0;
1280 limits
->turbo_disabled
= 0;
1281 limits
->max_perf_pct
= 100;
1282 limits
->max_perf
= int_tofp(1);
1283 limits
->min_perf_pct
= 100;
1284 limits
->min_perf
= int_tofp(1);
1285 limits
->max_policy_pct
= 100;
1286 limits
->max_sysfs_pct
= 100;
1287 limits
->min_policy_pct
= 0;
1288 limits
->min_sysfs_pct
= 0;
1291 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
1293 if (!policy
->cpuinfo
.max_freq
)
1296 intel_pstate_clear_update_util_hook(policy
->cpu
);
1298 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
1299 limits
= &performance_limits
;
1300 if (policy
->max
>= policy
->cpuinfo
.max_freq
) {
1301 pr_debug("set performance\n");
1302 intel_pstate_set_performance_limits(limits
);
1306 pr_debug("set powersave\n");
1307 limits
= &powersave_limits
;
1310 limits
->min_policy_pct
= (policy
->min
* 100) / policy
->cpuinfo
.max_freq
;
1311 limits
->min_policy_pct
= clamp_t(int, limits
->min_policy_pct
, 0 , 100);
1312 limits
->max_policy_pct
= DIV_ROUND_UP(policy
->max
* 100,
1313 policy
->cpuinfo
.max_freq
);
1314 limits
->max_policy_pct
= clamp_t(int, limits
->max_policy_pct
, 0 , 100);
1316 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1317 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
1318 limits
->min_sysfs_pct
);
1319 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
1320 limits
->min_perf_pct
);
1321 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
1322 limits
->max_sysfs_pct
);
1323 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
1324 limits
->max_perf_pct
);
1325 limits
->max_perf
= round_up(limits
->max_perf
, FRAC_BITS
);
1327 /* Make sure min_perf_pct <= max_perf_pct */
1328 limits
->min_perf_pct
= min(limits
->max_perf_pct
, limits
->min_perf_pct
);
1330 limits
->min_perf
= div_fp(limits
->min_perf_pct
, 100);
1331 limits
->max_perf
= div_fp(limits
->max_perf_pct
, 100);
1334 intel_pstate_set_update_util_hook(policy
->cpu
);
1337 intel_pstate_hwp_set(policy
->cpus
);
1342 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
1344 cpufreq_verify_within_cpu_limits(policy
);
1346 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
1347 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
1353 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
1355 int cpu_num
= policy
->cpu
;
1356 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1358 pr_debug("CPU %d exiting\n", cpu_num
);
1360 intel_pstate_clear_update_util_hook(cpu_num
);
1365 intel_pstate_set_min_pstate(cpu
);
1368 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
1370 struct cpudata
*cpu
;
1373 rc
= intel_pstate_init_cpu(policy
->cpu
);
1377 cpu
= all_cpu_data
[policy
->cpu
];
1379 if (limits
->min_perf_pct
== 100 && limits
->max_perf_pct
== 100)
1380 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
1382 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
1384 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1385 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1387 /* cpuinfo and default policy values */
1388 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1389 policy
->cpuinfo
.max_freq
=
1390 cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1391 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
1392 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
1397 static struct cpufreq_driver intel_pstate_driver
= {
1398 .flags
= CPUFREQ_CONST_LOOPS
,
1399 .verify
= intel_pstate_verify_policy
,
1400 .setpolicy
= intel_pstate_set_policy
,
1401 .get
= intel_pstate_get
,
1402 .init
= intel_pstate_cpu_init
,
1403 .stop_cpu
= intel_pstate_stop_cpu
,
1404 .name
= "intel_pstate",
1407 static int __initdata no_load
;
1408 static int __initdata no_hwp
;
1409 static int __initdata hwp_only
;
1410 static unsigned int force_load
;
1412 static int intel_pstate_msrs_not_valid(void)
1414 if (!pstate_funcs
.get_max() ||
1415 !pstate_funcs
.get_min() ||
1416 !pstate_funcs
.get_turbo())
1422 static void copy_pid_params(struct pstate_adjust_policy
*policy
)
1424 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
1425 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
1426 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
1427 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
1428 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
1429 pid_params
.deadband
= policy
->deadband
;
1430 pid_params
.setpoint
= policy
->setpoint
;
1433 static void copy_cpu_funcs(struct pstate_funcs
*funcs
)
1435 pstate_funcs
.get_max
= funcs
->get_max
;
1436 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
1437 pstate_funcs
.get_min
= funcs
->get_min
;
1438 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
1439 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
1440 pstate_funcs
.get_val
= funcs
->get_val
;
1441 pstate_funcs
.get_vid
= funcs
->get_vid
;
1442 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
1446 #if IS_ENABLED(CONFIG_ACPI)
1447 #include <acpi/processor.h>
1449 static bool intel_pstate_no_acpi_pss(void)
1453 for_each_possible_cpu(i
) {
1455 union acpi_object
*pss
;
1456 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1457 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1462 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
1463 if (ACPI_FAILURE(status
))
1466 pss
= buffer
.pointer
;
1467 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
1478 static bool intel_pstate_has_acpi_ppc(void)
1482 for_each_possible_cpu(i
) {
1483 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1487 if (acpi_has_method(pr
->handle
, "_PPC"))
1498 struct hw_vendor_info
{
1500 char oem_id
[ACPI_OEM_ID_SIZE
];
1501 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
1505 /* Hardware vendor-specific info that has its own power management modes */
1506 static struct hw_vendor_info vendor_info
[] = {
1507 {1, "HP ", "ProLiant", PSS
},
1508 {1, "ORACLE", "X4-2 ", PPC
},
1509 {1, "ORACLE", "X4-2L ", PPC
},
1510 {1, "ORACLE", "X4-2B ", PPC
},
1511 {1, "ORACLE", "X3-2 ", PPC
},
1512 {1, "ORACLE", "X3-2L ", PPC
},
1513 {1, "ORACLE", "X3-2B ", PPC
},
1514 {1, "ORACLE", "X4470M2 ", PPC
},
1515 {1, "ORACLE", "X4270M3 ", PPC
},
1516 {1, "ORACLE", "X4270M2 ", PPC
},
1517 {1, "ORACLE", "X4170M2 ", PPC
},
1518 {1, "ORACLE", "X4170 M3", PPC
},
1519 {1, "ORACLE", "X4275 M3", PPC
},
1520 {1, "ORACLE", "X6-2 ", PPC
},
1521 {1, "ORACLE", "Sudbury ", PPC
},
1525 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1527 struct acpi_table_header hdr
;
1528 struct hw_vendor_info
*v_info
;
1529 const struct x86_cpu_id
*id
;
1532 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
1534 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
1535 if ( misc_pwr
& (1 << 8))
1539 if (acpi_disabled
||
1540 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
1543 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
1544 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
1545 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
1546 ACPI_OEM_TABLE_ID_SIZE
))
1547 switch (v_info
->oem_pwr_table
) {
1549 return intel_pstate_no_acpi_pss();
1551 return intel_pstate_has_acpi_ppc() &&
1558 #else /* CONFIG_ACPI not enabled */
1559 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1560 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1561 #endif /* CONFIG_ACPI */
1563 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
1564 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
1568 static int __init
intel_pstate_init(void)
1571 const struct x86_cpu_id
*id
;
1572 struct cpu_defaults
*cpu_def
;
1577 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
1578 copy_cpu_funcs(&core_params
.funcs
);
1580 goto hwp_cpu_matched
;
1583 id
= x86_match_cpu(intel_pstate_cpu_ids
);
1587 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
1589 copy_pid_params(&cpu_def
->pid_policy
);
1590 copy_cpu_funcs(&cpu_def
->funcs
);
1592 if (intel_pstate_msrs_not_valid())
1597 * The Intel pstate driver will be ignored if the platform
1598 * firmware has its own power management modes.
1600 if (intel_pstate_platform_pwr_mgmt_exists())
1603 pr_info("Intel P-state driver initializing\n");
1605 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
1609 if (!hwp_active
&& hwp_only
)
1612 rc
= cpufreq_register_driver(&intel_pstate_driver
);
1616 intel_pstate_debug_expose_params();
1617 intel_pstate_sysfs_expose_params();
1620 pr_info("HWP enabled\n");
1625 for_each_online_cpu(cpu
) {
1626 if (all_cpu_data
[cpu
]) {
1627 intel_pstate_clear_update_util_hook(cpu
);
1628 kfree(all_cpu_data
[cpu
]);
1633 vfree(all_cpu_data
);
1636 device_initcall(intel_pstate_init
);
1638 static int __init
intel_pstate_setup(char *str
)
1643 if (!strcmp(str
, "disable"))
1645 if (!strcmp(str
, "no_hwp")) {
1646 pr_info("HWP disabled\n");
1649 if (!strcmp(str
, "force"))
1651 if (!strcmp(str
, "hwp_only"))
1655 early_param("intel_pstate", intel_pstate_setup
);
1657 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1658 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1659 MODULE_LICENSE("GPL");