2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
39 #define ATOM_RATIOS 0x66a
40 #define ATOM_VIDS 0x66b
41 #define ATOM_TURBO_RATIOS 0x66c
42 #define ATOM_TURBO_VIDS 0x66d
45 #include <acpi/processor.h>
49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
50 #define fp_toint(X) ((X) >> FRAC_BITS)
52 static inline int32_t mul_fp(int32_t x
, int32_t y
)
54 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
57 static inline int32_t div_fp(s64 x
, s64 y
)
59 return div64_s64((int64_t)x
<< FRAC_BITS
, y
);
62 static inline int ceiling_fp(int32_t x
)
67 mask
= (1 << FRAC_BITS
) - 1;
74 * struct sample - Store performance sample
75 * @core_pct_busy: Ratio of APERF/MPERF in percent, which is actual
76 * performance during last sample period
77 * @busy_scaled: Scaled busy value which is used to calculate next
78 * P state. This can be different than core_pct_busy
79 * to account for cpu idle period
80 * @aperf: Difference of actual performance frequency clock count
81 * read from APERF MSR between last and current sample
82 * @mperf: Difference of maximum performance frequency clock count
83 * read from MPERF MSR between last and current sample
84 * @tsc: Difference of time stamp counter between last and
86 * @freq: Effective frequency calculated from APERF/MPERF
87 * @time: Current time from scheduler
89 * This structure is used in the cpudata structure to store performance sample
90 * data for choosing next P State.
93 int32_t core_pct_busy
;
103 * struct pstate_data - Store P state data
104 * @current_pstate: Current requested P state
105 * @min_pstate: Min P state possible for this platform
106 * @max_pstate: Max P state possible for this platform
107 * @max_pstate_physical:This is physical Max P state for a processor
108 * This can be higher than the max_pstate which can
109 * be limited by platform thermal design power limits
110 * @scaling: Scaling factor to convert frequency to cpufreq
112 * @turbo_pstate: Max Turbo P state possible for this platform
114 * Stores the per cpu model P state limits and current P state.
120 int max_pstate_physical
;
126 * struct vid_data - Stores voltage information data
127 * @min: VID data for this platform corresponding to
129 * @max: VID data corresponding to the highest P State.
130 * @turbo: VID data for turbo P state
131 * @ratio: Ratio of (vid max - vid min) /
132 * (max P state - Min P State)
134 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
135 * This data is used in Atom platforms, where in addition to target P state,
136 * the voltage data needs to be specified to select next P State.
146 * struct _pid - Stores PID data
147 * @setpoint: Target set point for busyness or performance
148 * @integral: Storage for accumulated error values
149 * @p_gain: PID proportional gain
150 * @i_gain: PID integral gain
151 * @d_gain: PID derivative gain
152 * @deadband: PID deadband
153 * @last_err: Last error storage for integral part of PID calculation
155 * Stores PID coefficients and last error for PID controller.
168 * struct cpudata - Per CPU instance data storage
169 * @cpu: CPU number for this instance data
170 * @update_util: CPUFreq utility callback information
171 * @pstate: Stores P state limits for this CPU
172 * @vid: Stores VID limits for this CPU
173 * @pid: Stores PID parameters for this CPU
174 * @last_sample_time: Last Sample time
175 * @prev_aperf: Last APERF value read from APERF MSR
176 * @prev_mperf: Last MPERF value read from MPERF MSR
177 * @prev_tsc: Last timestamp counter (TSC) value
178 * @prev_cummulative_iowait: IO Wait time difference from last and
180 * @sample: Storage for storing last Sample data
181 * @acpi_perf_data: Stores ACPI perf information read from _PSS
182 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
184 * This structure stores per CPU instance data for all CPUs.
189 struct update_util_data update_util
;
191 struct pstate_data pstate
;
195 u64 last_sample_time
;
199 u64 prev_cummulative_iowait
;
200 struct sample sample
;
202 struct acpi_processor_performance acpi_perf_data
;
203 bool valid_pss_table
;
207 static struct cpudata
**all_cpu_data
;
210 * struct pid_adjust_policy - Stores static PID configuration data
211 * @sample_rate_ms: PID calculation sample rate in ms
212 * @sample_rate_ns: Sample rate calculation in ns
213 * @deadband: PID deadband
214 * @setpoint: PID Setpoint
215 * @p_gain_pct: PID proportional gain
216 * @i_gain_pct: PID integral gain
217 * @d_gain_pct: PID derivative gain
219 * Stores per CPU model static PID configuration data.
221 struct pstate_adjust_policy
{
232 * struct pstate_funcs - Per CPU model specific callbacks
233 * @get_max: Callback to get maximum non turbo effective P state
234 * @get_max_physical: Callback to get maximum non turbo physical P state
235 * @get_min: Callback to get minimum P state
236 * @get_turbo: Callback to get turbo P state
237 * @get_scaling: Callback to get frequency scaling factor
238 * @get_val: Callback to convert P state to actual MSR write value
239 * @get_vid: Callback to get VID data for Atom platforms
240 * @get_target_pstate: Callback to a function to calculate next P state to use
242 * Core and Atom CPU models have different way to get P State limits. This
243 * structure is used to store those callbacks.
245 struct pstate_funcs
{
246 int (*get_max
)(void);
247 int (*get_max_physical
)(void);
248 int (*get_min
)(void);
249 int (*get_turbo
)(void);
250 int (*get_scaling
)(void);
251 u64 (*get_val
)(struct cpudata
*, int pstate
);
252 void (*get_vid
)(struct cpudata
*);
253 int32_t (*get_target_pstate
)(struct cpudata
*);
257 * struct cpu_defaults- Per CPU model default config data
258 * @pid_policy: PID config data
259 * @funcs: Callback function data
261 struct cpu_defaults
{
262 struct pstate_adjust_policy pid_policy
;
263 struct pstate_funcs funcs
;
266 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
);
267 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
);
269 static struct pstate_adjust_policy pid_params
;
270 static struct pstate_funcs pstate_funcs
;
271 static int hwp_active
;
274 static bool acpi_ppc
;
278 * struct perf_limits - Store user and policy limits
279 * @no_turbo: User requested turbo state from intel_pstate sysfs
280 * @turbo_disabled: Platform turbo status either from msr
281 * MSR_IA32_MISC_ENABLE or when maximum available pstate
282 * matches the maximum turbo pstate
283 * @max_perf_pct: Effective maximum performance limit in percentage, this
284 * is minimum of either limits enforced by cpufreq policy
285 * or limits from user set limits via intel_pstate sysfs
286 * @min_perf_pct: Effective minimum performance limit in percentage, this
287 * is maximum of either limits enforced by cpufreq policy
288 * or limits from user set limits via intel_pstate sysfs
289 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
290 * This value is used to limit max pstate
291 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
292 * This value is used to limit min pstate
293 * @max_policy_pct: The maximum performance in percentage enforced by
294 * cpufreq setpolicy interface
295 * @max_sysfs_pct: The maximum performance in percentage enforced by
296 * intel pstate sysfs interface
297 * @min_policy_pct: The minimum performance in percentage enforced by
298 * cpufreq setpolicy interface
299 * @min_sysfs_pct: The minimum performance in percentage enforced by
300 * intel pstate sysfs interface
302 * Storage for user and policy defined limits.
317 static struct perf_limits performance_limits
= {
321 .max_perf
= int_tofp(1),
323 .min_perf
= int_tofp(1),
324 .max_policy_pct
= 100,
325 .max_sysfs_pct
= 100,
330 static struct perf_limits powersave_limits
= {
334 .max_perf
= int_tofp(1),
337 .max_policy_pct
= 100,
338 .max_sysfs_pct
= 100,
343 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
344 static struct perf_limits
*limits
= &performance_limits
;
346 static struct perf_limits
*limits
= &powersave_limits
;
351 static bool intel_pstate_get_ppc_enable_status(void)
353 if (acpi_gbl_FADT
.preferred_profile
== PM_ENTERPRISE_SERVER
||
354 acpi_gbl_FADT
.preferred_profile
== PM_PERFORMANCE_SERVER
)
361 * The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and
362 * in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and
363 * max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state
364 * ratio, out of it only high 8 bits are used. For example 0x1700 is setting
365 * target ratio 0x17. The _PSS control value stores in a format which can be
366 * directly written to PERF_CTL MSR. But in intel_pstate driver this shift
367 * occurs during write to PERF_CTL (E.g. for cores core_set_pstate()).
368 * This function converts the _PSS control value to intel pstate driver format
369 * for comparison and assignment.
371 static int convert_to_native_pstate_format(struct cpudata
*cpu
, int index
)
373 return cpu
->acpi_perf_data
.states
[index
].control
>> 8;
376 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
386 if (!intel_pstate_get_ppc_enable_status())
389 cpu
= all_cpu_data
[policy
->cpu
];
391 ret
= acpi_processor_register_performance(&cpu
->acpi_perf_data
,
397 * Check if the control value in _PSS is for PERF_CTL MSR, which should
398 * guarantee that the states returned by it map to the states in our
401 if (cpu
->acpi_perf_data
.control_register
.space_id
!=
402 ACPI_ADR_SPACE_FIXED_HARDWARE
)
406 * If there is only one entry _PSS, simply ignore _PSS and continue as
407 * usual without taking _PSS into account
409 if (cpu
->acpi_perf_data
.state_count
< 2)
412 pr_debug("CPU%u - ACPI _PSS perf data\n", policy
->cpu
);
413 for (i
= 0; i
< cpu
->acpi_perf_data
.state_count
; i
++) {
414 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
415 (i
== cpu
->acpi_perf_data
.state
? '*' : ' '), i
,
416 (u32
) cpu
->acpi_perf_data
.states
[i
].core_frequency
,
417 (u32
) cpu
->acpi_perf_data
.states
[i
].power
,
418 (u32
) cpu
->acpi_perf_data
.states
[i
].control
);
422 * The _PSS table doesn't contain whole turbo frequency range.
423 * This just contains +1 MHZ above the max non turbo frequency,
424 * with control value corresponding to max turbo ratio. But
425 * when cpufreq set policy is called, it will call with this
426 * max frequency, which will cause a reduced performance as
427 * this driver uses real max turbo frequency as the max
428 * frequency. So correct this frequency in _PSS table to
429 * correct max turbo frequency based on the turbo ratio.
430 * Also need to convert to MHz as _PSS freq is in MHz.
432 turbo_pss_ctl
= convert_to_native_pstate_format(cpu
, 0);
433 if (turbo_pss_ctl
> cpu
->pstate
.max_pstate
)
434 cpu
->acpi_perf_data
.states
[0].core_frequency
=
435 policy
->cpuinfo
.max_freq
/ 1000;
436 cpu
->valid_pss_table
= true;
437 pr_info("_PPC limits will be enforced\n");
442 cpu
->valid_pss_table
= false;
443 acpi_processor_unregister_performance(policy
->cpu
);
446 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
450 cpu
= all_cpu_data
[policy
->cpu
];
451 if (!cpu
->valid_pss_table
)
454 acpi_processor_unregister_performance(policy
->cpu
);
458 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy
*policy
)
462 static void intel_pstate_exit_perf_limits(struct cpufreq_policy
*policy
)
467 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
468 int deadband
, int integral
) {
469 pid
->setpoint
= int_tofp(setpoint
);
470 pid
->deadband
= int_tofp(deadband
);
471 pid
->integral
= int_tofp(integral
);
472 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
475 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
477 pid
->p_gain
= div_fp(percent
, 100);
480 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
482 pid
->i_gain
= div_fp(percent
, 100);
485 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
487 pid
->d_gain
= div_fp(percent
, 100);
490 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
493 int32_t pterm
, dterm
, fp_error
;
494 int32_t integral_limit
;
496 fp_error
= pid
->setpoint
- busy
;
498 if (abs(fp_error
) <= pid
->deadband
)
501 pterm
= mul_fp(pid
->p_gain
, fp_error
);
503 pid
->integral
+= fp_error
;
506 * We limit the integral here so that it will never
507 * get higher than 30. This prevents it from becoming
508 * too large an input over long periods of time and allows
509 * it to get factored out sooner.
511 * The value of 30 was chosen through experimentation.
513 integral_limit
= int_tofp(30);
514 if (pid
->integral
> integral_limit
)
515 pid
->integral
= integral_limit
;
516 if (pid
->integral
< -integral_limit
)
517 pid
->integral
= -integral_limit
;
519 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
520 pid
->last_err
= fp_error
;
522 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
523 result
= result
+ (1 << (FRAC_BITS
-1));
524 return (signed int)fp_toint(result
);
527 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
529 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
530 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
531 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
533 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
536 static inline void intel_pstate_reset_all_pid(void)
540 for_each_online_cpu(cpu
) {
541 if (all_cpu_data
[cpu
])
542 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
546 static inline void update_turbo_state(void)
551 cpu
= all_cpu_data
[0];
552 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
553 limits
->turbo_disabled
=
554 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
555 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
558 static void intel_pstate_hwp_set(const struct cpumask
*cpumask
)
560 int min
, hw_min
, max
, hw_max
, cpu
, range
, adj_range
;
563 rdmsrl(MSR_HWP_CAPABILITIES
, cap
);
564 hw_min
= HWP_LOWEST_PERF(cap
);
565 hw_max
= HWP_HIGHEST_PERF(cap
);
566 range
= hw_max
- hw_min
;
568 for_each_cpu(cpu
, cpumask
) {
569 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
570 adj_range
= limits
->min_perf_pct
* range
/ 100;
571 min
= hw_min
+ adj_range
;
572 value
&= ~HWP_MIN_PERF(~0L);
573 value
|= HWP_MIN_PERF(min
);
575 adj_range
= limits
->max_perf_pct
* range
/ 100;
576 max
= hw_min
+ adj_range
;
577 if (limits
->no_turbo
) {
578 hw_max
= HWP_GUARANTEED_PERF(cap
);
583 value
&= ~HWP_MAX_PERF(~0L);
584 value
|= HWP_MAX_PERF(max
);
585 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
589 static int intel_pstate_hwp_set_policy(struct cpufreq_policy
*policy
)
592 intel_pstate_hwp_set(policy
->cpus
);
597 static void intel_pstate_hwp_set_online_cpus(void)
600 intel_pstate_hwp_set(cpu_online_mask
);
604 /************************** debugfs begin ************************/
605 static int pid_param_set(void *data
, u64 val
)
608 intel_pstate_reset_all_pid();
612 static int pid_param_get(void *data
, u64
*val
)
617 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
624 static struct pid_param pid_files
[] = {
625 {"sample_rate_ms", &pid_params
.sample_rate_ms
},
626 {"d_gain_pct", &pid_params
.d_gain_pct
},
627 {"i_gain_pct", &pid_params
.i_gain_pct
},
628 {"deadband", &pid_params
.deadband
},
629 {"setpoint", &pid_params
.setpoint
},
630 {"p_gain_pct", &pid_params
.p_gain_pct
},
634 static void __init
intel_pstate_debug_expose_params(void)
636 struct dentry
*debugfs_parent
;
641 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
642 if (IS_ERR_OR_NULL(debugfs_parent
))
644 while (pid_files
[i
].name
) {
645 debugfs_create_file(pid_files
[i
].name
, 0660,
646 debugfs_parent
, pid_files
[i
].value
,
652 /************************** debugfs end ************************/
654 /************************** sysfs begin ************************/
655 #define show_one(file_name, object) \
656 static ssize_t show_##file_name \
657 (struct kobject *kobj, struct attribute *attr, char *buf) \
659 return sprintf(buf, "%u\n", limits->object); \
662 static ssize_t
show_turbo_pct(struct kobject
*kobj
,
663 struct attribute
*attr
, char *buf
)
666 int total
, no_turbo
, turbo_pct
;
669 cpu
= all_cpu_data
[0];
671 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
672 no_turbo
= cpu
->pstate
.max_pstate
- cpu
->pstate
.min_pstate
+ 1;
673 turbo_fp
= div_fp(no_turbo
, total
);
674 turbo_pct
= 100 - fp_toint(mul_fp(turbo_fp
, int_tofp(100)));
675 return sprintf(buf
, "%u\n", turbo_pct
);
678 static ssize_t
show_num_pstates(struct kobject
*kobj
,
679 struct attribute
*attr
, char *buf
)
684 cpu
= all_cpu_data
[0];
685 total
= cpu
->pstate
.turbo_pstate
- cpu
->pstate
.min_pstate
+ 1;
686 return sprintf(buf
, "%u\n", total
);
689 static ssize_t
show_no_turbo(struct kobject
*kobj
,
690 struct attribute
*attr
, char *buf
)
694 update_turbo_state();
695 if (limits
->turbo_disabled
)
696 ret
= sprintf(buf
, "%u\n", limits
->turbo_disabled
);
698 ret
= sprintf(buf
, "%u\n", limits
->no_turbo
);
703 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
704 const char *buf
, size_t count
)
709 ret
= sscanf(buf
, "%u", &input
);
713 update_turbo_state();
714 if (limits
->turbo_disabled
) {
715 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
719 limits
->no_turbo
= clamp_t(int, input
, 0, 1);
722 intel_pstate_hwp_set_online_cpus();
727 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
728 const char *buf
, size_t count
)
733 ret
= sscanf(buf
, "%u", &input
);
737 limits
->max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
738 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
739 limits
->max_sysfs_pct
);
740 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
741 limits
->max_perf_pct
);
742 limits
->max_perf_pct
= max(limits
->min_perf_pct
,
743 limits
->max_perf_pct
);
744 limits
->max_perf
= div_fp(limits
->max_perf_pct
, 100);
747 intel_pstate_hwp_set_online_cpus();
751 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
752 const char *buf
, size_t count
)
757 ret
= sscanf(buf
, "%u", &input
);
761 limits
->min_sysfs_pct
= clamp_t(int, input
, 0 , 100);
762 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
763 limits
->min_sysfs_pct
);
764 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
765 limits
->min_perf_pct
);
766 limits
->min_perf_pct
= min(limits
->max_perf_pct
,
767 limits
->min_perf_pct
);
768 limits
->min_perf
= div_fp(limits
->min_perf_pct
, 100);
771 intel_pstate_hwp_set_online_cpus();
775 show_one(max_perf_pct
, max_perf_pct
);
776 show_one(min_perf_pct
, min_perf_pct
);
778 define_one_global_rw(no_turbo
);
779 define_one_global_rw(max_perf_pct
);
780 define_one_global_rw(min_perf_pct
);
781 define_one_global_ro(turbo_pct
);
782 define_one_global_ro(num_pstates
);
784 static struct attribute
*intel_pstate_attributes
[] = {
793 static struct attribute_group intel_pstate_attr_group
= {
794 .attrs
= intel_pstate_attributes
,
797 static void __init
intel_pstate_sysfs_expose_params(void)
799 struct kobject
*intel_pstate_kobject
;
802 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
803 &cpu_subsys
.dev_root
->kobj
);
804 BUG_ON(!intel_pstate_kobject
);
805 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
808 /************************** sysfs end ************************/
810 static void intel_pstate_hwp_enable(struct cpudata
*cpudata
)
812 /* First disable HWP notification interrupt as we don't process them */
813 wrmsrl_on_cpu(cpudata
->cpu
, MSR_HWP_INTERRUPT
, 0x00);
815 wrmsrl_on_cpu(cpudata
->cpu
, MSR_PM_ENABLE
, 0x1);
818 static int atom_get_min_pstate(void)
822 rdmsrl(ATOM_RATIOS
, value
);
823 return (value
>> 8) & 0x7F;
826 static int atom_get_max_pstate(void)
830 rdmsrl(ATOM_RATIOS
, value
);
831 return (value
>> 16) & 0x7F;
834 static int atom_get_turbo_pstate(void)
838 rdmsrl(ATOM_TURBO_RATIOS
, value
);
842 static u64
atom_get_val(struct cpudata
*cpudata
, int pstate
)
848 val
= (u64
)pstate
<< 8;
849 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
852 vid_fp
= cpudata
->vid
.min
+ mul_fp(
853 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
856 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
857 vid
= ceiling_fp(vid_fp
);
859 if (pstate
> cpudata
->pstate
.max_pstate
)
860 vid
= cpudata
->vid
.turbo
;
865 static int silvermont_get_scaling(void)
869 /* Defined in Table 35-6 from SDM (Sept 2015) */
870 static int silvermont_freq_table
[] = {
871 83300, 100000, 133300, 116700, 80000};
873 rdmsrl(MSR_FSB_FREQ
, value
);
877 return silvermont_freq_table
[i
];
880 static int airmont_get_scaling(void)
884 /* Defined in Table 35-10 from SDM (Sept 2015) */
885 static int airmont_freq_table
[] = {
886 83300, 100000, 133300, 116700, 80000,
887 93300, 90000, 88900, 87500};
889 rdmsrl(MSR_FSB_FREQ
, value
);
893 return airmont_freq_table
[i
];
896 static void atom_get_vid(struct cpudata
*cpudata
)
900 rdmsrl(ATOM_VIDS
, value
);
901 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
902 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
903 cpudata
->vid
.ratio
= div_fp(
904 cpudata
->vid
.max
- cpudata
->vid
.min
,
905 int_tofp(cpudata
->pstate
.max_pstate
-
906 cpudata
->pstate
.min_pstate
));
908 rdmsrl(ATOM_TURBO_VIDS
, value
);
909 cpudata
->vid
.turbo
= value
& 0x7f;
912 static int core_get_min_pstate(void)
916 rdmsrl(MSR_PLATFORM_INFO
, value
);
917 return (value
>> 40) & 0xFF;
920 static int core_get_max_pstate_physical(void)
924 rdmsrl(MSR_PLATFORM_INFO
, value
);
925 return (value
>> 8) & 0xFF;
928 static int core_get_max_pstate(void)
935 rdmsrl(MSR_PLATFORM_INFO
, plat_info
);
936 max_pstate
= (plat_info
>> 8) & 0xFF;
938 err
= rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO
, &tar
);
940 /* Do some sanity checking for safety */
941 if (plat_info
& 0x600000000) {
946 err
= rdmsrl_safe(MSR_CONFIG_TDP_CONTROL
, &tdp_ctrl
);
950 tdp_msr
= MSR_CONFIG_TDP_NOMINAL
+ tdp_ctrl
;
951 err
= rdmsrl_safe(tdp_msr
, &tdp_ratio
);
955 /* For level 1 and 2, bits[23:16] contain the ratio */
959 tdp_ratio
&= 0xff; /* ratios are only 8 bits long */
960 if (tdp_ratio
- 1 == tar
) {
962 pr_debug("max_pstate=TAC %x\n", max_pstate
);
973 static int core_get_turbo_pstate(void)
978 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
979 nont
= core_get_max_pstate();
986 static inline int core_get_scaling(void)
991 static u64
core_get_val(struct cpudata
*cpudata
, int pstate
)
995 val
= (u64
)pstate
<< 8;
996 if (limits
->no_turbo
&& !limits
->turbo_disabled
)
1002 static int knl_get_turbo_pstate(void)
1007 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
1008 nont
= core_get_max_pstate();
1009 ret
= (((value
) >> 8) & 0xFF);
1015 static struct cpu_defaults core_params
= {
1017 .sample_rate_ms
= 10,
1025 .get_max
= core_get_max_pstate
,
1026 .get_max_physical
= core_get_max_pstate_physical
,
1027 .get_min
= core_get_min_pstate
,
1028 .get_turbo
= core_get_turbo_pstate
,
1029 .get_scaling
= core_get_scaling
,
1030 .get_val
= core_get_val
,
1031 .get_target_pstate
= get_target_pstate_use_performance
,
1035 static struct cpu_defaults silvermont_params
= {
1037 .sample_rate_ms
= 10,
1045 .get_max
= atom_get_max_pstate
,
1046 .get_max_physical
= atom_get_max_pstate
,
1047 .get_min
= atom_get_min_pstate
,
1048 .get_turbo
= atom_get_turbo_pstate
,
1049 .get_val
= atom_get_val
,
1050 .get_scaling
= silvermont_get_scaling
,
1051 .get_vid
= atom_get_vid
,
1052 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1056 static struct cpu_defaults airmont_params
= {
1058 .sample_rate_ms
= 10,
1066 .get_max
= atom_get_max_pstate
,
1067 .get_max_physical
= atom_get_max_pstate
,
1068 .get_min
= atom_get_min_pstate
,
1069 .get_turbo
= atom_get_turbo_pstate
,
1070 .get_val
= atom_get_val
,
1071 .get_scaling
= airmont_get_scaling
,
1072 .get_vid
= atom_get_vid
,
1073 .get_target_pstate
= get_target_pstate_use_cpu_load
,
1077 static struct cpu_defaults knl_params
= {
1079 .sample_rate_ms
= 10,
1087 .get_max
= core_get_max_pstate
,
1088 .get_max_physical
= core_get_max_pstate_physical
,
1089 .get_min
= core_get_min_pstate
,
1090 .get_turbo
= knl_get_turbo_pstate
,
1091 .get_scaling
= core_get_scaling
,
1092 .get_val
= core_get_val
,
1093 .get_target_pstate
= get_target_pstate_use_performance
,
1097 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
1099 int max_perf
= cpu
->pstate
.turbo_pstate
;
1103 if (limits
->no_turbo
|| limits
->turbo_disabled
)
1104 max_perf
= cpu
->pstate
.max_pstate
;
1107 * performance can be limited by user through sysfs, by cpufreq
1108 * policy, or by cpu specific default values determined through
1111 max_perf_adj
= fp_toint(max_perf
* limits
->max_perf
);
1112 *max
= clamp_t(int, max_perf_adj
,
1113 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
1115 min_perf
= fp_toint(max_perf
* limits
->min_perf
);
1116 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
1119 static inline void intel_pstate_record_pstate(struct cpudata
*cpu
, int pstate
)
1121 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
1122 cpu
->pstate
.current_pstate
= pstate
;
1125 static void intel_pstate_set_min_pstate(struct cpudata
*cpu
)
1127 int pstate
= cpu
->pstate
.min_pstate
;
1129 intel_pstate_record_pstate(cpu
, pstate
);
1131 * Generally, there is no guarantee that this code will always run on
1132 * the CPU being updated, so force the register update to run on the
1135 wrmsrl_on_cpu(cpu
->cpu
, MSR_IA32_PERF_CTL
,
1136 pstate_funcs
.get_val(cpu
, pstate
));
1139 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
1141 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
1142 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
1143 cpu
->pstate
.max_pstate_physical
= pstate_funcs
.get_max_physical();
1144 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
1145 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
1147 if (pstate_funcs
.get_vid
)
1148 pstate_funcs
.get_vid(cpu
);
1150 intel_pstate_set_min_pstate(cpu
);
1153 static inline void intel_pstate_calc_busy(struct cpudata
*cpu
)
1155 struct sample
*sample
= &cpu
->sample
;
1158 core_pct
= sample
->aperf
* int_tofp(100);
1159 core_pct
= div64_u64(core_pct
, sample
->mperf
);
1161 sample
->core_pct_busy
= (int32_t)core_pct
;
1164 static inline bool intel_pstate_sample(struct cpudata
*cpu
, u64 time
)
1167 unsigned long flags
;
1170 local_irq_save(flags
);
1171 rdmsrl(MSR_IA32_APERF
, aperf
);
1172 rdmsrl(MSR_IA32_MPERF
, mperf
);
1174 if (cpu
->prev_mperf
== mperf
|| cpu
->prev_tsc
== tsc
) {
1175 local_irq_restore(flags
);
1178 local_irq_restore(flags
);
1180 cpu
->last_sample_time
= cpu
->sample
.time
;
1181 cpu
->sample
.time
= time
;
1182 cpu
->sample
.aperf
= aperf
;
1183 cpu
->sample
.mperf
= mperf
;
1184 cpu
->sample
.tsc
= tsc
;
1185 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
1186 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
1187 cpu
->sample
.tsc
-= cpu
->prev_tsc
;
1189 cpu
->prev_aperf
= aperf
;
1190 cpu
->prev_mperf
= mperf
;
1191 cpu
->prev_tsc
= tsc
;
1193 * First time this function is invoked in a given cycle, all of the
1194 * previous sample data fields are equal to zero or stale and they must
1195 * be populated with meaningful numbers for things to work, so assume
1196 * that sample.time will always be reset before setting the utilization
1197 * update hook and make the caller skip the sample then.
1199 return !!cpu
->last_sample_time
;
1202 static inline int32_t get_avg_frequency(struct cpudata
*cpu
)
1204 return fp_toint(mul_fp(cpu
->sample
.core_pct_busy
,
1205 int_tofp(cpu
->pstate
.max_pstate_physical
*
1206 cpu
->pstate
.scaling
/ 100)));
1209 static inline int32_t get_avg_pstate(struct cpudata
*cpu
)
1211 return div64_u64(cpu
->pstate
.max_pstate_physical
* cpu
->sample
.aperf
,
1215 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata
*cpu
)
1217 struct sample
*sample
= &cpu
->sample
;
1218 u64 cummulative_iowait
, delta_iowait_us
;
1219 u64 delta_iowait_mperf
;
1223 cummulative_iowait
= get_cpu_iowait_time_us(cpu
->cpu
, &now
);
1226 * Convert iowait time into number of IO cycles spent at max_freq.
1227 * IO is considered as busy only for the cpu_load algorithm. For
1228 * performance this is not needed since we always try to reach the
1229 * maximum P-State, so we are already boosting the IOs.
1231 delta_iowait_us
= cummulative_iowait
- cpu
->prev_cummulative_iowait
;
1232 delta_iowait_mperf
= div64_u64(delta_iowait_us
* cpu
->pstate
.scaling
*
1233 cpu
->pstate
.max_pstate
, MSEC_PER_SEC
);
1235 mperf
= cpu
->sample
.mperf
+ delta_iowait_mperf
;
1236 cpu
->prev_cummulative_iowait
= cummulative_iowait
;
1239 * The load can be estimated as the ratio of the mperf counter
1240 * running at a constant frequency during active periods
1241 * (C0) and the time stamp counter running at the same frequency
1242 * also during C-states.
1244 cpu_load
= div64_u64(int_tofp(100) * mperf
, sample
->tsc
);
1245 cpu
->sample
.busy_scaled
= cpu_load
;
1247 return get_avg_pstate(cpu
) - pid_calc(&cpu
->pid
, cpu_load
);
1250 static inline int32_t get_target_pstate_use_performance(struct cpudata
*cpu
)
1252 int32_t core_busy
, max_pstate
, current_pstate
, sample_ratio
;
1256 * core_busy is the ratio of actual performance to max
1257 * max_pstate is the max non turbo pstate available
1258 * current_pstate was the pstate that was requested during
1259 * the last sample period.
1261 * We normalize core_busy, which was our actual percent
1262 * performance to what we requested during the last sample
1263 * period. The result will be a percentage of busy at a
1266 core_busy
= cpu
->sample
.core_pct_busy
;
1267 max_pstate
= cpu
->pstate
.max_pstate_physical
;
1268 current_pstate
= cpu
->pstate
.current_pstate
;
1269 core_busy
= mul_fp(core_busy
, div_fp(max_pstate
, current_pstate
));
1272 * Since our utilization update callback will not run unless we are
1273 * in C0, check if the actual elapsed time is significantly greater (3x)
1274 * than our sample interval. If it is, then we were idle for a long
1275 * enough period of time to adjust our busyness.
1277 duration_ns
= cpu
->sample
.time
- cpu
->last_sample_time
;
1278 if ((s64
)duration_ns
> pid_params
.sample_rate_ns
* 3) {
1279 sample_ratio
= div_fp(pid_params
.sample_rate_ns
, duration_ns
);
1280 core_busy
= mul_fp(core_busy
, sample_ratio
);
1282 sample_ratio
= div_fp(100 * cpu
->sample
.mperf
, cpu
->sample
.tsc
);
1283 if (sample_ratio
< int_tofp(1))
1287 cpu
->sample
.busy_scaled
= core_busy
;
1288 return cpu
->pstate
.current_pstate
- pid_calc(&cpu
->pid
, core_busy
);
1291 static inline void intel_pstate_update_pstate(struct cpudata
*cpu
, int pstate
)
1293 int max_perf
, min_perf
;
1295 update_turbo_state();
1297 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
1298 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
1299 if (pstate
== cpu
->pstate
.current_pstate
)
1302 intel_pstate_record_pstate(cpu
, pstate
);
1303 wrmsrl(MSR_IA32_PERF_CTL
, pstate_funcs
.get_val(cpu
, pstate
));
1306 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
1308 int from
, target_pstate
;
1309 struct sample
*sample
;
1311 from
= cpu
->pstate
.current_pstate
;
1313 target_pstate
= pstate_funcs
.get_target_pstate(cpu
);
1315 intel_pstate_update_pstate(cpu
, target_pstate
);
1317 sample
= &cpu
->sample
;
1318 trace_pstate_sample(fp_toint(sample
->core_pct_busy
),
1319 fp_toint(sample
->busy_scaled
),
1321 cpu
->pstate
.current_pstate
,
1325 get_avg_frequency(cpu
));
1328 static void intel_pstate_update_util(struct update_util_data
*data
, u64 time
,
1329 unsigned long util
, unsigned long max
)
1331 struct cpudata
*cpu
= container_of(data
, struct cpudata
, update_util
);
1332 u64 delta_ns
= time
- cpu
->sample
.time
;
1334 if ((s64
)delta_ns
>= pid_params
.sample_rate_ns
) {
1335 bool sample_taken
= intel_pstate_sample(cpu
, time
);
1338 intel_pstate_calc_busy(cpu
);
1340 intel_pstate_adjust_busy_pstate(cpu
);
1345 #define ICPU(model, policy) \
1346 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1347 (unsigned long)&policy }
1349 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
1350 ICPU(0x2a, core_params
),
1351 ICPU(0x2d, core_params
),
1352 ICPU(0x37, silvermont_params
),
1353 ICPU(0x3a, core_params
),
1354 ICPU(0x3c, core_params
),
1355 ICPU(0x3d, core_params
),
1356 ICPU(0x3e, core_params
),
1357 ICPU(0x3f, core_params
),
1358 ICPU(0x45, core_params
),
1359 ICPU(0x46, core_params
),
1360 ICPU(0x47, core_params
),
1361 ICPU(0x4c, airmont_params
),
1362 ICPU(0x4e, core_params
),
1363 ICPU(0x4f, core_params
),
1364 ICPU(0x5e, core_params
),
1365 ICPU(0x56, core_params
),
1366 ICPU(0x57, knl_params
),
1369 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
1371 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] = {
1372 ICPU(0x56, core_params
),
1376 static int intel_pstate_init_cpu(unsigned int cpunum
)
1378 struct cpudata
*cpu
;
1380 if (!all_cpu_data
[cpunum
])
1381 all_cpu_data
[cpunum
] = kzalloc(sizeof(struct cpudata
),
1383 if (!all_cpu_data
[cpunum
])
1386 cpu
= all_cpu_data
[cpunum
];
1391 intel_pstate_hwp_enable(cpu
);
1392 pid_params
.sample_rate_ms
= 50;
1393 pid_params
.sample_rate_ns
= 50 * NSEC_PER_MSEC
;
1396 intel_pstate_get_cpu_pstates(cpu
);
1398 intel_pstate_busy_pid_reset(cpu
);
1400 pr_debug("controlling: cpu %d\n", cpunum
);
1405 static unsigned int intel_pstate_get(unsigned int cpu_num
)
1407 struct sample
*sample
;
1408 struct cpudata
*cpu
;
1410 cpu
= all_cpu_data
[cpu_num
];
1413 sample
= &cpu
->sample
;
1414 return get_avg_frequency(cpu
);
1417 static void intel_pstate_set_update_util_hook(unsigned int cpu_num
)
1419 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1421 /* Prevent intel_pstate_update_util() from using stale data. */
1422 cpu
->sample
.time
= 0;
1423 cpufreq_add_update_util_hook(cpu_num
, &cpu
->update_util
,
1424 intel_pstate_update_util
);
1427 static void intel_pstate_clear_update_util_hook(unsigned int cpu
)
1429 cpufreq_remove_update_util_hook(cpu
);
1430 synchronize_sched();
1433 static void intel_pstate_set_performance_limits(struct perf_limits
*limits
)
1435 limits
->no_turbo
= 0;
1436 limits
->turbo_disabled
= 0;
1437 limits
->max_perf_pct
= 100;
1438 limits
->max_perf
= int_tofp(1);
1439 limits
->min_perf_pct
= 100;
1440 limits
->min_perf
= int_tofp(1);
1441 limits
->max_policy_pct
= 100;
1442 limits
->max_sysfs_pct
= 100;
1443 limits
->min_policy_pct
= 0;
1444 limits
->min_sysfs_pct
= 0;
1447 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
1449 struct cpudata
*cpu
;
1451 if (!policy
->cpuinfo
.max_freq
)
1454 intel_pstate_clear_update_util_hook(policy
->cpu
);
1456 cpu
= all_cpu_data
[0];
1457 if (cpu
->pstate
.max_pstate_physical
> cpu
->pstate
.max_pstate
) {
1458 if (policy
->max
< policy
->cpuinfo
.max_freq
&&
1459 policy
->max
> cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
) {
1460 pr_debug("policy->max > max non turbo frequency\n");
1461 policy
->max
= policy
->cpuinfo
.max_freq
;
1465 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
1466 limits
= &performance_limits
;
1467 if (policy
->max
>= policy
->cpuinfo
.max_freq
) {
1468 pr_debug("set performance\n");
1469 intel_pstate_set_performance_limits(limits
);
1473 pr_debug("set powersave\n");
1474 limits
= &powersave_limits
;
1477 limits
->min_policy_pct
= (policy
->min
* 100) / policy
->cpuinfo
.max_freq
;
1478 limits
->min_policy_pct
= clamp_t(int, limits
->min_policy_pct
, 0 , 100);
1479 limits
->max_policy_pct
= DIV_ROUND_UP(policy
->max
* 100,
1480 policy
->cpuinfo
.max_freq
);
1481 limits
->max_policy_pct
= clamp_t(int, limits
->max_policy_pct
, 0 , 100);
1483 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1484 limits
->min_perf_pct
= max(limits
->min_policy_pct
,
1485 limits
->min_sysfs_pct
);
1486 limits
->min_perf_pct
= min(limits
->max_policy_pct
,
1487 limits
->min_perf_pct
);
1488 limits
->max_perf_pct
= min(limits
->max_policy_pct
,
1489 limits
->max_sysfs_pct
);
1490 limits
->max_perf_pct
= max(limits
->min_policy_pct
,
1491 limits
->max_perf_pct
);
1492 limits
->max_perf
= round_up(limits
->max_perf
, FRAC_BITS
);
1494 /* Make sure min_perf_pct <= max_perf_pct */
1495 limits
->min_perf_pct
= min(limits
->max_perf_pct
, limits
->min_perf_pct
);
1497 limits
->min_perf
= div_fp(limits
->min_perf_pct
, 100);
1498 limits
->max_perf
= div_fp(limits
->max_perf_pct
, 100);
1501 intel_pstate_set_update_util_hook(policy
->cpu
);
1503 intel_pstate_hwp_set_policy(policy
);
1508 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
1510 cpufreq_verify_within_cpu_limits(policy
);
1512 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
1513 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
1519 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
1521 int cpu_num
= policy
->cpu
;
1522 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
1524 pr_debug("CPU %d exiting\n", cpu_num
);
1526 intel_pstate_clear_update_util_hook(cpu_num
);
1531 intel_pstate_set_min_pstate(cpu
);
1534 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
1536 struct cpudata
*cpu
;
1539 rc
= intel_pstate_init_cpu(policy
->cpu
);
1543 cpu
= all_cpu_data
[policy
->cpu
];
1545 if (limits
->min_perf_pct
== 100 && limits
->max_perf_pct
== 100)
1546 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
1548 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
1550 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1551 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1553 /* cpuinfo and default policy values */
1554 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
1555 policy
->cpuinfo
.max_freq
=
1556 cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
1557 intel_pstate_init_acpi_perf_limits(policy
);
1558 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
1559 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
1564 static int intel_pstate_cpu_exit(struct cpufreq_policy
*policy
)
1566 intel_pstate_exit_perf_limits(policy
);
1571 static struct cpufreq_driver intel_pstate_driver
= {
1572 .flags
= CPUFREQ_CONST_LOOPS
,
1573 .verify
= intel_pstate_verify_policy
,
1574 .setpolicy
= intel_pstate_set_policy
,
1575 .resume
= intel_pstate_hwp_set_policy
,
1576 .get
= intel_pstate_get
,
1577 .init
= intel_pstate_cpu_init
,
1578 .exit
= intel_pstate_cpu_exit
,
1579 .stop_cpu
= intel_pstate_stop_cpu
,
1580 .name
= "intel_pstate",
1583 static int __initdata no_load
;
1584 static int __initdata no_hwp
;
1585 static int __initdata hwp_only
;
1586 static unsigned int force_load
;
1588 static int intel_pstate_msrs_not_valid(void)
1590 if (!pstate_funcs
.get_max() ||
1591 !pstate_funcs
.get_min() ||
1592 !pstate_funcs
.get_turbo())
1598 static void copy_pid_params(struct pstate_adjust_policy
*policy
)
1600 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
1601 pid_params
.sample_rate_ns
= pid_params
.sample_rate_ms
* NSEC_PER_MSEC
;
1602 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
1603 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
1604 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
1605 pid_params
.deadband
= policy
->deadband
;
1606 pid_params
.setpoint
= policy
->setpoint
;
1609 static void copy_cpu_funcs(struct pstate_funcs
*funcs
)
1611 pstate_funcs
.get_max
= funcs
->get_max
;
1612 pstate_funcs
.get_max_physical
= funcs
->get_max_physical
;
1613 pstate_funcs
.get_min
= funcs
->get_min
;
1614 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
1615 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
1616 pstate_funcs
.get_val
= funcs
->get_val
;
1617 pstate_funcs
.get_vid
= funcs
->get_vid
;
1618 pstate_funcs
.get_target_pstate
= funcs
->get_target_pstate
;
1624 static bool intel_pstate_no_acpi_pss(void)
1628 for_each_possible_cpu(i
) {
1630 union acpi_object
*pss
;
1631 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1632 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1637 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
1638 if (ACPI_FAILURE(status
))
1641 pss
= buffer
.pointer
;
1642 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
1653 static bool intel_pstate_has_acpi_ppc(void)
1657 for_each_possible_cpu(i
) {
1658 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1662 if (acpi_has_method(pr
->handle
, "_PPC"))
1673 struct hw_vendor_info
{
1675 char oem_id
[ACPI_OEM_ID_SIZE
];
1676 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
1680 /* Hardware vendor-specific info that has its own power management modes */
1681 static struct hw_vendor_info vendor_info
[] = {
1682 {1, "HP ", "ProLiant", PSS
},
1683 {1, "ORACLE", "X4-2 ", PPC
},
1684 {1, "ORACLE", "X4-2L ", PPC
},
1685 {1, "ORACLE", "X4-2B ", PPC
},
1686 {1, "ORACLE", "X3-2 ", PPC
},
1687 {1, "ORACLE", "X3-2L ", PPC
},
1688 {1, "ORACLE", "X3-2B ", PPC
},
1689 {1, "ORACLE", "X4470M2 ", PPC
},
1690 {1, "ORACLE", "X4270M3 ", PPC
},
1691 {1, "ORACLE", "X4270M2 ", PPC
},
1692 {1, "ORACLE", "X4170M2 ", PPC
},
1693 {1, "ORACLE", "X4170 M3", PPC
},
1694 {1, "ORACLE", "X4275 M3", PPC
},
1695 {1, "ORACLE", "X6-2 ", PPC
},
1696 {1, "ORACLE", "Sudbury ", PPC
},
1700 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1702 struct acpi_table_header hdr
;
1703 struct hw_vendor_info
*v_info
;
1704 const struct x86_cpu_id
*id
;
1707 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
1709 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
1710 if ( misc_pwr
& (1 << 8))
1714 if (acpi_disabled
||
1715 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
1718 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
1719 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
1720 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
1721 ACPI_OEM_TABLE_ID_SIZE
))
1722 switch (v_info
->oem_pwr_table
) {
1724 return intel_pstate_no_acpi_pss();
1726 return intel_pstate_has_acpi_ppc() &&
1733 #else /* CONFIG_ACPI not enabled */
1734 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1735 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1736 #endif /* CONFIG_ACPI */
1738 static const struct x86_cpu_id hwp_support_ids
[] __initconst
= {
1739 { X86_VENDOR_INTEL
, 6, X86_MODEL_ANY
, X86_FEATURE_HWP
},
1743 static int __init
intel_pstate_init(void)
1746 const struct x86_cpu_id
*id
;
1747 struct cpu_defaults
*cpu_def
;
1752 if (x86_match_cpu(hwp_support_ids
) && !no_hwp
) {
1753 copy_cpu_funcs(&core_params
.funcs
);
1755 goto hwp_cpu_matched
;
1758 id
= x86_match_cpu(intel_pstate_cpu_ids
);
1762 cpu_def
= (struct cpu_defaults
*)id
->driver_data
;
1764 copy_pid_params(&cpu_def
->pid_policy
);
1765 copy_cpu_funcs(&cpu_def
->funcs
);
1767 if (intel_pstate_msrs_not_valid())
1772 * The Intel pstate driver will be ignored if the platform
1773 * firmware has its own power management modes.
1775 if (intel_pstate_platform_pwr_mgmt_exists())
1778 pr_info("Intel P-state driver initializing\n");
1780 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
1784 if (!hwp_active
&& hwp_only
)
1787 rc
= cpufreq_register_driver(&intel_pstate_driver
);
1791 intel_pstate_debug_expose_params();
1792 intel_pstate_sysfs_expose_params();
1795 pr_info("HWP enabled\n");
1800 for_each_online_cpu(cpu
) {
1801 if (all_cpu_data
[cpu
]) {
1802 intel_pstate_clear_update_util_hook(cpu
);
1803 kfree(all_cpu_data
[cpu
]);
1808 vfree(all_cpu_data
);
1811 device_initcall(intel_pstate_init
);
1813 static int __init
intel_pstate_setup(char *str
)
1818 if (!strcmp(str
, "disable"))
1820 if (!strcmp(str
, "no_hwp")) {
1821 pr_info("HWP disabled\n");
1824 if (!strcmp(str
, "force"))
1826 if (!strcmp(str
, "hwp_only"))
1830 if (!strcmp(str
, "support_acpi_ppc"))
1836 early_param("intel_pstate", intel_pstate_setup
);
1838 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1839 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1840 MODULE_LICENSE("GPL");