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[deliverable/linux.git] / drivers / dma / dw / core.c
1 /*
2 * Core driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/bitops.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmapool.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/mm.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
26
27 #include "../dmaengine.h"
28 #include "internal.h"
29
30 /*
31 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
33 * of which use ARM any more). See the "Databook" from Synopsys for
34 * information beyond what licensees probably provide.
35 *
36 * The driver has been tested with the Atmel AT32AP7000, which does not
37 * support descriptor writeback.
38 */
39
40 #define DWC_DEFAULT_CTLLO(_chan) ({ \
41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \
42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
43 bool _is_slave = is_slave_direction(_dwc->direction); \
44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \
45 DW_DMA_MSIZE_16; \
46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \
47 DW_DMA_MSIZE_16; \
48 u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \
49 _dwc->p_master : _dwc->m_master; \
50 u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \
51 _dwc->p_master : _dwc->m_master; \
52 \
53 (DWC_CTLL_DST_MSIZE(_dmsize) \
54 | DWC_CTLL_SRC_MSIZE(_smsize) \
55 | DWC_CTLL_LLP_D_EN \
56 | DWC_CTLL_LLP_S_EN \
57 | DWC_CTLL_DMS(_dms) \
58 | DWC_CTLL_SMS(_sms)); \
59 })
60
61 /* The set of bus widths supported by the DMA controller */
62 #define DW_DMA_BUSWIDTHS \
63 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
64 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
65 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
66 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
67
68 /*----------------------------------------------------------------------*/
69
70 static struct device *chan2dev(struct dma_chan *chan)
71 {
72 return &chan->dev->device;
73 }
74
75 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
76 {
77 return to_dw_desc(dwc->active_list.next);
78 }
79
80 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
81 {
82 struct dw_desc *desc = txd_to_dw_desc(tx);
83 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
84 dma_cookie_t cookie;
85 unsigned long flags;
86
87 spin_lock_irqsave(&dwc->lock, flags);
88 cookie = dma_cookie_assign(tx);
89
90 /*
91 * REVISIT: We should attempt to chain as many descriptors as
92 * possible, perhaps even appending to those already submitted
93 * for DMA. But this is hard to do in a race-free manner.
94 */
95
96 list_add_tail(&desc->desc_node, &dwc->queue);
97 spin_unlock_irqrestore(&dwc->lock, flags);
98 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n",
99 __func__, desc->txd.cookie);
100
101 return cookie;
102 }
103
104 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
105 {
106 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
107 struct dw_desc *desc;
108 dma_addr_t phys;
109
110 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys);
111 if (!desc)
112 return NULL;
113
114 dwc->descs_allocated++;
115 INIT_LIST_HEAD(&desc->tx_list);
116 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan);
117 desc->txd.tx_submit = dwc_tx_submit;
118 desc->txd.flags = DMA_CTRL_ACK;
119 desc->txd.phys = phys;
120 return desc;
121 }
122
123 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
124 {
125 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
126 struct dw_desc *child, *_next;
127
128 if (unlikely(!desc))
129 return;
130
131 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) {
132 list_del(&child->desc_node);
133 dma_pool_free(dw->desc_pool, child, child->txd.phys);
134 dwc->descs_allocated--;
135 }
136
137 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
138 dwc->descs_allocated--;
139 }
140
141 static void dwc_initialize(struct dw_dma_chan *dwc)
142 {
143 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
144 u32 cfghi = DWC_CFGH_FIFO_MODE;
145 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
146
147 if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags))
148 return;
149
150 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
151 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
152
153 channel_writel(dwc, CFG_LO, cfglo);
154 channel_writel(dwc, CFG_HI, cfghi);
155
156 /* Enable interrupts */
157 channel_set_bit(dw, MASK.XFER, dwc->mask);
158 channel_set_bit(dw, MASK.ERROR, dwc->mask);
159
160 set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
161 }
162
163 /*----------------------------------------------------------------------*/
164
165 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
166 {
167 dev_err(chan2dev(&dwc->chan),
168 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
169 channel_readl(dwc, SAR),
170 channel_readl(dwc, DAR),
171 channel_readl(dwc, LLP),
172 channel_readl(dwc, CTL_HI),
173 channel_readl(dwc, CTL_LO));
174 }
175
176 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
177 {
178 channel_clear_bit(dw, CH_EN, dwc->mask);
179 while (dma_readl(dw, CH_EN) & dwc->mask)
180 cpu_relax();
181 }
182
183 /*----------------------------------------------------------------------*/
184
185 /* Perform single block transfer */
186 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
187 struct dw_desc *desc)
188 {
189 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
190 u32 ctllo;
191
192 /*
193 * Software emulation of LLP mode relies on interrupts to continue
194 * multi block transfer.
195 */
196 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN;
197
198 channel_writel(dwc, SAR, lli_read(desc, sar));
199 channel_writel(dwc, DAR, lli_read(desc, dar));
200 channel_writel(dwc, CTL_LO, ctllo);
201 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi));
202 channel_set_bit(dw, CH_EN, dwc->mask);
203
204 /* Move pointer to next descriptor */
205 dwc->tx_node_active = dwc->tx_node_active->next;
206 }
207
208 /* Called with dwc->lock held and bh disabled */
209 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
210 {
211 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
212 u8 lms = DWC_LLP_LMS(dwc->m_master);
213 unsigned long was_soft_llp;
214
215 /* ASSERT: channel is idle */
216 if (dma_readl(dw, CH_EN) & dwc->mask) {
217 dev_err(chan2dev(&dwc->chan),
218 "%s: BUG: Attempted to start non-idle channel\n",
219 __func__);
220 dwc_dump_chan_regs(dwc);
221
222 /* The tasklet will hopefully advance the queue... */
223 return;
224 }
225
226 if (dwc->nollp) {
227 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
228 &dwc->flags);
229 if (was_soft_llp) {
230 dev_err(chan2dev(&dwc->chan),
231 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
232 return;
233 }
234
235 dwc_initialize(dwc);
236
237 first->residue = first->total_len;
238 dwc->tx_node_active = &first->tx_list;
239
240 /* Submit first block */
241 dwc_do_single_block(dwc, first);
242
243 return;
244 }
245
246 dwc_initialize(dwc);
247
248 channel_writel(dwc, LLP, first->txd.phys | lms);
249 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
250 channel_writel(dwc, CTL_HI, 0);
251 channel_set_bit(dw, CH_EN, dwc->mask);
252 }
253
254 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
255 {
256 struct dw_desc *desc;
257
258 if (list_empty(&dwc->queue))
259 return;
260
261 list_move(dwc->queue.next, &dwc->active_list);
262 desc = dwc_first_active(dwc);
263 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
264 dwc_dostart(dwc, desc);
265 }
266
267 /*----------------------------------------------------------------------*/
268
269 static void
270 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
271 bool callback_required)
272 {
273 struct dma_async_tx_descriptor *txd = &desc->txd;
274 struct dw_desc *child;
275 unsigned long flags;
276 struct dmaengine_desc_callback cb;
277
278 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
279
280 spin_lock_irqsave(&dwc->lock, flags);
281 dma_cookie_complete(txd);
282 if (callback_required)
283 dmaengine_desc_get_callback(txd, &cb);
284 else
285 memset(&cb, 0, sizeof(cb));
286
287 /* async_tx_ack */
288 list_for_each_entry(child, &desc->tx_list, desc_node)
289 async_tx_ack(&child->txd);
290 async_tx_ack(&desc->txd);
291 dwc_desc_put(dwc, desc);
292 spin_unlock_irqrestore(&dwc->lock, flags);
293
294 dmaengine_desc_callback_invoke(&cb, NULL);
295 }
296
297 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
298 {
299 struct dw_desc *desc, *_desc;
300 LIST_HEAD(list);
301 unsigned long flags;
302
303 spin_lock_irqsave(&dwc->lock, flags);
304 if (dma_readl(dw, CH_EN) & dwc->mask) {
305 dev_err(chan2dev(&dwc->chan),
306 "BUG: XFER bit set, but channel not idle!\n");
307
308 /* Try to continue after resetting the channel... */
309 dwc_chan_disable(dw, dwc);
310 }
311
312 /*
313 * Submit queued descriptors ASAP, i.e. before we go through
314 * the completed ones.
315 */
316 list_splice_init(&dwc->active_list, &list);
317 dwc_dostart_first_queued(dwc);
318
319 spin_unlock_irqrestore(&dwc->lock, flags);
320
321 list_for_each_entry_safe(desc, _desc, &list, desc_node)
322 dwc_descriptor_complete(dwc, desc, true);
323 }
324
325 /* Returns how many bytes were already received from source */
326 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
327 {
328 u32 ctlhi = channel_readl(dwc, CTL_HI);
329 u32 ctllo = channel_readl(dwc, CTL_LO);
330
331 return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
332 }
333
334 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
335 {
336 dma_addr_t llp;
337 struct dw_desc *desc, *_desc;
338 struct dw_desc *child;
339 u32 status_xfer;
340 unsigned long flags;
341
342 spin_lock_irqsave(&dwc->lock, flags);
343 llp = channel_readl(dwc, LLP);
344 status_xfer = dma_readl(dw, RAW.XFER);
345
346 if (status_xfer & dwc->mask) {
347 /* Everything we've submitted is done */
348 dma_writel(dw, CLEAR.XFER, dwc->mask);
349
350 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
351 struct list_head *head, *active = dwc->tx_node_active;
352
353 /*
354 * We are inside first active descriptor.
355 * Otherwise something is really wrong.
356 */
357 desc = dwc_first_active(dwc);
358
359 head = &desc->tx_list;
360 if (active != head) {
361 /* Update residue to reflect last sent descriptor */
362 if (active == head->next)
363 desc->residue -= desc->len;
364 else
365 desc->residue -= to_dw_desc(active->prev)->len;
366
367 child = to_dw_desc(active);
368
369 /* Submit next block */
370 dwc_do_single_block(dwc, child);
371
372 spin_unlock_irqrestore(&dwc->lock, flags);
373 return;
374 }
375
376 /* We are done here */
377 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
378 }
379
380 spin_unlock_irqrestore(&dwc->lock, flags);
381
382 dwc_complete_all(dw, dwc);
383 return;
384 }
385
386 if (list_empty(&dwc->active_list)) {
387 spin_unlock_irqrestore(&dwc->lock, flags);
388 return;
389 }
390
391 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
392 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
393 spin_unlock_irqrestore(&dwc->lock, flags);
394 return;
395 }
396
397 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
398
399 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
400 /* Initial residue value */
401 desc->residue = desc->total_len;
402
403 /* Check first descriptors addr */
404 if (desc->txd.phys == DWC_LLP_LOC(llp)) {
405 spin_unlock_irqrestore(&dwc->lock, flags);
406 return;
407 }
408
409 /* Check first descriptors llp */
410 if (lli_read(desc, llp) == llp) {
411 /* This one is currently in progress */
412 desc->residue -= dwc_get_sent(dwc);
413 spin_unlock_irqrestore(&dwc->lock, flags);
414 return;
415 }
416
417 desc->residue -= desc->len;
418 list_for_each_entry(child, &desc->tx_list, desc_node) {
419 if (lli_read(child, llp) == llp) {
420 /* Currently in progress */
421 desc->residue -= dwc_get_sent(dwc);
422 spin_unlock_irqrestore(&dwc->lock, flags);
423 return;
424 }
425 desc->residue -= child->len;
426 }
427
428 /*
429 * No descriptors so far seem to be in progress, i.e.
430 * this one must be done.
431 */
432 spin_unlock_irqrestore(&dwc->lock, flags);
433 dwc_descriptor_complete(dwc, desc, true);
434 spin_lock_irqsave(&dwc->lock, flags);
435 }
436
437 dev_err(chan2dev(&dwc->chan),
438 "BUG: All descriptors done, but channel not idle!\n");
439
440 /* Try to continue after resetting the channel... */
441 dwc_chan_disable(dw, dwc);
442
443 dwc_dostart_first_queued(dwc);
444 spin_unlock_irqrestore(&dwc->lock, flags);
445 }
446
447 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc)
448 {
449 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
450 lli_read(desc, sar),
451 lli_read(desc, dar),
452 lli_read(desc, llp),
453 lli_read(desc, ctlhi),
454 lli_read(desc, ctllo));
455 }
456
457 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
458 {
459 struct dw_desc *bad_desc;
460 struct dw_desc *child;
461 unsigned long flags;
462
463 dwc_scan_descriptors(dw, dwc);
464
465 spin_lock_irqsave(&dwc->lock, flags);
466
467 /*
468 * The descriptor currently at the head of the active list is
469 * borked. Since we don't have any way to report errors, we'll
470 * just have to scream loudly and try to carry on.
471 */
472 bad_desc = dwc_first_active(dwc);
473 list_del_init(&bad_desc->desc_node);
474 list_move(dwc->queue.next, dwc->active_list.prev);
475
476 /* Clear the error flag and try to restart the controller */
477 dma_writel(dw, CLEAR.ERROR, dwc->mask);
478 if (!list_empty(&dwc->active_list))
479 dwc_dostart(dwc, dwc_first_active(dwc));
480
481 /*
482 * WARN may seem harsh, but since this only happens
483 * when someone submits a bad physical address in a
484 * descriptor, we should consider ourselves lucky that the
485 * controller flagged an error instead of scribbling over
486 * random memory locations.
487 */
488 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
489 " cookie: %d\n", bad_desc->txd.cookie);
490 dwc_dump_lli(dwc, bad_desc);
491 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
492 dwc_dump_lli(dwc, child);
493
494 spin_unlock_irqrestore(&dwc->lock, flags);
495
496 /* Pretend the descriptor completed successfully */
497 dwc_descriptor_complete(dwc, bad_desc, true);
498 }
499
500 /* --------------------- Cyclic DMA API extensions -------------------- */
501
502 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
503 {
504 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
505 return channel_readl(dwc, SAR);
506 }
507 EXPORT_SYMBOL(dw_dma_get_src_addr);
508
509 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
510 {
511 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
512 return channel_readl(dwc, DAR);
513 }
514 EXPORT_SYMBOL(dw_dma_get_dst_addr);
515
516 /* Called with dwc->lock held and all DMAC interrupts disabled */
517 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
518 u32 status_block, u32 status_err, u32 status_xfer)
519 {
520 unsigned long flags;
521
522 if (status_block & dwc->mask) {
523 void (*callback)(void *param);
524 void *callback_param;
525
526 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
527 channel_readl(dwc, LLP));
528 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
529
530 callback = dwc->cdesc->period_callback;
531 callback_param = dwc->cdesc->period_callback_param;
532
533 if (callback)
534 callback(callback_param);
535 }
536
537 /*
538 * Error and transfer complete are highly unlikely, and will most
539 * likely be due to a configuration error by the user.
540 */
541 if (unlikely(status_err & dwc->mask) ||
542 unlikely(status_xfer & dwc->mask)) {
543 unsigned int i;
544
545 dev_err(chan2dev(&dwc->chan),
546 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
547 status_xfer ? "xfer" : "error");
548
549 spin_lock_irqsave(&dwc->lock, flags);
550
551 dwc_dump_chan_regs(dwc);
552
553 dwc_chan_disable(dw, dwc);
554
555 /* Make sure DMA does not restart by loading a new list */
556 channel_writel(dwc, LLP, 0);
557 channel_writel(dwc, CTL_LO, 0);
558 channel_writel(dwc, CTL_HI, 0);
559
560 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
561 dma_writel(dw, CLEAR.ERROR, dwc->mask);
562 dma_writel(dw, CLEAR.XFER, dwc->mask);
563
564 for (i = 0; i < dwc->cdesc->periods; i++)
565 dwc_dump_lli(dwc, dwc->cdesc->desc[i]);
566
567 spin_unlock_irqrestore(&dwc->lock, flags);
568 }
569
570 /* Re-enable interrupts */
571 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
572 }
573
574 /* ------------------------------------------------------------------------- */
575
576 static void dw_dma_tasklet(unsigned long data)
577 {
578 struct dw_dma *dw = (struct dw_dma *)data;
579 struct dw_dma_chan *dwc;
580 u32 status_block;
581 u32 status_xfer;
582 u32 status_err;
583 unsigned int i;
584
585 status_block = dma_readl(dw, RAW.BLOCK);
586 status_xfer = dma_readl(dw, RAW.XFER);
587 status_err = dma_readl(dw, RAW.ERROR);
588
589 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
590
591 for (i = 0; i < dw->dma.chancnt; i++) {
592 dwc = &dw->chan[i];
593 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
594 dwc_handle_cyclic(dw, dwc, status_block, status_err,
595 status_xfer);
596 else if (status_err & (1 << i))
597 dwc_handle_error(dw, dwc);
598 else if (status_xfer & (1 << i))
599 dwc_scan_descriptors(dw, dwc);
600 }
601
602 /* Re-enable interrupts */
603 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
604 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
605 }
606
607 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
608 {
609 struct dw_dma *dw = dev_id;
610 u32 status;
611
612 /* Check if we have any interrupt from the DMAC which is not in use */
613 if (!dw->in_use)
614 return IRQ_NONE;
615
616 status = dma_readl(dw, STATUS_INT);
617 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
618
619 /* Check if we have any interrupt from the DMAC */
620 if (!status)
621 return IRQ_NONE;
622
623 /*
624 * Just disable the interrupts. We'll turn them back on in the
625 * softirq handler.
626 */
627 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
628 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
629 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
630
631 status = dma_readl(dw, STATUS_INT);
632 if (status) {
633 dev_err(dw->dma.dev,
634 "BUG: Unexpected interrupts pending: 0x%x\n",
635 status);
636
637 /* Try to recover */
638 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
639 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
640 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
641 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
642 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
643 }
644
645 tasklet_schedule(&dw->tasklet);
646
647 return IRQ_HANDLED;
648 }
649
650 /*----------------------------------------------------------------------*/
651
652 static struct dma_async_tx_descriptor *
653 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
654 size_t len, unsigned long flags)
655 {
656 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
657 struct dw_dma *dw = to_dw_dma(chan->device);
658 struct dw_desc *desc;
659 struct dw_desc *first;
660 struct dw_desc *prev;
661 size_t xfer_count;
662 size_t offset;
663 u8 m_master = dwc->m_master;
664 unsigned int src_width;
665 unsigned int dst_width;
666 unsigned int data_width = dw->pdata->data_width[m_master];
667 u32 ctllo;
668 u8 lms = DWC_LLP_LMS(m_master);
669
670 dev_vdbg(chan2dev(chan),
671 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
672 &dest, &src, len, flags);
673
674 if (unlikely(!len)) {
675 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
676 return NULL;
677 }
678
679 dwc->direction = DMA_MEM_TO_MEM;
680
681 src_width = dst_width = __ffs(data_width | src | dest | len);
682
683 ctllo = DWC_DEFAULT_CTLLO(chan)
684 | DWC_CTLL_DST_WIDTH(dst_width)
685 | DWC_CTLL_SRC_WIDTH(src_width)
686 | DWC_CTLL_DST_INC
687 | DWC_CTLL_SRC_INC
688 | DWC_CTLL_FC_M2M;
689 prev = first = NULL;
690
691 for (offset = 0; offset < len; offset += xfer_count << src_width) {
692 xfer_count = min_t(size_t, (len - offset) >> src_width,
693 dwc->block_size);
694
695 desc = dwc_desc_get(dwc);
696 if (!desc)
697 goto err_desc_get;
698
699 lli_write(desc, sar, src + offset);
700 lli_write(desc, dar, dest + offset);
701 lli_write(desc, ctllo, ctllo);
702 lli_write(desc, ctlhi, xfer_count);
703 desc->len = xfer_count << src_width;
704
705 if (!first) {
706 first = desc;
707 } else {
708 lli_write(prev, llp, desc->txd.phys | lms);
709 list_add_tail(&desc->desc_node, &first->tx_list);
710 }
711 prev = desc;
712 }
713
714 if (flags & DMA_PREP_INTERRUPT)
715 /* Trigger interrupt after last block */
716 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
717
718 prev->lli.llp = 0;
719 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
720 first->txd.flags = flags;
721 first->total_len = len;
722
723 return &first->txd;
724
725 err_desc_get:
726 dwc_desc_put(dwc, first);
727 return NULL;
728 }
729
730 static struct dma_async_tx_descriptor *
731 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
732 unsigned int sg_len, enum dma_transfer_direction direction,
733 unsigned long flags, void *context)
734 {
735 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
736 struct dw_dma *dw = to_dw_dma(chan->device);
737 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
738 struct dw_desc *prev;
739 struct dw_desc *first;
740 u32 ctllo;
741 u8 m_master = dwc->m_master;
742 u8 lms = DWC_LLP_LMS(m_master);
743 dma_addr_t reg;
744 unsigned int reg_width;
745 unsigned int mem_width;
746 unsigned int data_width = dw->pdata->data_width[m_master];
747 unsigned int i;
748 struct scatterlist *sg;
749 size_t total_len = 0;
750
751 dev_vdbg(chan2dev(chan), "%s\n", __func__);
752
753 if (unlikely(!is_slave_direction(direction) || !sg_len))
754 return NULL;
755
756 dwc->direction = direction;
757
758 prev = first = NULL;
759
760 switch (direction) {
761 case DMA_MEM_TO_DEV:
762 reg_width = __ffs(sconfig->dst_addr_width);
763 reg = sconfig->dst_addr;
764 ctllo = (DWC_DEFAULT_CTLLO(chan)
765 | DWC_CTLL_DST_WIDTH(reg_width)
766 | DWC_CTLL_DST_FIX
767 | DWC_CTLL_SRC_INC);
768
769 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
770 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
771
772 for_each_sg(sgl, sg, sg_len, i) {
773 struct dw_desc *desc;
774 u32 len, dlen, mem;
775
776 mem = sg_dma_address(sg);
777 len = sg_dma_len(sg);
778
779 mem_width = __ffs(data_width | mem | len);
780
781 slave_sg_todev_fill_desc:
782 desc = dwc_desc_get(dwc);
783 if (!desc)
784 goto err_desc_get;
785
786 lli_write(desc, sar, mem);
787 lli_write(desc, dar, reg);
788 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
789 if ((len >> mem_width) > dwc->block_size) {
790 dlen = dwc->block_size << mem_width;
791 mem += dlen;
792 len -= dlen;
793 } else {
794 dlen = len;
795 len = 0;
796 }
797
798 lli_write(desc, ctlhi, dlen >> mem_width);
799 desc->len = dlen;
800
801 if (!first) {
802 first = desc;
803 } else {
804 lli_write(prev, llp, desc->txd.phys | lms);
805 list_add_tail(&desc->desc_node, &first->tx_list);
806 }
807 prev = desc;
808 total_len += dlen;
809
810 if (len)
811 goto slave_sg_todev_fill_desc;
812 }
813 break;
814 case DMA_DEV_TO_MEM:
815 reg_width = __ffs(sconfig->src_addr_width);
816 reg = sconfig->src_addr;
817 ctllo = (DWC_DEFAULT_CTLLO(chan)
818 | DWC_CTLL_SRC_WIDTH(reg_width)
819 | DWC_CTLL_DST_INC
820 | DWC_CTLL_SRC_FIX);
821
822 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
823 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
824
825 for_each_sg(sgl, sg, sg_len, i) {
826 struct dw_desc *desc;
827 u32 len, dlen, mem;
828
829 mem = sg_dma_address(sg);
830 len = sg_dma_len(sg);
831
832 mem_width = __ffs(data_width | mem | len);
833
834 slave_sg_fromdev_fill_desc:
835 desc = dwc_desc_get(dwc);
836 if (!desc)
837 goto err_desc_get;
838
839 lli_write(desc, sar, reg);
840 lli_write(desc, dar, mem);
841 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
842 if ((len >> reg_width) > dwc->block_size) {
843 dlen = dwc->block_size << reg_width;
844 mem += dlen;
845 len -= dlen;
846 } else {
847 dlen = len;
848 len = 0;
849 }
850 lli_write(desc, ctlhi, dlen >> reg_width);
851 desc->len = dlen;
852
853 if (!first) {
854 first = desc;
855 } else {
856 lli_write(prev, llp, desc->txd.phys | lms);
857 list_add_tail(&desc->desc_node, &first->tx_list);
858 }
859 prev = desc;
860 total_len += dlen;
861
862 if (len)
863 goto slave_sg_fromdev_fill_desc;
864 }
865 break;
866 default:
867 return NULL;
868 }
869
870 if (flags & DMA_PREP_INTERRUPT)
871 /* Trigger interrupt after last block */
872 lli_set(prev, ctllo, DWC_CTLL_INT_EN);
873
874 prev->lli.llp = 0;
875 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
876 first->total_len = total_len;
877
878 return &first->txd;
879
880 err_desc_get:
881 dev_err(chan2dev(chan),
882 "not enough descriptors available. Direction %d\n", direction);
883 dwc_desc_put(dwc, first);
884 return NULL;
885 }
886
887 bool dw_dma_filter(struct dma_chan *chan, void *param)
888 {
889 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
890 struct dw_dma_slave *dws = param;
891
892 if (dws->dma_dev != chan->device->dev)
893 return false;
894
895 /* We have to copy data since dws can be temporary storage */
896
897 dwc->src_id = dws->src_id;
898 dwc->dst_id = dws->dst_id;
899
900 dwc->m_master = dws->m_master;
901 dwc->p_master = dws->p_master;
902
903 return true;
904 }
905 EXPORT_SYMBOL_GPL(dw_dma_filter);
906
907 /*
908 * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
909 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
910 *
911 * NOTE: burst size 2 is not supported by controller.
912 *
913 * This can be done by finding least significant bit set: n & (n - 1)
914 */
915 static inline void convert_burst(u32 *maxburst)
916 {
917 if (*maxburst > 1)
918 *maxburst = fls(*maxburst) - 2;
919 else
920 *maxburst = 0;
921 }
922
923 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
924 {
925 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
926
927 /* Check if chan will be configured for slave transfers */
928 if (!is_slave_direction(sconfig->direction))
929 return -EINVAL;
930
931 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
932 dwc->direction = sconfig->direction;
933
934 convert_burst(&dwc->dma_sconfig.src_maxburst);
935 convert_burst(&dwc->dma_sconfig.dst_maxburst);
936
937 return 0;
938 }
939
940 static int dwc_pause(struct dma_chan *chan)
941 {
942 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
943 unsigned long flags;
944 unsigned int count = 20; /* timeout iterations */
945 u32 cfglo;
946
947 spin_lock_irqsave(&dwc->lock, flags);
948
949 cfglo = channel_readl(dwc, CFG_LO);
950 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
951 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
952 udelay(2);
953
954 set_bit(DW_DMA_IS_PAUSED, &dwc->flags);
955
956 spin_unlock_irqrestore(&dwc->lock, flags);
957
958 return 0;
959 }
960
961 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
962 {
963 u32 cfglo = channel_readl(dwc, CFG_LO);
964
965 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
966
967 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags);
968 }
969
970 static int dwc_resume(struct dma_chan *chan)
971 {
972 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
973 unsigned long flags;
974
975 spin_lock_irqsave(&dwc->lock, flags);
976
977 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
978 dwc_chan_resume(dwc);
979
980 spin_unlock_irqrestore(&dwc->lock, flags);
981
982 return 0;
983 }
984
985 static int dwc_terminate_all(struct dma_chan *chan)
986 {
987 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
988 struct dw_dma *dw = to_dw_dma(chan->device);
989 struct dw_desc *desc, *_desc;
990 unsigned long flags;
991 LIST_HEAD(list);
992
993 spin_lock_irqsave(&dwc->lock, flags);
994
995 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
996
997 dwc_chan_disable(dw, dwc);
998
999 dwc_chan_resume(dwc);
1000
1001 /* active_list entries will end up before queued entries */
1002 list_splice_init(&dwc->queue, &list);
1003 list_splice_init(&dwc->active_list, &list);
1004
1005 spin_unlock_irqrestore(&dwc->lock, flags);
1006
1007 /* Flush all pending and queued descriptors */
1008 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1009 dwc_descriptor_complete(dwc, desc, false);
1010
1011 return 0;
1012 }
1013
1014 static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c)
1015 {
1016 struct dw_desc *desc;
1017
1018 list_for_each_entry(desc, &dwc->active_list, desc_node)
1019 if (desc->txd.cookie == c)
1020 return desc;
1021
1022 return NULL;
1023 }
1024
1025 static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie)
1026 {
1027 struct dw_desc *desc;
1028 unsigned long flags;
1029 u32 residue;
1030
1031 spin_lock_irqsave(&dwc->lock, flags);
1032
1033 desc = dwc_find_desc(dwc, cookie);
1034 if (desc) {
1035 if (desc == dwc_first_active(dwc)) {
1036 residue = desc->residue;
1037 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1038 residue -= dwc_get_sent(dwc);
1039 } else {
1040 residue = desc->total_len;
1041 }
1042 } else {
1043 residue = 0;
1044 }
1045
1046 spin_unlock_irqrestore(&dwc->lock, flags);
1047 return residue;
1048 }
1049
1050 static enum dma_status
1051 dwc_tx_status(struct dma_chan *chan,
1052 dma_cookie_t cookie,
1053 struct dma_tx_state *txstate)
1054 {
1055 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1056 enum dma_status ret;
1057
1058 ret = dma_cookie_status(chan, cookie, txstate);
1059 if (ret == DMA_COMPLETE)
1060 return ret;
1061
1062 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1063
1064 ret = dma_cookie_status(chan, cookie, txstate);
1065 if (ret == DMA_COMPLETE)
1066 return ret;
1067
1068 dma_set_residue(txstate, dwc_get_residue(dwc, cookie));
1069
1070 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS)
1071 return DMA_PAUSED;
1072
1073 return ret;
1074 }
1075
1076 static void dwc_issue_pending(struct dma_chan *chan)
1077 {
1078 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1079 unsigned long flags;
1080
1081 spin_lock_irqsave(&dwc->lock, flags);
1082 if (list_empty(&dwc->active_list))
1083 dwc_dostart_first_queued(dwc);
1084 spin_unlock_irqrestore(&dwc->lock, flags);
1085 }
1086
1087 /*----------------------------------------------------------------------*/
1088
1089 static void dw_dma_off(struct dw_dma *dw)
1090 {
1091 unsigned int i;
1092
1093 dma_writel(dw, CFG, 0);
1094
1095 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1096 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1097 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1098 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1099 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1100
1101 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1102 cpu_relax();
1103
1104 for (i = 0; i < dw->dma.chancnt; i++)
1105 clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags);
1106 }
1107
1108 static void dw_dma_on(struct dw_dma *dw)
1109 {
1110 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1111 }
1112
1113 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1114 {
1115 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1116 struct dw_dma *dw = to_dw_dma(chan->device);
1117
1118 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1119
1120 /* ASSERT: channel is idle */
1121 if (dma_readl(dw, CH_EN) & dwc->mask) {
1122 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1123 return -EIO;
1124 }
1125
1126 dma_cookie_init(chan);
1127
1128 /*
1129 * NOTE: some controllers may have additional features that we
1130 * need to initialize here, like "scatter-gather" (which
1131 * doesn't mean what you think it means), and status writeback.
1132 */
1133
1134 /*
1135 * We need controller-specific data to set up slave transfers.
1136 */
1137 if (chan->private && !dw_dma_filter(chan, chan->private)) {
1138 dev_warn(chan2dev(chan), "Wrong controller-specific data\n");
1139 return -EINVAL;
1140 }
1141
1142 /* Enable controller here if needed */
1143 if (!dw->in_use)
1144 dw_dma_on(dw);
1145 dw->in_use |= dwc->mask;
1146
1147 return 0;
1148 }
1149
1150 static void dwc_free_chan_resources(struct dma_chan *chan)
1151 {
1152 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1153 struct dw_dma *dw = to_dw_dma(chan->device);
1154 unsigned long flags;
1155 LIST_HEAD(list);
1156
1157 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1158 dwc->descs_allocated);
1159
1160 /* ASSERT: channel is idle */
1161 BUG_ON(!list_empty(&dwc->active_list));
1162 BUG_ON(!list_empty(&dwc->queue));
1163 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1164
1165 spin_lock_irqsave(&dwc->lock, flags);
1166
1167 /* Clear custom channel configuration */
1168 dwc->src_id = 0;
1169 dwc->dst_id = 0;
1170
1171 dwc->m_master = 0;
1172 dwc->p_master = 0;
1173
1174 clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags);
1175
1176 /* Disable interrupts */
1177 channel_clear_bit(dw, MASK.XFER, dwc->mask);
1178 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1179 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1180
1181 spin_unlock_irqrestore(&dwc->lock, flags);
1182
1183 /* Disable controller in case it was a last user */
1184 dw->in_use &= ~dwc->mask;
1185 if (!dw->in_use)
1186 dw_dma_off(dw);
1187
1188 dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1189 }
1190
1191 /* --------------------- Cyclic DMA API extensions -------------------- */
1192
1193 /**
1194 * dw_dma_cyclic_start - start the cyclic DMA transfer
1195 * @chan: the DMA channel to start
1196 *
1197 * Must be called with soft interrupts disabled. Returns zero on success or
1198 * -errno on failure.
1199 */
1200 int dw_dma_cyclic_start(struct dma_chan *chan)
1201 {
1202 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1203 struct dw_dma *dw = to_dw_dma(chan->device);
1204 unsigned long flags;
1205
1206 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1207 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1208 return -ENODEV;
1209 }
1210
1211 spin_lock_irqsave(&dwc->lock, flags);
1212
1213 /* Enable interrupts to perform cyclic transfer */
1214 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1215
1216 dwc_dostart(dwc, dwc->cdesc->desc[0]);
1217
1218 spin_unlock_irqrestore(&dwc->lock, flags);
1219
1220 return 0;
1221 }
1222 EXPORT_SYMBOL(dw_dma_cyclic_start);
1223
1224 /**
1225 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1226 * @chan: the DMA channel to stop
1227 *
1228 * Must be called with soft interrupts disabled.
1229 */
1230 void dw_dma_cyclic_stop(struct dma_chan *chan)
1231 {
1232 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1233 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1234 unsigned long flags;
1235
1236 spin_lock_irqsave(&dwc->lock, flags);
1237
1238 dwc_chan_disable(dw, dwc);
1239
1240 spin_unlock_irqrestore(&dwc->lock, flags);
1241 }
1242 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1243
1244 /**
1245 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1246 * @chan: the DMA channel to prepare
1247 * @buf_addr: physical DMA address where the buffer starts
1248 * @buf_len: total number of bytes for the entire buffer
1249 * @period_len: number of bytes for each period
1250 * @direction: transfer direction, to or from device
1251 *
1252 * Must be called before trying to start the transfer. Returns a valid struct
1253 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1254 */
1255 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1256 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1257 enum dma_transfer_direction direction)
1258 {
1259 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1260 struct dma_slave_config *sconfig = &dwc->dma_sconfig;
1261 struct dw_cyclic_desc *cdesc;
1262 struct dw_cyclic_desc *retval = NULL;
1263 struct dw_desc *desc;
1264 struct dw_desc *last = NULL;
1265 u8 lms = DWC_LLP_LMS(dwc->m_master);
1266 unsigned long was_cyclic;
1267 unsigned int reg_width;
1268 unsigned int periods;
1269 unsigned int i;
1270 unsigned long flags;
1271
1272 spin_lock_irqsave(&dwc->lock, flags);
1273 if (dwc->nollp) {
1274 spin_unlock_irqrestore(&dwc->lock, flags);
1275 dev_dbg(chan2dev(&dwc->chan),
1276 "channel doesn't support LLP transfers\n");
1277 return ERR_PTR(-EINVAL);
1278 }
1279
1280 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1281 spin_unlock_irqrestore(&dwc->lock, flags);
1282 dev_dbg(chan2dev(&dwc->chan),
1283 "queue and/or active list are not empty\n");
1284 return ERR_PTR(-EBUSY);
1285 }
1286
1287 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1288 spin_unlock_irqrestore(&dwc->lock, flags);
1289 if (was_cyclic) {
1290 dev_dbg(chan2dev(&dwc->chan),
1291 "channel already prepared for cyclic DMA\n");
1292 return ERR_PTR(-EBUSY);
1293 }
1294
1295 retval = ERR_PTR(-EINVAL);
1296
1297 if (unlikely(!is_slave_direction(direction)))
1298 goto out_err;
1299
1300 dwc->direction = direction;
1301
1302 if (direction == DMA_MEM_TO_DEV)
1303 reg_width = __ffs(sconfig->dst_addr_width);
1304 else
1305 reg_width = __ffs(sconfig->src_addr_width);
1306
1307 periods = buf_len / period_len;
1308
1309 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1310 if (period_len > (dwc->block_size << reg_width))
1311 goto out_err;
1312 if (unlikely(period_len & ((1 << reg_width) - 1)))
1313 goto out_err;
1314 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1315 goto out_err;
1316
1317 retval = ERR_PTR(-ENOMEM);
1318
1319 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1320 if (!cdesc)
1321 goto out_err;
1322
1323 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1324 if (!cdesc->desc)
1325 goto out_err_alloc;
1326
1327 for (i = 0; i < periods; i++) {
1328 desc = dwc_desc_get(dwc);
1329 if (!desc)
1330 goto out_err_desc_get;
1331
1332 switch (direction) {
1333 case DMA_MEM_TO_DEV:
1334 lli_write(desc, dar, sconfig->dst_addr);
1335 lli_write(desc, sar, buf_addr + period_len * i);
1336 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan)
1337 | DWC_CTLL_DST_WIDTH(reg_width)
1338 | DWC_CTLL_SRC_WIDTH(reg_width)
1339 | DWC_CTLL_DST_FIX
1340 | DWC_CTLL_SRC_INC
1341 | DWC_CTLL_INT_EN));
1342
1343 lli_set(desc, ctllo, sconfig->device_fc ?
1344 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1345 DWC_CTLL_FC(DW_DMA_FC_D_M2P));
1346
1347 break;
1348 case DMA_DEV_TO_MEM:
1349 lli_write(desc, dar, buf_addr + period_len * i);
1350 lli_write(desc, sar, sconfig->src_addr);
1351 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan)
1352 | DWC_CTLL_SRC_WIDTH(reg_width)
1353 | DWC_CTLL_DST_WIDTH(reg_width)
1354 | DWC_CTLL_DST_INC
1355 | DWC_CTLL_SRC_FIX
1356 | DWC_CTLL_INT_EN));
1357
1358 lli_set(desc, ctllo, sconfig->device_fc ?
1359 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1360 DWC_CTLL_FC(DW_DMA_FC_D_P2M));
1361
1362 break;
1363 default:
1364 break;
1365 }
1366
1367 lli_write(desc, ctlhi, period_len >> reg_width);
1368 cdesc->desc[i] = desc;
1369
1370 if (last)
1371 lli_write(last, llp, desc->txd.phys | lms);
1372
1373 last = desc;
1374 }
1375
1376 /* Let's make a cyclic list */
1377 lli_write(last, llp, cdesc->desc[0]->txd.phys | lms);
1378
1379 dev_dbg(chan2dev(&dwc->chan),
1380 "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1381 &buf_addr, buf_len, period_len, periods);
1382
1383 cdesc->periods = periods;
1384 dwc->cdesc = cdesc;
1385
1386 return cdesc;
1387
1388 out_err_desc_get:
1389 while (i--)
1390 dwc_desc_put(dwc, cdesc->desc[i]);
1391 out_err_alloc:
1392 kfree(cdesc);
1393 out_err:
1394 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1395 return (struct dw_cyclic_desc *)retval;
1396 }
1397 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1398
1399 /**
1400 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1401 * @chan: the DMA channel to free
1402 */
1403 void dw_dma_cyclic_free(struct dma_chan *chan)
1404 {
1405 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1406 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1407 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1408 unsigned int i;
1409 unsigned long flags;
1410
1411 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1412
1413 if (!cdesc)
1414 return;
1415
1416 spin_lock_irqsave(&dwc->lock, flags);
1417
1418 dwc_chan_disable(dw, dwc);
1419
1420 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1421 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1422 dma_writel(dw, CLEAR.XFER, dwc->mask);
1423
1424 spin_unlock_irqrestore(&dwc->lock, flags);
1425
1426 for (i = 0; i < cdesc->periods; i++)
1427 dwc_desc_put(dwc, cdesc->desc[i]);
1428
1429 kfree(cdesc->desc);
1430 kfree(cdesc);
1431
1432 dwc->cdesc = NULL;
1433
1434 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1435 }
1436 EXPORT_SYMBOL(dw_dma_cyclic_free);
1437
1438 /*----------------------------------------------------------------------*/
1439
1440 int dw_dma_probe(struct dw_dma_chip *chip)
1441 {
1442 struct dw_dma_platform_data *pdata;
1443 struct dw_dma *dw;
1444 bool autocfg = false;
1445 unsigned int dw_params;
1446 unsigned int i;
1447 int err;
1448
1449 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1450 if (!dw)
1451 return -ENOMEM;
1452
1453 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
1454 if (!dw->pdata)
1455 return -ENOMEM;
1456
1457 dw->regs = chip->regs;
1458 chip->dw = dw;
1459
1460 pm_runtime_get_sync(chip->dev);
1461
1462 if (!chip->pdata) {
1463 dw_params = dma_readl(dw, DW_PARAMS);
1464 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1465
1466 autocfg = dw_params >> DW_PARAMS_EN & 1;
1467 if (!autocfg) {
1468 err = -EINVAL;
1469 goto err_pdata;
1470 }
1471
1472 /* Reassign the platform data pointer */
1473 pdata = dw->pdata;
1474
1475 /* Get hardware configuration parameters */
1476 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1477 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1478 for (i = 0; i < pdata->nr_masters; i++) {
1479 pdata->data_width[i] =
1480 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3);
1481 }
1482 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE);
1483
1484 /* Fill platform data with the default values */
1485 pdata->is_private = true;
1486 pdata->is_memcpy = true;
1487 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1488 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1489 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1490 err = -EINVAL;
1491 goto err_pdata;
1492 } else {
1493 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
1494
1495 /* Reassign the platform data pointer */
1496 pdata = dw->pdata;
1497 }
1498
1499 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1500 GFP_KERNEL);
1501 if (!dw->chan) {
1502 err = -ENOMEM;
1503 goto err_pdata;
1504 }
1505
1506 /* Calculate all channel mask before DMA setup */
1507 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1508
1509 /* Force dma off, just in case */
1510 dw_dma_off(dw);
1511
1512 /* Create a pool of consistent memory blocks for hardware descriptors */
1513 dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1514 sizeof(struct dw_desc), 4, 0);
1515 if (!dw->desc_pool) {
1516 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1517 err = -ENOMEM;
1518 goto err_pdata;
1519 }
1520
1521 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1522
1523 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1524 "dw_dmac", dw);
1525 if (err)
1526 goto err_pdata;
1527
1528 INIT_LIST_HEAD(&dw->dma.channels);
1529 for (i = 0; i < pdata->nr_channels; i++) {
1530 struct dw_dma_chan *dwc = &dw->chan[i];
1531
1532 dwc->chan.device = &dw->dma;
1533 dma_cookie_init(&dwc->chan);
1534 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1535 list_add_tail(&dwc->chan.device_node,
1536 &dw->dma.channels);
1537 else
1538 list_add(&dwc->chan.device_node, &dw->dma.channels);
1539
1540 /* 7 is highest priority & 0 is lowest. */
1541 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1542 dwc->priority = pdata->nr_channels - i - 1;
1543 else
1544 dwc->priority = i;
1545
1546 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1547 spin_lock_init(&dwc->lock);
1548 dwc->mask = 1 << i;
1549
1550 INIT_LIST_HEAD(&dwc->active_list);
1551 INIT_LIST_HEAD(&dwc->queue);
1552
1553 channel_clear_bit(dw, CH_EN, dwc->mask);
1554
1555 dwc->direction = DMA_TRANS_NONE;
1556
1557 /* Hardware configuration */
1558 if (autocfg) {
1559 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1560 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r];
1561 unsigned int dwc_params = dma_readl_native(addr);
1562
1563 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1564 dwc_params);
1565
1566 /*
1567 * Decode maximum block size for given channel. The
1568 * stored 4 bit value represents blocks from 0x00 for 3
1569 * up to 0x0a for 4095.
1570 */
1571 dwc->block_size =
1572 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;
1573 dwc->nollp =
1574 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1575 } else {
1576 dwc->block_size = pdata->block_size;
1577
1578 /* Check if channel supports multi block transfer */
1579 channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff));
1580 dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0;
1581 channel_writel(dwc, LLP, 0);
1582 }
1583 }
1584
1585 /* Clear all interrupts on all channels. */
1586 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1587 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1588 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1589 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1590 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1591
1592 /* Set capabilities */
1593 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1594 if (pdata->is_private)
1595 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1596 if (pdata->is_memcpy)
1597 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1598
1599 dw->dma.dev = chip->dev;
1600 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1601 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1602
1603 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1604 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1605
1606 dw->dma.device_config = dwc_config;
1607 dw->dma.device_pause = dwc_pause;
1608 dw->dma.device_resume = dwc_resume;
1609 dw->dma.device_terminate_all = dwc_terminate_all;
1610
1611 dw->dma.device_tx_status = dwc_tx_status;
1612 dw->dma.device_issue_pending = dwc_issue_pending;
1613
1614 /* DMA capabilities */
1615 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1616 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1617 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1618 BIT(DMA_MEM_TO_MEM);
1619 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1620
1621 err = dma_async_device_register(&dw->dma);
1622 if (err)
1623 goto err_dma_register;
1624
1625 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1626 pdata->nr_channels);
1627
1628 pm_runtime_put_sync_suspend(chip->dev);
1629
1630 return 0;
1631
1632 err_dma_register:
1633 free_irq(chip->irq, dw);
1634 err_pdata:
1635 pm_runtime_put_sync_suspend(chip->dev);
1636 return err;
1637 }
1638 EXPORT_SYMBOL_GPL(dw_dma_probe);
1639
1640 int dw_dma_remove(struct dw_dma_chip *chip)
1641 {
1642 struct dw_dma *dw = chip->dw;
1643 struct dw_dma_chan *dwc, *_dwc;
1644
1645 pm_runtime_get_sync(chip->dev);
1646
1647 dw_dma_off(dw);
1648 dma_async_device_unregister(&dw->dma);
1649
1650 free_irq(chip->irq, dw);
1651 tasklet_kill(&dw->tasklet);
1652
1653 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1654 chan.device_node) {
1655 list_del(&dwc->chan.device_node);
1656 channel_clear_bit(dw, CH_EN, dwc->mask);
1657 }
1658
1659 pm_runtime_put_sync_suspend(chip->dev);
1660 return 0;
1661 }
1662 EXPORT_SYMBOL_GPL(dw_dma_remove);
1663
1664 int dw_dma_disable(struct dw_dma_chip *chip)
1665 {
1666 struct dw_dma *dw = chip->dw;
1667
1668 dw_dma_off(dw);
1669 return 0;
1670 }
1671 EXPORT_SYMBOL_GPL(dw_dma_disable);
1672
1673 int dw_dma_enable(struct dw_dma_chip *chip)
1674 {
1675 struct dw_dma *dw = chip->dw;
1676
1677 dw_dma_on(dw);
1678 return 0;
1679 }
1680 EXPORT_SYMBOL_GPL(dw_dma_enable);
1681
1682 MODULE_LICENSE("GPL v2");
1683 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1684 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1685 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
Linux kernel - Deliverables
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