Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / dma / pl330.c
1 /*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/io.h>
16 #include <linux/init.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/string.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/amba/bus.h>
25 #include <linux/amba/pl330.h>
26 #include <linux/scatterlist.h>
27 #include <linux/of.h>
28 #include <linux/of_dma.h>
29 #include <linux/err.h>
30 #include <linux/pm_runtime.h>
31
32 #include "dmaengine.h"
33 #define PL330_MAX_CHAN 8
34 #define PL330_MAX_IRQS 32
35 #define PL330_MAX_PERI 32
36 #define PL330_MAX_BURST 16
37
38 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39
40 enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
46 INVALID2,
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
49 };
50
51 enum pl330_byteswap {
52 SWAP_NO,
53 SWAP_2,
54 SWAP_4,
55 SWAP_8,
56 SWAP_16,
57 };
58
59 /* Register and Bit field Definitions */
60 #define DS 0x0
61 #define DS_ST_STOP 0x0
62 #define DS_ST_EXEC 0x1
63 #define DS_ST_CMISS 0x2
64 #define DS_ST_UPDTPC 0x3
65 #define DS_ST_WFE 0x4
66 #define DS_ST_ATBRR 0x5
67 #define DS_ST_QBUSY 0x6
68 #define DS_ST_WFP 0x7
69 #define DS_ST_KILL 0x8
70 #define DS_ST_CMPLT 0x9
71 #define DS_ST_FLTCMP 0xe
72 #define DS_ST_FAULT 0xf
73
74 #define DPC 0x4
75 #define INTEN 0x20
76 #define ES 0x24
77 #define INTSTATUS 0x28
78 #define INTCLR 0x2c
79 #define FSM 0x30
80 #define FSC 0x34
81 #define FTM 0x38
82
83 #define _FTC 0x40
84 #define FTC(n) (_FTC + (n)*0x4)
85
86 #define _CS 0x100
87 #define CS(n) (_CS + (n)*0x8)
88 #define CS_CNS (1 << 21)
89
90 #define _CPC 0x104
91 #define CPC(n) (_CPC + (n)*0x8)
92
93 #define _SA 0x400
94 #define SA(n) (_SA + (n)*0x20)
95
96 #define _DA 0x404
97 #define DA(n) (_DA + (n)*0x20)
98
99 #define _CC 0x408
100 #define CC(n) (_CC + (n)*0x20)
101
102 #define CC_SRCINC (1 << 0)
103 #define CC_DSTINC (1 << 14)
104 #define CC_SRCPRI (1 << 8)
105 #define CC_DSTPRI (1 << 22)
106 #define CC_SRCNS (1 << 9)
107 #define CC_DSTNS (1 << 23)
108 #define CC_SRCIA (1 << 10)
109 #define CC_DSTIA (1 << 24)
110 #define CC_SRCBRSTLEN_SHFT 4
111 #define CC_DSTBRSTLEN_SHFT 18
112 #define CC_SRCBRSTSIZE_SHFT 1
113 #define CC_DSTBRSTSIZE_SHFT 15
114 #define CC_SRCCCTRL_SHFT 11
115 #define CC_SRCCCTRL_MASK 0x7
116 #define CC_DSTCCTRL_SHFT 25
117 #define CC_DRCCCTRL_MASK 0x7
118 #define CC_SWAP_SHFT 28
119
120 #define _LC0 0x40c
121 #define LC0(n) (_LC0 + (n)*0x20)
122
123 #define _LC1 0x410
124 #define LC1(n) (_LC1 + (n)*0x20)
125
126 #define DBGSTATUS 0xd00
127 #define DBG_BUSY (1 << 0)
128
129 #define DBGCMD 0xd04
130 #define DBGINST0 0xd08
131 #define DBGINST1 0xd0c
132
133 #define CR0 0xe00
134 #define CR1 0xe04
135 #define CR2 0xe08
136 #define CR3 0xe0c
137 #define CR4 0xe10
138 #define CRD 0xe14
139
140 #define PERIPH_ID 0xfe0
141 #define PERIPH_REV_SHIFT 20
142 #define PERIPH_REV_MASK 0xf
143 #define PERIPH_REV_R0P0 0
144 #define PERIPH_REV_R1P0 1
145 #define PERIPH_REV_R1P1 2
146
147 #define CR0_PERIPH_REQ_SET (1 << 0)
148 #define CR0_BOOT_EN_SET (1 << 1)
149 #define CR0_BOOT_MAN_NS (1 << 2)
150 #define CR0_NUM_CHANS_SHIFT 4
151 #define CR0_NUM_CHANS_MASK 0x7
152 #define CR0_NUM_PERIPH_SHIFT 12
153 #define CR0_NUM_PERIPH_MASK 0x1f
154 #define CR0_NUM_EVENTS_SHIFT 17
155 #define CR0_NUM_EVENTS_MASK 0x1f
156
157 #define CR1_ICACHE_LEN_SHIFT 0
158 #define CR1_ICACHE_LEN_MASK 0x7
159 #define CR1_NUM_ICACHELINES_SHIFT 4
160 #define CR1_NUM_ICACHELINES_MASK 0xf
161
162 #define CRD_DATA_WIDTH_SHIFT 0
163 #define CRD_DATA_WIDTH_MASK 0x7
164 #define CRD_WR_CAP_SHIFT 4
165 #define CRD_WR_CAP_MASK 0x7
166 #define CRD_WR_Q_DEP_SHIFT 8
167 #define CRD_WR_Q_DEP_MASK 0xf
168 #define CRD_RD_CAP_SHIFT 12
169 #define CRD_RD_CAP_MASK 0x7
170 #define CRD_RD_Q_DEP_SHIFT 16
171 #define CRD_RD_Q_DEP_MASK 0xf
172 #define CRD_DATA_BUFF_SHIFT 20
173 #define CRD_DATA_BUFF_MASK 0x3ff
174
175 #define PART 0x330
176 #define DESIGNER 0x41
177 #define REVISION 0x0
178 #define INTEG_CFG 0x0
179 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180
181 #define PL330_STATE_STOPPED (1 << 0)
182 #define PL330_STATE_EXECUTING (1 << 1)
183 #define PL330_STATE_WFE (1 << 2)
184 #define PL330_STATE_FAULTING (1 << 3)
185 #define PL330_STATE_COMPLETING (1 << 4)
186 #define PL330_STATE_WFP (1 << 5)
187 #define PL330_STATE_KILLING (1 << 6)
188 #define PL330_STATE_FAULT_COMPLETING (1 << 7)
189 #define PL330_STATE_CACHEMISS (1 << 8)
190 #define PL330_STATE_UPDTPC (1 << 9)
191 #define PL330_STATE_ATBARRIER (1 << 10)
192 #define PL330_STATE_QUEUEBUSY (1 << 11)
193 #define PL330_STATE_INVALID (1 << 15)
194
195 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197
198 #define CMD_DMAADDH 0x54
199 #define CMD_DMAEND 0x00
200 #define CMD_DMAFLUSHP 0x35
201 #define CMD_DMAGO 0xa0
202 #define CMD_DMALD 0x04
203 #define CMD_DMALDP 0x25
204 #define CMD_DMALP 0x20
205 #define CMD_DMALPEND 0x28
206 #define CMD_DMAKILL 0x01
207 #define CMD_DMAMOV 0xbc
208 #define CMD_DMANOP 0x18
209 #define CMD_DMARMB 0x12
210 #define CMD_DMASEV 0x34
211 #define CMD_DMAST 0x08
212 #define CMD_DMASTP 0x29
213 #define CMD_DMASTZ 0x0c
214 #define CMD_DMAWFE 0x36
215 #define CMD_DMAWFP 0x30
216 #define CMD_DMAWMB 0x13
217
218 #define SZ_DMAADDH 3
219 #define SZ_DMAEND 1
220 #define SZ_DMAFLUSHP 2
221 #define SZ_DMALD 1
222 #define SZ_DMALDP 2
223 #define SZ_DMALP 2
224 #define SZ_DMALPEND 2
225 #define SZ_DMAKILL 1
226 #define SZ_DMAMOV 6
227 #define SZ_DMANOP 1
228 #define SZ_DMARMB 1
229 #define SZ_DMASEV 2
230 #define SZ_DMAST 1
231 #define SZ_DMASTP 2
232 #define SZ_DMASTZ 1
233 #define SZ_DMAWFE 2
234 #define SZ_DMAWFP 2
235 #define SZ_DMAWMB 1
236 #define SZ_DMAGO 6
237
238 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240
241 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243
244 /*
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
249 */
250 #define MCODE_BUFF_PER_REQ 256
251
252 /* Use this _only_ to wait on transient states */
253 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254
255 #ifdef PL330_DEBUG_MCGEN
256 static unsigned cmd_line;
257 #define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
259 printk(x); \
260 cmd_line += off; \
261 } while (0)
262 #define PL330_DBGMC_START(addr) (cmd_line = addr)
263 #else
264 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265 #define PL330_DBGMC_START(addr) do {} while (0)
266 #endif
267
268 /* The number of default descriptors */
269
270 #define NR_DEFAULT_DESC 16
271
272 /* Delay for runtime PM autosuspend, ms */
273 #define PL330_AUTOSUSPEND_DELAY 20
274
275 /* Populated by the PL330 core driver for DMA API driver's info */
276 struct pl330_config {
277 u32 periph_id;
278 #define DMAC_MODE_NS (1 << 0)
279 unsigned int mode;
280 unsigned int data_bus_width:10; /* In number of bits */
281 unsigned int data_buf_dep:11;
282 unsigned int num_chan:4;
283 unsigned int num_peri:6;
284 u32 peri_ns;
285 unsigned int num_events:6;
286 u32 irq_ns;
287 };
288
289 /**
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
293 *
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
296 */
297 struct pl330_reqcfg {
298 /* Address Incrementing */
299 unsigned dst_inc:1;
300 unsigned src_inc:1;
301
302 /*
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
305 */
306 bool nonsecure;
307 bool privileged;
308 bool insnaccess;
309 unsigned brst_len:5;
310 unsigned brst_size:3; /* in power of 2 */
311
312 enum pl330_cachectrl dcctl;
313 enum pl330_cachectrl scctl;
314 enum pl330_byteswap swap;
315 struct pl330_config *pcfg;
316 };
317
318 /*
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
321 */
322 struct pl330_xfer {
323 u32 src_addr;
324 u32 dst_addr;
325 /* Size to xfer */
326 u32 bytes;
327 };
328
329 /* The xfer callbacks are made with one of these arguments. */
330 enum pl330_op_err {
331 /* The all xfers in the request were success. */
332 PL330_ERR_NONE,
333 /* If req aborted due to global error. */
334 PL330_ERR_ABORT,
335 /* If req failed due to problem with Channel. */
336 PL330_ERR_FAIL,
337 };
338
339 enum dmamov_dst {
340 SAR = 0,
341 CCR,
342 DAR,
343 };
344
345 enum pl330_dst {
346 SRC = 0,
347 DST,
348 };
349
350 enum pl330_cond {
351 SINGLE,
352 BURST,
353 ALWAYS,
354 };
355
356 struct dma_pl330_desc;
357
358 struct _pl330_req {
359 u32 mc_bus;
360 void *mc_cpu;
361 struct dma_pl330_desc *desc;
362 };
363
364 /* ToBeDone for tasklet */
365 struct _pl330_tbd {
366 bool reset_dmac;
367 bool reset_mngr;
368 u8 reset_chan;
369 };
370
371 /* A DMAC Thread */
372 struct pl330_thread {
373 u8 id;
374 int ev;
375 /* If the channel is not yet acquired by any client */
376 bool free;
377 /* Parent DMAC */
378 struct pl330_dmac *dmac;
379 /* Only two at a time */
380 struct _pl330_req req[2];
381 /* Index of the last enqueued request */
382 unsigned lstenq;
383 /* Index of the last submitted request or -1 if the DMA is stopped */
384 int req_running;
385 };
386
387 enum pl330_dmac_state {
388 UNINIT,
389 INIT,
390 DYING,
391 };
392
393 enum desc_status {
394 /* In the DMAC pool */
395 FREE,
396 /*
397 * Allocated to some channel during prep_xxx
398 * Also may be sitting on the work_list.
399 */
400 PREP,
401 /*
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
405 */
406 BUSY,
407 /*
408 * Sitting on the channel work_list but xfer done
409 * by PL330 core
410 */
411 DONE,
412 };
413
414 struct dma_pl330_chan {
415 /* Schedule desc completion */
416 struct tasklet_struct task;
417
418 /* DMA-Engine Channel */
419 struct dma_chan chan;
420
421 /* List of submitted descriptors */
422 struct list_head submitted_list;
423 /* List of issued descriptors */
424 struct list_head work_list;
425 /* List of completed descriptors */
426 struct list_head completed_list;
427
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
431 * to the channel.
432 */
433 struct pl330_dmac *dmac;
434
435 /* To protect channel manipulation */
436 spinlock_t lock;
437
438 /*
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
440 * available.
441 */
442 struct pl330_thread *thread;
443
444 /* For D-to-M and M-to-D channels */
445 int burst_sz; /* the peripheral fifo width */
446 int burst_len; /* the number of burst */
447 dma_addr_t fifo_addr;
448
449 /* for cyclic capability */
450 bool cyclic;
451 };
452
453 struct pl330_dmac {
454 /* DMA-Engine Device */
455 struct dma_device ddma;
456
457 /* Holds info about sg limitations */
458 struct device_dma_parameters dma_parms;
459
460 /* Pool of descriptors available for the DMAC's channels */
461 struct list_head desc_pool;
462 /* To protect desc_pool manipulation */
463 spinlock_t pool_lock;
464
465 /* Size of MicroCode buffers for each channel. */
466 unsigned mcbufsz;
467 /* ioremap'ed address of PL330 registers. */
468 void __iomem *base;
469 /* Populated by the PL330 core driver during pl330_add */
470 struct pl330_config pcfg;
471
472 spinlock_t lock;
473 /* Maximum possible events/irqs */
474 int events[32];
475 /* BUS address of MicroCode buffer */
476 dma_addr_t mcode_bus;
477 /* CPU address of MicroCode buffer */
478 void *mcode_cpu;
479 /* List of all Channel threads */
480 struct pl330_thread *channels;
481 /* Pointer to the MANAGER thread */
482 struct pl330_thread *manager;
483 /* To handle bad news in interrupt */
484 struct tasklet_struct tasks;
485 struct _pl330_tbd dmac_tbd;
486 /* State of DMAC operation */
487 enum pl330_dmac_state state;
488 /* Holds list of reqs with due callbacks */
489 struct list_head req_done;
490
491 /* Peripheral channels connected to this DMAC */
492 unsigned int num_peripherals;
493 struct dma_pl330_chan *peripherals; /* keep at end */
494 int quirks;
495 };
496
497 static struct pl330_of_quirks {
498 char *quirk;
499 int id;
500 } of_quirks[] = {
501 {
502 .quirk = "arm,pl330-broken-no-flushp",
503 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
504 }
505 };
506
507 struct dma_pl330_desc {
508 /* To attach to a queue as child */
509 struct list_head node;
510
511 /* Descriptor for the DMA Engine API */
512 struct dma_async_tx_descriptor txd;
513
514 /* Xfer for PL330 core */
515 struct pl330_xfer px;
516
517 struct pl330_reqcfg rqcfg;
518
519 enum desc_status status;
520
521 int bytes_requested;
522 bool last;
523
524 /* The channel which currently holds this desc */
525 struct dma_pl330_chan *pchan;
526
527 enum dma_transfer_direction rqtype;
528 /* Index of peripheral for the xfer. */
529 unsigned peri:5;
530 /* Hook to attach to DMAC's list of reqs with due callback */
531 struct list_head rqd;
532 };
533
534 struct _xfer_spec {
535 u32 ccr;
536 struct dma_pl330_desc *desc;
537 };
538
539 static inline bool _queue_empty(struct pl330_thread *thrd)
540 {
541 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
542 }
543
544 static inline bool _queue_full(struct pl330_thread *thrd)
545 {
546 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
547 }
548
549 static inline bool is_manager(struct pl330_thread *thrd)
550 {
551 return thrd->dmac->manager == thrd;
552 }
553
554 /* If manager of the thread is in Non-Secure mode */
555 static inline bool _manager_ns(struct pl330_thread *thrd)
556 {
557 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
558 }
559
560 static inline u32 get_revision(u32 periph_id)
561 {
562 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
563 }
564
565 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
566 enum pl330_dst da, u16 val)
567 {
568 if (dry_run)
569 return SZ_DMAADDH;
570
571 buf[0] = CMD_DMAADDH;
572 buf[0] |= (da << 1);
573 *((__le16 *)&buf[1]) = cpu_to_le16(val);
574
575 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
576 da == 1 ? "DA" : "SA", val);
577
578 return SZ_DMAADDH;
579 }
580
581 static inline u32 _emit_END(unsigned dry_run, u8 buf[])
582 {
583 if (dry_run)
584 return SZ_DMAEND;
585
586 buf[0] = CMD_DMAEND;
587
588 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589
590 return SZ_DMAEND;
591 }
592
593 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594 {
595 if (dry_run)
596 return SZ_DMAFLUSHP;
597
598 buf[0] = CMD_DMAFLUSHP;
599
600 peri &= 0x1f;
601 peri <<= 3;
602 buf[1] = peri;
603
604 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605
606 return SZ_DMAFLUSHP;
607 }
608
609 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
610 {
611 if (dry_run)
612 return SZ_DMALD;
613
614 buf[0] = CMD_DMALD;
615
616 if (cond == SINGLE)
617 buf[0] |= (0 << 1) | (1 << 0);
618 else if (cond == BURST)
619 buf[0] |= (1 << 1) | (1 << 0);
620
621 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
622 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623
624 return SZ_DMALD;
625 }
626
627 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
628 enum pl330_cond cond, u8 peri)
629 {
630 if (dry_run)
631 return SZ_DMALDP;
632
633 buf[0] = CMD_DMALDP;
634
635 if (cond == BURST)
636 buf[0] |= (1 << 1);
637
638 peri &= 0x1f;
639 peri <<= 3;
640 buf[1] = peri;
641
642 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
643 cond == SINGLE ? 'S' : 'B', peri >> 3);
644
645 return SZ_DMALDP;
646 }
647
648 static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
649 unsigned loop, u8 cnt)
650 {
651 if (dry_run)
652 return SZ_DMALP;
653
654 buf[0] = CMD_DMALP;
655
656 if (loop)
657 buf[0] |= (1 << 1);
658
659 cnt--; /* DMAC increments by 1 internally */
660 buf[1] = cnt;
661
662 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
663
664 return SZ_DMALP;
665 }
666
667 struct _arg_LPEND {
668 enum pl330_cond cond;
669 bool forever;
670 unsigned loop;
671 u8 bjump;
672 };
673
674 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
675 const struct _arg_LPEND *arg)
676 {
677 enum pl330_cond cond = arg->cond;
678 bool forever = arg->forever;
679 unsigned loop = arg->loop;
680 u8 bjump = arg->bjump;
681
682 if (dry_run)
683 return SZ_DMALPEND;
684
685 buf[0] = CMD_DMALPEND;
686
687 if (loop)
688 buf[0] |= (1 << 2);
689
690 if (!forever)
691 buf[0] |= (1 << 4);
692
693 if (cond == SINGLE)
694 buf[0] |= (0 << 1) | (1 << 0);
695 else if (cond == BURST)
696 buf[0] |= (1 << 1) | (1 << 0);
697
698 buf[1] = bjump;
699
700 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
701 forever ? "FE" : "END",
702 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
703 loop ? '1' : '0',
704 bjump);
705
706 return SZ_DMALPEND;
707 }
708
709 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710 {
711 if (dry_run)
712 return SZ_DMAKILL;
713
714 buf[0] = CMD_DMAKILL;
715
716 return SZ_DMAKILL;
717 }
718
719 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
720 enum dmamov_dst dst, u32 val)
721 {
722 if (dry_run)
723 return SZ_DMAMOV;
724
725 buf[0] = CMD_DMAMOV;
726 buf[1] = dst;
727 *((__le32 *)&buf[2]) = cpu_to_le32(val);
728
729 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
730 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
731
732 return SZ_DMAMOV;
733 }
734
735 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
736 {
737 if (dry_run)
738 return SZ_DMANOP;
739
740 buf[0] = CMD_DMANOP;
741
742 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
743
744 return SZ_DMANOP;
745 }
746
747 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
748 {
749 if (dry_run)
750 return SZ_DMARMB;
751
752 buf[0] = CMD_DMARMB;
753
754 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
755
756 return SZ_DMARMB;
757 }
758
759 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
760 {
761 if (dry_run)
762 return SZ_DMASEV;
763
764 buf[0] = CMD_DMASEV;
765
766 ev &= 0x1f;
767 ev <<= 3;
768 buf[1] = ev;
769
770 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
771
772 return SZ_DMASEV;
773 }
774
775 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
776 {
777 if (dry_run)
778 return SZ_DMAST;
779
780 buf[0] = CMD_DMAST;
781
782 if (cond == SINGLE)
783 buf[0] |= (0 << 1) | (1 << 0);
784 else if (cond == BURST)
785 buf[0] |= (1 << 1) | (1 << 0);
786
787 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
788 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
789
790 return SZ_DMAST;
791 }
792
793 static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
794 enum pl330_cond cond, u8 peri)
795 {
796 if (dry_run)
797 return SZ_DMASTP;
798
799 buf[0] = CMD_DMASTP;
800
801 if (cond == BURST)
802 buf[0] |= (1 << 1);
803
804 peri &= 0x1f;
805 peri <<= 3;
806 buf[1] = peri;
807
808 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
809 cond == SINGLE ? 'S' : 'B', peri >> 3);
810
811 return SZ_DMASTP;
812 }
813
814 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
815 {
816 if (dry_run)
817 return SZ_DMASTZ;
818
819 buf[0] = CMD_DMASTZ;
820
821 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
822
823 return SZ_DMASTZ;
824 }
825
826 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
827 unsigned invalidate)
828 {
829 if (dry_run)
830 return SZ_DMAWFE;
831
832 buf[0] = CMD_DMAWFE;
833
834 ev &= 0x1f;
835 ev <<= 3;
836 buf[1] = ev;
837
838 if (invalidate)
839 buf[1] |= (1 << 1);
840
841 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
842 ev >> 3, invalidate ? ", I" : "");
843
844 return SZ_DMAWFE;
845 }
846
847 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
848 enum pl330_cond cond, u8 peri)
849 {
850 if (dry_run)
851 return SZ_DMAWFP;
852
853 buf[0] = CMD_DMAWFP;
854
855 if (cond == SINGLE)
856 buf[0] |= (0 << 1) | (0 << 0);
857 else if (cond == BURST)
858 buf[0] |= (1 << 1) | (0 << 0);
859 else
860 buf[0] |= (0 << 1) | (1 << 0);
861
862 peri &= 0x1f;
863 peri <<= 3;
864 buf[1] = peri;
865
866 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
867 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
868
869 return SZ_DMAWFP;
870 }
871
872 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
873 {
874 if (dry_run)
875 return SZ_DMAWMB;
876
877 buf[0] = CMD_DMAWMB;
878
879 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
880
881 return SZ_DMAWMB;
882 }
883
884 struct _arg_GO {
885 u8 chan;
886 u32 addr;
887 unsigned ns;
888 };
889
890 static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
891 const struct _arg_GO *arg)
892 {
893 u8 chan = arg->chan;
894 u32 addr = arg->addr;
895 unsigned ns = arg->ns;
896
897 if (dry_run)
898 return SZ_DMAGO;
899
900 buf[0] = CMD_DMAGO;
901 buf[0] |= (ns << 1);
902
903 buf[1] = chan & 0x7;
904
905 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
906
907 return SZ_DMAGO;
908 }
909
910 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
911
912 /* Returns Time-Out */
913 static bool _until_dmac_idle(struct pl330_thread *thrd)
914 {
915 void __iomem *regs = thrd->dmac->base;
916 unsigned long loops = msecs_to_loops(5);
917
918 do {
919 /* Until Manager is Idle */
920 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
921 break;
922
923 cpu_relax();
924 } while (--loops);
925
926 if (!loops)
927 return true;
928
929 return false;
930 }
931
932 static inline void _execute_DBGINSN(struct pl330_thread *thrd,
933 u8 insn[], bool as_manager)
934 {
935 void __iomem *regs = thrd->dmac->base;
936 u32 val;
937
938 val = (insn[0] << 16) | (insn[1] << 24);
939 if (!as_manager) {
940 val |= (1 << 0);
941 val |= (thrd->id << 8); /* Channel Number */
942 }
943 writel(val, regs + DBGINST0);
944
945 val = le32_to_cpu(*((__le32 *)&insn[2]));
946 writel(val, regs + DBGINST1);
947
948 /* If timed out due to halted state-machine */
949 if (_until_dmac_idle(thrd)) {
950 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
951 return;
952 }
953
954 /* Get going */
955 writel(0, regs + DBGCMD);
956 }
957
958 static inline u32 _state(struct pl330_thread *thrd)
959 {
960 void __iomem *regs = thrd->dmac->base;
961 u32 val;
962
963 if (is_manager(thrd))
964 val = readl(regs + DS) & 0xf;
965 else
966 val = readl(regs + CS(thrd->id)) & 0xf;
967
968 switch (val) {
969 case DS_ST_STOP:
970 return PL330_STATE_STOPPED;
971 case DS_ST_EXEC:
972 return PL330_STATE_EXECUTING;
973 case DS_ST_CMISS:
974 return PL330_STATE_CACHEMISS;
975 case DS_ST_UPDTPC:
976 return PL330_STATE_UPDTPC;
977 case DS_ST_WFE:
978 return PL330_STATE_WFE;
979 case DS_ST_FAULT:
980 return PL330_STATE_FAULTING;
981 case DS_ST_ATBRR:
982 if (is_manager(thrd))
983 return PL330_STATE_INVALID;
984 else
985 return PL330_STATE_ATBARRIER;
986 case DS_ST_QBUSY:
987 if (is_manager(thrd))
988 return PL330_STATE_INVALID;
989 else
990 return PL330_STATE_QUEUEBUSY;
991 case DS_ST_WFP:
992 if (is_manager(thrd))
993 return PL330_STATE_INVALID;
994 else
995 return PL330_STATE_WFP;
996 case DS_ST_KILL:
997 if (is_manager(thrd))
998 return PL330_STATE_INVALID;
999 else
1000 return PL330_STATE_KILLING;
1001 case DS_ST_CMPLT:
1002 if (is_manager(thrd))
1003 return PL330_STATE_INVALID;
1004 else
1005 return PL330_STATE_COMPLETING;
1006 case DS_ST_FLTCMP:
1007 if (is_manager(thrd))
1008 return PL330_STATE_INVALID;
1009 else
1010 return PL330_STATE_FAULT_COMPLETING;
1011 default:
1012 return PL330_STATE_INVALID;
1013 }
1014 }
1015
1016 static void _stop(struct pl330_thread *thrd)
1017 {
1018 void __iomem *regs = thrd->dmac->base;
1019 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1020
1021 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1022 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1023
1024 /* Return if nothing needs to be done */
1025 if (_state(thrd) == PL330_STATE_COMPLETING
1026 || _state(thrd) == PL330_STATE_KILLING
1027 || _state(thrd) == PL330_STATE_STOPPED)
1028 return;
1029
1030 _emit_KILL(0, insn);
1031
1032 /* Stop generating interrupts for SEV */
1033 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1034
1035 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1036 }
1037
1038 /* Start doing req 'idx' of thread 'thrd' */
1039 static bool _trigger(struct pl330_thread *thrd)
1040 {
1041 void __iomem *regs = thrd->dmac->base;
1042 struct _pl330_req *req;
1043 struct dma_pl330_desc *desc;
1044 struct _arg_GO go;
1045 unsigned ns;
1046 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1047 int idx;
1048
1049 /* Return if already ACTIVE */
1050 if (_state(thrd) != PL330_STATE_STOPPED)
1051 return true;
1052
1053 idx = 1 - thrd->lstenq;
1054 if (thrd->req[idx].desc != NULL) {
1055 req = &thrd->req[idx];
1056 } else {
1057 idx = thrd->lstenq;
1058 if (thrd->req[idx].desc != NULL)
1059 req = &thrd->req[idx];
1060 else
1061 req = NULL;
1062 }
1063
1064 /* Return if no request */
1065 if (!req)
1066 return true;
1067
1068 /* Return if req is running */
1069 if (idx == thrd->req_running)
1070 return true;
1071
1072 desc = req->desc;
1073
1074 ns = desc->rqcfg.nonsecure ? 1 : 0;
1075
1076 /* See 'Abort Sources' point-4 at Page 2-25 */
1077 if (_manager_ns(thrd) && !ns)
1078 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1079 __func__, __LINE__);
1080
1081 go.chan = thrd->id;
1082 go.addr = req->mc_bus;
1083 go.ns = ns;
1084 _emit_GO(0, insn, &go);
1085
1086 /* Set to generate interrupts for SEV */
1087 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1088
1089 /* Only manager can execute GO */
1090 _execute_DBGINSN(thrd, insn, true);
1091
1092 thrd->req_running = idx;
1093
1094 return true;
1095 }
1096
1097 static bool _start(struct pl330_thread *thrd)
1098 {
1099 switch (_state(thrd)) {
1100 case PL330_STATE_FAULT_COMPLETING:
1101 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1102
1103 if (_state(thrd) == PL330_STATE_KILLING)
1104 UNTIL(thrd, PL330_STATE_STOPPED)
1105
1106 case PL330_STATE_FAULTING:
1107 _stop(thrd);
1108
1109 case PL330_STATE_KILLING:
1110 case PL330_STATE_COMPLETING:
1111 UNTIL(thrd, PL330_STATE_STOPPED)
1112
1113 case PL330_STATE_STOPPED:
1114 return _trigger(thrd);
1115
1116 case PL330_STATE_WFP:
1117 case PL330_STATE_QUEUEBUSY:
1118 case PL330_STATE_ATBARRIER:
1119 case PL330_STATE_UPDTPC:
1120 case PL330_STATE_CACHEMISS:
1121 case PL330_STATE_EXECUTING:
1122 return true;
1123
1124 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1125 default:
1126 return false;
1127 }
1128 }
1129
1130 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1131 const struct _xfer_spec *pxs, int cyc)
1132 {
1133 int off = 0;
1134 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1135
1136 /* check lock-up free version */
1137 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1138 while (cyc--) {
1139 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1140 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1141 }
1142 } else {
1143 while (cyc--) {
1144 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1145 off += _emit_RMB(dry_run, &buf[off]);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1147 off += _emit_WMB(dry_run, &buf[off]);
1148 }
1149 }
1150
1151 return off;
1152 }
1153
1154 static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1155 u8 buf[], const struct _xfer_spec *pxs,
1156 int cyc)
1157 {
1158 int off = 0;
1159 enum pl330_cond cond;
1160
1161 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1162 cond = BURST;
1163 else
1164 cond = SINGLE;
1165
1166 while (cyc--) {
1167 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1168 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1169 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1170
1171 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1172 off += _emit_FLUSHP(dry_run, &buf[off],
1173 pxs->desc->peri);
1174 }
1175
1176 return off;
1177 }
1178
1179 static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc)
1182 {
1183 int off = 0;
1184 enum pl330_cond cond;
1185
1186 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1187 cond = BURST;
1188 else
1189 cond = SINGLE;
1190
1191 while (cyc--) {
1192 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1193 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1194 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1195
1196 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1197 off += _emit_FLUSHP(dry_run, &buf[off],
1198 pxs->desc->peri);
1199 }
1200
1201 return off;
1202 }
1203
1204 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1205 const struct _xfer_spec *pxs, int cyc)
1206 {
1207 int off = 0;
1208
1209 switch (pxs->desc->rqtype) {
1210 case DMA_MEM_TO_DEV:
1211 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1212 break;
1213 case DMA_DEV_TO_MEM:
1214 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1215 break;
1216 case DMA_MEM_TO_MEM:
1217 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1218 break;
1219 default:
1220 off += 0x40000000; /* Scare off the Client */
1221 break;
1222 }
1223
1224 return off;
1225 }
1226
1227 /* Returns bytes consumed and updates bursts */
1228 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1229 unsigned long *bursts, const struct _xfer_spec *pxs)
1230 {
1231 int cyc, cycmax, szlp, szlpend, szbrst, off;
1232 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1233 struct _arg_LPEND lpend;
1234
1235 if (*bursts == 1)
1236 return _bursts(pl330, dry_run, buf, pxs, 1);
1237
1238 /* Max iterations possible in DMALP is 256 */
1239 if (*bursts >= 256*256) {
1240 lcnt1 = 256;
1241 lcnt0 = 256;
1242 cyc = *bursts / lcnt1 / lcnt0;
1243 } else if (*bursts > 256) {
1244 lcnt1 = 256;
1245 lcnt0 = *bursts / lcnt1;
1246 cyc = 1;
1247 } else {
1248 lcnt1 = *bursts;
1249 lcnt0 = 0;
1250 cyc = 1;
1251 }
1252
1253 szlp = _emit_LP(1, buf, 0, 0);
1254 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1255
1256 lpend.cond = ALWAYS;
1257 lpend.forever = false;
1258 lpend.loop = 0;
1259 lpend.bjump = 0;
1260 szlpend = _emit_LPEND(1, buf, &lpend);
1261
1262 if (lcnt0) {
1263 szlp *= 2;
1264 szlpend *= 2;
1265 }
1266
1267 /*
1268 * Max bursts that we can unroll due to limit on the
1269 * size of backward jump that can be encoded in DMALPEND
1270 * which is 8-bits and hence 255
1271 */
1272 cycmax = (255 - (szlp + szlpend)) / szbrst;
1273
1274 cyc = (cycmax < cyc) ? cycmax : cyc;
1275
1276 off = 0;
1277
1278 if (lcnt0) {
1279 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1280 ljmp0 = off;
1281 }
1282
1283 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1284 ljmp1 = off;
1285
1286 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1287
1288 lpend.cond = ALWAYS;
1289 lpend.forever = false;
1290 lpend.loop = 1;
1291 lpend.bjump = off - ljmp1;
1292 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1293
1294 if (lcnt0) {
1295 lpend.cond = ALWAYS;
1296 lpend.forever = false;
1297 lpend.loop = 0;
1298 lpend.bjump = off - ljmp0;
1299 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1300 }
1301
1302 *bursts = lcnt1 * cyc;
1303 if (lcnt0)
1304 *bursts *= lcnt0;
1305
1306 return off;
1307 }
1308
1309 static inline int _setup_loops(struct pl330_dmac *pl330,
1310 unsigned dry_run, u8 buf[],
1311 const struct _xfer_spec *pxs)
1312 {
1313 struct pl330_xfer *x = &pxs->desc->px;
1314 u32 ccr = pxs->ccr;
1315 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1316 int off = 0;
1317
1318 while (bursts) {
1319 c = bursts;
1320 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1321 bursts -= c;
1322 }
1323
1324 return off;
1325 }
1326
1327 static inline int _setup_xfer(struct pl330_dmac *pl330,
1328 unsigned dry_run, u8 buf[],
1329 const struct _xfer_spec *pxs)
1330 {
1331 struct pl330_xfer *x = &pxs->desc->px;
1332 int off = 0;
1333
1334 /* DMAMOV SAR, x->src_addr */
1335 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1336 /* DMAMOV DAR, x->dst_addr */
1337 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1338
1339 /* Setup Loop(s) */
1340 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1341
1342 return off;
1343 }
1344
1345 /*
1346 * A req is a sequence of one or more xfer units.
1347 * Returns the number of bytes taken to setup the MC for the req.
1348 */
1349 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1350 struct pl330_thread *thrd, unsigned index,
1351 struct _xfer_spec *pxs)
1352 {
1353 struct _pl330_req *req = &thrd->req[index];
1354 struct pl330_xfer *x;
1355 u8 *buf = req->mc_cpu;
1356 int off = 0;
1357
1358 PL330_DBGMC_START(req->mc_bus);
1359
1360 /* DMAMOV CCR, ccr */
1361 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1362
1363 x = &pxs->desc->px;
1364 /* Error if xfer length is not aligned at burst size */
1365 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1366 return -EINVAL;
1367
1368 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1369
1370 /* DMASEV peripheral/event */
1371 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1372 /* DMAEND */
1373 off += _emit_END(dry_run, &buf[off]);
1374
1375 return off;
1376 }
1377
1378 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1379 {
1380 u32 ccr = 0;
1381
1382 if (rqc->src_inc)
1383 ccr |= CC_SRCINC;
1384
1385 if (rqc->dst_inc)
1386 ccr |= CC_DSTINC;
1387
1388 /* We set same protection levels for Src and DST for now */
1389 if (rqc->privileged)
1390 ccr |= CC_SRCPRI | CC_DSTPRI;
1391 if (rqc->nonsecure)
1392 ccr |= CC_SRCNS | CC_DSTNS;
1393 if (rqc->insnaccess)
1394 ccr |= CC_SRCIA | CC_DSTIA;
1395
1396 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1397 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1398
1399 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1400 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1401
1402 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1403 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1404
1405 ccr |= (rqc->swap << CC_SWAP_SHFT);
1406
1407 return ccr;
1408 }
1409
1410 /*
1411 * Submit a list of xfers after which the client wants notification.
1412 * Client is not notified after each xfer unit, just once after all
1413 * xfer units are done or some error occurs.
1414 */
1415 static int pl330_submit_req(struct pl330_thread *thrd,
1416 struct dma_pl330_desc *desc)
1417 {
1418 struct pl330_dmac *pl330 = thrd->dmac;
1419 struct _xfer_spec xs;
1420 unsigned long flags;
1421 unsigned idx;
1422 u32 ccr;
1423 int ret = 0;
1424
1425 if (pl330->state == DYING
1426 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1427 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1428 __func__, __LINE__);
1429 return -EAGAIN;
1430 }
1431
1432 /* If request for non-existing peripheral */
1433 if (desc->rqtype != DMA_MEM_TO_MEM &&
1434 desc->peri >= pl330->pcfg.num_peri) {
1435 dev_info(thrd->dmac->ddma.dev,
1436 "%s:%d Invalid peripheral(%u)!\n",
1437 __func__, __LINE__, desc->peri);
1438 return -EINVAL;
1439 }
1440
1441 spin_lock_irqsave(&pl330->lock, flags);
1442
1443 if (_queue_full(thrd)) {
1444 ret = -EAGAIN;
1445 goto xfer_exit;
1446 }
1447
1448 /* Prefer Secure Channel */
1449 if (!_manager_ns(thrd))
1450 desc->rqcfg.nonsecure = 0;
1451 else
1452 desc->rqcfg.nonsecure = 1;
1453
1454 ccr = _prepare_ccr(&desc->rqcfg);
1455
1456 idx = thrd->req[0].desc == NULL ? 0 : 1;
1457
1458 xs.ccr = ccr;
1459 xs.desc = desc;
1460
1461 /* First dry run to check if req is acceptable */
1462 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1463 if (ret < 0)
1464 goto xfer_exit;
1465
1466 if (ret > pl330->mcbufsz / 2) {
1467 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1468 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1469 ret = -ENOMEM;
1470 goto xfer_exit;
1471 }
1472
1473 /* Hook the request */
1474 thrd->lstenq = idx;
1475 thrd->req[idx].desc = desc;
1476 _setup_req(pl330, 0, thrd, idx, &xs);
1477
1478 ret = 0;
1479
1480 xfer_exit:
1481 spin_unlock_irqrestore(&pl330->lock, flags);
1482
1483 return ret;
1484 }
1485
1486 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1487 {
1488 struct dma_pl330_chan *pch;
1489 unsigned long flags;
1490
1491 if (!desc)
1492 return;
1493
1494 pch = desc->pchan;
1495
1496 /* If desc aborted */
1497 if (!pch)
1498 return;
1499
1500 spin_lock_irqsave(&pch->lock, flags);
1501
1502 desc->status = DONE;
1503
1504 spin_unlock_irqrestore(&pch->lock, flags);
1505
1506 tasklet_schedule(&pch->task);
1507 }
1508
1509 static void pl330_dotask(unsigned long data)
1510 {
1511 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1512 unsigned long flags;
1513 int i;
1514
1515 spin_lock_irqsave(&pl330->lock, flags);
1516
1517 /* The DMAC itself gone nuts */
1518 if (pl330->dmac_tbd.reset_dmac) {
1519 pl330->state = DYING;
1520 /* Reset the manager too */
1521 pl330->dmac_tbd.reset_mngr = true;
1522 /* Clear the reset flag */
1523 pl330->dmac_tbd.reset_dmac = false;
1524 }
1525
1526 if (pl330->dmac_tbd.reset_mngr) {
1527 _stop(pl330->manager);
1528 /* Reset all channels */
1529 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1530 /* Clear the reset flag */
1531 pl330->dmac_tbd.reset_mngr = false;
1532 }
1533
1534 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1535
1536 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1537 struct pl330_thread *thrd = &pl330->channels[i];
1538 void __iomem *regs = pl330->base;
1539 enum pl330_op_err err;
1540
1541 _stop(thrd);
1542
1543 if (readl(regs + FSC) & (1 << thrd->id))
1544 err = PL330_ERR_FAIL;
1545 else
1546 err = PL330_ERR_ABORT;
1547
1548 spin_unlock_irqrestore(&pl330->lock, flags);
1549 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1550 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1551 spin_lock_irqsave(&pl330->lock, flags);
1552
1553 thrd->req[0].desc = NULL;
1554 thrd->req[1].desc = NULL;
1555 thrd->req_running = -1;
1556
1557 /* Clear the reset flag */
1558 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1559 }
1560 }
1561
1562 spin_unlock_irqrestore(&pl330->lock, flags);
1563
1564 return;
1565 }
1566
1567 /* Returns 1 if state was updated, 0 otherwise */
1568 static int pl330_update(struct pl330_dmac *pl330)
1569 {
1570 struct dma_pl330_desc *descdone, *tmp;
1571 unsigned long flags;
1572 void __iomem *regs;
1573 u32 val;
1574 int id, ev, ret = 0;
1575
1576 regs = pl330->base;
1577
1578 spin_lock_irqsave(&pl330->lock, flags);
1579
1580 val = readl(regs + FSM) & 0x1;
1581 if (val)
1582 pl330->dmac_tbd.reset_mngr = true;
1583 else
1584 pl330->dmac_tbd.reset_mngr = false;
1585
1586 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1587 pl330->dmac_tbd.reset_chan |= val;
1588 if (val) {
1589 int i = 0;
1590 while (i < pl330->pcfg.num_chan) {
1591 if (val & (1 << i)) {
1592 dev_info(pl330->ddma.dev,
1593 "Reset Channel-%d\t CS-%x FTC-%x\n",
1594 i, readl(regs + CS(i)),
1595 readl(regs + FTC(i)));
1596 _stop(&pl330->channels[i]);
1597 }
1598 i++;
1599 }
1600 }
1601
1602 /* Check which event happened i.e, thread notified */
1603 val = readl(regs + ES);
1604 if (pl330->pcfg.num_events < 32
1605 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1606 pl330->dmac_tbd.reset_dmac = true;
1607 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1608 __LINE__);
1609 ret = 1;
1610 goto updt_exit;
1611 }
1612
1613 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1614 if (val & (1 << ev)) { /* Event occurred */
1615 struct pl330_thread *thrd;
1616 u32 inten = readl(regs + INTEN);
1617 int active;
1618
1619 /* Clear the event */
1620 if (inten & (1 << ev))
1621 writel(1 << ev, regs + INTCLR);
1622
1623 ret = 1;
1624
1625 id = pl330->events[ev];
1626
1627 thrd = &pl330->channels[id];
1628
1629 active = thrd->req_running;
1630 if (active == -1) /* Aborted */
1631 continue;
1632
1633 /* Detach the req */
1634 descdone = thrd->req[active].desc;
1635 thrd->req[active].desc = NULL;
1636
1637 thrd->req_running = -1;
1638
1639 /* Get going again ASAP */
1640 _start(thrd);
1641
1642 /* For now, just make a list of callbacks to be done */
1643 list_add_tail(&descdone->rqd, &pl330->req_done);
1644 }
1645 }
1646
1647 /* Now that we are in no hurry, do the callbacks */
1648 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1649 list_del(&descdone->rqd);
1650 spin_unlock_irqrestore(&pl330->lock, flags);
1651 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1652 spin_lock_irqsave(&pl330->lock, flags);
1653 }
1654
1655 updt_exit:
1656 spin_unlock_irqrestore(&pl330->lock, flags);
1657
1658 if (pl330->dmac_tbd.reset_dmac
1659 || pl330->dmac_tbd.reset_mngr
1660 || pl330->dmac_tbd.reset_chan) {
1661 ret = 1;
1662 tasklet_schedule(&pl330->tasks);
1663 }
1664
1665 return ret;
1666 }
1667
1668 /* Reserve an event */
1669 static inline int _alloc_event(struct pl330_thread *thrd)
1670 {
1671 struct pl330_dmac *pl330 = thrd->dmac;
1672 int ev;
1673
1674 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1675 if (pl330->events[ev] == -1) {
1676 pl330->events[ev] = thrd->id;
1677 return ev;
1678 }
1679
1680 return -1;
1681 }
1682
1683 static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1684 {
1685 return pl330->pcfg.irq_ns & (1 << i);
1686 }
1687
1688 /* Upon success, returns IdentityToken for the
1689 * allocated channel, NULL otherwise.
1690 */
1691 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1692 {
1693 struct pl330_thread *thrd = NULL;
1694 unsigned long flags;
1695 int chans, i;
1696
1697 if (pl330->state == DYING)
1698 return NULL;
1699
1700 chans = pl330->pcfg.num_chan;
1701
1702 spin_lock_irqsave(&pl330->lock, flags);
1703
1704 for (i = 0; i < chans; i++) {
1705 thrd = &pl330->channels[i];
1706 if ((thrd->free) && (!_manager_ns(thrd) ||
1707 _chan_ns(pl330, i))) {
1708 thrd->ev = _alloc_event(thrd);
1709 if (thrd->ev >= 0) {
1710 thrd->free = false;
1711 thrd->lstenq = 1;
1712 thrd->req[0].desc = NULL;
1713 thrd->req[1].desc = NULL;
1714 thrd->req_running = -1;
1715 break;
1716 }
1717 }
1718 thrd = NULL;
1719 }
1720
1721 spin_unlock_irqrestore(&pl330->lock, flags);
1722
1723 return thrd;
1724 }
1725
1726 /* Release an event */
1727 static inline void _free_event(struct pl330_thread *thrd, int ev)
1728 {
1729 struct pl330_dmac *pl330 = thrd->dmac;
1730
1731 /* If the event is valid and was held by the thread */
1732 if (ev >= 0 && ev < pl330->pcfg.num_events
1733 && pl330->events[ev] == thrd->id)
1734 pl330->events[ev] = -1;
1735 }
1736
1737 static void pl330_release_channel(struct pl330_thread *thrd)
1738 {
1739 struct pl330_dmac *pl330;
1740 unsigned long flags;
1741
1742 if (!thrd || thrd->free)
1743 return;
1744
1745 _stop(thrd);
1746
1747 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1748 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1749
1750 pl330 = thrd->dmac;
1751
1752 spin_lock_irqsave(&pl330->lock, flags);
1753 _free_event(thrd, thrd->ev);
1754 thrd->free = true;
1755 spin_unlock_irqrestore(&pl330->lock, flags);
1756 }
1757
1758 /* Initialize the structure for PL330 configuration, that can be used
1759 * by the client driver the make best use of the DMAC
1760 */
1761 static void read_dmac_config(struct pl330_dmac *pl330)
1762 {
1763 void __iomem *regs = pl330->base;
1764 u32 val;
1765
1766 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1767 val &= CRD_DATA_WIDTH_MASK;
1768 pl330->pcfg.data_bus_width = 8 * (1 << val);
1769
1770 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1771 val &= CRD_DATA_BUFF_MASK;
1772 pl330->pcfg.data_buf_dep = val + 1;
1773
1774 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1775 val &= CR0_NUM_CHANS_MASK;
1776 val += 1;
1777 pl330->pcfg.num_chan = val;
1778
1779 val = readl(regs + CR0);
1780 if (val & CR0_PERIPH_REQ_SET) {
1781 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1782 val += 1;
1783 pl330->pcfg.num_peri = val;
1784 pl330->pcfg.peri_ns = readl(regs + CR4);
1785 } else {
1786 pl330->pcfg.num_peri = 0;
1787 }
1788
1789 val = readl(regs + CR0);
1790 if (val & CR0_BOOT_MAN_NS)
1791 pl330->pcfg.mode |= DMAC_MODE_NS;
1792 else
1793 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1794
1795 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1796 val &= CR0_NUM_EVENTS_MASK;
1797 val += 1;
1798 pl330->pcfg.num_events = val;
1799
1800 pl330->pcfg.irq_ns = readl(regs + CR3);
1801 }
1802
1803 static inline void _reset_thread(struct pl330_thread *thrd)
1804 {
1805 struct pl330_dmac *pl330 = thrd->dmac;
1806
1807 thrd->req[0].mc_cpu = pl330->mcode_cpu
1808 + (thrd->id * pl330->mcbufsz);
1809 thrd->req[0].mc_bus = pl330->mcode_bus
1810 + (thrd->id * pl330->mcbufsz);
1811 thrd->req[0].desc = NULL;
1812
1813 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1814 + pl330->mcbufsz / 2;
1815 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1816 + pl330->mcbufsz / 2;
1817 thrd->req[1].desc = NULL;
1818
1819 thrd->req_running = -1;
1820 }
1821
1822 static int dmac_alloc_threads(struct pl330_dmac *pl330)
1823 {
1824 int chans = pl330->pcfg.num_chan;
1825 struct pl330_thread *thrd;
1826 int i;
1827
1828 /* Allocate 1 Manager and 'chans' Channel threads */
1829 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1830 GFP_KERNEL);
1831 if (!pl330->channels)
1832 return -ENOMEM;
1833
1834 /* Init Channel threads */
1835 for (i = 0; i < chans; i++) {
1836 thrd = &pl330->channels[i];
1837 thrd->id = i;
1838 thrd->dmac = pl330;
1839 _reset_thread(thrd);
1840 thrd->free = true;
1841 }
1842
1843 /* MANAGER is indexed at the end */
1844 thrd = &pl330->channels[chans];
1845 thrd->id = chans;
1846 thrd->dmac = pl330;
1847 thrd->free = false;
1848 pl330->manager = thrd;
1849
1850 return 0;
1851 }
1852
1853 static int dmac_alloc_resources(struct pl330_dmac *pl330)
1854 {
1855 int chans = pl330->pcfg.num_chan;
1856 int ret;
1857
1858 /*
1859 * Alloc MicroCode buffer for 'chans' Channel threads.
1860 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861 */
1862 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1863 chans * pl330->mcbufsz,
1864 &pl330->mcode_bus, GFP_KERNEL);
1865 if (!pl330->mcode_cpu) {
1866 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1867 __func__, __LINE__);
1868 return -ENOMEM;
1869 }
1870
1871 ret = dmac_alloc_threads(pl330);
1872 if (ret) {
1873 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1874 __func__, __LINE__);
1875 dma_free_coherent(pl330->ddma.dev,
1876 chans * pl330->mcbufsz,
1877 pl330->mcode_cpu, pl330->mcode_bus);
1878 return ret;
1879 }
1880
1881 return 0;
1882 }
1883
1884 static int pl330_add(struct pl330_dmac *pl330)
1885 {
1886 void __iomem *regs;
1887 int i, ret;
1888
1889 regs = pl330->base;
1890
1891 /* Check if we can handle this DMAC */
1892 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1893 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1894 pl330->pcfg.periph_id);
1895 return -EINVAL;
1896 }
1897
1898 /* Read the configuration of the DMAC */
1899 read_dmac_config(pl330);
1900
1901 if (pl330->pcfg.num_events == 0) {
1902 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1903 __func__, __LINE__);
1904 return -EINVAL;
1905 }
1906
1907 spin_lock_init(&pl330->lock);
1908
1909 INIT_LIST_HEAD(&pl330->req_done);
1910
1911 /* Use default MC buffer size if not provided */
1912 if (!pl330->mcbufsz)
1913 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1914
1915 /* Mark all events as free */
1916 for (i = 0; i < pl330->pcfg.num_events; i++)
1917 pl330->events[i] = -1;
1918
1919 /* Allocate resources needed by the DMAC */
1920 ret = dmac_alloc_resources(pl330);
1921 if (ret) {
1922 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1923 return ret;
1924 }
1925
1926 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1927
1928 pl330->state = INIT;
1929
1930 return 0;
1931 }
1932
1933 static int dmac_free_threads(struct pl330_dmac *pl330)
1934 {
1935 struct pl330_thread *thrd;
1936 int i;
1937
1938 /* Release Channel threads */
1939 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1940 thrd = &pl330->channels[i];
1941 pl330_release_channel(thrd);
1942 }
1943
1944 /* Free memory */
1945 kfree(pl330->channels);
1946
1947 return 0;
1948 }
1949
1950 static void pl330_del(struct pl330_dmac *pl330)
1951 {
1952 pl330->state = UNINIT;
1953
1954 tasklet_kill(&pl330->tasks);
1955
1956 /* Free DMAC resources */
1957 dmac_free_threads(pl330);
1958
1959 dma_free_coherent(pl330->ddma.dev,
1960 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1961 pl330->mcode_bus);
1962 }
1963
1964 /* forward declaration */
1965 static struct amba_driver pl330_driver;
1966
1967 static inline struct dma_pl330_chan *
1968 to_pchan(struct dma_chan *ch)
1969 {
1970 if (!ch)
1971 return NULL;
1972
1973 return container_of(ch, struct dma_pl330_chan, chan);
1974 }
1975
1976 static inline struct dma_pl330_desc *
1977 to_desc(struct dma_async_tx_descriptor *tx)
1978 {
1979 return container_of(tx, struct dma_pl330_desc, txd);
1980 }
1981
1982 static inline void fill_queue(struct dma_pl330_chan *pch)
1983 {
1984 struct dma_pl330_desc *desc;
1985 int ret;
1986
1987 list_for_each_entry(desc, &pch->work_list, node) {
1988
1989 /* If already submitted */
1990 if (desc->status == BUSY)
1991 continue;
1992
1993 ret = pl330_submit_req(pch->thread, desc);
1994 if (!ret) {
1995 desc->status = BUSY;
1996 } else if (ret == -EAGAIN) {
1997 /* QFull or DMAC Dying */
1998 break;
1999 } else {
2000 /* Unacceptable request */
2001 desc->status = DONE;
2002 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2003 __func__, __LINE__, desc->txd.cookie);
2004 tasklet_schedule(&pch->task);
2005 }
2006 }
2007 }
2008
2009 static void pl330_tasklet(unsigned long data)
2010 {
2011 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2012 struct dma_pl330_desc *desc, *_dt;
2013 unsigned long flags;
2014 bool power_down = false;
2015
2016 spin_lock_irqsave(&pch->lock, flags);
2017
2018 /* Pick up ripe tomatoes */
2019 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2020 if (desc->status == DONE) {
2021 if (!pch->cyclic)
2022 dma_cookie_complete(&desc->txd);
2023 list_move_tail(&desc->node, &pch->completed_list);
2024 }
2025
2026 /* Try to submit a req imm. next to the last completed cookie */
2027 fill_queue(pch);
2028
2029 if (list_empty(&pch->work_list)) {
2030 spin_lock(&pch->thread->dmac->lock);
2031 _stop(pch->thread);
2032 spin_unlock(&pch->thread->dmac->lock);
2033 power_down = true;
2034 } else {
2035 /* Make sure the PL330 Channel thread is active */
2036 spin_lock(&pch->thread->dmac->lock);
2037 _start(pch->thread);
2038 spin_unlock(&pch->thread->dmac->lock);
2039 }
2040
2041 while (!list_empty(&pch->completed_list)) {
2042 struct dmaengine_desc_callback cb;
2043
2044 desc = list_first_entry(&pch->completed_list,
2045 struct dma_pl330_desc, node);
2046
2047 dmaengine_desc_get_callback(&desc->txd, &cb);
2048
2049 if (pch->cyclic) {
2050 desc->status = PREP;
2051 list_move_tail(&desc->node, &pch->work_list);
2052 if (power_down) {
2053 spin_lock(&pch->thread->dmac->lock);
2054 _start(pch->thread);
2055 spin_unlock(&pch->thread->dmac->lock);
2056 power_down = false;
2057 }
2058 } else {
2059 desc->status = FREE;
2060 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2061 }
2062
2063 dma_descriptor_unmap(&desc->txd);
2064
2065 if (dmaengine_desc_callback_valid(&cb)) {
2066 spin_unlock_irqrestore(&pch->lock, flags);
2067 dmaengine_desc_callback_invoke(&cb, NULL);
2068 spin_lock_irqsave(&pch->lock, flags);
2069 }
2070 }
2071 spin_unlock_irqrestore(&pch->lock, flags);
2072
2073 /* If work list empty, power down */
2074 if (power_down) {
2075 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2076 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2077 }
2078 }
2079
2080 bool pl330_filter(struct dma_chan *chan, void *param)
2081 {
2082 u8 *peri_id;
2083
2084 if (chan->device->dev->driver != &pl330_driver.drv)
2085 return false;
2086
2087 peri_id = chan->private;
2088 return *peri_id == (unsigned long)param;
2089 }
2090 EXPORT_SYMBOL(pl330_filter);
2091
2092 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2093 struct of_dma *ofdma)
2094 {
2095 int count = dma_spec->args_count;
2096 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2097 unsigned int chan_id;
2098
2099 if (!pl330)
2100 return NULL;
2101
2102 if (count != 1)
2103 return NULL;
2104
2105 chan_id = dma_spec->args[0];
2106 if (chan_id >= pl330->num_peripherals)
2107 return NULL;
2108
2109 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2110 }
2111
2112 static int pl330_alloc_chan_resources(struct dma_chan *chan)
2113 {
2114 struct dma_pl330_chan *pch = to_pchan(chan);
2115 struct pl330_dmac *pl330 = pch->dmac;
2116 unsigned long flags;
2117
2118 spin_lock_irqsave(&pch->lock, flags);
2119
2120 dma_cookie_init(chan);
2121 pch->cyclic = false;
2122
2123 pch->thread = pl330_request_channel(pl330);
2124 if (!pch->thread) {
2125 spin_unlock_irqrestore(&pch->lock, flags);
2126 return -ENOMEM;
2127 }
2128
2129 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2130
2131 spin_unlock_irqrestore(&pch->lock, flags);
2132
2133 return 1;
2134 }
2135
2136 static int pl330_config(struct dma_chan *chan,
2137 struct dma_slave_config *slave_config)
2138 {
2139 struct dma_pl330_chan *pch = to_pchan(chan);
2140
2141 if (slave_config->direction == DMA_MEM_TO_DEV) {
2142 if (slave_config->dst_addr)
2143 pch->fifo_addr = slave_config->dst_addr;
2144 if (slave_config->dst_addr_width)
2145 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2146 if (slave_config->dst_maxburst)
2147 pch->burst_len = slave_config->dst_maxburst;
2148 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2149 if (slave_config->src_addr)
2150 pch->fifo_addr = slave_config->src_addr;
2151 if (slave_config->src_addr_width)
2152 pch->burst_sz = __ffs(slave_config->src_addr_width);
2153 if (slave_config->src_maxburst)
2154 pch->burst_len = slave_config->src_maxburst;
2155 }
2156
2157 return 0;
2158 }
2159
2160 static int pl330_terminate_all(struct dma_chan *chan)
2161 {
2162 struct dma_pl330_chan *pch = to_pchan(chan);
2163 struct dma_pl330_desc *desc;
2164 unsigned long flags;
2165 struct pl330_dmac *pl330 = pch->dmac;
2166 LIST_HEAD(list);
2167
2168 pm_runtime_get_sync(pl330->ddma.dev);
2169 spin_lock_irqsave(&pch->lock, flags);
2170 spin_lock(&pl330->lock);
2171 _stop(pch->thread);
2172 spin_unlock(&pl330->lock);
2173
2174 pch->thread->req[0].desc = NULL;
2175 pch->thread->req[1].desc = NULL;
2176 pch->thread->req_running = -1;
2177
2178 /* Mark all desc done */
2179 list_for_each_entry(desc, &pch->submitted_list, node) {
2180 desc->status = FREE;
2181 dma_cookie_complete(&desc->txd);
2182 }
2183
2184 list_for_each_entry(desc, &pch->work_list , node) {
2185 desc->status = FREE;
2186 dma_cookie_complete(&desc->txd);
2187 }
2188
2189 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2190 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2191 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2192 spin_unlock_irqrestore(&pch->lock, flags);
2193 pm_runtime_mark_last_busy(pl330->ddma.dev);
2194 pm_runtime_put_autosuspend(pl330->ddma.dev);
2195
2196 return 0;
2197 }
2198
2199 /*
2200 * We don't support DMA_RESUME command because of hardware
2201 * limitations, so after pausing the channel we cannot restore
2202 * it to active state. We have to terminate channel and setup
2203 * DMA transfer again. This pause feature was implemented to
2204 * allow safely read residue before channel termination.
2205 */
2206 static int pl330_pause(struct dma_chan *chan)
2207 {
2208 struct dma_pl330_chan *pch = to_pchan(chan);
2209 struct pl330_dmac *pl330 = pch->dmac;
2210 unsigned long flags;
2211
2212 pm_runtime_get_sync(pl330->ddma.dev);
2213 spin_lock_irqsave(&pch->lock, flags);
2214
2215 spin_lock(&pl330->lock);
2216 _stop(pch->thread);
2217 spin_unlock(&pl330->lock);
2218
2219 spin_unlock_irqrestore(&pch->lock, flags);
2220 pm_runtime_mark_last_busy(pl330->ddma.dev);
2221 pm_runtime_put_autosuspend(pl330->ddma.dev);
2222
2223 return 0;
2224 }
2225
2226 static void pl330_free_chan_resources(struct dma_chan *chan)
2227 {
2228 struct dma_pl330_chan *pch = to_pchan(chan);
2229 unsigned long flags;
2230
2231 tasklet_kill(&pch->task);
2232
2233 pm_runtime_get_sync(pch->dmac->ddma.dev);
2234 spin_lock_irqsave(&pch->lock, flags);
2235
2236 pl330_release_channel(pch->thread);
2237 pch->thread = NULL;
2238
2239 if (pch->cyclic)
2240 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2241
2242 spin_unlock_irqrestore(&pch->lock, flags);
2243 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2244 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2245 }
2246
2247 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2248 struct dma_pl330_desc *desc)
2249 {
2250 struct pl330_thread *thrd = pch->thread;
2251 struct pl330_dmac *pl330 = pch->dmac;
2252 void __iomem *regs = thrd->dmac->base;
2253 u32 val, addr;
2254
2255 pm_runtime_get_sync(pl330->ddma.dev);
2256 val = addr = 0;
2257 if (desc->rqcfg.src_inc) {
2258 val = readl(regs + SA(thrd->id));
2259 addr = desc->px.src_addr;
2260 } else {
2261 val = readl(regs + DA(thrd->id));
2262 addr = desc->px.dst_addr;
2263 }
2264 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2265 pm_runtime_put_autosuspend(pl330->ddma.dev);
2266 return val - addr;
2267 }
2268
2269 static enum dma_status
2270 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2271 struct dma_tx_state *txstate)
2272 {
2273 enum dma_status ret;
2274 unsigned long flags;
2275 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2276 struct dma_pl330_chan *pch = to_pchan(chan);
2277 unsigned int transferred, residual = 0;
2278
2279 ret = dma_cookie_status(chan, cookie, txstate);
2280
2281 if (!txstate)
2282 return ret;
2283
2284 if (ret == DMA_COMPLETE)
2285 goto out;
2286
2287 spin_lock_irqsave(&pch->lock, flags);
2288 spin_lock(&pch->thread->dmac->lock);
2289
2290 if (pch->thread->req_running != -1)
2291 running = pch->thread->req[pch->thread->req_running].desc;
2292
2293 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2294
2295 /* Check in pending list */
2296 list_for_each_entry(desc, &pch->work_list, node) {
2297 if (desc->status == DONE)
2298 transferred = desc->bytes_requested;
2299 else if (running && desc == running)
2300 transferred =
2301 pl330_get_current_xferred_count(pch, desc);
2302 else if (desc->status == BUSY)
2303 /*
2304 * Busy but not running means either just enqueued,
2305 * or finished and not yet marked done
2306 */
2307 if (desc == last_enq)
2308 transferred = 0;
2309 else
2310 transferred = desc->bytes_requested;
2311 else
2312 transferred = 0;
2313 residual += desc->bytes_requested - transferred;
2314 if (desc->txd.cookie == cookie) {
2315 switch (desc->status) {
2316 case DONE:
2317 ret = DMA_COMPLETE;
2318 break;
2319 case PREP:
2320 case BUSY:
2321 ret = DMA_IN_PROGRESS;
2322 break;
2323 default:
2324 WARN_ON(1);
2325 }
2326 break;
2327 }
2328 if (desc->last)
2329 residual = 0;
2330 }
2331 spin_unlock(&pch->thread->dmac->lock);
2332 spin_unlock_irqrestore(&pch->lock, flags);
2333
2334 out:
2335 dma_set_residue(txstate, residual);
2336
2337 return ret;
2338 }
2339
2340 static void pl330_issue_pending(struct dma_chan *chan)
2341 {
2342 struct dma_pl330_chan *pch = to_pchan(chan);
2343 unsigned long flags;
2344
2345 spin_lock_irqsave(&pch->lock, flags);
2346 if (list_empty(&pch->work_list)) {
2347 /*
2348 * Warn on nothing pending. Empty submitted_list may
2349 * break our pm_runtime usage counter as it is
2350 * updated on work_list emptiness status.
2351 */
2352 WARN_ON(list_empty(&pch->submitted_list));
2353 pm_runtime_get_sync(pch->dmac->ddma.dev);
2354 }
2355 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2356 spin_unlock_irqrestore(&pch->lock, flags);
2357
2358 pl330_tasklet((unsigned long)pch);
2359 }
2360
2361 /*
2362 * We returned the last one of the circular list of descriptor(s)
2363 * from prep_xxx, so the argument to submit corresponds to the last
2364 * descriptor of the list.
2365 */
2366 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2367 {
2368 struct dma_pl330_desc *desc, *last = to_desc(tx);
2369 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2370 dma_cookie_t cookie;
2371 unsigned long flags;
2372
2373 spin_lock_irqsave(&pch->lock, flags);
2374
2375 /* Assign cookies to all nodes */
2376 while (!list_empty(&last->node)) {
2377 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2378 if (pch->cyclic) {
2379 desc->txd.callback = last->txd.callback;
2380 desc->txd.callback_param = last->txd.callback_param;
2381 }
2382 desc->last = false;
2383
2384 dma_cookie_assign(&desc->txd);
2385
2386 list_move_tail(&desc->node, &pch->submitted_list);
2387 }
2388
2389 last->last = true;
2390 cookie = dma_cookie_assign(&last->txd);
2391 list_add_tail(&last->node, &pch->submitted_list);
2392 spin_unlock_irqrestore(&pch->lock, flags);
2393
2394 return cookie;
2395 }
2396
2397 static inline void _init_desc(struct dma_pl330_desc *desc)
2398 {
2399 desc->rqcfg.swap = SWAP_NO;
2400 desc->rqcfg.scctl = CCTRL0;
2401 desc->rqcfg.dcctl = CCTRL0;
2402 desc->txd.tx_submit = pl330_tx_submit;
2403
2404 INIT_LIST_HEAD(&desc->node);
2405 }
2406
2407 /* Returns the number of descriptors added to the DMAC pool */
2408 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2409 {
2410 struct dma_pl330_desc *desc;
2411 unsigned long flags;
2412 int i;
2413
2414 desc = kcalloc(count, sizeof(*desc), flg);
2415 if (!desc)
2416 return 0;
2417
2418 spin_lock_irqsave(&pl330->pool_lock, flags);
2419
2420 for (i = 0; i < count; i++) {
2421 _init_desc(&desc[i]);
2422 list_add_tail(&desc[i].node, &pl330->desc_pool);
2423 }
2424
2425 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2426
2427 return count;
2428 }
2429
2430 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2431 {
2432 struct dma_pl330_desc *desc = NULL;
2433 unsigned long flags;
2434
2435 spin_lock_irqsave(&pl330->pool_lock, flags);
2436
2437 if (!list_empty(&pl330->desc_pool)) {
2438 desc = list_entry(pl330->desc_pool.next,
2439 struct dma_pl330_desc, node);
2440
2441 list_del_init(&desc->node);
2442
2443 desc->status = PREP;
2444 desc->txd.callback = NULL;
2445 }
2446
2447 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2448
2449 return desc;
2450 }
2451
2452 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2453 {
2454 struct pl330_dmac *pl330 = pch->dmac;
2455 u8 *peri_id = pch->chan.private;
2456 struct dma_pl330_desc *desc;
2457
2458 /* Pluck one desc from the pool of DMAC */
2459 desc = pluck_desc(pl330);
2460
2461 /* If the DMAC pool is empty, alloc new */
2462 if (!desc) {
2463 if (!add_desc(pl330, GFP_ATOMIC, 1))
2464 return NULL;
2465
2466 /* Try again */
2467 desc = pluck_desc(pl330);
2468 if (!desc) {
2469 dev_err(pch->dmac->ddma.dev,
2470 "%s:%d ALERT!\n", __func__, __LINE__);
2471 return NULL;
2472 }
2473 }
2474
2475 /* Initialize the descriptor */
2476 desc->pchan = pch;
2477 desc->txd.cookie = 0;
2478 async_tx_ack(&desc->txd);
2479
2480 desc->peri = peri_id ? pch->chan.chan_id : 0;
2481 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2482
2483 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2484
2485 return desc;
2486 }
2487
2488 static inline void fill_px(struct pl330_xfer *px,
2489 dma_addr_t dst, dma_addr_t src, size_t len)
2490 {
2491 px->bytes = len;
2492 px->dst_addr = dst;
2493 px->src_addr = src;
2494 }
2495
2496 static struct dma_pl330_desc *
2497 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2498 dma_addr_t src, size_t len)
2499 {
2500 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2501
2502 if (!desc) {
2503 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2504 __func__, __LINE__);
2505 return NULL;
2506 }
2507
2508 /*
2509 * Ideally we should lookout for reqs bigger than
2510 * those that can be programmed with 256 bytes of
2511 * MC buffer, but considering a req size is seldom
2512 * going to be word-unaligned and more than 200MB,
2513 * we take it easy.
2514 * Also, should the limit is reached we'd rather
2515 * have the platform increase MC buffer size than
2516 * complicating this API driver.
2517 */
2518 fill_px(&desc->px, dst, src, len);
2519
2520 return desc;
2521 }
2522
2523 /* Call after fixing burst size */
2524 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2525 {
2526 struct dma_pl330_chan *pch = desc->pchan;
2527 struct pl330_dmac *pl330 = pch->dmac;
2528 int burst_len;
2529
2530 burst_len = pl330->pcfg.data_bus_width / 8;
2531 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2532 burst_len >>= desc->rqcfg.brst_size;
2533
2534 /* src/dst_burst_len can't be more than 16 */
2535 if (burst_len > 16)
2536 burst_len = 16;
2537
2538 while (burst_len > 1) {
2539 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2540 break;
2541 burst_len--;
2542 }
2543
2544 return burst_len;
2545 }
2546
2547 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2548 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2549 size_t period_len, enum dma_transfer_direction direction,
2550 unsigned long flags)
2551 {
2552 struct dma_pl330_desc *desc = NULL, *first = NULL;
2553 struct dma_pl330_chan *pch = to_pchan(chan);
2554 struct pl330_dmac *pl330 = pch->dmac;
2555 unsigned int i;
2556 dma_addr_t dst;
2557 dma_addr_t src;
2558
2559 if (len % period_len != 0)
2560 return NULL;
2561
2562 if (!is_slave_direction(direction)) {
2563 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2564 __func__, __LINE__);
2565 return NULL;
2566 }
2567
2568 for (i = 0; i < len / period_len; i++) {
2569 desc = pl330_get_desc(pch);
2570 if (!desc) {
2571 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2572 __func__, __LINE__);
2573
2574 if (!first)
2575 return NULL;
2576
2577 spin_lock_irqsave(&pl330->pool_lock, flags);
2578
2579 while (!list_empty(&first->node)) {
2580 desc = list_entry(first->node.next,
2581 struct dma_pl330_desc, node);
2582 list_move_tail(&desc->node, &pl330->desc_pool);
2583 }
2584
2585 list_move_tail(&first->node, &pl330->desc_pool);
2586
2587 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2588
2589 return NULL;
2590 }
2591
2592 switch (direction) {
2593 case DMA_MEM_TO_DEV:
2594 desc->rqcfg.src_inc = 1;
2595 desc->rqcfg.dst_inc = 0;
2596 src = dma_addr;
2597 dst = pch->fifo_addr;
2598 break;
2599 case DMA_DEV_TO_MEM:
2600 desc->rqcfg.src_inc = 0;
2601 desc->rqcfg.dst_inc = 1;
2602 src = pch->fifo_addr;
2603 dst = dma_addr;
2604 break;
2605 default:
2606 break;
2607 }
2608
2609 desc->rqtype = direction;
2610 desc->rqcfg.brst_size = pch->burst_sz;
2611 desc->rqcfg.brst_len = 1;
2612 desc->bytes_requested = period_len;
2613 fill_px(&desc->px, dst, src, period_len);
2614
2615 if (!first)
2616 first = desc;
2617 else
2618 list_add_tail(&desc->node, &first->node);
2619
2620 dma_addr += period_len;
2621 }
2622
2623 if (!desc)
2624 return NULL;
2625
2626 pch->cyclic = true;
2627 desc->txd.flags = flags;
2628
2629 return &desc->txd;
2630 }
2631
2632 static struct dma_async_tx_descriptor *
2633 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2634 dma_addr_t src, size_t len, unsigned long flags)
2635 {
2636 struct dma_pl330_desc *desc;
2637 struct dma_pl330_chan *pch = to_pchan(chan);
2638 struct pl330_dmac *pl330;
2639 int burst;
2640
2641 if (unlikely(!pch || !len))
2642 return NULL;
2643
2644 pl330 = pch->dmac;
2645
2646 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2647 if (!desc)
2648 return NULL;
2649
2650 desc->rqcfg.src_inc = 1;
2651 desc->rqcfg.dst_inc = 1;
2652 desc->rqtype = DMA_MEM_TO_MEM;
2653
2654 /* Select max possible burst size */
2655 burst = pl330->pcfg.data_bus_width / 8;
2656
2657 /*
2658 * Make sure we use a burst size that aligns with all the memcpy
2659 * parameters because our DMA programming algorithm doesn't cope with
2660 * transfers which straddle an entry in the DMA device's MFIFO.
2661 */
2662 while ((src | dst | len) & (burst - 1))
2663 burst /= 2;
2664
2665 desc->rqcfg.brst_size = 0;
2666 while (burst != (1 << desc->rqcfg.brst_size))
2667 desc->rqcfg.brst_size++;
2668
2669 /*
2670 * If burst size is smaller than bus width then make sure we only
2671 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2672 */
2673 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2674 desc->rqcfg.brst_len = 1;
2675
2676 desc->rqcfg.brst_len = get_burst_len(desc, len);
2677 desc->bytes_requested = len;
2678
2679 desc->txd.flags = flags;
2680
2681 return &desc->txd;
2682 }
2683
2684 static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2685 struct dma_pl330_desc *first)
2686 {
2687 unsigned long flags;
2688 struct dma_pl330_desc *desc;
2689
2690 if (!first)
2691 return;
2692
2693 spin_lock_irqsave(&pl330->pool_lock, flags);
2694
2695 while (!list_empty(&first->node)) {
2696 desc = list_entry(first->node.next,
2697 struct dma_pl330_desc, node);
2698 list_move_tail(&desc->node, &pl330->desc_pool);
2699 }
2700
2701 list_move_tail(&first->node, &pl330->desc_pool);
2702
2703 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2704 }
2705
2706 static struct dma_async_tx_descriptor *
2707 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2708 unsigned int sg_len, enum dma_transfer_direction direction,
2709 unsigned long flg, void *context)
2710 {
2711 struct dma_pl330_desc *first, *desc = NULL;
2712 struct dma_pl330_chan *pch = to_pchan(chan);
2713 struct scatterlist *sg;
2714 int i;
2715 dma_addr_t addr;
2716
2717 if (unlikely(!pch || !sgl || !sg_len))
2718 return NULL;
2719
2720 addr = pch->fifo_addr;
2721
2722 first = NULL;
2723
2724 for_each_sg(sgl, sg, sg_len, i) {
2725
2726 desc = pl330_get_desc(pch);
2727 if (!desc) {
2728 struct pl330_dmac *pl330 = pch->dmac;
2729
2730 dev_err(pch->dmac->ddma.dev,
2731 "%s:%d Unable to fetch desc\n",
2732 __func__, __LINE__);
2733 __pl330_giveback_desc(pl330, first);
2734
2735 return NULL;
2736 }
2737
2738 if (!first)
2739 first = desc;
2740 else
2741 list_add_tail(&desc->node, &first->node);
2742
2743 if (direction == DMA_MEM_TO_DEV) {
2744 desc->rqcfg.src_inc = 1;
2745 desc->rqcfg.dst_inc = 0;
2746 fill_px(&desc->px,
2747 addr, sg_dma_address(sg), sg_dma_len(sg));
2748 } else {
2749 desc->rqcfg.src_inc = 0;
2750 desc->rqcfg.dst_inc = 1;
2751 fill_px(&desc->px,
2752 sg_dma_address(sg), addr, sg_dma_len(sg));
2753 }
2754
2755 desc->rqcfg.brst_size = pch->burst_sz;
2756 desc->rqcfg.brst_len = 1;
2757 desc->rqtype = direction;
2758 desc->bytes_requested = sg_dma_len(sg);
2759 }
2760
2761 /* Return the last desc in the chain */
2762 desc->txd.flags = flg;
2763 return &desc->txd;
2764 }
2765
2766 static irqreturn_t pl330_irq_handler(int irq, void *data)
2767 {
2768 if (pl330_update(data))
2769 return IRQ_HANDLED;
2770 else
2771 return IRQ_NONE;
2772 }
2773
2774 #define PL330_DMA_BUSWIDTHS \
2775 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2776 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2777 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2778 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2779 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2780
2781 /*
2782 * Runtime PM callbacks are provided by amba/bus.c driver.
2783 *
2784 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2785 * bus driver will only disable/enable the clock in runtime PM callbacks.
2786 */
2787 static int __maybe_unused pl330_suspend(struct device *dev)
2788 {
2789 struct amba_device *pcdev = to_amba_device(dev);
2790
2791 pm_runtime_disable(dev);
2792
2793 if (!pm_runtime_status_suspended(dev)) {
2794 /* amba did not disable the clock */
2795 amba_pclk_disable(pcdev);
2796 }
2797 amba_pclk_unprepare(pcdev);
2798
2799 return 0;
2800 }
2801
2802 static int __maybe_unused pl330_resume(struct device *dev)
2803 {
2804 struct amba_device *pcdev = to_amba_device(dev);
2805 int ret;
2806
2807 ret = amba_pclk_prepare(pcdev);
2808 if (ret)
2809 return ret;
2810
2811 if (!pm_runtime_status_suspended(dev))
2812 ret = amba_pclk_enable(pcdev);
2813
2814 pm_runtime_enable(dev);
2815
2816 return ret;
2817 }
2818
2819 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2820
2821 static int
2822 pl330_probe(struct amba_device *adev, const struct amba_id *id)
2823 {
2824 struct dma_pl330_platdata *pdat;
2825 struct pl330_config *pcfg;
2826 struct pl330_dmac *pl330;
2827 struct dma_pl330_chan *pch, *_p;
2828 struct dma_device *pd;
2829 struct resource *res;
2830 int i, ret, irq;
2831 int num_chan;
2832 struct device_node *np = adev->dev.of_node;
2833
2834 pdat = dev_get_platdata(&adev->dev);
2835
2836 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2837 if (ret)
2838 return ret;
2839
2840 /* Allocate a new DMAC and its Channels */
2841 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2842 if (!pl330)
2843 return -ENOMEM;
2844
2845 pd = &pl330->ddma;
2846 pd->dev = &adev->dev;
2847
2848 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2849
2850 /* get quirk */
2851 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2852 if (of_property_read_bool(np, of_quirks[i].quirk))
2853 pl330->quirks |= of_quirks[i].id;
2854
2855 res = &adev->res;
2856 pl330->base = devm_ioremap_resource(&adev->dev, res);
2857 if (IS_ERR(pl330->base))
2858 return PTR_ERR(pl330->base);
2859
2860 amba_set_drvdata(adev, pl330);
2861
2862 for (i = 0; i < AMBA_NR_IRQS; i++) {
2863 irq = adev->irq[i];
2864 if (irq) {
2865 ret = devm_request_irq(&adev->dev, irq,
2866 pl330_irq_handler, 0,
2867 dev_name(&adev->dev), pl330);
2868 if (ret)
2869 return ret;
2870 } else {
2871 break;
2872 }
2873 }
2874
2875 pcfg = &pl330->pcfg;
2876
2877 pcfg->periph_id = adev->periphid;
2878 ret = pl330_add(pl330);
2879 if (ret)
2880 return ret;
2881
2882 INIT_LIST_HEAD(&pl330->desc_pool);
2883 spin_lock_init(&pl330->pool_lock);
2884
2885 /* Create a descriptor pool of default size */
2886 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2887 dev_warn(&adev->dev, "unable to allocate desc\n");
2888
2889 INIT_LIST_HEAD(&pd->channels);
2890
2891 /* Initialize channel parameters */
2892 if (pdat)
2893 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2894 else
2895 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2896
2897 pl330->num_peripherals = num_chan;
2898
2899 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2900 if (!pl330->peripherals) {
2901 ret = -ENOMEM;
2902 goto probe_err2;
2903 }
2904
2905 for (i = 0; i < num_chan; i++) {
2906 pch = &pl330->peripherals[i];
2907 if (!adev->dev.of_node)
2908 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2909 else
2910 pch->chan.private = adev->dev.of_node;
2911
2912 INIT_LIST_HEAD(&pch->submitted_list);
2913 INIT_LIST_HEAD(&pch->work_list);
2914 INIT_LIST_HEAD(&pch->completed_list);
2915 spin_lock_init(&pch->lock);
2916 pch->thread = NULL;
2917 pch->chan.device = pd;
2918 pch->dmac = pl330;
2919
2920 /* Add the channel to the DMAC list */
2921 list_add_tail(&pch->chan.device_node, &pd->channels);
2922 }
2923
2924 if (pdat) {
2925 pd->cap_mask = pdat->cap_mask;
2926 } else {
2927 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2928 if (pcfg->num_peri) {
2929 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2930 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2931 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2932 }
2933 }
2934
2935 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2936 pd->device_free_chan_resources = pl330_free_chan_resources;
2937 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2938 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2939 pd->device_tx_status = pl330_tx_status;
2940 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2941 pd->device_config = pl330_config;
2942 pd->device_pause = pl330_pause;
2943 pd->device_terminate_all = pl330_terminate_all;
2944 pd->device_issue_pending = pl330_issue_pending;
2945 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2946 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2947 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2948 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2949 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2950 1 : PL330_MAX_BURST);
2951
2952 ret = dma_async_device_register(pd);
2953 if (ret) {
2954 dev_err(&adev->dev, "unable to register DMAC\n");
2955 goto probe_err3;
2956 }
2957
2958 if (adev->dev.of_node) {
2959 ret = of_dma_controller_register(adev->dev.of_node,
2960 of_dma_pl330_xlate, pl330);
2961 if (ret) {
2962 dev_err(&adev->dev,
2963 "unable to register DMA to the generic DT DMA helpers\n");
2964 }
2965 }
2966
2967 adev->dev.dma_parms = &pl330->dma_parms;
2968
2969 /*
2970 * This is the limit for transfers with a buswidth of 1, larger
2971 * buswidths will have larger limits.
2972 */
2973 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2974 if (ret)
2975 dev_err(&adev->dev, "unable to set the seg size\n");
2976
2977
2978 dev_info(&adev->dev,
2979 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2980 dev_info(&adev->dev,
2981 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2982 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2983 pcfg->num_peri, pcfg->num_events);
2984
2985 pm_runtime_irq_safe(&adev->dev);
2986 pm_runtime_use_autosuspend(&adev->dev);
2987 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2988 pm_runtime_mark_last_busy(&adev->dev);
2989 pm_runtime_put_autosuspend(&adev->dev);
2990
2991 return 0;
2992 probe_err3:
2993 /* Idle the DMAC */
2994 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2995 chan.device_node) {
2996
2997 /* Remove the channel */
2998 list_del(&pch->chan.device_node);
2999
3000 /* Flush the channel */
3001 if (pch->thread) {
3002 pl330_terminate_all(&pch->chan);
3003 pl330_free_chan_resources(&pch->chan);
3004 }
3005 }
3006 probe_err2:
3007 pl330_del(pl330);
3008
3009 return ret;
3010 }
3011
3012 static int pl330_remove(struct amba_device *adev)
3013 {
3014 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3015 struct dma_pl330_chan *pch, *_p;
3016 int i, irq;
3017
3018 pm_runtime_get_noresume(pl330->ddma.dev);
3019
3020 if (adev->dev.of_node)
3021 of_dma_controller_free(adev->dev.of_node);
3022
3023 for (i = 0; i < AMBA_NR_IRQS; i++) {
3024 irq = adev->irq[i];
3025 devm_free_irq(&adev->dev, irq, pl330);
3026 }
3027
3028 dma_async_device_unregister(&pl330->ddma);
3029
3030 /* Idle the DMAC */
3031 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3032 chan.device_node) {
3033
3034 /* Remove the channel */
3035 list_del(&pch->chan.device_node);
3036
3037 /* Flush the channel */
3038 if (pch->thread) {
3039 pl330_terminate_all(&pch->chan);
3040 pl330_free_chan_resources(&pch->chan);
3041 }
3042 }
3043
3044 pl330_del(pl330);
3045
3046 return 0;
3047 }
3048
3049 static struct amba_id pl330_ids[] = {
3050 {
3051 .id = 0x00041330,
3052 .mask = 0x000fffff,
3053 },
3054 { 0, 0 },
3055 };
3056
3057 MODULE_DEVICE_TABLE(amba, pl330_ids);
3058
3059 static struct amba_driver pl330_driver = {
3060 .drv = {
3061 .owner = THIS_MODULE,
3062 .name = "dma-pl330",
3063 .pm = &pl330_pm,
3064 },
3065 .id_table = pl330_ids,
3066 .probe = pl330_probe,
3067 .remove = pl330_remove,
3068 };
3069
3070 module_amba_driver(pl330_driver);
3071
3072 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3073 MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3074 MODULE_LICENSE("GPL");
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