drivers/gpio/gpio-mpc8xxx.c

   1 /*
   2  * GPIOs on MPC512x/8349/8572/8610 and compatible
   3  *
   4  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/gpio.h>
  20 #include <linux/slab.h>
  21 #include <linux/irq.h>
  22
  23 #define MPC8XXX_GPIO_PINS       32
  24
  25 #define GPIO_DIR                0x00
  26 #define GPIO_ODR                0x04
  27 #define GPIO_DAT                0x08
  28 #define GPIO_IER                0x0c
  29 #define GPIO_IMR                0x10
  30 #define GPIO_ICR                0x14
  31 #define GPIO_ICR2               0x18
  32
  33 struct mpc8xxx_gpio_chip {
  34         struct of_mm_gpio_chip mm_gc;
  35         raw_spinlock_t lock;
  36
  37         /*
  38          * shadowed data register to be able to clear/set output pins in
  39          * open drain mode safely
  40          */
  41         u32 data;
  42         struct irq_domain *irq;
  43         unsigned int irqn;
  44         const void *of_dev_id_data;
  45 };
  46
  47 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
  48 {
  49         return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
  50 }
  51
  52 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
  53 {
  54         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(&mm->gc);
  55
  56         mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
  57 }
  58
  59 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
  60  * defined as output cannot be determined by reading GPDAT register,
  61  * so we use shadow data register instead. The status of input pins
  62  * is determined by reading GPDAT register.
  63  */
  64 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  65 {
  66         u32 val;
  67         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
  68         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  69         u32 out_mask, out_shadow;
  70
  71         out_mask = in_be32(mm->regs + GPIO_DIR);
  72
  73         val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
  74         out_shadow = mpc8xxx_gc->data & out_mask;
  75
  76         return !!((val | out_shadow) & mpc8xxx_gpio2mask(gpio));
  77 }
  78
  79 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  80 {
  81         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
  82
  83         return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
  84 }
  85
  86 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  87 {
  88         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
  89         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  90         unsigned long flags;
  91
  92         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
  93
  94         if (val)
  95                 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
  96         else
  97                 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
  98
  99         out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
 100
 101         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 102 }
 103
 104 static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
 105                                       unsigned long *mask, unsigned long *bits)
 106 {
 107         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 108         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 109         unsigned long flags;
 110         int i;
 111
 112         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 113
 114         for (i = 0; i < gc->ngpio; i++) {
 115                 if (*mask == 0)
 116                         break;
 117                 if (__test_and_clear_bit(i, mask)) {
 118                         if (test_bit(i, bits))
 119                                 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
 120                         else
 121                                 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
 122                 }
 123         }
 124
 125         out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
 126
 127         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 128 }
 129
 130 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 131 {
 132         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 133         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 134         unsigned long flags;
 135
 136         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 137
 138         clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
 139
 140         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 141
 142         return 0;
 143 }
 144
 145 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 146 {
 147         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 148         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 149         unsigned long flags;
 150
 151         mpc8xxx_gpio_set(gc, gpio, val);
 152
 153         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 154
 155         setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
 156
 157         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 158
 159         return 0;
 160 }
 161
 162 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 163 {
 164         /* GPIO 28..31 are input only on MPC5121 */
 165         if (gpio >= 28)
 166                 return -EINVAL;
 167
 168         return mpc8xxx_gpio_dir_out(gc, gpio, val);
 169 }
 170
 171 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 172 {
 173         /* GPIO 0..3 are input only on MPC5125 */
 174         if (gpio <= 3)
 175                 return -EINVAL;
 176
 177         return mpc8xxx_gpio_dir_out(gc, gpio, val);
 178 }
 179
 180 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 181 {
 182         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 183
 184         if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
 185                 return irq_create_mapping(mpc8xxx_gc->irq, offset);
 186         else
 187                 return -ENXIO;
 188 }
 189
 190 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
 191 {
 192         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
 193         struct irq_chip *chip = irq_desc_get_chip(desc);
 194         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 195         unsigned int mask;
 196
 197         mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
 198         if (mask)
 199                 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
 200                                                      32 - ffs(mask)));
 201         if (chip->irq_eoi)
 202                 chip->irq_eoi(&desc->irq_data);
 203 }
 204
 205 static void mpc8xxx_irq_unmask(struct irq_data *d)
 206 {
 207         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 208         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 209         unsigned long flags;
 210
 211         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 212
 213         setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 214
 215         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 216 }
 217
 218 static void mpc8xxx_irq_mask(struct irq_data *d)
 219 {
 220         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 221         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 222         unsigned long flags;
 223
 224         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 225
 226         clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 227
 228         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 229 }
 230
 231 static void mpc8xxx_irq_ack(struct irq_data *d)
 232 {
 233         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 234         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 235
 236         out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 237 }
 238
 239 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
 240 {
 241         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 242         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 243         unsigned long flags;
 244
 245         switch (flow_type) {
 246         case IRQ_TYPE_EDGE_FALLING:
 247                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 248                 setbits32(mm->regs + GPIO_ICR,
 249                           mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 250                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 251                 break;
 252
 253         case IRQ_TYPE_EDGE_BOTH:
 254                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 255                 clrbits32(mm->regs + GPIO_ICR,
 256                           mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 257                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 258                 break;
 259
 260         default:
 261                 return -EINVAL;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
 268 {
 269         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 270         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 271         unsigned long gpio = irqd_to_hwirq(d);
 272         void __iomem *reg;
 273         unsigned int shift;
 274         unsigned long flags;
 275
 276         if (gpio < 16) {
 277                 reg = mm->regs + GPIO_ICR;
 278                 shift = (15 - gpio) * 2;
 279         } else {
 280                 reg = mm->regs + GPIO_ICR2;
 281                 shift = (15 - (gpio % 16)) * 2;
 282         }
 283
 284         switch (flow_type) {
 285         case IRQ_TYPE_EDGE_FALLING:
 286         case IRQ_TYPE_LEVEL_LOW:
 287                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 288                 clrsetbits_be32(reg, 3 << shift, 2 << shift);
 289                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 290                 break;
 291
 292         case IRQ_TYPE_EDGE_RISING:
 293         case IRQ_TYPE_LEVEL_HIGH:
 294                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 295                 clrsetbits_be32(reg, 3 << shift, 1 << shift);
 296                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 297                 break;
 298
 299         case IRQ_TYPE_EDGE_BOTH:
 300                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 301                 clrbits32(reg, 3 << shift);
 302                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 303                 break;
 304
 305         default:
 306                 return -EINVAL;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static struct irq_chip mpc8xxx_irq_chip = {
 313         .name           = "mpc8xxx-gpio",
 314         .irq_unmask     = mpc8xxx_irq_unmask,
 315         .irq_mask       = mpc8xxx_irq_mask,
 316         .irq_ack        = mpc8xxx_irq_ack,
 317         /* this might get overwritten in mpc8xxx_probe() */
 318         .irq_set_type   = mpc8xxx_irq_set_type,
 319 };
 320
 321 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
 322                                 irq_hw_number_t hwirq)
 323 {
 324         irq_set_chip_data(irq, h->host_data);
 325         irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
 326
 327         return 0;
 328 }
 329
 330 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
 331         .map    = mpc8xxx_gpio_irq_map,
 332         .xlate  = irq_domain_xlate_twocell,
 333 };
 334
 335 struct mpc8xxx_gpio_devtype {
 336         int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
 337         int (*gpio_get)(struct gpio_chip *, unsigned int);
 338         int (*irq_set_type)(struct irq_data *, unsigned int);
 339 };
 340
 341 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
 342         .gpio_dir_out = mpc5121_gpio_dir_out,
 343         .irq_set_type = mpc512x_irq_set_type,
 344 };
 345
 346 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
 347         .gpio_dir_out = mpc5125_gpio_dir_out,
 348         .irq_set_type = mpc512x_irq_set_type,
 349 };
 350
 351 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
 352         .gpio_get = mpc8572_gpio_get,
 353 };
 354
 355 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
 356         .gpio_dir_out = mpc8xxx_gpio_dir_out,
 357         .gpio_get = mpc8xxx_gpio_get,
 358         .irq_set_type = mpc8xxx_irq_set_type,
 359 };
 360
 361 static const struct of_device_id mpc8xxx_gpio_ids[] = {
 362         { .compatible = "fsl,mpc8349-gpio", },
 363         { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
 364         { .compatible = "fsl,mpc8610-gpio", },
 365         { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
 366         { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
 367         { .compatible = "fsl,pq3-gpio",     },
 368         { .compatible = "fsl,qoriq-gpio",   },
 369         {}
 370 };
 371
 372 static int mpc8xxx_probe(struct platform_device *pdev)
 373 {
 374         struct device_node *np = pdev->dev.of_node;
 375         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
 376         struct of_mm_gpio_chip *mm_gc;
 377         struct gpio_chip *gc;
 378         const struct of_device_id *id;
 379         const struct mpc8xxx_gpio_devtype *devtype =
 380                 of_device_get_match_data(&pdev->dev);
 381         int ret;
 382
 383         mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
 384         if (!mpc8xxx_gc)
 385                 return -ENOMEM;
 386
 387         platform_set_drvdata(pdev, mpc8xxx_gc);
 388
 389         raw_spin_lock_init(&mpc8xxx_gc->lock);
 390
 391         mm_gc = &mpc8xxx_gc->mm_gc;
 392         gc = &mm_gc->gc;
 393
 394         mm_gc->save_regs = mpc8xxx_gpio_save_regs;
 395         gc->ngpio = MPC8XXX_GPIO_PINS;
 396         gc->direction_input = mpc8xxx_gpio_dir_in;
 397
 398         if (!devtype)
 399                 devtype = &mpc8xxx_gpio_devtype_default;
 400
 401         /*
 402          * It's assumed that only a single type of gpio controller is available
 403          * on the current machine, so overwriting global data is fine.
 404          */
 405         mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
 406
 407         gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
 408         gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
 409         gc->set = mpc8xxx_gpio_set;
 410         gc->set_multiple = mpc8xxx_gpio_set_multiple;
 411         gc->to_irq = mpc8xxx_gpio_to_irq;
 412
 413         ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc);
 414         if (ret)
 415                 return ret;
 416
 417         mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
 418         if (mpc8xxx_gc->irqn == NO_IRQ)
 419                 return 0;
 420
 421         mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
 422                                         &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
 423         if (!mpc8xxx_gc->irq)
 424                 return 0;
 425
 426         id = of_match_node(mpc8xxx_gpio_ids, np);
 427         if (id)
 428                 mpc8xxx_gc->of_dev_id_data = id->data;
 429
 430         /* ack and mask all irqs */
 431         out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
 432         out_be32(mm_gc->regs + GPIO_IMR, 0);
 433
 434         irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
 435                                          mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
 436
 437         return 0;
 438 }
 439
 440 static int mpc8xxx_remove(struct platform_device *pdev)
 441 {
 442         struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
 443
 444         if (mpc8xxx_gc->irq) {
 445                 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
 446                 irq_domain_remove(mpc8xxx_gc->irq);
 447         }
 448
 449         of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
 450
 451         return 0;
 452 }
 453
 454 static struct platform_driver mpc8xxx_plat_driver = {
 455         .probe          = mpc8xxx_probe,
 456         .remove         = mpc8xxx_remove,
 457         .driver         = {
 458                 .name = "gpio-mpc8xxx",
 459                 .of_match_table = mpc8xxx_gpio_ids,
 460         },
 461 };
 462
 463 static int __init mpc8xxx_init(void)
 464 {
 465         return platform_driver_register(&mpc8xxx_plat_driver);
 466 }
 467
 468 arch_initcall(mpc8xxx_init);