drivers/gpio/gpio-mpc8xxx.c

   1 /*
   2  * GPIOs on MPC512x/8349/8572/8610 and compatible
   3  *
   4  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/gpio.h>
  20 #include <linux/slab.h>
  21 #include <linux/irq.h>
  22
  23 #define MPC8XXX_GPIO_PINS       32
  24
  25 #define GPIO_DIR                0x00
  26 #define GPIO_ODR                0x04
  27 #define GPIO_DAT                0x08
  28 #define GPIO_IER                0x0c
  29 #define GPIO_IMR                0x10
  30 #define GPIO_ICR                0x14
  31 #define GPIO_ICR2               0x18
  32
  33 struct mpc8xxx_gpio_chip {
  34         struct of_mm_gpio_chip mm_gc;
  35         raw_spinlock_t lock;
  36
  37         /*
  38          * shadowed data register to be able to clear/set output pins in
  39          * open drain mode safely
  40          */
  41         u32 data;
  42         struct irq_domain *irq;
  43         unsigned int irqn;
  44         const void *of_dev_id_data;
  45 };
  46
  47 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
  48 {
  49         return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
  50 }
  51
  52 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
  53 {
  54         struct mpc8xxx_gpio_chip *mpc8xxx_gc =
  55                 container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
  56
  57         mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
  58 }
  59
  60 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
  61  * defined as output cannot be determined by reading GPDAT register,
  62  * so we use shadow data register instead. The status of input pins
  63  * is determined by reading GPDAT register.
  64  */
  65 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  66 {
  67         u32 val;
  68         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
  69         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  70         u32 out_mask, out_shadow;
  71
  72         out_mask = in_be32(mm->regs + GPIO_DIR);
  73
  74         val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
  75         out_shadow = mpc8xxx_gc->data & out_mask;
  76
  77         return !!((val | out_shadow) & mpc8xxx_gpio2mask(gpio));
  78 }
  79
  80 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  81 {
  82         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
  83
  84         return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
  85 }
  86
  87 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  88 {
  89         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
  90         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
  91         unsigned long flags;
  92
  93         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
  94
  95         if (val)
  96                 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
  97         else
  98                 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
  99
 100         out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
 101
 102         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 103 }
 104
 105 static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
 106                                       unsigned long *mask, unsigned long *bits)
 107 {
 108         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 109         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 110         unsigned long flags;
 111         int i;
 112
 113         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 114
 115         for (i = 0; i < gc->ngpio; i++) {
 116                 if (*mask == 0)
 117                         break;
 118                 if (__test_and_clear_bit(i, mask)) {
 119                         if (test_bit(i, bits))
 120                                 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
 121                         else
 122                                 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
 123                 }
 124         }
 125
 126         out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
 127
 128         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 129 }
 130
 131 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 132 {
 133         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 134         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 135         unsigned long flags;
 136
 137         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 138
 139         clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
 140
 141         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 142
 143         return 0;
 144 }
 145
 146 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 147 {
 148         struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 149         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 150         unsigned long flags;
 151
 152         mpc8xxx_gpio_set(gc, gpio, val);
 153
 154         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 155
 156         setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
 157
 158         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 159
 160         return 0;
 161 }
 162
 163 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 164 {
 165         /* GPIO 28..31 are input only on MPC5121 */
 166         if (gpio >= 28)
 167                 return -EINVAL;
 168
 169         return mpc8xxx_gpio_dir_out(gc, gpio, val);
 170 }
 171
 172 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 173 {
 174         /* GPIO 0..3 are input only on MPC5125 */
 175         if (gpio <= 3)
 176                 return -EINVAL;
 177
 178         return mpc8xxx_gpio_dir_out(gc, gpio, val);
 179 }
 180
 181 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 182 {
 183         struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
 184
 185         if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
 186                 return irq_create_mapping(mpc8xxx_gc->irq, offset);
 187         else
 188                 return -ENXIO;
 189 }
 190
 191 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc)
 192 {
 193         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
 194         struct irq_chip *chip = irq_desc_get_chip(desc);
 195         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 196         unsigned int mask;
 197
 198         mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
 199         if (mask)
 200                 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
 201                                                      32 - ffs(mask)));
 202         if (chip->irq_eoi)
 203                 chip->irq_eoi(&desc->irq_data);
 204 }
 205
 206 static void mpc8xxx_irq_unmask(struct irq_data *d)
 207 {
 208         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 209         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 210         unsigned long flags;
 211
 212         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 213
 214         setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 215
 216         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 217 }
 218
 219 static void mpc8xxx_irq_mask(struct irq_data *d)
 220 {
 221         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 222         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 223         unsigned long flags;
 224
 225         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 226
 227         clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 228
 229         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 230 }
 231
 232 static void mpc8xxx_irq_ack(struct irq_data *d)
 233 {
 234         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 235         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 236
 237         out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 238 }
 239
 240 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
 241 {
 242         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 243         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 244         unsigned long flags;
 245
 246         switch (flow_type) {
 247         case IRQ_TYPE_EDGE_FALLING:
 248                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 249                 setbits32(mm->regs + GPIO_ICR,
 250                           mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 251                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 252                 break;
 253
 254         case IRQ_TYPE_EDGE_BOTH:
 255                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 256                 clrbits32(mm->regs + GPIO_ICR,
 257                           mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
 258                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 259                 break;
 260
 261         default:
 262                 return -EINVAL;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
 269 {
 270         struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
 271         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
 272         unsigned long gpio = irqd_to_hwirq(d);
 273         void __iomem *reg;
 274         unsigned int shift;
 275         unsigned long flags;
 276
 277         if (gpio < 16) {
 278                 reg = mm->regs + GPIO_ICR;
 279                 shift = (15 - gpio) * 2;
 280         } else {
 281                 reg = mm->regs + GPIO_ICR2;
 282                 shift = (15 - (gpio % 16)) * 2;
 283         }
 284
 285         switch (flow_type) {
 286         case IRQ_TYPE_EDGE_FALLING:
 287         case IRQ_TYPE_LEVEL_LOW:
 288                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 289                 clrsetbits_be32(reg, 3 << shift, 2 << shift);
 290                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 291                 break;
 292
 293         case IRQ_TYPE_EDGE_RISING:
 294         case IRQ_TYPE_LEVEL_HIGH:
 295                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 296                 clrsetbits_be32(reg, 3 << shift, 1 << shift);
 297                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 298                 break;
 299
 300         case IRQ_TYPE_EDGE_BOTH:
 301                 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 302                 clrbits32(reg, 3 << shift);
 303                 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
 304                 break;
 305
 306         default:
 307                 return -EINVAL;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static struct irq_chip mpc8xxx_irq_chip = {
 314         .name           = "mpc8xxx-gpio",
 315         .irq_unmask     = mpc8xxx_irq_unmask,
 316         .irq_mask       = mpc8xxx_irq_mask,
 317         .irq_ack        = mpc8xxx_irq_ack,
 318         /* this might get overwritten in mpc8xxx_probe() */
 319         .irq_set_type   = mpc8xxx_irq_set_type,
 320 };
 321
 322 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
 323                                 irq_hw_number_t hwirq)
 324 {
 325         irq_set_chip_data(irq, h->host_data);
 326         irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
 327
 328         return 0;
 329 }
 330
 331 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
 332         .map    = mpc8xxx_gpio_irq_map,
 333         .xlate  = irq_domain_xlate_twocell,
 334 };
 335
 336 struct mpc8xxx_gpio_devtype {
 337         int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
 338         int (*gpio_get)(struct gpio_chip *, unsigned int);
 339         int (*irq_set_type)(struct irq_data *, unsigned int);
 340 };
 341
 342 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
 343         .gpio_dir_out = mpc5121_gpio_dir_out,
 344         .irq_set_type = mpc512x_irq_set_type,
 345 };
 346
 347 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
 348         .gpio_dir_out = mpc5125_gpio_dir_out,
 349         .irq_set_type = mpc512x_irq_set_type,
 350 };
 351
 352 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
 353         .gpio_get = mpc8572_gpio_get,
 354 };
 355
 356 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
 357         .gpio_dir_out = mpc8xxx_gpio_dir_out,
 358         .gpio_get = mpc8xxx_gpio_get,
 359         .irq_set_type = mpc8xxx_irq_set_type,
 360 };
 361
 362 static const struct of_device_id mpc8xxx_gpio_ids[] = {
 363         { .compatible = "fsl,mpc8349-gpio", },
 364         { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
 365         { .compatible = "fsl,mpc8610-gpio", },
 366         { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
 367         { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
 368         { .compatible = "fsl,pq3-gpio",     },
 369         { .compatible = "fsl,qoriq-gpio",   },
 370         {}
 371 };
 372
 373 static int mpc8xxx_probe(struct platform_device *pdev)
 374 {
 375         struct device_node *np = pdev->dev.of_node;
 376         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
 377         struct of_mm_gpio_chip *mm_gc;
 378         struct gpio_chip *gc;
 379         const struct of_device_id *id;
 380         const struct mpc8xxx_gpio_devtype *devtype =
 381                 of_device_get_match_data(&pdev->dev);
 382         int ret;
 383
 384         mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
 385         if (!mpc8xxx_gc)
 386                 return -ENOMEM;
 387
 388         platform_set_drvdata(pdev, mpc8xxx_gc);
 389
 390         raw_spin_lock_init(&mpc8xxx_gc->lock);
 391
 392         mm_gc = &mpc8xxx_gc->mm_gc;
 393         gc = &mm_gc->gc;
 394
 395         mm_gc->save_regs = mpc8xxx_gpio_save_regs;
 396         gc->ngpio = MPC8XXX_GPIO_PINS;
 397         gc->direction_input = mpc8xxx_gpio_dir_in;
 398
 399         if (!devtype)
 400                 devtype = &mpc8xxx_gpio_devtype_default;
 401
 402         /*
 403          * It's assumed that only a single type of gpio controller is available
 404          * on the current machine, so overwriting global data is fine.
 405          */
 406         mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
 407
 408         gc->direction_output = devtype->gpio_dir_out ?: mpc8xxx_gpio_dir_out;
 409         gc->get = devtype->gpio_get ?: mpc8xxx_gpio_get;
 410         gc->set = mpc8xxx_gpio_set;
 411         gc->set_multiple = mpc8xxx_gpio_set_multiple;
 412         gc->to_irq = mpc8xxx_gpio_to_irq;
 413
 414         ret = of_mm_gpiochip_add_data(np, mm_gc, mpc8xxx_gc);
 415         if (ret)
 416                 return ret;
 417
 418         mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
 419         if (mpc8xxx_gc->irqn == NO_IRQ)
 420                 return 0;
 421
 422         mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
 423                                         &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
 424         if (!mpc8xxx_gc->irq)
 425                 return 0;
 426
 427         id = of_match_node(mpc8xxx_gpio_ids, np);
 428         if (id)
 429                 mpc8xxx_gc->of_dev_id_data = id->data;
 430
 431         /* ack and mask all irqs */
 432         out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
 433         out_be32(mm_gc->regs + GPIO_IMR, 0);
 434
 435         irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
 436                                          mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
 437
 438         return 0;
 439 }
 440
 441 static int mpc8xxx_remove(struct platform_device *pdev)
 442 {
 443         struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
 444
 445         if (mpc8xxx_gc->irq) {
 446                 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
 447                 irq_domain_remove(mpc8xxx_gc->irq);
 448         }
 449
 450         of_mm_gpiochip_remove(&mpc8xxx_gc->mm_gc);
 451
 452         return 0;
 453 }
 454
 455 static struct platform_driver mpc8xxx_plat_driver = {
 456         .probe          = mpc8xxx_probe,
 457         .remove         = mpc8xxx_remove,
 458         .driver         = {
 459                 .name = "gpio-mpc8xxx",
 460                 .of_match_table = mpc8xxx_gpio_ids,
 461         },
 462 };
 463
 464 static int __init mpc8xxx_init(void)
 465 {
 466         return platform_driver_register(&mpc8xxx_plat_driver);
 467 }
 468
 469 arch_initcall(mpc8xxx_init);