2 * Copyright (C) ST-Ericsson SA 2010
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
14 #include <linux/mfd/stmpe.h>
15 #include <linux/seq_file.h>
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
21 enum { REG_RE
, REG_FE
, REG_IE
};
23 enum { LSB
, CSB
, MSB
};
25 #define CACHE_NR_REGS 3
26 /* No variant has more than 24 GPIOs */
27 #define CACHE_NR_BANKS (24 / 8)
30 struct gpio_chip chip
;
33 struct mutex irq_lock
;
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs
[CACHE_NR_REGS
][CACHE_NR_BANKS
];
37 u8 oldregs
[CACHE_NR_REGS
][CACHE_NR_BANKS
];
40 static int stmpe_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
42 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(chip
);
43 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
44 u8 reg
= stmpe
->regs
[STMPE_IDX_GPMR_LSB
+ (offset
/ 8)];
45 u8 mask
= 1 << (offset
% 8);
48 ret
= stmpe_reg_read(stmpe
, reg
);
52 return !!(ret
& mask
);
55 static void stmpe_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
57 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(chip
);
58 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
59 int which
= val
? STMPE_IDX_GPSR_LSB
: STMPE_IDX_GPCR_LSB
;
60 u8 reg
= stmpe
->regs
[which
+ (offset
/ 8)];
61 u8 mask
= 1 << (offset
% 8);
64 * Some variants have single register for gpio set/clear functionality.
65 * For them we need to write 0 to clear and 1 to set.
67 if (stmpe
->regs
[STMPE_IDX_GPSR_LSB
] == stmpe
->regs
[STMPE_IDX_GPCR_LSB
])
68 stmpe_set_bits(stmpe
, reg
, mask
, val
? mask
: 0);
70 stmpe_reg_write(stmpe
, reg
, mask
);
73 static int stmpe_gpio_get_direction(struct gpio_chip
*chip
,
76 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(chip
);
77 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
78 u8 reg
= stmpe
->regs
[STMPE_IDX_GPDR_LSB
] - (offset
/ 8);
79 u8 mask
= 1 << (offset
% 8);
82 ret
= stmpe_reg_read(stmpe
, reg
);
89 static int stmpe_gpio_direction_output(struct gpio_chip
*chip
,
90 unsigned offset
, int val
)
92 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(chip
);
93 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
94 u8 reg
= stmpe
->regs
[STMPE_IDX_GPDR_LSB
+ (offset
/ 8)];
95 u8 mask
= 1 << (offset
% 8);
97 stmpe_gpio_set(chip
, offset
, val
);
99 return stmpe_set_bits(stmpe
, reg
, mask
, mask
);
102 static int stmpe_gpio_direction_input(struct gpio_chip
*chip
,
105 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(chip
);
106 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
107 u8 reg
= stmpe
->regs
[STMPE_IDX_GPDR_LSB
+ (offset
/ 8)];
108 u8 mask
= 1 << (offset
% 8);
110 return stmpe_set_bits(stmpe
, reg
, mask
, 0);
113 static int stmpe_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
115 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(chip
);
116 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
118 if (stmpe_gpio
->norequest_mask
& (1 << offset
))
121 return stmpe_set_altfunc(stmpe
, 1 << offset
, STMPE_BLOCK_GPIO
);
124 static struct gpio_chip template_chip
= {
126 .owner
= THIS_MODULE
,
127 .get_direction
= stmpe_gpio_get_direction
,
128 .direction_input
= stmpe_gpio_direction_input
,
129 .get
= stmpe_gpio_get
,
130 .direction_output
= stmpe_gpio_direction_output
,
131 .set
= stmpe_gpio_set
,
132 .request
= stmpe_gpio_request
,
136 static int stmpe_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
138 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
139 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(gc
);
140 int offset
= d
->hwirq
;
141 int regoffset
= offset
/ 8;
142 int mask
= 1 << (offset
% 8);
144 if (type
& IRQ_TYPE_LEVEL_LOW
|| type
& IRQ_TYPE_LEVEL_HIGH
)
147 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
148 if (stmpe_gpio
->stmpe
->partnum
== STMPE801
||
149 stmpe_gpio
->stmpe
->partnum
== STMPE1600
)
152 if (type
& IRQ_TYPE_EDGE_RISING
)
153 stmpe_gpio
->regs
[REG_RE
][regoffset
] |= mask
;
155 stmpe_gpio
->regs
[REG_RE
][regoffset
] &= ~mask
;
157 if (type
& IRQ_TYPE_EDGE_FALLING
)
158 stmpe_gpio
->regs
[REG_FE
][regoffset
] |= mask
;
160 stmpe_gpio
->regs
[REG_FE
][regoffset
] &= ~mask
;
165 static void stmpe_gpio_irq_lock(struct irq_data
*d
)
167 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
168 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(gc
);
170 mutex_lock(&stmpe_gpio
->irq_lock
);
173 static void stmpe_gpio_irq_sync_unlock(struct irq_data
*d
)
175 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
176 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(gc
);
177 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
178 int num_banks
= DIV_ROUND_UP(stmpe
->num_gpios
, 8);
179 static const u8 regmap
[CACHE_NR_REGS
][CACHE_NR_BANKS
] = {
180 [REG_RE
][LSB
] = STMPE_IDX_GPRER_LSB
,
181 [REG_RE
][CSB
] = STMPE_IDX_GPRER_CSB
,
182 [REG_RE
][MSB
] = STMPE_IDX_GPRER_MSB
,
183 [REG_FE
][LSB
] = STMPE_IDX_GPFER_LSB
,
184 [REG_FE
][CSB
] = STMPE_IDX_GPFER_CSB
,
185 [REG_FE
][MSB
] = STMPE_IDX_GPFER_MSB
,
186 [REG_IE
][LSB
] = STMPE_IDX_IEGPIOR_LSB
,
187 [REG_IE
][CSB
] = STMPE_IDX_IEGPIOR_CSB
,
188 [REG_IE
][MSB
] = STMPE_IDX_IEGPIOR_MSB
,
192 for (i
= 0; i
< CACHE_NR_REGS
; i
++) {
193 /* STMPE801 and STMPE1600 don't have RE and FE registers */
194 if ((stmpe
->partnum
== STMPE801
||
195 stmpe
->partnum
== STMPE1600
) &&
199 for (j
= 0; j
< num_banks
; j
++) {
200 u8 old
= stmpe_gpio
->oldregs
[i
][j
];
201 u8
new = stmpe_gpio
->regs
[i
][j
];
206 stmpe_gpio
->oldregs
[i
][j
] = new;
207 stmpe_reg_write(stmpe
, stmpe
->regs
[regmap
[i
][j
]], new);
211 mutex_unlock(&stmpe_gpio
->irq_lock
);
214 static void stmpe_gpio_irq_mask(struct irq_data
*d
)
216 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
217 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(gc
);
218 int offset
= d
->hwirq
;
219 int regoffset
= offset
/ 8;
220 int mask
= 1 << (offset
% 8);
222 stmpe_gpio
->regs
[REG_IE
][regoffset
] &= ~mask
;
225 static void stmpe_gpio_irq_unmask(struct irq_data
*d
)
227 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
228 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(gc
);
229 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
230 int offset
= d
->hwirq
;
231 int regoffset
= offset
/ 8;
232 int mask
= 1 << (offset
% 8);
234 stmpe_gpio
->regs
[REG_IE
][regoffset
] |= mask
;
237 * STMPE1600 workaround: to be able to get IRQ from pins,
238 * a read must be done on GPMR register, or a write in
239 * GPSR or GPCR registers
241 if (stmpe
->partnum
== STMPE1600
)
242 stmpe_reg_read(stmpe
,
243 stmpe
->regs
[STMPE_IDX_GPMR_LSB
+ regoffset
]);
246 static void stmpe_dbg_show_one(struct seq_file
*s
,
247 struct gpio_chip
*gc
,
248 unsigned offset
, unsigned gpio
)
250 struct stmpe_gpio
*stmpe_gpio
= gpiochip_get_data(gc
);
251 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
252 const char *label
= gpiochip_is_requested(gc
, offset
);
253 bool val
= !!stmpe_gpio_get(gc
, offset
);
254 u8 bank
= offset
/ 8;
255 u8 dir_reg
= stmpe
->regs
[STMPE_IDX_GPDR_LSB
+ bank
];
256 u8 mask
= 1 << (offset
% 8);
260 ret
= stmpe_reg_read(stmpe
, dir_reg
);
263 dir
= !!(ret
& mask
);
266 seq_printf(s
, " gpio-%-3d (%-20.20s) out %s",
267 gpio
, label
?: "(none)",
275 char *edge_det_values
[] = {"edge-inactive",
278 char *rise_values
[] = {"no-rising-edge-detection",
279 "rising-edge-detection",
281 char *fall_values
[] = {"no-falling-edge-detection",
282 "falling-edge-detection",
284 #define NOT_SUPPORTED_IDX 2
285 u8 edge_det
= NOT_SUPPORTED_IDX
;
286 u8 rise
= NOT_SUPPORTED_IDX
;
287 u8 fall
= NOT_SUPPORTED_IDX
;
290 switch (stmpe
->partnum
) {
296 edge_det_reg
= stmpe
->regs
[STMPE_IDX_GPEDR_LSB
+ bank
];
297 ret
= stmpe_reg_read(stmpe
, edge_det_reg
);
300 edge_det
= !!(ret
& mask
);
303 rise_reg
= stmpe
->regs
[STMPE_IDX_GPRER_LSB
+ bank
];
304 fall_reg
= stmpe
->regs
[STMPE_IDX_GPFER_LSB
+ bank
];
306 ret
= stmpe_reg_read(stmpe
, rise_reg
);
309 rise
= !!(ret
& mask
);
310 ret
= stmpe_reg_read(stmpe
, fall_reg
);
313 fall
= !!(ret
& mask
);
317 irqen_reg
= stmpe
->regs
[STMPE_IDX_IEGPIOR_LSB
+ bank
];
324 ret
= stmpe_reg_read(stmpe
, irqen_reg
);
327 irqen
= !!(ret
& mask
);
329 seq_printf(s
, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
330 gpio
, label
?: "(none)",
332 edge_det_values
[edge_det
],
333 irqen
? "IRQ-enabled" : "IRQ-disabled",
339 static void stmpe_dbg_show(struct seq_file
*s
, struct gpio_chip
*gc
)
342 unsigned gpio
= gc
->base
;
344 for (i
= 0; i
< gc
->ngpio
; i
++, gpio
++) {
345 stmpe_dbg_show_one(s
, gc
, i
, gpio
);
350 static struct irq_chip stmpe_gpio_irq_chip
= {
351 .name
= "stmpe-gpio",
352 .irq_bus_lock
= stmpe_gpio_irq_lock
,
353 .irq_bus_sync_unlock
= stmpe_gpio_irq_sync_unlock
,
354 .irq_mask
= stmpe_gpio_irq_mask
,
355 .irq_unmask
= stmpe_gpio_irq_unmask
,
356 .irq_set_type
= stmpe_gpio_irq_set_type
,
359 static irqreturn_t
stmpe_gpio_irq(int irq
, void *dev
)
361 struct stmpe_gpio
*stmpe_gpio
= dev
;
362 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
364 int num_banks
= DIV_ROUND_UP(stmpe
->num_gpios
, 8);
365 u8 status
[num_banks
];
370 * the stmpe_block_read() call below, imposes to set statmsbreg
371 * with the register located at the lowest address. As STMPE1600
372 * variant is the only one which respect registers address's order
373 * (LSB regs located at lowest address than MSB ones) whereas all
374 * the others have a registers layout with MSB located before the
377 if (stmpe
->partnum
== STMPE1600
)
378 statmsbreg
= stmpe
->regs
[STMPE_IDX_ISGPIOR_LSB
];
380 statmsbreg
= stmpe
->regs
[STMPE_IDX_ISGPIOR_MSB
];
382 ret
= stmpe_block_read(stmpe
, statmsbreg
, num_banks
, status
);
386 for (i
= 0; i
< num_banks
; i
++) {
387 int bank
= (stmpe_gpio
->stmpe
->partnum
== STMPE1600
) ? i
:
389 unsigned int enabled
= stmpe_gpio
->regs
[REG_IE
][bank
];
390 unsigned int stat
= status
[i
];
397 int bit
= __ffs(stat
);
398 int line
= bank
* 8 + bit
;
399 int child_irq
= irq_find_mapping(stmpe_gpio
->chip
.irqdomain
,
402 handle_nested_irq(child_irq
);
407 * interrupt status register write has no effect on
408 * 801/1801/1600, bits are cleared when read.
409 * Edge detect register is not present on 801/1600/1801
411 if (stmpe
->partnum
!= STMPE801
|| stmpe
->partnum
!= STMPE1600
||
412 stmpe
->partnum
!= STMPE1801
) {
413 stmpe_reg_write(stmpe
, statmsbreg
+ i
, status
[i
]);
414 stmpe_reg_write(stmpe
,
415 stmpe
->regs
[STMPE_IDX_GPEDR_LSB
+ i
],
423 static int stmpe_gpio_probe(struct platform_device
*pdev
)
425 struct stmpe
*stmpe
= dev_get_drvdata(pdev
->dev
.parent
);
426 struct device_node
*np
= pdev
->dev
.of_node
;
427 struct stmpe_gpio
*stmpe_gpio
;
431 irq
= platform_get_irq(pdev
, 0);
433 stmpe_gpio
= kzalloc(sizeof(struct stmpe_gpio
), GFP_KERNEL
);
437 mutex_init(&stmpe_gpio
->irq_lock
);
439 stmpe_gpio
->dev
= &pdev
->dev
;
440 stmpe_gpio
->stmpe
= stmpe
;
441 stmpe_gpio
->chip
= template_chip
;
442 stmpe_gpio
->chip
.ngpio
= stmpe
->num_gpios
;
443 stmpe_gpio
->chip
.parent
= &pdev
->dev
;
444 stmpe_gpio
->chip
.of_node
= np
;
445 stmpe_gpio
->chip
.base
= -1;
447 if (IS_ENABLED(CONFIG_DEBUG_FS
))
448 stmpe_gpio
->chip
.dbg_show
= stmpe_dbg_show
;
450 of_property_read_u32(np
, "st,norequest-mask",
451 &stmpe_gpio
->norequest_mask
);
455 "device configured in no-irq mode: "
456 "irqs are not available\n");
458 ret
= stmpe_enable(stmpe
, STMPE_BLOCK_GPIO
);
462 ret
= gpiochip_add_data(&stmpe_gpio
->chip
, stmpe_gpio
);
464 dev_err(&pdev
->dev
, "unable to add gpiochip: %d\n", ret
);
469 ret
= devm_request_threaded_irq(&pdev
->dev
, irq
, NULL
,
470 stmpe_gpio_irq
, IRQF_ONESHOT
,
471 "stmpe-gpio", stmpe_gpio
);
473 dev_err(&pdev
->dev
, "unable to get irq: %d\n", ret
);
476 ret
= gpiochip_irqchip_add(&stmpe_gpio
->chip
,
477 &stmpe_gpio_irq_chip
,
483 "could not connect irqchip to gpiochip\n");
487 gpiochip_set_chained_irqchip(&stmpe_gpio
->chip
,
488 &stmpe_gpio_irq_chip
,
493 platform_set_drvdata(pdev
, stmpe_gpio
);
498 stmpe_disable(stmpe
, STMPE_BLOCK_GPIO
);
499 gpiochip_remove(&stmpe_gpio
->chip
);
505 static struct platform_driver stmpe_gpio_driver
= {
507 .suppress_bind_attrs
= true,
508 .name
= "stmpe-gpio",
510 .probe
= stmpe_gpio_probe
,
513 static int __init
stmpe_gpio_init(void)
515 return platform_driver_register(&stmpe_gpio_driver
);
517 subsys_initcall(stmpe_gpio_init
);