drivers/gpio/gpio-stmpe.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License Terms: GNU General Public License, version 2
   5  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/slab.h>
  11 #include <linux/gpio.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/of.h>
  14 #include <linux/mfd/stmpe.h>
  15 #include <linux/seq_file.h>
  16
  17 /*
  18  * These registers are modified under the irq bus lock and cached to avoid
  19  * unnecessary writes in bus_sync_unlock.
  20  */
  21 enum { REG_RE, REG_FE, REG_IE };
  22
  23 #define CACHE_NR_REGS   3
  24 /* No variant has more than 24 GPIOs */
  25 #define CACHE_NR_BANKS  (24 / 8)
  26
  27 struct stmpe_gpio {
  28         struct gpio_chip chip;
  29         struct stmpe *stmpe;
  30         struct device *dev;
  31         struct mutex irq_lock;
  32         u32 norequest_mask;
  33         /* Caches of interrupt control registers for bus_lock */
  34         u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  35         u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  36 };
  37
  38 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
  39 {
  40         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  41         struct stmpe *stmpe = stmpe_gpio->stmpe;
  42         u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
  43         u8 mask = 1 << (offset % 8);
  44         int ret;
  45
  46         ret = stmpe_reg_read(stmpe, reg);
  47         if (ret < 0)
  48                 return ret;
  49
  50         return !!(ret & mask);
  51 }
  52
  53 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  54 {
  55         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  56         struct stmpe *stmpe = stmpe_gpio->stmpe;
  57         int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
  58         u8 reg = stmpe->regs[which] - (offset / 8);
  59         u8 mask = 1 << (offset % 8);
  60
  61         /*
  62          * Some variants have single register for gpio set/clear functionality.
  63          * For them we need to write 0 to clear and 1 to set.
  64          */
  65         if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
  66                 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
  67         else
  68                 stmpe_reg_write(stmpe, reg, mask);
  69 }
  70
  71 static int stmpe_gpio_get_direction(struct gpio_chip *chip,
  72                                     unsigned offset)
  73 {
  74         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  75         struct stmpe *stmpe = stmpe_gpio->stmpe;
  76         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  77         u8 mask = 1 << (offset % 8);
  78         int ret;
  79
  80         ret = stmpe_reg_read(stmpe, reg);
  81         if (ret < 0)
  82                 return ret;
  83
  84         return !(ret & mask);
  85 }
  86
  87 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
  88                                          unsigned offset, int val)
  89 {
  90         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  91         struct stmpe *stmpe = stmpe_gpio->stmpe;
  92         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  93         u8 mask = 1 << (offset % 8);
  94
  95         stmpe_gpio_set(chip, offset, val);
  96
  97         return stmpe_set_bits(stmpe, reg, mask, mask);
  98 }
  99
 100 static int stmpe_gpio_direction_input(struct gpio_chip *chip,
 101                                         unsigned offset)
 102 {
 103         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 104         struct stmpe *stmpe = stmpe_gpio->stmpe;
 105         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
 106         u8 mask = 1 << (offset % 8);
 107
 108         return stmpe_set_bits(stmpe, reg, mask, 0);
 109 }
 110
 111 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
 112 {
 113         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 114         struct stmpe *stmpe = stmpe_gpio->stmpe;
 115
 116         if (stmpe_gpio->norequest_mask & (1 << offset))
 117                 return -EINVAL;
 118
 119         return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
 120 }
 121
 122 static struct gpio_chip template_chip = {
 123         .label                  = "stmpe",
 124         .owner                  = THIS_MODULE,
 125         .get_direction          = stmpe_gpio_get_direction,
 126         .direction_input        = stmpe_gpio_direction_input,
 127         .get                    = stmpe_gpio_get,
 128         .direction_output       = stmpe_gpio_direction_output,
 129         .set                    = stmpe_gpio_set,
 130         .request                = stmpe_gpio_request,
 131         .can_sleep              = true,
 132 };
 133
 134 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 135 {
 136         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 137         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 138         int offset = d->hwirq;
 139         int regoffset = offset / 8;
 140         int mask = 1 << (offset % 8);
 141
 142         if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
 143                 return -EINVAL;
 144
 145         /* STMPE801 doesn't have RE and FE registers */
 146         if (stmpe_gpio->stmpe->partnum == STMPE801)
 147                 return 0;
 148
 149         if (type & IRQ_TYPE_EDGE_RISING)
 150                 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
 151         else
 152                 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
 153
 154         if (type & IRQ_TYPE_EDGE_FALLING)
 155                 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
 156         else
 157                 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
 158
 159         return 0;
 160 }
 161
 162 static void stmpe_gpio_irq_lock(struct irq_data *d)
 163 {
 164         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 165         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 166
 167         mutex_lock(&stmpe_gpio->irq_lock);
 168 }
 169
 170 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
 171 {
 172         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 173         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 174         struct stmpe *stmpe = stmpe_gpio->stmpe;
 175         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 176         static const u8 regmap[] = {
 177                 [REG_RE]        = STMPE_IDX_GPRER_LSB,
 178                 [REG_FE]        = STMPE_IDX_GPFER_LSB,
 179                 [REG_IE]        = STMPE_IDX_IEGPIOR_LSB,
 180         };
 181         int i, j;
 182
 183         for (i = 0; i < CACHE_NR_REGS; i++) {
 184                 /* STMPE801 doesn't have RE and FE registers */
 185                 if ((stmpe->partnum == STMPE801) &&
 186                                 (i != REG_IE))
 187                         continue;
 188
 189                 for (j = 0; j < num_banks; j++) {
 190                         u8 old = stmpe_gpio->oldregs[i][j];
 191                         u8 new = stmpe_gpio->regs[i][j];
 192
 193                         if (new == old)
 194                                 continue;
 195
 196                         stmpe_gpio->oldregs[i][j] = new;
 197                         stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
 198                 }
 199         }
 200
 201         mutex_unlock(&stmpe_gpio->irq_lock);
 202 }
 203
 204 static void stmpe_gpio_irq_mask(struct irq_data *d)
 205 {
 206         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 207         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 208         int offset = d->hwirq;
 209         int regoffset = offset / 8;
 210         int mask = 1 << (offset % 8);
 211
 212         stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
 213 }
 214
 215 static void stmpe_gpio_irq_unmask(struct irq_data *d)
 216 {
 217         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 218         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 219         int offset = d->hwirq;
 220         int regoffset = offset / 8;
 221         int mask = 1 << (offset % 8);
 222
 223         stmpe_gpio->regs[REG_IE][regoffset] |= mask;
 224 }
 225
 226 static void stmpe_dbg_show_one(struct seq_file *s,
 227                                struct gpio_chip *gc,
 228                                unsigned offset, unsigned gpio)
 229 {
 230         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 231         struct stmpe *stmpe = stmpe_gpio->stmpe;
 232         const char *label = gpiochip_is_requested(gc, offset);
 233         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 234         bool val = !!stmpe_gpio_get(gc, offset);
 235         u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
 236         u8 mask = 1 << (offset % 8);
 237         int ret;
 238         u8 dir;
 239
 240         ret = stmpe_reg_read(stmpe, dir_reg);
 241         if (ret < 0)
 242                 return;
 243         dir = !!(ret & mask);
 244
 245         if (dir) {
 246                 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
 247                            gpio, label ?: "(none)",
 248                            val ? "hi" : "lo");
 249         } else {
 250                 u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8);
 251                 u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8);
 252                 u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8);
 253                 u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8);
 254                 bool edge_det;
 255                 bool rise;
 256                 bool fall;
 257                 bool irqen;
 258
 259                 ret = stmpe_reg_read(stmpe, edge_det_reg);
 260                 if (ret < 0)
 261                         return;
 262                 edge_det = !!(ret & mask);
 263                 ret = stmpe_reg_read(stmpe, rise_reg);
 264                 if (ret < 0)
 265                         return;
 266                 rise = !!(ret & mask);
 267                 ret = stmpe_reg_read(stmpe, fall_reg);
 268                 if (ret < 0)
 269                         return;
 270                 fall = !!(ret & mask);
 271                 ret = stmpe_reg_read(stmpe, irqen_reg);
 272                 if (ret < 0)
 273                         return;
 274                 irqen = !!(ret & mask);
 275
 276                 seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %s %s%s%s",
 277                            gpio, label ?: "(none)",
 278                            val ? "hi" : "lo",
 279                            edge_det ? "edge-asserted" : "edge-inactive",
 280                            irqen ? "IRQ-enabled" : "",
 281                            rise ? " rising-edge-detection" : "",
 282                            fall ? " falling-edge-detection" : "");
 283         }
 284 }
 285
 286 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
 287 {
 288         unsigned i;
 289         unsigned gpio = gc->base;
 290
 291         for (i = 0; i < gc->ngpio; i++, gpio++) {
 292                 stmpe_dbg_show_one(s, gc, i, gpio);
 293                 seq_printf(s, "\n");
 294         }
 295 }
 296
 297 static struct irq_chip stmpe_gpio_irq_chip = {
 298         .name                   = "stmpe-gpio",
 299         .irq_bus_lock           = stmpe_gpio_irq_lock,
 300         .irq_bus_sync_unlock    = stmpe_gpio_irq_sync_unlock,
 301         .irq_mask               = stmpe_gpio_irq_mask,
 302         .irq_unmask             = stmpe_gpio_irq_unmask,
 303         .irq_set_type           = stmpe_gpio_irq_set_type,
 304 };
 305
 306 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
 307 {
 308         struct stmpe_gpio *stmpe_gpio = dev;
 309         struct stmpe *stmpe = stmpe_gpio->stmpe;
 310         u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
 311         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 312         u8 status[num_banks];
 313         int ret;
 314         int i;
 315
 316         ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
 317         if (ret < 0)
 318                 return IRQ_NONE;
 319
 320         for (i = 0; i < num_banks; i++) {
 321                 int bank = num_banks - i - 1;
 322                 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
 323                 unsigned int stat = status[i];
 324
 325                 stat &= enabled;
 326                 if (!stat)
 327                         continue;
 328
 329                 while (stat) {
 330                         int bit = __ffs(stat);
 331                         int line = bank * 8 + bit;
 332                         int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
 333                                                          line);
 334
 335                         handle_nested_irq(child_irq);
 336                         stat &= ~(1 << bit);
 337                 }
 338
 339                 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
 340
 341                 /* Edge detect register is not present on 801 */
 342                 if (stmpe->partnum != STMPE801)
 343                         stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
 344                                         + i, status[i]);
 345         }
 346
 347         return IRQ_HANDLED;
 348 }
 349
 350 static int stmpe_gpio_probe(struct platform_device *pdev)
 351 {
 352         struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
 353         struct device_node *np = pdev->dev.of_node;
 354         struct stmpe_gpio *stmpe_gpio;
 355         int ret;
 356         int irq = 0;
 357
 358         irq = platform_get_irq(pdev, 0);
 359
 360         stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
 361         if (!stmpe_gpio)
 362                 return -ENOMEM;
 363
 364         mutex_init(&stmpe_gpio->irq_lock);
 365
 366         stmpe_gpio->dev = &pdev->dev;
 367         stmpe_gpio->stmpe = stmpe;
 368         stmpe_gpio->chip = template_chip;
 369         stmpe_gpio->chip.ngpio = stmpe->num_gpios;
 370         stmpe_gpio->chip.parent = &pdev->dev;
 371         stmpe_gpio->chip.of_node = np;
 372         stmpe_gpio->chip.base = -1;
 373
 374         if (IS_ENABLED(CONFIG_DEBUG_FS))
 375                 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
 376
 377         of_property_read_u32(np, "st,norequest-mask",
 378                         &stmpe_gpio->norequest_mask);
 379
 380         if (irq < 0)
 381                 dev_info(&pdev->dev,
 382                         "device configured in no-irq mode: "
 383                         "irqs are not available\n");
 384
 385         ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
 386         if (ret)
 387                 goto out_free;
 388
 389         ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
 390         if (ret) {
 391                 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
 392                 goto out_disable;
 393         }
 394
 395         if (irq > 0) {
 396                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 397                                 stmpe_gpio_irq, IRQF_ONESHOT,
 398                                 "stmpe-gpio", stmpe_gpio);
 399                 if (ret) {
 400                         dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
 401                         goto out_disable;
 402                 }
 403                 ret =  gpiochip_irqchip_add(&stmpe_gpio->chip,
 404                                             &stmpe_gpio_irq_chip,
 405                                             0,
 406                                             handle_simple_irq,
 407                                             IRQ_TYPE_NONE);
 408                 if (ret) {
 409                         dev_err(&pdev->dev,
 410                                 "could not connect irqchip to gpiochip\n");
 411                         goto out_disable;
 412                 }
 413
 414                 gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
 415                                              &stmpe_gpio_irq_chip,
 416                                              irq,
 417                                              NULL);
 418         }
 419
 420         platform_set_drvdata(pdev, stmpe_gpio);
 421
 422         return 0;
 423
 424 out_disable:
 425         stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 426         gpiochip_remove(&stmpe_gpio->chip);
 427 out_free:
 428         kfree(stmpe_gpio);
 429         return ret;
 430 }
 431
 432 static struct platform_driver stmpe_gpio_driver = {
 433         .driver = {
 434                 .suppress_bind_attrs    = true,
 435                 .name                   = "stmpe-gpio",
 436         },
 437         .probe          = stmpe_gpio_probe,
 438 };
 439
 440 static int __init stmpe_gpio_init(void)
 441 {
 442         return platform_driver_register(&stmpe_gpio_driver);
 443 }
 444 subsys_initcall(stmpe_gpio_init);