2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_ttm.h"
55 #include "amdgpu_gds.h"
56 #include "amd_powerplay.h"
57 #include "amdgpu_acp.h"
59 #include "gpu_scheduler.h"
64 extern int amdgpu_modeset
;
65 extern int amdgpu_vram_limit
;
66 extern int amdgpu_gart_size
;
67 extern int amdgpu_benchmarking
;
68 extern int amdgpu_testing
;
69 extern int amdgpu_audio
;
70 extern int amdgpu_disp_priority
;
71 extern int amdgpu_hw_i2c
;
72 extern int amdgpu_pcie_gen2
;
73 extern int amdgpu_msi
;
74 extern int amdgpu_lockup_timeout
;
75 extern int amdgpu_dpm
;
76 extern int amdgpu_smc_load_fw
;
77 extern int amdgpu_aspm
;
78 extern int amdgpu_runtime_pm
;
79 extern unsigned amdgpu_ip_block_mask
;
80 extern int amdgpu_bapm
;
81 extern int amdgpu_deep_color
;
82 extern int amdgpu_vm_size
;
83 extern int amdgpu_vm_block_size
;
84 extern int amdgpu_vm_fault_stop
;
85 extern int amdgpu_vm_debug
;
86 extern int amdgpu_sched_jobs
;
87 extern int amdgpu_sched_hw_submission
;
88 extern int amdgpu_powerplay
;
89 extern int amdgpu_powercontainment
;
90 extern unsigned amdgpu_pcie_gen_cap
;
91 extern unsigned amdgpu_pcie_lane_cap
;
92 extern unsigned amdgpu_cg_mask
;
93 extern unsigned amdgpu_pg_mask
;
94 extern char *amdgpu_disable_cu
;
95 extern int amdgpu_sclk_deep_sleep_en
;
96 extern char *amdgpu_virtual_display
;
98 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
99 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
101 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
102 #define AMDGPU_IB_POOL_SIZE 16
103 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
104 #define AMDGPUFB_CONN_LIMIT 4
105 #define AMDGPU_BIOS_NUM_SCRATCH 8
107 /* max number of rings */
108 #define AMDGPU_MAX_RINGS 16
109 #define AMDGPU_MAX_GFX_RINGS 1
110 #define AMDGPU_MAX_COMPUTE_RINGS 8
111 #define AMDGPU_MAX_VCE_RINGS 2
113 /* max number of IP instances */
114 #define AMDGPU_MAX_SDMA_INSTANCES 2
116 /* hardcode that limit for now */
117 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
119 /* hard reset data */
120 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
123 #define AMDGPU_RESET_GFX (1 << 0)
124 #define AMDGPU_RESET_COMPUTE (1 << 1)
125 #define AMDGPU_RESET_DMA (1 << 2)
126 #define AMDGPU_RESET_CP (1 << 3)
127 #define AMDGPU_RESET_GRBM (1 << 4)
128 #define AMDGPU_RESET_DMA1 (1 << 5)
129 #define AMDGPU_RESET_RLC (1 << 6)
130 #define AMDGPU_RESET_SEM (1 << 7)
131 #define AMDGPU_RESET_IH (1 << 8)
132 #define AMDGPU_RESET_VMC (1 << 9)
133 #define AMDGPU_RESET_MC (1 << 10)
134 #define AMDGPU_RESET_DISPLAY (1 << 11)
135 #define AMDGPU_RESET_UVD (1 << 12)
136 #define AMDGPU_RESET_VCE (1 << 13)
137 #define AMDGPU_RESET_VCE1 (1 << 14)
139 /* GFX current status */
140 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
141 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
142 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
143 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
144 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
146 /* max cursor sizes (in pixels) */
147 #define CIK_CURSOR_WIDTH 128
148 #define CIK_CURSOR_HEIGHT 128
150 struct amdgpu_device
;
154 struct amdgpu_cs_parser
;
156 struct amdgpu_irq_src
;
160 AMDGPU_CP_IRQ_GFX_EOP
= 0,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
173 enum amdgpu_sdma_irq
{
174 AMDGPU_SDMA_IRQ_TRAP0
= 0,
175 AMDGPU_SDMA_IRQ_TRAP1
,
180 enum amdgpu_thermal_irq
{
181 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
182 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
184 AMDGPU_THERMAL_IRQ_LAST
187 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
188 enum amd_ip_block_type block_type
,
189 enum amd_clockgating_state state
);
190 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
191 enum amd_ip_block_type block_type
,
192 enum amd_powergating_state state
);
193 int amdgpu_wait_for_idle(struct amdgpu_device
*adev
,
194 enum amd_ip_block_type block_type
);
195 bool amdgpu_is_idle(struct amdgpu_device
*adev
,
196 enum amd_ip_block_type block_type
);
198 struct amdgpu_ip_block_version
{
199 enum amd_ip_block_type type
;
203 const struct amd_ip_funcs
*funcs
;
206 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
207 enum amd_ip_block_type type
,
208 u32 major
, u32 minor
);
210 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
211 struct amdgpu_device
*adev
,
212 enum amd_ip_block_type type
);
214 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
215 struct amdgpu_buffer_funcs
{
216 /* maximum bytes in a single operation */
217 uint32_t copy_max_bytes
;
219 /* number of dw to reserve per operation */
220 unsigned copy_num_dw
;
222 /* used for buffer migration */
223 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
224 /* src addr in bytes */
226 /* dst addr in bytes */
228 /* number of byte to transfer */
229 uint32_t byte_count
);
231 /* maximum bytes in a single operation */
232 uint32_t fill_max_bytes
;
234 /* number of dw to reserve per operation */
235 unsigned fill_num_dw
;
237 /* used for buffer clearing */
238 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
239 /* value to write to memory */
241 /* dst addr in bytes */
243 /* number of byte to fill */
244 uint32_t byte_count
);
247 /* provided by hw blocks that can write ptes, e.g., sdma */
248 struct amdgpu_vm_pte_funcs
{
249 /* copy pte entries from GART */
250 void (*copy_pte
)(struct amdgpu_ib
*ib
,
251 uint64_t pe
, uint64_t src
,
253 /* write pte one entry at a time with addr mapping */
254 void (*write_pte
)(struct amdgpu_ib
*ib
, uint64_t pe
,
255 uint64_t value
, unsigned count
,
257 /* for linear pte/pde updates without addr mapping */
258 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
260 uint64_t addr
, unsigned count
,
261 uint32_t incr
, uint32_t flags
);
264 /* provided by the gmc block */
265 struct amdgpu_gart_funcs
{
266 /* flush the vm tlb via mmio */
267 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
269 /* write pte/pde updates using the cpu */
270 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
271 void *cpu_pt_addr
, /* cpu addr of page table */
272 uint32_t gpu_page_idx
, /* pte/pde to update */
273 uint64_t addr
, /* addr to write into pte/pde */
274 uint32_t flags
); /* access flags */
277 /* provided by the ih block */
278 struct amdgpu_ih_funcs
{
279 /* ring read/write ptr handling, called from interrupt context */
280 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
281 void (*decode_iv
)(struct amdgpu_device
*adev
,
282 struct amdgpu_iv_entry
*entry
);
283 void (*set_rptr
)(struct amdgpu_device
*adev
);
286 /* provided by hw blocks that expose a ring buffer for commands */
287 struct amdgpu_ring_funcs
{
288 /* ring read/write ptr handling */
289 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
290 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
291 void (*set_wptr
)(struct amdgpu_ring
*ring
);
292 /* validating and patching of IBs */
293 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
294 /* command emit functions */
295 void (*emit_ib
)(struct amdgpu_ring
*ring
,
296 struct amdgpu_ib
*ib
,
297 unsigned vm_id
, bool ctx_switch
);
298 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
299 uint64_t seq
, unsigned flags
);
300 void (*emit_pipeline_sync
)(struct amdgpu_ring
*ring
);
301 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
303 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
304 void (*emit_hdp_invalidate
)(struct amdgpu_ring
*ring
);
305 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
306 uint32_t gds_base
, uint32_t gds_size
,
307 uint32_t gws_base
, uint32_t gws_size
,
308 uint32_t oa_base
, uint32_t oa_size
);
309 /* testing functions */
310 int (*test_ring
)(struct amdgpu_ring
*ring
);
311 int (*test_ib
)(struct amdgpu_ring
*ring
, long timeout
);
312 /* insert NOP packets */
313 void (*insert_nop
)(struct amdgpu_ring
*ring
, uint32_t count
);
314 /* pad the indirect buffer to the necessary number of dw */
315 void (*pad_ib
)(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
);
316 unsigned (*init_cond_exec
)(struct amdgpu_ring
*ring
);
317 void (*patch_cond_exec
)(struct amdgpu_ring
*ring
, unsigned offset
);
318 /* note usage for clock and power gating */
319 void (*begin_use
)(struct amdgpu_ring
*ring
);
320 void (*end_use
)(struct amdgpu_ring
*ring
);
326 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
327 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
332 struct amdgpu_dummy_page
{
336 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
337 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
344 #define AMDGPU_MAX_PPLL 3
346 struct amdgpu_clock
{
347 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
348 struct amdgpu_pll spll
;
349 struct amdgpu_pll mpll
;
351 uint32_t default_mclk
;
352 uint32_t default_sclk
;
353 uint32_t default_dispclk
;
354 uint32_t current_dispclk
;
356 uint32_t max_pixel_clock
;
362 struct amdgpu_fence_driver
{
364 volatile uint32_t *cpu_addr
;
365 /* sync_seq is protected by ring emission lock */
369 struct amdgpu_irq_src
*irq_src
;
371 struct timer_list fallback_timer
;
372 unsigned num_fences_mask
;
374 struct fence
**fences
;
377 /* some special values for the owner field */
378 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
379 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
381 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
382 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
384 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
385 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
386 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
388 int amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
,
389 unsigned num_hw_submission
);
390 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
391 struct amdgpu_irq_src
*irq_src
,
393 void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev
);
394 void amdgpu_fence_driver_resume(struct amdgpu_device
*adev
);
395 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, struct fence
**fence
);
396 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
397 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
398 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
404 struct amdgpu_bo_list_entry
{
405 struct amdgpu_bo
*robj
;
406 struct ttm_validate_buffer tv
;
407 struct amdgpu_bo_va
*bo_va
;
409 struct page
**user_pages
;
410 int user_invalidated
;
413 struct amdgpu_bo_va_mapping
{
414 struct list_head list
;
415 struct interval_tree_node it
;
420 /* bo virtual addresses in a specific vm */
421 struct amdgpu_bo_va
{
422 /* protected by bo being reserved */
423 struct list_head bo_list
;
424 struct fence
*last_pt_update
;
427 /* protected by vm mutex and spinlock */
428 struct list_head vm_status
;
430 /* mappings for this bo_va */
431 struct list_head invalids
;
432 struct list_head valids
;
434 /* constant after initialization */
435 struct amdgpu_vm
*vm
;
436 struct amdgpu_bo
*bo
;
439 #define AMDGPU_GEM_DOMAIN_MAX 0x3
442 /* Protected by gem.mutex */
443 struct list_head list
;
444 /* Protected by tbo.reserved */
445 u32 prefered_domains
;
447 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
448 struct ttm_placement placement
;
449 struct ttm_buffer_object tbo
;
450 struct ttm_bo_kmap_obj kmap
;
458 /* list of all virtual address to which this bo
462 /* Constant after initialization */
463 struct amdgpu_device
*adev
;
464 struct drm_gem_object gem_base
;
465 struct amdgpu_bo
*parent
;
466 struct amdgpu_bo
*shadow
;
468 struct ttm_bo_kmap_obj dma_buf_vmap
;
469 struct amdgpu_mn
*mn
;
470 struct list_head mn_list
;
471 struct list_head shadow_list
;
473 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
475 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
476 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
477 struct drm_file
*file_priv
);
478 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
479 struct drm_file
*file_priv
);
480 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
481 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
482 struct drm_gem_object
*
483 amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
484 struct dma_buf_attachment
*attach
,
485 struct sg_table
*sg
);
486 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
487 struct drm_gem_object
*gobj
,
489 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
490 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
491 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
492 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
493 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
494 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
496 /* sub-allocation manager, it has to be protected by another lock.
497 * By conception this is an helper for other part of the driver
498 * like the indirect buffer or semaphore, which both have their
501 * Principe is simple, we keep a list of sub allocation in offset
502 * order (first entry has offset == 0, last entry has the highest
505 * When allocating new object we first check if there is room at
506 * the end total_size - (last_object_offset + last_object_size) >=
507 * alloc_size. If so we allocate new object there.
509 * When there is not enough room at the end, we start waiting for
510 * each sub object until we reach object_offset+object_size >=
511 * alloc_size, this object then become the sub object we return.
513 * Alignment can't be bigger than page size.
515 * Hole are not considered for allocation to keep things simple.
516 * Assumption is that there won't be hole (all object on same
520 #define AMDGPU_SA_NUM_FENCE_LISTS 32
522 struct amdgpu_sa_manager
{
523 wait_queue_head_t wq
;
524 struct amdgpu_bo
*bo
;
525 struct list_head
*hole
;
526 struct list_head flist
[AMDGPU_SA_NUM_FENCE_LISTS
];
527 struct list_head olist
;
535 /* sub-allocation buffer */
536 struct amdgpu_sa_bo
{
537 struct list_head olist
;
538 struct list_head flist
;
539 struct amdgpu_sa_manager
*manager
;
548 void amdgpu_gem_force_release(struct amdgpu_device
*adev
);
549 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
550 int alignment
, u32 initial_domain
,
551 u64 flags
, bool kernel
,
552 struct drm_gem_object
**obj
);
554 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
555 struct drm_device
*dev
,
556 struct drm_mode_create_dumb
*args
);
557 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
558 struct drm_device
*dev
,
559 uint32_t handle
, uint64_t *offset_p
);
564 DECLARE_HASHTABLE(fences
, 4);
565 struct fence
*last_vm_update
;
568 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
569 int amdgpu_sync_fence(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
571 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
572 struct amdgpu_sync
*sync
,
573 struct reservation_object
*resv
,
575 struct fence
*amdgpu_sync_peek_fence(struct amdgpu_sync
*sync
,
576 struct amdgpu_ring
*ring
);
577 struct fence
*amdgpu_sync_get_fence(struct amdgpu_sync
*sync
);
578 void amdgpu_sync_free(struct amdgpu_sync
*sync
);
579 int amdgpu_sync_init(void);
580 void amdgpu_sync_fini(void);
581 int amdgpu_fence_slab_init(void);
582 void amdgpu_fence_slab_fini(void);
585 * GART structures, functions & helpers
589 #define AMDGPU_GPU_PAGE_SIZE 4096
590 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
591 #define AMDGPU_GPU_PAGE_SHIFT 12
592 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
595 dma_addr_t table_addr
;
596 struct amdgpu_bo
*robj
;
598 unsigned num_gpu_pages
;
599 unsigned num_cpu_pages
;
601 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
605 const struct amdgpu_gart_funcs
*gart_funcs
;
608 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
609 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
610 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
611 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
612 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
613 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
614 int amdgpu_gart_init(struct amdgpu_device
*adev
);
615 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
616 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, uint64_t offset
,
618 int amdgpu_gart_bind(struct amdgpu_device
*adev
, uint64_t offset
,
619 int pages
, struct page
**pagelist
,
620 dma_addr_t
*dma_addr
, uint32_t flags
);
623 * GPU MC structures, functions & helpers
626 resource_size_t aper_size
;
627 resource_size_t aper_base
;
628 resource_size_t agp_base
;
629 /* for some chips with <= 32MB we need to lie
630 * about vram size near mc fb location */
632 u64 visible_vram_size
;
643 const struct firmware
*fw
; /* MC firmware */
645 struct amdgpu_irq_src vm_fault
;
647 uint32_t srbm_soft_reset
;
648 struct amdgpu_mode_mc_save save
;
652 * GPU doorbell structures, functions & helpers
654 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
656 AMDGPU_DOORBELL_KIQ
= 0x000,
657 AMDGPU_DOORBELL_HIQ
= 0x001,
658 AMDGPU_DOORBELL_DIQ
= 0x002,
659 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
660 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
661 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
662 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
663 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
664 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
665 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
666 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
667 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
668 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
669 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
670 AMDGPU_DOORBELL_IH
= 0x1E8,
671 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
672 AMDGPU_DOORBELL_INVALID
= 0xFFFF
673 } AMDGPU_DOORBELL_ASSIGNMENT
;
675 struct amdgpu_doorbell
{
677 resource_size_t base
;
678 resource_size_t size
;
680 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
683 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
684 phys_addr_t
*aperture_base
,
685 size_t *aperture_size
,
686 size_t *start_offset
);
692 struct amdgpu_flip_work
{
693 struct delayed_work flip_work
;
694 struct work_struct unpin_work
;
695 struct amdgpu_device
*adev
;
699 struct drm_pending_vblank_event
*event
;
700 struct amdgpu_bo
*old_rbo
;
702 unsigned shared_count
;
703 struct fence
**shared
;
714 struct amdgpu_sa_bo
*sa_bo
;
721 enum amdgpu_ring_type
{
722 AMDGPU_RING_TYPE_GFX
,
723 AMDGPU_RING_TYPE_COMPUTE
,
724 AMDGPU_RING_TYPE_SDMA
,
725 AMDGPU_RING_TYPE_UVD
,
729 extern const struct amd_sched_backend_ops amdgpu_sched_ops
;
731 int amdgpu_job_alloc(struct amdgpu_device
*adev
, unsigned num_ibs
,
732 struct amdgpu_job
**job
, struct amdgpu_vm
*vm
);
733 int amdgpu_job_alloc_with_ib(struct amdgpu_device
*adev
, unsigned size
,
734 struct amdgpu_job
**job
);
736 void amdgpu_job_free_resources(struct amdgpu_job
*job
);
737 void amdgpu_job_free(struct amdgpu_job
*job
);
738 int amdgpu_job_submit(struct amdgpu_job
*job
, struct amdgpu_ring
*ring
,
739 struct amd_sched_entity
*entity
, void *owner
,
743 struct amdgpu_device
*adev
;
744 const struct amdgpu_ring_funcs
*funcs
;
745 struct amdgpu_fence_driver fence_drv
;
746 struct amd_gpu_scheduler sched
;
748 struct amdgpu_bo
*ring_obj
;
749 volatile uint32_t *ring
;
765 struct amdgpu_bo
*mqd_obj
;
770 uint64_t current_ctx
;
771 enum amdgpu_ring_type type
;
773 unsigned cond_exe_offs
;
774 u64 cond_exe_gpu_addr
;
775 volatile u32
*cond_exe_cpu_addr
;
776 #if defined(CONFIG_DEBUG_FS)
785 /* maximum number of VMIDs */
786 #define AMDGPU_NUM_VM 16
788 /* Maximum number of PTEs the hardware can write with one command */
789 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
791 /* number of entries in page table */
792 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
794 /* PTBs (Page Table Blocks) need to be aligned to 32K */
795 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
797 /* LOG2 number of continuous pages for the fragment field */
798 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
800 #define AMDGPU_PTE_VALID (1 << 0)
801 #define AMDGPU_PTE_SYSTEM (1 << 1)
802 #define AMDGPU_PTE_SNOOPED (1 << 2)
805 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
807 #define AMDGPU_PTE_READABLE (1 << 5)
808 #define AMDGPU_PTE_WRITEABLE (1 << 6)
810 #define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7)
812 /* How to programm VM fault handling */
813 #define AMDGPU_VM_FAULT_STOP_NEVER 0
814 #define AMDGPU_VM_FAULT_STOP_FIRST 1
815 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
817 struct amdgpu_vm_pt
{
818 struct amdgpu_bo_list_entry entry
;
820 uint64_t shadow_addr
;
824 /* tree of virtual addresses mapped */
827 /* protecting invalidated */
828 spinlock_t status_lock
;
830 /* BOs moved, but not yet updated in the PT */
831 struct list_head invalidated
;
833 /* BOs cleared in the PT because of a move */
834 struct list_head cleared
;
836 /* BO mappings freed, but not yet updated in the PT */
837 struct list_head freed
;
839 /* contains the page directory */
840 struct amdgpu_bo
*page_directory
;
841 unsigned max_pde_used
;
842 struct fence
*page_directory_fence
;
843 uint64_t last_eviction_counter
;
845 /* array of page tables, one for each page directory entry */
846 struct amdgpu_vm_pt
*page_tables
;
848 /* for id and flush management per ring */
849 struct amdgpu_vm_id
*ids
[AMDGPU_MAX_RINGS
];
851 /* protecting freed */
852 spinlock_t freed_lock
;
854 /* Scheduler entity for page table updates */
855 struct amd_sched_entity entity
;
861 struct amdgpu_vm_id
{
862 struct list_head list
;
864 struct amdgpu_sync active
;
865 struct fence
*last_flush
;
868 uint64_t pd_gpu_addr
;
869 /* last flushed PD/PT update */
870 struct fence
*flushed_updates
;
872 uint32_t current_gpu_reset_count
;
882 struct amdgpu_vm_manager
{
883 /* Handling of VMIDs */
886 struct list_head ids_lru
;
887 struct amdgpu_vm_id ids
[AMDGPU_NUM_VM
];
889 /* Handling of VM fences */
891 unsigned seqno
[AMDGPU_MAX_RINGS
];
894 /* vram base address for page table entry */
895 u64 vram_base_offset
;
898 /* vm pte handling */
899 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
900 struct amdgpu_ring
*vm_pte_rings
[AMDGPU_MAX_RINGS
];
901 unsigned vm_pte_num_rings
;
902 atomic_t vm_pte_next_ring
;
903 /* client id counter */
904 atomic64_t client_counter
;
907 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
);
908 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
);
909 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
910 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
911 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
912 struct list_head
*validated
,
913 struct amdgpu_bo_list_entry
*entry
);
914 void amdgpu_vm_get_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
915 struct list_head
*duplicates
);
916 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
917 struct amdgpu_vm
*vm
);
918 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
919 struct amdgpu_sync
*sync
, struct fence
*fence
,
920 struct amdgpu_job
*job
);
921 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
);
922 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
);
923 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
924 struct amdgpu_vm
*vm
);
925 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
926 struct amdgpu_vm
*vm
);
927 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
928 struct amdgpu_sync
*sync
);
929 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
930 struct amdgpu_bo_va
*bo_va
,
932 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
933 struct amdgpu_bo
*bo
);
934 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
935 struct amdgpu_bo
*bo
);
936 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
937 struct amdgpu_vm
*vm
,
938 struct amdgpu_bo
*bo
);
939 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
940 struct amdgpu_bo_va
*bo_va
,
941 uint64_t addr
, uint64_t offset
,
942 uint64_t size
, uint32_t flags
);
943 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
944 struct amdgpu_bo_va
*bo_va
,
946 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
947 struct amdgpu_bo_va
*bo_va
);
950 * context related structures
953 struct amdgpu_ctx_ring
{
955 struct fence
**fences
;
956 struct amd_sched_entity entity
;
960 struct kref refcount
;
961 struct amdgpu_device
*adev
;
962 unsigned reset_counter
;
963 spinlock_t ring_lock
;
964 struct fence
**fences
;
965 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
968 struct amdgpu_ctx_mgr
{
969 struct amdgpu_device
*adev
;
971 /* protected by lock */
972 struct idr ctx_handles
;
975 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
976 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
978 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
979 struct fence
*fence
);
980 struct fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
981 struct amdgpu_ring
*ring
, uint64_t seq
);
983 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
984 struct drm_file
*filp
);
986 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
987 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
990 * file private structure
993 struct amdgpu_fpriv
{
995 struct mutex bo_list_lock
;
996 struct idr bo_list_handles
;
997 struct amdgpu_ctx_mgr ctx_mgr
;
1004 struct amdgpu_bo_list
{
1006 struct amdgpu_bo
*gds_obj
;
1007 struct amdgpu_bo
*gws_obj
;
1008 struct amdgpu_bo
*oa_obj
;
1009 unsigned first_userptr
;
1010 unsigned num_entries
;
1011 struct amdgpu_bo_list_entry
*array
;
1014 struct amdgpu_bo_list
*
1015 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1016 void amdgpu_bo_list_get_list(struct amdgpu_bo_list
*list
,
1017 struct list_head
*validated
);
1018 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1019 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1024 #include "clearstate_defs.h"
1026 struct amdgpu_rlc_funcs
{
1027 void (*enter_safe_mode
)(struct amdgpu_device
*adev
);
1028 void (*exit_safe_mode
)(struct amdgpu_device
*adev
);
1032 /* for power gating */
1033 struct amdgpu_bo
*save_restore_obj
;
1034 uint64_t save_restore_gpu_addr
;
1035 volatile uint32_t *sr_ptr
;
1036 const u32
*reg_list
;
1038 /* for clear state */
1039 struct amdgpu_bo
*clear_state_obj
;
1040 uint64_t clear_state_gpu_addr
;
1041 volatile uint32_t *cs_ptr
;
1042 const struct cs_section_def
*cs_data
;
1043 u32 clear_state_size
;
1045 struct amdgpu_bo
*cp_table_obj
;
1046 uint64_t cp_table_gpu_addr
;
1047 volatile uint32_t *cp_table_ptr
;
1050 /* safe mode for updating CG/PG state */
1052 const struct amdgpu_rlc_funcs
*funcs
;
1054 /* for firmware data */
1055 u32 save_and_restore_offset
;
1056 u32 clear_state_descriptor_offset
;
1057 u32 avail_scratch_ram_locations
;
1058 u32 reg_restore_list_size
;
1059 u32 reg_list_format_start
;
1060 u32 reg_list_format_separate_start
;
1061 u32 starting_offsets_start
;
1062 u32 reg_list_format_size_bytes
;
1063 u32 reg_list_size_bytes
;
1065 u32
*register_list_format
;
1066 u32
*register_restore
;
1070 struct amdgpu_bo
*hpd_eop_obj
;
1071 u64 hpd_eop_gpu_addr
;
1078 * GPU scratch registers structures, functions & helpers
1080 struct amdgpu_scratch
{
1088 * GFX configurations
1090 struct amdgpu_gca_config
{
1091 unsigned max_shader_engines
;
1092 unsigned max_tile_pipes
;
1093 unsigned max_cu_per_sh
;
1094 unsigned max_sh_per_se
;
1095 unsigned max_backends_per_se
;
1096 unsigned max_texture_channel_caches
;
1098 unsigned max_gs_threads
;
1099 unsigned max_hw_contexts
;
1100 unsigned sc_prim_fifo_size_frontend
;
1101 unsigned sc_prim_fifo_size_backend
;
1102 unsigned sc_hiz_tile_fifo_size
;
1103 unsigned sc_earlyz_tile_fifo_size
;
1105 unsigned num_tile_pipes
;
1106 unsigned backend_enable_mask
;
1107 unsigned mem_max_burst_length_bytes
;
1108 unsigned mem_row_size_in_kb
;
1109 unsigned shader_engine_tile_size
;
1111 unsigned multi_gpu_tile_size
;
1112 unsigned mc_arb_ramcfg
;
1113 unsigned gb_addr_config
;
1116 uint32_t tile_mode_array
[32];
1117 uint32_t macrotile_mode_array
[16];
1120 struct amdgpu_cu_info
{
1121 uint32_t number
; /* total active CU number */
1122 uint32_t ao_cu_mask
;
1123 uint32_t bitmap
[4][4];
1126 struct amdgpu_gfx_funcs
{
1127 /* get the gpu clock counter */
1128 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1129 void (*select_se_sh
)(struct amdgpu_device
*adev
, u32 se_num
, u32 sh_num
, u32 instance
);
1133 struct mutex gpu_clock_mutex
;
1134 struct amdgpu_gca_config config
;
1135 struct amdgpu_rlc rlc
;
1136 struct amdgpu_mec mec
;
1137 struct amdgpu_scratch scratch
;
1138 const struct firmware
*me_fw
; /* ME firmware */
1139 uint32_t me_fw_version
;
1140 const struct firmware
*pfp_fw
; /* PFP firmware */
1141 uint32_t pfp_fw_version
;
1142 const struct firmware
*ce_fw
; /* CE firmware */
1143 uint32_t ce_fw_version
;
1144 const struct firmware
*rlc_fw
; /* RLC firmware */
1145 uint32_t rlc_fw_version
;
1146 const struct firmware
*mec_fw
; /* MEC firmware */
1147 uint32_t mec_fw_version
;
1148 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1149 uint32_t mec2_fw_version
;
1150 uint32_t me_feature_version
;
1151 uint32_t ce_feature_version
;
1152 uint32_t pfp_feature_version
;
1153 uint32_t rlc_feature_version
;
1154 uint32_t mec_feature_version
;
1155 uint32_t mec2_feature_version
;
1156 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1157 unsigned num_gfx_rings
;
1158 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1159 unsigned num_compute_rings
;
1160 struct amdgpu_irq_src eop_irq
;
1161 struct amdgpu_irq_src priv_reg_irq
;
1162 struct amdgpu_irq_src priv_inst_irq
;
1164 uint32_t gfx_current_status
;
1166 unsigned ce_ram_size
;
1167 struct amdgpu_cu_info cu_info
;
1168 const struct amdgpu_gfx_funcs
*funcs
;
1171 uint32_t grbm_soft_reset
;
1172 uint32_t srbm_soft_reset
;
1175 int amdgpu_ib_get(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1176 unsigned size
, struct amdgpu_ib
*ib
);
1177 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
,
1179 int amdgpu_ib_schedule(struct amdgpu_ring
*ring
, unsigned num_ibs
,
1180 struct amdgpu_ib
*ib
, struct fence
*last_vm_update
,
1181 struct amdgpu_job
*job
, struct fence
**f
);
1182 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1183 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1184 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1185 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1186 void amdgpu_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
);
1187 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
);
1188 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1189 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1190 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1191 unsigned ring_size
, u32 nop
, u32 align_mask
,
1192 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1193 enum amdgpu_ring_type ring_type
);
1194 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1199 struct amdgpu_cs_chunk
{
1205 struct amdgpu_cs_parser
{
1206 struct amdgpu_device
*adev
;
1207 struct drm_file
*filp
;
1208 struct amdgpu_ctx
*ctx
;
1212 struct amdgpu_cs_chunk
*chunks
;
1214 /* scheduler job object */
1215 struct amdgpu_job
*job
;
1217 /* buffer objects */
1218 struct ww_acquire_ctx ticket
;
1219 struct amdgpu_bo_list
*bo_list
;
1220 struct amdgpu_bo_list_entry vm_pd
;
1221 struct list_head validated
;
1222 struct fence
*fence
;
1223 uint64_t bytes_moved_threshold
;
1224 uint64_t bytes_moved
;
1227 struct amdgpu_bo_list_entry uf_entry
;
1231 struct amd_sched_job base
;
1232 struct amdgpu_device
*adev
;
1233 struct amdgpu_vm
*vm
;
1234 struct amdgpu_ring
*ring
;
1235 struct amdgpu_sync sync
;
1236 struct amdgpu_ib
*ibs
;
1237 struct fence
*fence
; /* the hw fence */
1241 bool vm_needs_flush
;
1243 uint64_t vm_pd_addr
;
1244 uint32_t gds_base
, gds_size
;
1245 uint32_t gws_base
, gws_size
;
1246 uint32_t oa_base
, oa_size
;
1248 /* user fence handling */
1250 uint64_t uf_sequence
;
1253 #define to_amdgpu_job(sched_job) \
1254 container_of((sched_job), struct amdgpu_job, base)
1256 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
,
1257 uint32_t ib_idx
, int idx
)
1259 return p
->job
->ibs
[ib_idx
].ptr
[idx
];
1262 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser
*p
,
1263 uint32_t ib_idx
, int idx
,
1266 p
->job
->ibs
[ib_idx
].ptr
[idx
] = value
;
1272 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1275 struct amdgpu_bo
*wb_obj
;
1276 volatile uint32_t *wb
;
1278 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1279 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1282 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1283 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1287 enum amdgpu_int_thermal_type
{
1289 THERMAL_TYPE_EXTERNAL
,
1290 THERMAL_TYPE_EXTERNAL_GPIO
,
1293 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1294 THERMAL_TYPE_EVERGREEN
,
1298 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1303 enum amdgpu_dpm_auto_throttle_src
{
1304 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1305 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1308 enum amdgpu_dpm_event_src
{
1309 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1310 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1311 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1312 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1313 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1316 #define AMDGPU_MAX_VCE_LEVELS 6
1318 enum amdgpu_vce_level
{
1319 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1320 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1321 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1322 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1323 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1324 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1328 u32 caps
; /* vbios flags */
1329 u32
class; /* vbios flags */
1330 u32 class2
; /* vbios flags */
1338 enum amdgpu_vce_level vce_level
;
1343 struct amdgpu_dpm_thermal
{
1344 /* thermal interrupt work */
1345 struct work_struct work
;
1346 /* low temperature threshold */
1348 /* high temperature threshold */
1350 /* was last interrupt low to high or high to low */
1352 /* interrupt source */
1353 struct amdgpu_irq_src irq
;
1356 enum amdgpu_clk_action
1362 struct amdgpu_blacklist_clocks
1366 enum amdgpu_clk_action action
;
1369 struct amdgpu_clock_and_voltage_limits
{
1376 struct amdgpu_clock_array
{
1381 struct amdgpu_clock_voltage_dependency_entry
{
1386 struct amdgpu_clock_voltage_dependency_table
{
1388 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1391 union amdgpu_cac_leakage_entry
{
1403 struct amdgpu_cac_leakage_table
{
1405 union amdgpu_cac_leakage_entry
*entries
;
1408 struct amdgpu_phase_shedding_limits_entry
{
1414 struct amdgpu_phase_shedding_limits_table
{
1416 struct amdgpu_phase_shedding_limits_entry
*entries
;
1419 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1425 struct amdgpu_uvd_clock_voltage_dependency_table
{
1427 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1430 struct amdgpu_vce_clock_voltage_dependency_entry
{
1436 struct amdgpu_vce_clock_voltage_dependency_table
{
1438 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1441 struct amdgpu_ppm_table
{
1443 u16 cpu_core_number
;
1445 u32 small_ac_platform_tdp
;
1447 u32 small_ac_platform_tdc
;
1454 struct amdgpu_cac_tdp_table
{
1456 u16 configurable_tdp
;
1458 u16 battery_power_limit
;
1459 u16 small_power_limit
;
1460 u16 low_cac_leakage
;
1461 u16 high_cac_leakage
;
1462 u16 maximum_power_delivery_limit
;
1465 struct amdgpu_dpm_dynamic_state
{
1466 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1467 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1468 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1469 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1470 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1471 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1472 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1473 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1474 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1475 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1476 struct amdgpu_clock_array valid_sclk_values
;
1477 struct amdgpu_clock_array valid_mclk_values
;
1478 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1479 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1480 u32 mclk_sclk_ratio
;
1481 u32 sclk_mclk_delta
;
1482 u16 vddc_vddci_delta
;
1483 u16 min_vddc_for_pcie_gen2
;
1484 struct amdgpu_cac_leakage_table cac_leakage_table
;
1485 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1486 struct amdgpu_ppm_table
*ppm_table
;
1487 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1490 struct amdgpu_dpm_fan
{
1501 u16 default_max_fan_pwm
;
1502 u16 default_fan_output_sensitivity
;
1503 u16 fan_output_sensitivity
;
1504 bool ucode_fan_control
;
1507 enum amdgpu_pcie_gen
{
1508 AMDGPU_PCIE_GEN1
= 0,
1509 AMDGPU_PCIE_GEN2
= 1,
1510 AMDGPU_PCIE_GEN3
= 2,
1511 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1514 enum amdgpu_dpm_forced_level
{
1515 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1516 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1517 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1518 AMDGPU_DPM_FORCED_LEVEL_MANUAL
= 3,
1521 struct amdgpu_vce_state
{
1532 struct amdgpu_dpm_funcs
{
1533 int (*get_temperature
)(struct amdgpu_device
*adev
);
1534 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1535 int (*set_power_state
)(struct amdgpu_device
*adev
);
1536 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1537 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1538 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1539 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1540 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1541 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1542 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1543 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1544 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1545 void (*powergate_vce
)(struct amdgpu_device
*adev
, bool gate
);
1546 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1547 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1548 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1549 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1550 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1551 int (*force_clock_level
)(struct amdgpu_device
*adev
, enum pp_clock_type type
, uint32_t mask
);
1552 int (*print_clock_levels
)(struct amdgpu_device
*adev
, enum pp_clock_type type
, char *buf
);
1553 int (*get_sclk_od
)(struct amdgpu_device
*adev
);
1554 int (*set_sclk_od
)(struct amdgpu_device
*adev
, uint32_t value
);
1555 int (*get_mclk_od
)(struct amdgpu_device
*adev
);
1556 int (*set_mclk_od
)(struct amdgpu_device
*adev
, uint32_t value
);
1560 struct amdgpu_ps
*ps
;
1561 /* number of valid power states */
1563 /* current power state that is active */
1564 struct amdgpu_ps
*current_ps
;
1565 /* requested power state */
1566 struct amdgpu_ps
*requested_ps
;
1567 /* boot up power state */
1568 struct amdgpu_ps
*boot_ps
;
1569 /* default uvd power state */
1570 struct amdgpu_ps
*uvd_ps
;
1571 /* vce requirements */
1572 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1573 enum amdgpu_vce_level vce_level
;
1574 enum amd_pm_state_type state
;
1575 enum amd_pm_state_type user_state
;
1577 u32 voltage_response_time
;
1578 u32 backbias_response_time
;
1580 u32 new_active_crtcs
;
1581 int new_active_crtc_count
;
1582 u32 current_active_crtcs
;
1583 int current_active_crtc_count
;
1584 struct amdgpu_dpm_dynamic_state dyn_state
;
1585 struct amdgpu_dpm_fan fan
;
1588 u32 near_tdp_limit_adjusted
;
1589 u32 sq_ramping_threshold
;
1593 u16 load_line_slope
;
1596 /* special states active */
1597 bool thermal_active
;
1600 /* thermal handling */
1601 struct amdgpu_dpm_thermal thermal
;
1603 enum amdgpu_dpm_forced_level forced_level
;
1612 struct amdgpu_i2c_chan
*i2c_bus
;
1613 /* internal thermal controller on rv6xx+ */
1614 enum amdgpu_int_thermal_type int_thermal_type
;
1615 struct device
*int_hwmon_dev
;
1616 /* fan control parameters */
1618 u8 fan_pulses_per_revolution
;
1623 bool sysfs_initialized
;
1624 struct amdgpu_dpm dpm
;
1625 const struct firmware
*fw
; /* SMC firmware */
1626 uint32_t fw_version
;
1627 const struct amdgpu_dpm_funcs
*funcs
;
1628 uint32_t pcie_gen_mask
;
1629 uint32_t pcie_mlw_mask
;
1630 struct amd_pp_display_configuration pm_display_cfg
;/* set by DAL */
1633 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
);
1638 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1639 #define AMDGPU_MAX_UVD_HANDLES 40
1640 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1641 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1642 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1643 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1646 struct amdgpu_bo
*vcpu_bo
;
1649 unsigned fw_version
;
1651 unsigned max_handles
;
1652 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1653 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1654 struct delayed_work idle_work
;
1655 const struct firmware
*fw
; /* UVD firmware */
1656 struct amdgpu_ring ring
;
1657 struct amdgpu_irq_src irq
;
1658 bool address_64_bit
;
1660 struct amd_sched_entity entity
;
1661 uint32_t srbm_soft_reset
;
1667 #define AMDGPU_MAX_VCE_HANDLES 16
1668 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1670 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1671 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1674 struct amdgpu_bo
*vcpu_bo
;
1676 unsigned fw_version
;
1677 unsigned fb_version
;
1678 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1679 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1680 uint32_t img_size
[AMDGPU_MAX_VCE_HANDLES
];
1681 struct delayed_work idle_work
;
1682 struct mutex idle_mutex
;
1683 const struct firmware
*fw
; /* VCE firmware */
1684 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1685 struct amdgpu_irq_src irq
;
1686 unsigned harvest_config
;
1687 struct amd_sched_entity entity
;
1688 uint32_t srbm_soft_reset
;
1694 struct amdgpu_sdma_instance
{
1696 const struct firmware
*fw
;
1697 uint32_t fw_version
;
1698 uint32_t feature_version
;
1700 struct amdgpu_ring ring
;
1704 struct amdgpu_sdma
{
1705 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1706 struct amdgpu_irq_src trap_irq
;
1707 struct amdgpu_irq_src illegal_inst_irq
;
1709 uint32_t srbm_soft_reset
;
1715 struct amdgpu_firmware
{
1716 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1718 struct amdgpu_bo
*fw_buf
;
1719 unsigned int fw_size
;
1725 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1731 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1732 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1733 struct amdgpu_ring
*cpA
,
1734 struct amdgpu_ring
*cpB
);
1735 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1740 #if defined(CONFIG_MMU_NOTIFIER)
1741 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1742 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1744 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1748 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1754 struct amdgpu_debugfs
{
1755 const struct drm_info_list
*files
;
1759 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1760 const struct drm_info_list
*files
,
1762 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1764 #if defined(CONFIG_DEBUG_FS)
1765 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1766 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1769 int amdgpu_debugfs_firmware_init(struct amdgpu_device
*adev
);
1772 * amdgpu smumgr functions
1774 struct amdgpu_smumgr_funcs
{
1775 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1776 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1777 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1783 struct amdgpu_smumgr
{
1784 struct amdgpu_bo
*toc_buf
;
1785 struct amdgpu_bo
*smu_buf
;
1786 /* asic priv smu data */
1788 spinlock_t smu_lock
;
1789 /* smumgr functions */
1790 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1791 /* ucode loading complete flag */
1796 * ASIC specific register table accessible by UMD
1798 struct amdgpu_allowed_register_entry
{
1799 uint32_t reg_offset
;
1805 * ASIC specific functions.
1807 struct amdgpu_asic_funcs
{
1808 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1809 bool (*read_bios_from_rom
)(struct amdgpu_device
*adev
,
1810 u8
*bios
, u32 length_bytes
);
1811 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1812 u32 sh_num
, u32 reg_offset
, u32
*value
);
1813 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1814 int (*reset
)(struct amdgpu_device
*adev
);
1815 /* get the reference clock */
1816 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1817 /* MM block clocks */
1818 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1819 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1820 /* query virtual capabilities */
1821 u32 (*get_virtual_caps
)(struct amdgpu_device
*adev
);
1827 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1828 struct drm_file
*filp
);
1829 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1830 struct drm_file
*filp
);
1832 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1833 struct drm_file
*filp
);
1834 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1835 struct drm_file
*filp
);
1836 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1837 struct drm_file
*filp
);
1838 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1839 struct drm_file
*filp
);
1840 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1841 struct drm_file
*filp
);
1842 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1843 struct drm_file
*filp
);
1844 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1845 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1847 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1848 struct drm_file
*filp
);
1850 /* VRAM scratch page for HDP bug, default vram page */
1851 struct amdgpu_vram_scratch
{
1852 struct amdgpu_bo
*robj
;
1853 volatile uint32_t *ptr
;
1860 struct amdgpu_atif_notification_cfg
{
1865 struct amdgpu_atif_notifications
{
1866 bool display_switch
;
1867 bool expansion_mode_change
;
1869 bool forced_power_state
;
1870 bool system_power_state
;
1871 bool display_conf_change
;
1873 bool brightness_change
;
1874 bool dgpu_display_event
;
1877 struct amdgpu_atif_functions
{
1879 bool sbios_requests
;
1880 bool select_active_disp
;
1882 bool get_tv_standard
;
1883 bool set_tv_standard
;
1884 bool get_panel_expansion_mode
;
1885 bool set_panel_expansion_mode
;
1886 bool temperature_change
;
1887 bool graphics_device_types
;
1890 struct amdgpu_atif
{
1891 struct amdgpu_atif_notifications notifications
;
1892 struct amdgpu_atif_functions functions
;
1893 struct amdgpu_atif_notification_cfg notification_cfg
;
1894 struct amdgpu_encoder
*encoder_for_bl
;
1897 struct amdgpu_atcs_functions
{
1901 bool pcie_bus_width
;
1904 struct amdgpu_atcs
{
1905 struct amdgpu_atcs_functions functions
;
1911 struct cgs_device
*amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1912 void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device
);
1915 /* GPU virtualization */
1916 #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1917 #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
1918 struct amdgpu_virtualization
{
1919 bool supports_sr_iov
;
1925 * Core structure, functions and helpers.
1927 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1928 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1930 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1931 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1933 struct amdgpu_ip_block_status
{
1940 struct amdgpu_device
{
1942 struct drm_device
*ddev
;
1943 struct pci_dev
*pdev
;
1945 #ifdef CONFIG_DRM_AMD_ACP
1946 struct amdgpu_acp acp
;
1950 enum amd_asic_type asic_type
;
1953 uint32_t external_rev_id
;
1954 unsigned long flags
;
1956 const struct amdgpu_asic_funcs
*asic_funcs
;
1960 struct work_struct reset_work
;
1961 struct notifier_block acpi_nb
;
1962 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1963 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1964 unsigned debugfs_count
;
1965 #if defined(CONFIG_DEBUG_FS)
1966 struct dentry
*debugfs_regs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1968 struct amdgpu_atif atif
;
1969 struct amdgpu_atcs atcs
;
1970 struct mutex srbm_mutex
;
1971 /* GRBM index mutex. Protects concurrent access to GRBM index */
1972 struct mutex grbm_idx_mutex
;
1973 struct dev_pm_domain vga_pm_domain
;
1974 bool have_disp_power_ref
;
1979 struct amdgpu_bo
*stollen_vga_memory
;
1980 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1982 /* Register/doorbell mmio */
1983 resource_size_t rmmio_base
;
1984 resource_size_t rmmio_size
;
1985 void __iomem
*rmmio
;
1986 /* protects concurrent MM_INDEX/DATA based register access */
1987 spinlock_t mmio_idx_lock
;
1988 /* protects concurrent SMC based register access */
1989 spinlock_t smc_idx_lock
;
1990 amdgpu_rreg_t smc_rreg
;
1991 amdgpu_wreg_t smc_wreg
;
1992 /* protects concurrent PCIE register access */
1993 spinlock_t pcie_idx_lock
;
1994 amdgpu_rreg_t pcie_rreg
;
1995 amdgpu_wreg_t pcie_wreg
;
1996 /* protects concurrent UVD register access */
1997 spinlock_t uvd_ctx_idx_lock
;
1998 amdgpu_rreg_t uvd_ctx_rreg
;
1999 amdgpu_wreg_t uvd_ctx_wreg
;
2000 /* protects concurrent DIDT register access */
2001 spinlock_t didt_idx_lock
;
2002 amdgpu_rreg_t didt_rreg
;
2003 amdgpu_wreg_t didt_wreg
;
2004 /* protects concurrent gc_cac register access */
2005 spinlock_t gc_cac_idx_lock
;
2006 amdgpu_rreg_t gc_cac_rreg
;
2007 amdgpu_wreg_t gc_cac_wreg
;
2008 /* protects concurrent ENDPOINT (audio) register access */
2009 spinlock_t audio_endpt_idx_lock
;
2010 amdgpu_block_rreg_t audio_endpt_rreg
;
2011 amdgpu_block_wreg_t audio_endpt_wreg
;
2012 void __iomem
*rio_mem
;
2013 resource_size_t rio_mem_size
;
2014 struct amdgpu_doorbell doorbell
;
2016 /* clock/pll info */
2017 struct amdgpu_clock clock
;
2020 struct amdgpu_mc mc
;
2021 struct amdgpu_gart gart
;
2022 struct amdgpu_dummy_page dummy_page
;
2023 struct amdgpu_vm_manager vm_manager
;
2025 /* memory management */
2026 struct amdgpu_mman mman
;
2027 struct amdgpu_vram_scratch vram_scratch
;
2028 struct amdgpu_wb wb
;
2029 atomic64_t vram_usage
;
2030 atomic64_t vram_vis_usage
;
2031 atomic64_t gtt_usage
;
2032 atomic64_t num_bytes_moved
;
2033 atomic64_t num_evictions
;
2034 atomic_t gpu_reset_counter
;
2037 bool enable_virtual_display
;
2038 struct amdgpu_mode_info mode_info
;
2039 struct work_struct hotplug_work
;
2040 struct amdgpu_irq_src crtc_irq
;
2041 struct amdgpu_irq_src pageflip_irq
;
2042 struct amdgpu_irq_src hpd_irq
;
2047 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
2049 struct amdgpu_sa_manager ring_tmp_bo
;
2052 struct amdgpu_irq irq
;
2055 struct amd_powerplay powerplay
;
2057 bool pp_force_state_enabled
;
2060 struct amdgpu_pm pm
;
2065 struct amdgpu_smumgr smu
;
2068 struct amdgpu_gfx gfx
;
2071 struct amdgpu_sdma sdma
;
2074 struct amdgpu_uvd uvd
;
2077 struct amdgpu_vce vce
;
2080 struct amdgpu_firmware firmware
;
2083 struct amdgpu_gds gds
;
2085 const struct amdgpu_ip_block_version
*ip_blocks
;
2087 struct amdgpu_ip_block_status
*ip_block_status
;
2088 struct mutex mn_lock
;
2089 DECLARE_HASHTABLE(mn_hash
, 7);
2091 /* tracking pinned memory */
2093 u64 invisible_pin_size
;
2096 /* amdkfd interface */
2097 struct kfd_dev
*kfd
;
2099 struct amdgpu_virtualization virtualization
;
2101 /* link all shadow bo */
2102 struct list_head shadow_list
;
2103 struct mutex shadow_list_lock
;
2106 bool amdgpu_device_is_px(struct drm_device
*dev
);
2107 int amdgpu_device_init(struct amdgpu_device
*adev
,
2108 struct drm_device
*ddev
,
2109 struct pci_dev
*pdev
,
2111 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2112 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2114 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2115 bool always_indirect
);
2116 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2117 bool always_indirect
);
2118 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2119 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2121 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2122 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2125 * Registers read & write functions.
2127 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2128 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2129 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2130 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2131 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2132 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2133 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2134 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2135 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2136 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2137 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2138 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2139 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2140 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2141 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2142 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
2143 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
2144 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2145 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2146 #define WREG32_P(reg, val, mask) \
2148 uint32_t tmp_ = RREG32(reg); \
2150 tmp_ |= ((val) & ~(mask)); \
2151 WREG32(reg, tmp_); \
2153 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2154 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2155 #define WREG32_PLL_P(reg, val, mask) \
2157 uint32_t tmp_ = RREG32_PLL(reg); \
2159 tmp_ |= ((val) & ~(mask)); \
2160 WREG32_PLL(reg, tmp_); \
2162 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2163 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2164 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2166 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2167 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2169 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2170 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2172 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2173 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2174 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2176 #define REG_GET_FIELD(value, reg, field) \
2177 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2179 #define WREG32_FIELD(reg, field, val) \
2180 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
2185 #define RBIOS8(i) (adev->bios[i])
2186 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2187 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2192 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2194 if (ring
->count_dw
<= 0)
2195 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2196 ring
->ring
[ring
->wptr
++] = v
;
2197 ring
->wptr
&= ring
->ptr_mask
;
2201 static inline struct amdgpu_sdma_instance
*
2202 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
2204 struct amdgpu_device
*adev
= ring
->adev
;
2207 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
2208 if (&adev
->sdma
.instance
[i
].ring
== ring
)
2211 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
2212 return &adev
->sdma
.instance
[i
];
2220 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2221 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2222 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2223 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2224 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2225 #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
2226 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2227 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2228 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2229 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2230 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2231 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2232 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
2233 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2234 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2235 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2236 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
2237 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2238 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2239 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2240 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
2241 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2242 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2243 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2244 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2245 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2246 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2247 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2248 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2249 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2250 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2251 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2252 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2253 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2254 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2255 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2256 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2257 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2258 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2259 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2260 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2261 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2262 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2263 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2264 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2265 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2266 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2267 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2268 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2269 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2270 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2271 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2272 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2273 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2274 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2275 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2276 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2277 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2278 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
2279 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
2281 #define amdgpu_dpm_get_temperature(adev) \
2282 ((adev)->pp_enabled ? \
2283 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2284 (adev)->pm.funcs->get_temperature((adev)))
2286 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2287 ((adev)->pp_enabled ? \
2288 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2289 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2291 #define amdgpu_dpm_get_fan_control_mode(adev) \
2292 ((adev)->pp_enabled ? \
2293 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2294 (adev)->pm.funcs->get_fan_control_mode((adev)))
2296 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2297 ((adev)->pp_enabled ? \
2298 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2299 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2301 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2302 ((adev)->pp_enabled ? \
2303 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2304 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2306 #define amdgpu_dpm_get_sclk(adev, l) \
2307 ((adev)->pp_enabled ? \
2308 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2309 (adev)->pm.funcs->get_sclk((adev), (l)))
2311 #define amdgpu_dpm_get_mclk(adev, l) \
2312 ((adev)->pp_enabled ? \
2313 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2314 (adev)->pm.funcs->get_mclk((adev), (l)))
2317 #define amdgpu_dpm_force_performance_level(adev, l) \
2318 ((adev)->pp_enabled ? \
2319 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2320 (adev)->pm.funcs->force_performance_level((adev), (l)))
2322 #define amdgpu_dpm_powergate_uvd(adev, g) \
2323 ((adev)->pp_enabled ? \
2324 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2325 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2327 #define amdgpu_dpm_powergate_vce(adev, g) \
2328 ((adev)->pp_enabled ? \
2329 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2330 (adev)->pm.funcs->powergate_vce((adev), (g)))
2332 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2333 ((adev)->pp_enabled ? \
2334 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2335 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2337 #define amdgpu_dpm_get_current_power_state(adev) \
2338 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2340 #define amdgpu_dpm_get_performance_level(adev) \
2341 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2343 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2344 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2346 #define amdgpu_dpm_get_pp_table(adev, table) \
2347 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2349 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2350 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2352 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2353 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2355 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2356 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2358 #define amdgpu_dpm_get_sclk_od(adev) \
2359 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2361 #define amdgpu_dpm_set_sclk_od(adev, value) \
2362 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2364 #define amdgpu_dpm_get_mclk_od(adev) \
2365 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2367 #define amdgpu_dpm_set_mclk_od(adev, value) \
2368 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2370 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2371 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2373 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2375 /* Common functions */
2376 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2377 bool amdgpu_need_backup(struct amdgpu_device
*adev
);
2378 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2379 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2380 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2382 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2383 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2384 u32 ip_instance
, u32 ring
,
2385 struct amdgpu_ring
**out_ring
);
2386 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2387 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2388 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
);
2389 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2391 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
2392 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
);
2393 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
2395 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt
*ttm
,
2396 int *last_invalidated
);
2397 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2398 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2399 struct ttm_mem_reg
*mem
);
2400 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2401 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2402 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2403 u64
amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device
*adev
);
2404 int amdgpu_ttm_global_init(struct amdgpu_device
*adev
);
2405 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2406 const u32
*registers
,
2407 const u32 array_size
);
2409 bool amdgpu_device_is_px(struct drm_device
*dev
);
2411 #if defined(CONFIG_VGA_SWITCHEROO)
2412 void amdgpu_register_atpx_handler(void);
2413 void amdgpu_unregister_atpx_handler(void);
2414 bool amdgpu_has_atpx_dgpu_power_cntl(void);
2415 bool amdgpu_is_atpx_hybrid(void);
2417 static inline void amdgpu_register_atpx_handler(void) {}
2418 static inline void amdgpu_unregister_atpx_handler(void) {}
2419 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2420 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
2426 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2427 extern const int amdgpu_max_kms_ioctl
;
2429 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2430 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2431 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2432 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2433 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2434 struct drm_file
*file_priv
);
2435 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2436 struct drm_file
*file_priv
);
2437 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2438 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2439 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
2440 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2441 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2442 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, unsigned int pipe
,
2444 struct timeval
*vblank_time
,
2446 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2450 * functions used by amdgpu_encoder.c
2452 struct amdgpu_afmt_acr
{
2466 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2469 #if defined(CONFIG_ACPI)
2470 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2471 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2472 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2473 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2474 u8 perf_req
, bool advertise
);
2475 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2477 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2478 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2481 struct amdgpu_bo_va_mapping
*
2482 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2483 uint64_t addr
, struct amdgpu_bo
**bo
);
2485 #include "amdgpu_object.h"