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drm/amdgpu: keep the prefered/allowed domains in the BO
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56
57 #include "gpu_scheduler.h"
58
59 /*
60 * Modules parameters.
61 */
62 extern int amdgpu_modeset;
63 extern int amdgpu_vram_limit;
64 extern int amdgpu_gart_size;
65 extern int amdgpu_benchmarking;
66 extern int amdgpu_testing;
67 extern int amdgpu_audio;
68 extern int amdgpu_disp_priority;
69 extern int amdgpu_hw_i2c;
70 extern int amdgpu_pcie_gen2;
71 extern int amdgpu_msi;
72 extern int amdgpu_lockup_timeout;
73 extern int amdgpu_dpm;
74 extern int amdgpu_smc_load_fw;
75 extern int amdgpu_aspm;
76 extern int amdgpu_runtime_pm;
77 extern int amdgpu_hard_reset;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_enable_scheduler;
86 extern int amdgpu_sched_jobs;
87 extern int amdgpu_sched_hw_submission;
88 extern int amdgpu_enable_semaphores;
89 extern int amdgpu_powerplay;
90
91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95 #define AMDGPU_IB_POOL_SIZE 16
96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97 #define AMDGPUFB_CONN_LIMIT 4
98 #define AMDGPU_BIOS_NUM_SCRATCH 8
99
100 /* max number of rings */
101 #define AMDGPU_MAX_RINGS 16
102 #define AMDGPU_MAX_GFX_RINGS 1
103 #define AMDGPU_MAX_COMPUTE_RINGS 8
104 #define AMDGPU_MAX_VCE_RINGS 2
105
106 /* max number of IP instances */
107 #define AMDGPU_MAX_SDMA_INSTANCES 2
108
109 /* number of hw syncs before falling back on blocking */
110 #define AMDGPU_NUM_SYNCS 4
111
112 /* hardcode that limit for now */
113 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
114
115 /* hard reset data */
116 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
117
118 /* reset flags */
119 #define AMDGPU_RESET_GFX (1 << 0)
120 #define AMDGPU_RESET_COMPUTE (1 << 1)
121 #define AMDGPU_RESET_DMA (1 << 2)
122 #define AMDGPU_RESET_CP (1 << 3)
123 #define AMDGPU_RESET_GRBM (1 << 4)
124 #define AMDGPU_RESET_DMA1 (1 << 5)
125 #define AMDGPU_RESET_RLC (1 << 6)
126 #define AMDGPU_RESET_SEM (1 << 7)
127 #define AMDGPU_RESET_IH (1 << 8)
128 #define AMDGPU_RESET_VMC (1 << 9)
129 #define AMDGPU_RESET_MC (1 << 10)
130 #define AMDGPU_RESET_DISPLAY (1 << 11)
131 #define AMDGPU_RESET_UVD (1 << 12)
132 #define AMDGPU_RESET_VCE (1 << 13)
133 #define AMDGPU_RESET_VCE1 (1 << 14)
134
135 /* CG block flags */
136 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
137 #define AMDGPU_CG_BLOCK_MC (1 << 1)
138 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
139 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
140 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
141 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
142 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
143
144 /* CG flags */
145 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
146 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
147 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
148 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
149 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
150 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
151 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
152 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
153 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
154 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
155 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
156 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
157 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
158 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
159 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
160 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
161 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
162
163 /* PG flags */
164 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
165 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
166 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
167 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
168 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
169 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
170 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
171 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
173 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
174 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
175
176 /* GFX current status */
177 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
178 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
179 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
180 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
181 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
182
183 /* max cursor sizes (in pixels) */
184 #define CIK_CURSOR_WIDTH 128
185 #define CIK_CURSOR_HEIGHT 128
186
187 struct amdgpu_device;
188 struct amdgpu_fence;
189 struct amdgpu_ib;
190 struct amdgpu_vm;
191 struct amdgpu_ring;
192 struct amdgpu_semaphore;
193 struct amdgpu_cs_parser;
194 struct amdgpu_job;
195 struct amdgpu_irq_src;
196 struct amdgpu_fpriv;
197
198 enum amdgpu_cp_irq {
199 AMDGPU_CP_IRQ_GFX_EOP = 0,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
208
209 AMDGPU_CP_IRQ_LAST
210 };
211
212 enum amdgpu_sdma_irq {
213 AMDGPU_SDMA_IRQ_TRAP0 = 0,
214 AMDGPU_SDMA_IRQ_TRAP1,
215
216 AMDGPU_SDMA_IRQ_LAST
217 };
218
219 enum amdgpu_thermal_irq {
220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
222
223 AMDGPU_THERMAL_IRQ_LAST
224 };
225
226 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
227 enum amd_ip_block_type block_type,
228 enum amd_clockgating_state state);
229 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
230 enum amd_ip_block_type block_type,
231 enum amd_powergating_state state);
232
233 struct amdgpu_ip_block_version {
234 enum amd_ip_block_type type;
235 u32 major;
236 u32 minor;
237 u32 rev;
238 const struct amd_ip_funcs *funcs;
239 };
240
241 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
242 enum amd_ip_block_type type,
243 u32 major, u32 minor);
244
245 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
246 struct amdgpu_device *adev,
247 enum amd_ip_block_type type);
248
249 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
250 struct amdgpu_buffer_funcs {
251 /* maximum bytes in a single operation */
252 uint32_t copy_max_bytes;
253
254 /* number of dw to reserve per operation */
255 unsigned copy_num_dw;
256
257 /* used for buffer migration */
258 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
259 /* src addr in bytes */
260 uint64_t src_offset,
261 /* dst addr in bytes */
262 uint64_t dst_offset,
263 /* number of byte to transfer */
264 uint32_t byte_count);
265
266 /* maximum bytes in a single operation */
267 uint32_t fill_max_bytes;
268
269 /* number of dw to reserve per operation */
270 unsigned fill_num_dw;
271
272 /* used for buffer clearing */
273 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
274 /* value to write to memory */
275 uint32_t src_data,
276 /* dst addr in bytes */
277 uint64_t dst_offset,
278 /* number of byte to fill */
279 uint32_t byte_count);
280 };
281
282 /* provided by hw blocks that can write ptes, e.g., sdma */
283 struct amdgpu_vm_pte_funcs {
284 /* copy pte entries from GART */
285 void (*copy_pte)(struct amdgpu_ib *ib,
286 uint64_t pe, uint64_t src,
287 unsigned count);
288 /* write pte one entry at a time with addr mapping */
289 void (*write_pte)(struct amdgpu_ib *ib,
290 uint64_t pe,
291 uint64_t addr, unsigned count,
292 uint32_t incr, uint32_t flags);
293 /* for linear pte/pde updates without addr mapping */
294 void (*set_pte_pde)(struct amdgpu_ib *ib,
295 uint64_t pe,
296 uint64_t addr, unsigned count,
297 uint32_t incr, uint32_t flags);
298 /* pad the indirect buffer to the necessary number of dw */
299 void (*pad_ib)(struct amdgpu_ib *ib);
300 };
301
302 /* provided by the gmc block */
303 struct amdgpu_gart_funcs {
304 /* flush the vm tlb via mmio */
305 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
306 uint32_t vmid);
307 /* write pte/pde updates using the cpu */
308 int (*set_pte_pde)(struct amdgpu_device *adev,
309 void *cpu_pt_addr, /* cpu addr of page table */
310 uint32_t gpu_page_idx, /* pte/pde to update */
311 uint64_t addr, /* addr to write into pte/pde */
312 uint32_t flags); /* access flags */
313 };
314
315 /* provided by the ih block */
316 struct amdgpu_ih_funcs {
317 /* ring read/write ptr handling, called from interrupt context */
318 u32 (*get_wptr)(struct amdgpu_device *adev);
319 void (*decode_iv)(struct amdgpu_device *adev,
320 struct amdgpu_iv_entry *entry);
321 void (*set_rptr)(struct amdgpu_device *adev);
322 };
323
324 /* provided by hw blocks that expose a ring buffer for commands */
325 struct amdgpu_ring_funcs {
326 /* ring read/write ptr handling */
327 u32 (*get_rptr)(struct amdgpu_ring *ring);
328 u32 (*get_wptr)(struct amdgpu_ring *ring);
329 void (*set_wptr)(struct amdgpu_ring *ring);
330 /* validating and patching of IBs */
331 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
332 /* command emit functions */
333 void (*emit_ib)(struct amdgpu_ring *ring,
334 struct amdgpu_ib *ib);
335 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
336 uint64_t seq, unsigned flags);
337 bool (*emit_semaphore)(struct amdgpu_ring *ring,
338 struct amdgpu_semaphore *semaphore,
339 bool emit_wait);
340 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
341 uint64_t pd_addr);
342 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
343 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
344 uint32_t gds_base, uint32_t gds_size,
345 uint32_t gws_base, uint32_t gws_size,
346 uint32_t oa_base, uint32_t oa_size);
347 /* testing functions */
348 int (*test_ring)(struct amdgpu_ring *ring);
349 int (*test_ib)(struct amdgpu_ring *ring);
350 /* insert NOP packets */
351 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
352 };
353
354 /*
355 * BIOS.
356 */
357 bool amdgpu_get_bios(struct amdgpu_device *adev);
358 bool amdgpu_read_bios(struct amdgpu_device *adev);
359
360 /*
361 * Dummy page
362 */
363 struct amdgpu_dummy_page {
364 struct page *page;
365 dma_addr_t addr;
366 };
367 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
368 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
369
370
371 /*
372 * Clocks
373 */
374
375 #define AMDGPU_MAX_PPLL 3
376
377 struct amdgpu_clock {
378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
379 struct amdgpu_pll spll;
380 struct amdgpu_pll mpll;
381 /* 10 Khz units */
382 uint32_t default_mclk;
383 uint32_t default_sclk;
384 uint32_t default_dispclk;
385 uint32_t current_dispclk;
386 uint32_t dp_extclk;
387 uint32_t max_pixel_clock;
388 };
389
390 /*
391 * Fences.
392 */
393 struct amdgpu_fence_driver {
394 uint64_t gpu_addr;
395 volatile uint32_t *cpu_addr;
396 /* sync_seq is protected by ring emission lock */
397 uint64_t sync_seq[AMDGPU_MAX_RINGS];
398 atomic64_t last_seq;
399 bool initialized;
400 struct amdgpu_irq_src *irq_src;
401 unsigned irq_type;
402 struct timer_list fallback_timer;
403 wait_queue_head_t fence_queue;
404 };
405
406 /* some special values for the owner field */
407 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
408 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
409
410 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
411 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
412
413 struct amdgpu_fence {
414 struct fence base;
415
416 /* RB, DMA, etc. */
417 struct amdgpu_ring *ring;
418 uint64_t seq;
419
420 /* filp or special value for fence creator */
421 void *owner;
422
423 wait_queue_t fence_wake;
424 };
425
426 struct amdgpu_user_fence {
427 /* write-back bo */
428 struct amdgpu_bo *bo;
429 /* write-back address offset to bo start */
430 uint32_t offset;
431 };
432
433 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
434 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
435 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
436
437 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
438 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
439 struct amdgpu_irq_src *irq_src,
440 unsigned irq_type);
441 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
442 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
443 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
444 struct amdgpu_fence **fence);
445 void amdgpu_fence_process(struct amdgpu_ring *ring);
446 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
447 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
448 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
449
450 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
453 struct amdgpu_ring *ring);
454
455 /*
456 * TTM.
457 */
458 struct amdgpu_mman {
459 struct ttm_bo_global_ref bo_global_ref;
460 struct drm_global_reference mem_global_ref;
461 struct ttm_bo_device bdev;
462 bool mem_global_referenced;
463 bool initialized;
464
465 #if defined(CONFIG_DEBUG_FS)
466 struct dentry *vram;
467 struct dentry *gtt;
468 #endif
469
470 /* buffer handling */
471 const struct amdgpu_buffer_funcs *buffer_funcs;
472 struct amdgpu_ring *buffer_funcs_ring;
473 };
474
475 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
476 uint64_t src_offset,
477 uint64_t dst_offset,
478 uint32_t byte_count,
479 struct reservation_object *resv,
480 struct fence **fence);
481 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
482
483 struct amdgpu_bo_list_entry {
484 struct amdgpu_bo *robj;
485 struct ttm_validate_buffer tv;
486 struct amdgpu_bo_va *bo_va;
487 uint32_t priority;
488 };
489
490 struct amdgpu_bo_va_mapping {
491 struct list_head list;
492 struct interval_tree_node it;
493 uint64_t offset;
494 uint32_t flags;
495 };
496
497 /* bo virtual addresses in a specific vm */
498 struct amdgpu_bo_va {
499 struct mutex mutex;
500 /* protected by bo being reserved */
501 struct list_head bo_list;
502 struct fence *last_pt_update;
503 unsigned ref_count;
504
505 /* protected by vm mutex and spinlock */
506 struct list_head vm_status;
507
508 /* mappings for this bo_va */
509 struct list_head invalids;
510 struct list_head valids;
511
512 /* constant after initialization */
513 struct amdgpu_vm *vm;
514 struct amdgpu_bo *bo;
515 };
516
517 #define AMDGPU_GEM_DOMAIN_MAX 0x3
518
519 struct amdgpu_bo {
520 /* Protected by gem.mutex */
521 struct list_head list;
522 /* Protected by tbo.reserved */
523 u32 prefered_domains;
524 u32 allowed_domains;
525 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
526 struct ttm_placement placement;
527 struct ttm_buffer_object tbo;
528 struct ttm_bo_kmap_obj kmap;
529 u64 flags;
530 unsigned pin_count;
531 void *kptr;
532 u64 tiling_flags;
533 u64 metadata_flags;
534 void *metadata;
535 u32 metadata_size;
536 /* list of all virtual address to which this bo
537 * is associated to
538 */
539 struct list_head va;
540 /* Constant after initialization */
541 struct amdgpu_device *adev;
542 struct drm_gem_object gem_base;
543 struct amdgpu_bo *parent;
544
545 struct ttm_bo_kmap_obj dma_buf_vmap;
546 pid_t pid;
547 struct amdgpu_mn *mn;
548 struct list_head mn_list;
549 };
550 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
551
552 void amdgpu_gem_object_free(struct drm_gem_object *obj);
553 int amdgpu_gem_object_open(struct drm_gem_object *obj,
554 struct drm_file *file_priv);
555 void amdgpu_gem_object_close(struct drm_gem_object *obj,
556 struct drm_file *file_priv);
557 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
558 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
559 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
560 struct dma_buf_attachment *attach,
561 struct sg_table *sg);
562 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
563 struct drm_gem_object *gobj,
564 int flags);
565 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
566 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
567 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
568 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
569 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
570 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
571
572 /* sub-allocation manager, it has to be protected by another lock.
573 * By conception this is an helper for other part of the driver
574 * like the indirect buffer or semaphore, which both have their
575 * locking.
576 *
577 * Principe is simple, we keep a list of sub allocation in offset
578 * order (first entry has offset == 0, last entry has the highest
579 * offset).
580 *
581 * When allocating new object we first check if there is room at
582 * the end total_size - (last_object_offset + last_object_size) >=
583 * alloc_size. If so we allocate new object there.
584 *
585 * When there is not enough room at the end, we start waiting for
586 * each sub object until we reach object_offset+object_size >=
587 * alloc_size, this object then become the sub object we return.
588 *
589 * Alignment can't be bigger than page size.
590 *
591 * Hole are not considered for allocation to keep things simple.
592 * Assumption is that there won't be hole (all object on same
593 * alignment).
594 */
595 struct amdgpu_sa_manager {
596 wait_queue_head_t wq;
597 struct amdgpu_bo *bo;
598 struct list_head *hole;
599 struct list_head flist[AMDGPU_MAX_RINGS];
600 struct list_head olist;
601 unsigned size;
602 uint64_t gpu_addr;
603 void *cpu_ptr;
604 uint32_t domain;
605 uint32_t align;
606 };
607
608 struct amdgpu_sa_bo;
609
610 /* sub-allocation buffer */
611 struct amdgpu_sa_bo {
612 struct list_head olist;
613 struct list_head flist;
614 struct amdgpu_sa_manager *manager;
615 unsigned soffset;
616 unsigned eoffset;
617 struct fence *fence;
618 };
619
620 /*
621 * GEM objects.
622 */
623 struct amdgpu_gem {
624 struct mutex mutex;
625 struct list_head objects;
626 };
627
628 int amdgpu_gem_init(struct amdgpu_device *adev);
629 void amdgpu_gem_fini(struct amdgpu_device *adev);
630 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
631 int alignment, u32 initial_domain,
632 u64 flags, bool kernel,
633 struct drm_gem_object **obj);
634
635 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
636 struct drm_device *dev,
637 struct drm_mode_create_dumb *args);
638 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
639 struct drm_device *dev,
640 uint32_t handle, uint64_t *offset_p);
641
642 /*
643 * Semaphores.
644 */
645 struct amdgpu_semaphore {
646 struct amdgpu_sa_bo *sa_bo;
647 signed waiters;
648 uint64_t gpu_addr;
649 };
650
651 int amdgpu_semaphore_create(struct amdgpu_device *adev,
652 struct amdgpu_semaphore **semaphore);
653 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
654 struct amdgpu_semaphore *semaphore);
655 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
656 struct amdgpu_semaphore *semaphore);
657 void amdgpu_semaphore_free(struct amdgpu_device *adev,
658 struct amdgpu_semaphore **semaphore,
659 struct fence *fence);
660
661 /*
662 * Synchronization
663 */
664 struct amdgpu_sync {
665 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
666 struct fence *sync_to[AMDGPU_MAX_RINGS];
667 DECLARE_HASHTABLE(fences, 4);
668 struct fence *last_vm_update;
669 };
670
671 void amdgpu_sync_create(struct amdgpu_sync *sync);
672 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
673 struct fence *f);
674 int amdgpu_sync_resv(struct amdgpu_device *adev,
675 struct amdgpu_sync *sync,
676 struct reservation_object *resv,
677 void *owner);
678 int amdgpu_sync_rings(struct amdgpu_sync *sync,
679 struct amdgpu_ring *ring);
680 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
681 int amdgpu_sync_wait(struct amdgpu_sync *sync);
682 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
683 struct fence *fence);
684
685 /*
686 * GART structures, functions & helpers
687 */
688 struct amdgpu_mc;
689
690 #define AMDGPU_GPU_PAGE_SIZE 4096
691 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
692 #define AMDGPU_GPU_PAGE_SHIFT 12
693 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
694
695 struct amdgpu_gart {
696 dma_addr_t table_addr;
697 struct amdgpu_bo *robj;
698 void *ptr;
699 unsigned num_gpu_pages;
700 unsigned num_cpu_pages;
701 unsigned table_size;
702 struct page **pages;
703 dma_addr_t *pages_addr;
704 bool ready;
705 const struct amdgpu_gart_funcs *gart_funcs;
706 };
707
708 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
709 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
710 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
711 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
712 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
713 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
714 int amdgpu_gart_init(struct amdgpu_device *adev);
715 void amdgpu_gart_fini(struct amdgpu_device *adev);
716 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
717 int pages);
718 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
719 int pages, struct page **pagelist,
720 dma_addr_t *dma_addr, uint32_t flags);
721
722 /*
723 * GPU MC structures, functions & helpers
724 */
725 struct amdgpu_mc {
726 resource_size_t aper_size;
727 resource_size_t aper_base;
728 resource_size_t agp_base;
729 /* for some chips with <= 32MB we need to lie
730 * about vram size near mc fb location */
731 u64 mc_vram_size;
732 u64 visible_vram_size;
733 u64 gtt_size;
734 u64 gtt_start;
735 u64 gtt_end;
736 u64 vram_start;
737 u64 vram_end;
738 unsigned vram_width;
739 u64 real_vram_size;
740 int vram_mtrr;
741 u64 gtt_base_align;
742 u64 mc_mask;
743 const struct firmware *fw; /* MC firmware */
744 uint32_t fw_version;
745 struct amdgpu_irq_src vm_fault;
746 uint32_t vram_type;
747 };
748
749 /*
750 * GPU doorbell structures, functions & helpers
751 */
752 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
753 {
754 AMDGPU_DOORBELL_KIQ = 0x000,
755 AMDGPU_DOORBELL_HIQ = 0x001,
756 AMDGPU_DOORBELL_DIQ = 0x002,
757 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
758 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
759 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
760 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
761 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
762 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
763 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
764 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
765 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
766 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
767 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
768 AMDGPU_DOORBELL_IH = 0x1E8,
769 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
770 AMDGPU_DOORBELL_INVALID = 0xFFFF
771 } AMDGPU_DOORBELL_ASSIGNMENT;
772
773 struct amdgpu_doorbell {
774 /* doorbell mmio */
775 resource_size_t base;
776 resource_size_t size;
777 u32 __iomem *ptr;
778 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
779 };
780
781 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
782 phys_addr_t *aperture_base,
783 size_t *aperture_size,
784 size_t *start_offset);
785
786 /*
787 * IRQS.
788 */
789
790 struct amdgpu_flip_work {
791 struct work_struct flip_work;
792 struct work_struct unpin_work;
793 struct amdgpu_device *adev;
794 int crtc_id;
795 uint64_t base;
796 struct drm_pending_vblank_event *event;
797 struct amdgpu_bo *old_rbo;
798 struct fence *excl;
799 unsigned shared_count;
800 struct fence **shared;
801 };
802
803
804 /*
805 * CP & rings.
806 */
807
808 struct amdgpu_ib {
809 struct amdgpu_sa_bo *sa_bo;
810 uint32_t length_dw;
811 uint64_t gpu_addr;
812 uint32_t *ptr;
813 struct amdgpu_ring *ring;
814 struct amdgpu_fence *fence;
815 struct amdgpu_user_fence *user;
816 struct amdgpu_vm *vm;
817 struct amdgpu_ctx *ctx;
818 struct amdgpu_sync sync;
819 uint32_t gds_base, gds_size;
820 uint32_t gws_base, gws_size;
821 uint32_t oa_base, oa_size;
822 uint32_t flags;
823 /* resulting sequence number */
824 uint64_t sequence;
825 };
826
827 enum amdgpu_ring_type {
828 AMDGPU_RING_TYPE_GFX,
829 AMDGPU_RING_TYPE_COMPUTE,
830 AMDGPU_RING_TYPE_SDMA,
831 AMDGPU_RING_TYPE_UVD,
832 AMDGPU_RING_TYPE_VCE
833 };
834
835 extern struct amd_sched_backend_ops amdgpu_sched_ops;
836
837 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
838 struct amdgpu_ring *ring,
839 struct amdgpu_ib *ibs,
840 unsigned num_ibs,
841 int (*free_job)(struct amdgpu_job *),
842 void *owner,
843 struct fence **fence);
844
845 struct amdgpu_ring {
846 struct amdgpu_device *adev;
847 const struct amdgpu_ring_funcs *funcs;
848 struct amdgpu_fence_driver fence_drv;
849 struct amd_gpu_scheduler sched;
850
851 spinlock_t fence_lock;
852 struct mutex *ring_lock;
853 struct amdgpu_bo *ring_obj;
854 volatile uint32_t *ring;
855 unsigned rptr_offs;
856 u64 next_rptr_gpu_addr;
857 volatile u32 *next_rptr_cpu_addr;
858 unsigned wptr;
859 unsigned wptr_old;
860 unsigned ring_size;
861 unsigned ring_free_dw;
862 int count_dw;
863 uint64_t gpu_addr;
864 uint32_t align_mask;
865 uint32_t ptr_mask;
866 bool ready;
867 u32 nop;
868 u32 idx;
869 u64 last_semaphore_signal_addr;
870 u64 last_semaphore_wait_addr;
871 u32 me;
872 u32 pipe;
873 u32 queue;
874 struct amdgpu_bo *mqd_obj;
875 u32 doorbell_index;
876 bool use_doorbell;
877 unsigned wptr_offs;
878 unsigned next_rptr_offs;
879 unsigned fence_offs;
880 struct amdgpu_ctx *current_ctx;
881 enum amdgpu_ring_type type;
882 char name[16];
883 bool is_pte_ring;
884 };
885
886 /*
887 * VM
888 */
889
890 /* maximum number of VMIDs */
891 #define AMDGPU_NUM_VM 16
892
893 /* number of entries in page table */
894 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
895
896 /* PTBs (Page Table Blocks) need to be aligned to 32K */
897 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
898 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
899 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
900
901 #define AMDGPU_PTE_VALID (1 << 0)
902 #define AMDGPU_PTE_SYSTEM (1 << 1)
903 #define AMDGPU_PTE_SNOOPED (1 << 2)
904
905 /* VI only */
906 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
907
908 #define AMDGPU_PTE_READABLE (1 << 5)
909 #define AMDGPU_PTE_WRITEABLE (1 << 6)
910
911 /* PTE (Page Table Entry) fragment field for different page sizes */
912 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
913 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
914 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
915
916 /* How to programm VM fault handling */
917 #define AMDGPU_VM_FAULT_STOP_NEVER 0
918 #define AMDGPU_VM_FAULT_STOP_FIRST 1
919 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
920
921 struct amdgpu_vm_pt {
922 struct amdgpu_bo_list_entry entry;
923 uint64_t addr;
924 };
925
926 struct amdgpu_vm_id {
927 unsigned id;
928 uint64_t pd_gpu_addr;
929 /* last flushed PD/PT update */
930 struct fence *flushed_updates;
931 };
932
933 struct amdgpu_vm {
934 /* tree of virtual addresses mapped */
935 spinlock_t it_lock;
936 struct rb_root va;
937
938 /* protecting invalidated */
939 spinlock_t status_lock;
940
941 /* BOs moved, but not yet updated in the PT */
942 struct list_head invalidated;
943
944 /* BOs cleared in the PT because of a move */
945 struct list_head cleared;
946
947 /* BO mappings freed, but not yet updated in the PT */
948 struct list_head freed;
949
950 /* contains the page directory */
951 struct amdgpu_bo *page_directory;
952 unsigned max_pde_used;
953 struct fence *page_directory_fence;
954
955 /* array of page tables, one for each page directory entry */
956 struct amdgpu_vm_pt *page_tables;
957
958 /* for id and flush management per ring */
959 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
960
961 /* protecting freed */
962 spinlock_t freed_lock;
963 };
964
965 struct amdgpu_vm_manager {
966 struct {
967 struct fence *active;
968 atomic_long_t owner;
969 } ids[AMDGPU_NUM_VM];
970
971 uint32_t max_pfn;
972 /* number of VMIDs */
973 unsigned nvm;
974 /* vram base address for page table entry */
975 u64 vram_base_offset;
976 /* is vm enabled? */
977 bool enabled;
978 /* vm pte handling */
979 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
980 struct amdgpu_ring *vm_pte_funcs_ring;
981 };
982
983 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
984 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
985 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
986 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
987 struct list_head *validated,
988 struct amdgpu_bo_list_entry *entry);
989 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
990 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
991 struct amdgpu_vm *vm);
992 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
993 struct amdgpu_sync *sync);
994 void amdgpu_vm_flush(struct amdgpu_ring *ring,
995 struct amdgpu_vm *vm,
996 struct fence *updates);
997 void amdgpu_vm_fence(struct amdgpu_device *adev,
998 struct amdgpu_vm *vm,
999 struct fence *fence);
1000 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
1001 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
1002 struct amdgpu_vm *vm);
1003 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1004 struct amdgpu_vm *vm);
1005 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1006 struct amdgpu_sync *sync);
1007 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1008 struct amdgpu_bo_va *bo_va,
1009 struct ttm_mem_reg *mem);
1010 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1011 struct amdgpu_bo *bo);
1012 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1013 struct amdgpu_bo *bo);
1014 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1015 struct amdgpu_vm *vm,
1016 struct amdgpu_bo *bo);
1017 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1018 struct amdgpu_bo_va *bo_va,
1019 uint64_t addr, uint64_t offset,
1020 uint64_t size, uint32_t flags);
1021 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1022 struct amdgpu_bo_va *bo_va,
1023 uint64_t addr);
1024 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1025 struct amdgpu_bo_va *bo_va);
1026 int amdgpu_vm_free_job(struct amdgpu_job *job);
1027
1028 /*
1029 * context related structures
1030 */
1031
1032 struct amdgpu_ctx_ring {
1033 uint64_t sequence;
1034 struct fence **fences;
1035 struct amd_sched_entity entity;
1036 };
1037
1038 struct amdgpu_ctx {
1039 struct kref refcount;
1040 struct amdgpu_device *adev;
1041 unsigned reset_counter;
1042 spinlock_t ring_lock;
1043 struct fence **fences;
1044 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1045 };
1046
1047 struct amdgpu_ctx_mgr {
1048 struct amdgpu_device *adev;
1049 struct mutex lock;
1050 /* protected by lock */
1051 struct idr ctx_handles;
1052 };
1053
1054 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
1055 struct amdgpu_ctx *ctx);
1056 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1057
1058 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1059 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1060
1061 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1062 struct fence *fence);
1063 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1064 struct amdgpu_ring *ring, uint64_t seq);
1065
1066 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *filp);
1068
1069 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1070 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1071
1072 /*
1073 * file private structure
1074 */
1075
1076 struct amdgpu_fpriv {
1077 struct amdgpu_vm vm;
1078 struct mutex bo_list_lock;
1079 struct idr bo_list_handles;
1080 struct amdgpu_ctx_mgr ctx_mgr;
1081 };
1082
1083 /*
1084 * residency list
1085 */
1086
1087 struct amdgpu_bo_list {
1088 struct mutex lock;
1089 struct amdgpu_bo *gds_obj;
1090 struct amdgpu_bo *gws_obj;
1091 struct amdgpu_bo *oa_obj;
1092 bool has_userptr;
1093 unsigned num_entries;
1094 struct amdgpu_bo_list_entry *array;
1095 };
1096
1097 struct amdgpu_bo_list *
1098 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1099 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1100 struct list_head *validated);
1101 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1102 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1103
1104 /*
1105 * GFX stuff
1106 */
1107 #include "clearstate_defs.h"
1108
1109 struct amdgpu_rlc {
1110 /* for power gating */
1111 struct amdgpu_bo *save_restore_obj;
1112 uint64_t save_restore_gpu_addr;
1113 volatile uint32_t *sr_ptr;
1114 const u32 *reg_list;
1115 u32 reg_list_size;
1116 /* for clear state */
1117 struct amdgpu_bo *clear_state_obj;
1118 uint64_t clear_state_gpu_addr;
1119 volatile uint32_t *cs_ptr;
1120 const struct cs_section_def *cs_data;
1121 u32 clear_state_size;
1122 /* for cp tables */
1123 struct amdgpu_bo *cp_table_obj;
1124 uint64_t cp_table_gpu_addr;
1125 volatile uint32_t *cp_table_ptr;
1126 u32 cp_table_size;
1127 };
1128
1129 struct amdgpu_mec {
1130 struct amdgpu_bo *hpd_eop_obj;
1131 u64 hpd_eop_gpu_addr;
1132 u32 num_pipe;
1133 u32 num_mec;
1134 u32 num_queue;
1135 };
1136
1137 /*
1138 * GPU scratch registers structures, functions & helpers
1139 */
1140 struct amdgpu_scratch {
1141 unsigned num_reg;
1142 uint32_t reg_base;
1143 bool free[32];
1144 uint32_t reg[32];
1145 };
1146
1147 /*
1148 * GFX configurations
1149 */
1150 struct amdgpu_gca_config {
1151 unsigned max_shader_engines;
1152 unsigned max_tile_pipes;
1153 unsigned max_cu_per_sh;
1154 unsigned max_sh_per_se;
1155 unsigned max_backends_per_se;
1156 unsigned max_texture_channel_caches;
1157 unsigned max_gprs;
1158 unsigned max_gs_threads;
1159 unsigned max_hw_contexts;
1160 unsigned sc_prim_fifo_size_frontend;
1161 unsigned sc_prim_fifo_size_backend;
1162 unsigned sc_hiz_tile_fifo_size;
1163 unsigned sc_earlyz_tile_fifo_size;
1164
1165 unsigned num_tile_pipes;
1166 unsigned backend_enable_mask;
1167 unsigned mem_max_burst_length_bytes;
1168 unsigned mem_row_size_in_kb;
1169 unsigned shader_engine_tile_size;
1170 unsigned num_gpus;
1171 unsigned multi_gpu_tile_size;
1172 unsigned mc_arb_ramcfg;
1173 unsigned gb_addr_config;
1174
1175 uint32_t tile_mode_array[32];
1176 uint32_t macrotile_mode_array[16];
1177 };
1178
1179 struct amdgpu_gfx {
1180 struct mutex gpu_clock_mutex;
1181 struct amdgpu_gca_config config;
1182 struct amdgpu_rlc rlc;
1183 struct amdgpu_mec mec;
1184 struct amdgpu_scratch scratch;
1185 const struct firmware *me_fw; /* ME firmware */
1186 uint32_t me_fw_version;
1187 const struct firmware *pfp_fw; /* PFP firmware */
1188 uint32_t pfp_fw_version;
1189 const struct firmware *ce_fw; /* CE firmware */
1190 uint32_t ce_fw_version;
1191 const struct firmware *rlc_fw; /* RLC firmware */
1192 uint32_t rlc_fw_version;
1193 const struct firmware *mec_fw; /* MEC firmware */
1194 uint32_t mec_fw_version;
1195 const struct firmware *mec2_fw; /* MEC2 firmware */
1196 uint32_t mec2_fw_version;
1197 uint32_t me_feature_version;
1198 uint32_t ce_feature_version;
1199 uint32_t pfp_feature_version;
1200 uint32_t rlc_feature_version;
1201 uint32_t mec_feature_version;
1202 uint32_t mec2_feature_version;
1203 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1204 unsigned num_gfx_rings;
1205 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1206 unsigned num_compute_rings;
1207 struct amdgpu_irq_src eop_irq;
1208 struct amdgpu_irq_src priv_reg_irq;
1209 struct amdgpu_irq_src priv_inst_irq;
1210 /* gfx status */
1211 uint32_t gfx_current_status;
1212 /* ce ram size*/
1213 unsigned ce_ram_size;
1214 };
1215
1216 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1217 unsigned size, struct amdgpu_ib *ib);
1218 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1219 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1220 struct amdgpu_ib *ib, void *owner);
1221 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1222 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1223 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1224 /* Ring access between begin & end cannot sleep */
1225 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1226 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1227 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1228 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1229 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1230 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1231 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1232 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1233 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1234 uint32_t **data);
1235 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1236 unsigned size, uint32_t *data);
1237 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1238 unsigned ring_size, u32 nop, u32 align_mask,
1239 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1240 enum amdgpu_ring_type ring_type);
1241 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1242 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1243
1244 /*
1245 * CS.
1246 */
1247 struct amdgpu_cs_chunk {
1248 uint32_t chunk_id;
1249 uint32_t length_dw;
1250 uint32_t *kdata;
1251 };
1252
1253 struct amdgpu_cs_parser {
1254 struct amdgpu_device *adev;
1255 struct drm_file *filp;
1256 struct amdgpu_ctx *ctx;
1257
1258 /* chunks */
1259 unsigned nchunks;
1260 struct amdgpu_cs_chunk *chunks;
1261
1262 /* indirect buffers */
1263 uint32_t num_ibs;
1264 struct amdgpu_ib *ibs;
1265
1266 /* buffer objects */
1267 struct ww_acquire_ctx ticket;
1268 struct amdgpu_bo_list *bo_list;
1269 struct amdgpu_bo_list_entry vm_pd;
1270 struct list_head validated;
1271 struct fence *fence;
1272 uint64_t bytes_moved_threshold;
1273 uint64_t bytes_moved;
1274
1275 /* user fence */
1276 struct amdgpu_user_fence uf;
1277 struct amdgpu_bo_list_entry uf_entry;
1278 };
1279
1280 struct amdgpu_job {
1281 struct amd_sched_job base;
1282 struct amdgpu_device *adev;
1283 struct amdgpu_ib *ibs;
1284 uint32_t num_ibs;
1285 void *owner;
1286 struct amdgpu_user_fence uf;
1287 int (*free_job)(struct amdgpu_job *job);
1288 };
1289 #define to_amdgpu_job(sched_job) \
1290 container_of((sched_job), struct amdgpu_job, base)
1291
1292 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1293 {
1294 return p->ibs[ib_idx].ptr[idx];
1295 }
1296
1297 /*
1298 * Writeback
1299 */
1300 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1301
1302 struct amdgpu_wb {
1303 struct amdgpu_bo *wb_obj;
1304 volatile uint32_t *wb;
1305 uint64_t gpu_addr;
1306 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1307 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1308 };
1309
1310 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1311 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1312
1313
1314
1315 enum amdgpu_int_thermal_type {
1316 THERMAL_TYPE_NONE,
1317 THERMAL_TYPE_EXTERNAL,
1318 THERMAL_TYPE_EXTERNAL_GPIO,
1319 THERMAL_TYPE_RV6XX,
1320 THERMAL_TYPE_RV770,
1321 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1322 THERMAL_TYPE_EVERGREEN,
1323 THERMAL_TYPE_SUMO,
1324 THERMAL_TYPE_NI,
1325 THERMAL_TYPE_SI,
1326 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1327 THERMAL_TYPE_CI,
1328 THERMAL_TYPE_KV,
1329 };
1330
1331 enum amdgpu_dpm_auto_throttle_src {
1332 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1333 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1334 };
1335
1336 enum amdgpu_dpm_event_src {
1337 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1338 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1339 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1340 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1341 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1342 };
1343
1344 #define AMDGPU_MAX_VCE_LEVELS 6
1345
1346 enum amdgpu_vce_level {
1347 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1348 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1349 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1350 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1351 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1352 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1353 };
1354
1355 struct amdgpu_ps {
1356 u32 caps; /* vbios flags */
1357 u32 class; /* vbios flags */
1358 u32 class2; /* vbios flags */
1359 /* UVD clocks */
1360 u32 vclk;
1361 u32 dclk;
1362 /* VCE clocks */
1363 u32 evclk;
1364 u32 ecclk;
1365 bool vce_active;
1366 enum amdgpu_vce_level vce_level;
1367 /* asic priv */
1368 void *ps_priv;
1369 };
1370
1371 struct amdgpu_dpm_thermal {
1372 /* thermal interrupt work */
1373 struct work_struct work;
1374 /* low temperature threshold */
1375 int min_temp;
1376 /* high temperature threshold */
1377 int max_temp;
1378 /* was last interrupt low to high or high to low */
1379 bool high_to_low;
1380 /* interrupt source */
1381 struct amdgpu_irq_src irq;
1382 };
1383
1384 enum amdgpu_clk_action
1385 {
1386 AMDGPU_SCLK_UP = 1,
1387 AMDGPU_SCLK_DOWN
1388 };
1389
1390 struct amdgpu_blacklist_clocks
1391 {
1392 u32 sclk;
1393 u32 mclk;
1394 enum amdgpu_clk_action action;
1395 };
1396
1397 struct amdgpu_clock_and_voltage_limits {
1398 u32 sclk;
1399 u32 mclk;
1400 u16 vddc;
1401 u16 vddci;
1402 };
1403
1404 struct amdgpu_clock_array {
1405 u32 count;
1406 u32 *values;
1407 };
1408
1409 struct amdgpu_clock_voltage_dependency_entry {
1410 u32 clk;
1411 u16 v;
1412 };
1413
1414 struct amdgpu_clock_voltage_dependency_table {
1415 u32 count;
1416 struct amdgpu_clock_voltage_dependency_entry *entries;
1417 };
1418
1419 union amdgpu_cac_leakage_entry {
1420 struct {
1421 u16 vddc;
1422 u32 leakage;
1423 };
1424 struct {
1425 u16 vddc1;
1426 u16 vddc2;
1427 u16 vddc3;
1428 };
1429 };
1430
1431 struct amdgpu_cac_leakage_table {
1432 u32 count;
1433 union amdgpu_cac_leakage_entry *entries;
1434 };
1435
1436 struct amdgpu_phase_shedding_limits_entry {
1437 u16 voltage;
1438 u32 sclk;
1439 u32 mclk;
1440 };
1441
1442 struct amdgpu_phase_shedding_limits_table {
1443 u32 count;
1444 struct amdgpu_phase_shedding_limits_entry *entries;
1445 };
1446
1447 struct amdgpu_uvd_clock_voltage_dependency_entry {
1448 u32 vclk;
1449 u32 dclk;
1450 u16 v;
1451 };
1452
1453 struct amdgpu_uvd_clock_voltage_dependency_table {
1454 u8 count;
1455 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1456 };
1457
1458 struct amdgpu_vce_clock_voltage_dependency_entry {
1459 u32 ecclk;
1460 u32 evclk;
1461 u16 v;
1462 };
1463
1464 struct amdgpu_vce_clock_voltage_dependency_table {
1465 u8 count;
1466 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1467 };
1468
1469 struct amdgpu_ppm_table {
1470 u8 ppm_design;
1471 u16 cpu_core_number;
1472 u32 platform_tdp;
1473 u32 small_ac_platform_tdp;
1474 u32 platform_tdc;
1475 u32 small_ac_platform_tdc;
1476 u32 apu_tdp;
1477 u32 dgpu_tdp;
1478 u32 dgpu_ulv_power;
1479 u32 tj_max;
1480 };
1481
1482 struct amdgpu_cac_tdp_table {
1483 u16 tdp;
1484 u16 configurable_tdp;
1485 u16 tdc;
1486 u16 battery_power_limit;
1487 u16 small_power_limit;
1488 u16 low_cac_leakage;
1489 u16 high_cac_leakage;
1490 u16 maximum_power_delivery_limit;
1491 };
1492
1493 struct amdgpu_dpm_dynamic_state {
1494 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1495 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1496 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1497 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1498 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1499 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1500 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1501 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1502 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1503 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1504 struct amdgpu_clock_array valid_sclk_values;
1505 struct amdgpu_clock_array valid_mclk_values;
1506 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1507 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1508 u32 mclk_sclk_ratio;
1509 u32 sclk_mclk_delta;
1510 u16 vddc_vddci_delta;
1511 u16 min_vddc_for_pcie_gen2;
1512 struct amdgpu_cac_leakage_table cac_leakage_table;
1513 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1514 struct amdgpu_ppm_table *ppm_table;
1515 struct amdgpu_cac_tdp_table *cac_tdp_table;
1516 };
1517
1518 struct amdgpu_dpm_fan {
1519 u16 t_min;
1520 u16 t_med;
1521 u16 t_high;
1522 u16 pwm_min;
1523 u16 pwm_med;
1524 u16 pwm_high;
1525 u8 t_hyst;
1526 u32 cycle_delay;
1527 u16 t_max;
1528 u8 control_mode;
1529 u16 default_max_fan_pwm;
1530 u16 default_fan_output_sensitivity;
1531 u16 fan_output_sensitivity;
1532 bool ucode_fan_control;
1533 };
1534
1535 enum amdgpu_pcie_gen {
1536 AMDGPU_PCIE_GEN1 = 0,
1537 AMDGPU_PCIE_GEN2 = 1,
1538 AMDGPU_PCIE_GEN3 = 2,
1539 AMDGPU_PCIE_GEN_INVALID = 0xffff
1540 };
1541
1542 enum amdgpu_dpm_forced_level {
1543 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1544 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1545 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1546 };
1547
1548 struct amdgpu_vce_state {
1549 /* vce clocks */
1550 u32 evclk;
1551 u32 ecclk;
1552 /* gpu clocks */
1553 u32 sclk;
1554 u32 mclk;
1555 u8 clk_idx;
1556 u8 pstate;
1557 };
1558
1559 struct amdgpu_dpm_funcs {
1560 int (*get_temperature)(struct amdgpu_device *adev);
1561 int (*pre_set_power_state)(struct amdgpu_device *adev);
1562 int (*set_power_state)(struct amdgpu_device *adev);
1563 void (*post_set_power_state)(struct amdgpu_device *adev);
1564 void (*display_configuration_changed)(struct amdgpu_device *adev);
1565 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1566 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1567 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1568 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1569 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1570 bool (*vblank_too_short)(struct amdgpu_device *adev);
1571 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1572 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1573 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1574 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1575 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1576 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1577 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1578 };
1579
1580 struct amdgpu_dpm {
1581 struct amdgpu_ps *ps;
1582 /* number of valid power states */
1583 int num_ps;
1584 /* current power state that is active */
1585 struct amdgpu_ps *current_ps;
1586 /* requested power state */
1587 struct amdgpu_ps *requested_ps;
1588 /* boot up power state */
1589 struct amdgpu_ps *boot_ps;
1590 /* default uvd power state */
1591 struct amdgpu_ps *uvd_ps;
1592 /* vce requirements */
1593 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1594 enum amdgpu_vce_level vce_level;
1595 enum amd_pm_state_type state;
1596 enum amd_pm_state_type user_state;
1597 u32 platform_caps;
1598 u32 voltage_response_time;
1599 u32 backbias_response_time;
1600 void *priv;
1601 u32 new_active_crtcs;
1602 int new_active_crtc_count;
1603 u32 current_active_crtcs;
1604 int current_active_crtc_count;
1605 struct amdgpu_dpm_dynamic_state dyn_state;
1606 struct amdgpu_dpm_fan fan;
1607 u32 tdp_limit;
1608 u32 near_tdp_limit;
1609 u32 near_tdp_limit_adjusted;
1610 u32 sq_ramping_threshold;
1611 u32 cac_leakage;
1612 u16 tdp_od_limit;
1613 u32 tdp_adjustment;
1614 u16 load_line_slope;
1615 bool power_control;
1616 bool ac_power;
1617 /* special states active */
1618 bool thermal_active;
1619 bool uvd_active;
1620 bool vce_active;
1621 /* thermal handling */
1622 struct amdgpu_dpm_thermal thermal;
1623 /* forced levels */
1624 enum amdgpu_dpm_forced_level forced_level;
1625 };
1626
1627 struct amdgpu_pm {
1628 struct mutex mutex;
1629 u32 current_sclk;
1630 u32 current_mclk;
1631 u32 default_sclk;
1632 u32 default_mclk;
1633 struct amdgpu_i2c_chan *i2c_bus;
1634 /* internal thermal controller on rv6xx+ */
1635 enum amdgpu_int_thermal_type int_thermal_type;
1636 struct device *int_hwmon_dev;
1637 /* fan control parameters */
1638 bool no_fan;
1639 u8 fan_pulses_per_revolution;
1640 u8 fan_min_rpm;
1641 u8 fan_max_rpm;
1642 /* dpm */
1643 bool dpm_enabled;
1644 bool sysfs_initialized;
1645 struct amdgpu_dpm dpm;
1646 const struct firmware *fw; /* SMC firmware */
1647 uint32_t fw_version;
1648 const struct amdgpu_dpm_funcs *funcs;
1649 uint32_t pcie_gen_mask;
1650 uint32_t pcie_mlw_mask;
1651 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1652 };
1653
1654 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1655
1656 /*
1657 * UVD
1658 */
1659 #define AMDGPU_MAX_UVD_HANDLES 10
1660 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1661 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1662 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1663
1664 struct amdgpu_uvd {
1665 struct amdgpu_bo *vcpu_bo;
1666 void *cpu_addr;
1667 uint64_t gpu_addr;
1668 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1669 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1670 struct delayed_work idle_work;
1671 const struct firmware *fw; /* UVD firmware */
1672 struct amdgpu_ring ring;
1673 struct amdgpu_irq_src irq;
1674 bool address_64_bit;
1675 };
1676
1677 /*
1678 * VCE
1679 */
1680 #define AMDGPU_MAX_VCE_HANDLES 16
1681 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1682
1683 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1684 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1685
1686 struct amdgpu_vce {
1687 struct amdgpu_bo *vcpu_bo;
1688 uint64_t gpu_addr;
1689 unsigned fw_version;
1690 unsigned fb_version;
1691 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1692 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1693 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1694 struct delayed_work idle_work;
1695 const struct firmware *fw; /* VCE firmware */
1696 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1697 struct amdgpu_irq_src irq;
1698 unsigned harvest_config;
1699 };
1700
1701 /*
1702 * SDMA
1703 */
1704 struct amdgpu_sdma_instance {
1705 /* SDMA firmware */
1706 const struct firmware *fw;
1707 uint32_t fw_version;
1708 uint32_t feature_version;
1709
1710 struct amdgpu_ring ring;
1711 bool burst_nop;
1712 };
1713
1714 struct amdgpu_sdma {
1715 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1716 struct amdgpu_irq_src trap_irq;
1717 struct amdgpu_irq_src illegal_inst_irq;
1718 int num_instances;
1719 };
1720
1721 /*
1722 * Firmware
1723 */
1724 struct amdgpu_firmware {
1725 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1726 bool smu_load;
1727 struct amdgpu_bo *fw_buf;
1728 unsigned int fw_size;
1729 };
1730
1731 /*
1732 * Benchmarking
1733 */
1734 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1735
1736
1737 /*
1738 * Testing
1739 */
1740 void amdgpu_test_moves(struct amdgpu_device *adev);
1741 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1742 struct amdgpu_ring *cpA,
1743 struct amdgpu_ring *cpB);
1744 void amdgpu_test_syncing(struct amdgpu_device *adev);
1745
1746 /*
1747 * MMU Notifier
1748 */
1749 #if defined(CONFIG_MMU_NOTIFIER)
1750 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1751 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1752 #else
1753 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1754 {
1755 return -ENODEV;
1756 }
1757 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1758 #endif
1759
1760 /*
1761 * Debugfs
1762 */
1763 struct amdgpu_debugfs {
1764 struct drm_info_list *files;
1765 unsigned num_files;
1766 };
1767
1768 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1769 struct drm_info_list *files,
1770 unsigned nfiles);
1771 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1772
1773 #if defined(CONFIG_DEBUG_FS)
1774 int amdgpu_debugfs_init(struct drm_minor *minor);
1775 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1776 #endif
1777
1778 /*
1779 * amdgpu smumgr functions
1780 */
1781 struct amdgpu_smumgr_funcs {
1782 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1783 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1784 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1785 };
1786
1787 /*
1788 * amdgpu smumgr
1789 */
1790 struct amdgpu_smumgr {
1791 struct amdgpu_bo *toc_buf;
1792 struct amdgpu_bo *smu_buf;
1793 /* asic priv smu data */
1794 void *priv;
1795 spinlock_t smu_lock;
1796 /* smumgr functions */
1797 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1798 /* ucode loading complete flag */
1799 uint32_t fw_flags;
1800 };
1801
1802 /*
1803 * ASIC specific register table accessible by UMD
1804 */
1805 struct amdgpu_allowed_register_entry {
1806 uint32_t reg_offset;
1807 bool untouched;
1808 bool grbm_indexed;
1809 };
1810
1811 struct amdgpu_cu_info {
1812 uint32_t number; /* total active CU number */
1813 uint32_t ao_cu_mask;
1814 uint32_t bitmap[4][4];
1815 };
1816
1817
1818 /*
1819 * ASIC specific functions.
1820 */
1821 struct amdgpu_asic_funcs {
1822 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1823 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1824 u8 *bios, u32 length_bytes);
1825 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1826 u32 sh_num, u32 reg_offset, u32 *value);
1827 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1828 int (*reset)(struct amdgpu_device *adev);
1829 /* wait for mc_idle */
1830 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1831 /* get the reference clock */
1832 u32 (*get_xclk)(struct amdgpu_device *adev);
1833 /* get the gpu clock counter */
1834 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1835 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1836 /* MM block clocks */
1837 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1838 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1839 };
1840
1841 /*
1842 * IOCTL.
1843 */
1844 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1847 struct drm_file *filp);
1848
1849 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1852 struct drm_file *filp);
1853 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1854 struct drm_file *filp);
1855 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1858 struct drm_file *filp);
1859 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1860 struct drm_file *filp);
1861 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1862 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1863
1864 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1865 struct drm_file *filp);
1866
1867 /* VRAM scratch page for HDP bug, default vram page */
1868 struct amdgpu_vram_scratch {
1869 struct amdgpu_bo *robj;
1870 volatile uint32_t *ptr;
1871 u64 gpu_addr;
1872 };
1873
1874 /*
1875 * ACPI
1876 */
1877 struct amdgpu_atif_notification_cfg {
1878 bool enabled;
1879 int command_code;
1880 };
1881
1882 struct amdgpu_atif_notifications {
1883 bool display_switch;
1884 bool expansion_mode_change;
1885 bool thermal_state;
1886 bool forced_power_state;
1887 bool system_power_state;
1888 bool display_conf_change;
1889 bool px_gfx_switch;
1890 bool brightness_change;
1891 bool dgpu_display_event;
1892 };
1893
1894 struct amdgpu_atif_functions {
1895 bool system_params;
1896 bool sbios_requests;
1897 bool select_active_disp;
1898 bool lid_state;
1899 bool get_tv_standard;
1900 bool set_tv_standard;
1901 bool get_panel_expansion_mode;
1902 bool set_panel_expansion_mode;
1903 bool temperature_change;
1904 bool graphics_device_types;
1905 };
1906
1907 struct amdgpu_atif {
1908 struct amdgpu_atif_notifications notifications;
1909 struct amdgpu_atif_functions functions;
1910 struct amdgpu_atif_notification_cfg notification_cfg;
1911 struct amdgpu_encoder *encoder_for_bl;
1912 };
1913
1914 struct amdgpu_atcs_functions {
1915 bool get_ext_state;
1916 bool pcie_perf_req;
1917 bool pcie_dev_rdy;
1918 bool pcie_bus_width;
1919 };
1920
1921 struct amdgpu_atcs {
1922 struct amdgpu_atcs_functions functions;
1923 };
1924
1925 /*
1926 * CGS
1927 */
1928 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1929 void amdgpu_cgs_destroy_device(void *cgs_device);
1930
1931
1932 /*
1933 * Core structure, functions and helpers.
1934 */
1935 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1936 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1937
1938 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1939 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1940
1941 struct amdgpu_ip_block_status {
1942 bool valid;
1943 bool sw;
1944 bool hw;
1945 };
1946
1947 struct amdgpu_device {
1948 struct device *dev;
1949 struct drm_device *ddev;
1950 struct pci_dev *pdev;
1951
1952 /* ASIC */
1953 enum amd_asic_type asic_type;
1954 uint32_t family;
1955 uint32_t rev_id;
1956 uint32_t external_rev_id;
1957 unsigned long flags;
1958 int usec_timeout;
1959 const struct amdgpu_asic_funcs *asic_funcs;
1960 bool shutdown;
1961 bool suspend;
1962 bool need_dma32;
1963 bool accel_working;
1964 struct work_struct reset_work;
1965 struct notifier_block acpi_nb;
1966 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1967 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1968 unsigned debugfs_count;
1969 #if defined(CONFIG_DEBUG_FS)
1970 struct dentry *debugfs_regs;
1971 #endif
1972 struct amdgpu_atif atif;
1973 struct amdgpu_atcs atcs;
1974 struct mutex srbm_mutex;
1975 /* GRBM index mutex. Protects concurrent access to GRBM index */
1976 struct mutex grbm_idx_mutex;
1977 struct dev_pm_domain vga_pm_domain;
1978 bool have_disp_power_ref;
1979
1980 /* BIOS */
1981 uint8_t *bios;
1982 bool is_atom_bios;
1983 uint16_t bios_header_start;
1984 struct amdgpu_bo *stollen_vga_memory;
1985 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1986
1987 /* Register/doorbell mmio */
1988 resource_size_t rmmio_base;
1989 resource_size_t rmmio_size;
1990 void __iomem *rmmio;
1991 /* protects concurrent MM_INDEX/DATA based register access */
1992 spinlock_t mmio_idx_lock;
1993 /* protects concurrent SMC based register access */
1994 spinlock_t smc_idx_lock;
1995 amdgpu_rreg_t smc_rreg;
1996 amdgpu_wreg_t smc_wreg;
1997 /* protects concurrent PCIE register access */
1998 spinlock_t pcie_idx_lock;
1999 amdgpu_rreg_t pcie_rreg;
2000 amdgpu_wreg_t pcie_wreg;
2001 /* protects concurrent UVD register access */
2002 spinlock_t uvd_ctx_idx_lock;
2003 amdgpu_rreg_t uvd_ctx_rreg;
2004 amdgpu_wreg_t uvd_ctx_wreg;
2005 /* protects concurrent DIDT register access */
2006 spinlock_t didt_idx_lock;
2007 amdgpu_rreg_t didt_rreg;
2008 amdgpu_wreg_t didt_wreg;
2009 /* protects concurrent ENDPOINT (audio) register access */
2010 spinlock_t audio_endpt_idx_lock;
2011 amdgpu_block_rreg_t audio_endpt_rreg;
2012 amdgpu_block_wreg_t audio_endpt_wreg;
2013 void __iomem *rio_mem;
2014 resource_size_t rio_mem_size;
2015 struct amdgpu_doorbell doorbell;
2016
2017 /* clock/pll info */
2018 struct amdgpu_clock clock;
2019
2020 /* MC */
2021 struct amdgpu_mc mc;
2022 struct amdgpu_gart gart;
2023 struct amdgpu_dummy_page dummy_page;
2024 struct amdgpu_vm_manager vm_manager;
2025
2026 /* memory management */
2027 struct amdgpu_mman mman;
2028 struct amdgpu_gem gem;
2029 struct amdgpu_vram_scratch vram_scratch;
2030 struct amdgpu_wb wb;
2031 atomic64_t vram_usage;
2032 atomic64_t vram_vis_usage;
2033 atomic64_t gtt_usage;
2034 atomic64_t num_bytes_moved;
2035 atomic_t gpu_reset_counter;
2036
2037 /* display */
2038 struct amdgpu_mode_info mode_info;
2039 struct work_struct hotplug_work;
2040 struct amdgpu_irq_src crtc_irq;
2041 struct amdgpu_irq_src pageflip_irq;
2042 struct amdgpu_irq_src hpd_irq;
2043
2044 /* rings */
2045 unsigned fence_context;
2046 struct mutex ring_lock;
2047 unsigned num_rings;
2048 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2049 bool ib_pool_ready;
2050 struct amdgpu_sa_manager ring_tmp_bo;
2051
2052 /* interrupts */
2053 struct amdgpu_irq irq;
2054
2055 /* powerplay */
2056 struct amd_powerplay powerplay;
2057 bool pp_enabled;
2058
2059 /* dpm */
2060 struct amdgpu_pm pm;
2061 u32 cg_flags;
2062 u32 pg_flags;
2063
2064 /* amdgpu smumgr */
2065 struct amdgpu_smumgr smu;
2066
2067 /* gfx */
2068 struct amdgpu_gfx gfx;
2069
2070 /* sdma */
2071 struct amdgpu_sdma sdma;
2072
2073 /* uvd */
2074 bool has_uvd;
2075 struct amdgpu_uvd uvd;
2076
2077 /* vce */
2078 struct amdgpu_vce vce;
2079
2080 /* firmwares */
2081 struct amdgpu_firmware firmware;
2082
2083 /* GDS */
2084 struct amdgpu_gds gds;
2085
2086 const struct amdgpu_ip_block_version *ip_blocks;
2087 int num_ip_blocks;
2088 struct amdgpu_ip_block_status *ip_block_status;
2089 struct mutex mn_lock;
2090 DECLARE_HASHTABLE(mn_hash, 7);
2091
2092 /* tracking pinned memory */
2093 u64 vram_pin_size;
2094 u64 gart_pin_size;
2095
2096 /* amdkfd interface */
2097 struct kfd_dev *kfd;
2098
2099 /* kernel conext for IB submission */
2100 struct amdgpu_ctx kernel_ctx;
2101 };
2102
2103 bool amdgpu_device_is_px(struct drm_device *dev);
2104 int amdgpu_device_init(struct amdgpu_device *adev,
2105 struct drm_device *ddev,
2106 struct pci_dev *pdev,
2107 uint32_t flags);
2108 void amdgpu_device_fini(struct amdgpu_device *adev);
2109 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2110
2111 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2112 bool always_indirect);
2113 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2114 bool always_indirect);
2115 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2116 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2117
2118 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2119 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2120
2121 /*
2122 * Cast helper
2123 */
2124 extern const struct fence_ops amdgpu_fence_ops;
2125 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2126 {
2127 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2128
2129 if (__f->base.ops == &amdgpu_fence_ops)
2130 return __f;
2131
2132 return NULL;
2133 }
2134
2135 /*
2136 * Registers read & write functions.
2137 */
2138 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2139 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2140 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2141 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2142 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2143 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2144 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2145 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2146 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2147 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2148 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2149 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2150 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2151 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2152 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2153 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2154 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2155 #define WREG32_P(reg, val, mask) \
2156 do { \
2157 uint32_t tmp_ = RREG32(reg); \
2158 tmp_ &= (mask); \
2159 tmp_ |= ((val) & ~(mask)); \
2160 WREG32(reg, tmp_); \
2161 } while (0)
2162 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2163 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2164 #define WREG32_PLL_P(reg, val, mask) \
2165 do { \
2166 uint32_t tmp_ = RREG32_PLL(reg); \
2167 tmp_ &= (mask); \
2168 tmp_ |= ((val) & ~(mask)); \
2169 WREG32_PLL(reg, tmp_); \
2170 } while (0)
2171 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2172 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2173 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2174
2175 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2176 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2177
2178 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2179 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2180
2181 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2182 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2183 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2184
2185 #define REG_GET_FIELD(value, reg, field) \
2186 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2187
2188 /*
2189 * BIOS helpers.
2190 */
2191 #define RBIOS8(i) (adev->bios[i])
2192 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2193 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2194
2195 /*
2196 * RING helpers.
2197 */
2198 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2199 {
2200 if (ring->count_dw <= 0)
2201 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2202 ring->ring[ring->wptr++] = v;
2203 ring->wptr &= ring->ptr_mask;
2204 ring->count_dw--;
2205 ring->ring_free_dw--;
2206 }
2207
2208 static inline struct amdgpu_sdma_instance *
2209 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2210 {
2211 struct amdgpu_device *adev = ring->adev;
2212 int i;
2213
2214 for (i = 0; i < adev->sdma.num_instances; i++)
2215 if (&adev->sdma.instance[i].ring == ring)
2216 break;
2217
2218 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2219 return &adev->sdma.instance[i];
2220 else
2221 return NULL;
2222 }
2223
2224 /*
2225 * ASICs macro.
2226 */
2227 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2228 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2229 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2230 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2231 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2232 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2233 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2234 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2235 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2236 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2237 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2238 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2239 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2240 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2241 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2242 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2243 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2244 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2245 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2246 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2247 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2248 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2249 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2250 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2251 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2252 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2253 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2254 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2255 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2256 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2257 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2258 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2259 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2260 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2261 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2262 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2263 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2264 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2265 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2266 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2267 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2268 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2269 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2270 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2271 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2272 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2273 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2274 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2275 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2276 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2277 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2278 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2279 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2280 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2281 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2282 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2283 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2284
2285 #define amdgpu_dpm_get_temperature(adev) \
2286 ((adev)->pp_enabled ? \
2287 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2288 (adev)->pm.funcs->get_temperature((adev)))
2289
2290 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2291 ((adev)->pp_enabled ? \
2292 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2293 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2294
2295 #define amdgpu_dpm_get_fan_control_mode(adev) \
2296 ((adev)->pp_enabled ? \
2297 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2298 (adev)->pm.funcs->get_fan_control_mode((adev)))
2299
2300 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2301 ((adev)->pp_enabled ? \
2302 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2303 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2304
2305 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2306 ((adev)->pp_enabled ? \
2307 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2308 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2309
2310 #define amdgpu_dpm_get_sclk(adev, l) \
2311 ((adev)->pp_enabled ? \
2312 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2313 (adev)->pm.funcs->get_sclk((adev), (l)))
2314
2315 #define amdgpu_dpm_get_mclk(adev, l) \
2316 ((adev)->pp_enabled ? \
2317 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2318 (adev)->pm.funcs->get_mclk((adev), (l)))
2319
2320
2321 #define amdgpu_dpm_force_performance_level(adev, l) \
2322 ((adev)->pp_enabled ? \
2323 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2324 (adev)->pm.funcs->force_performance_level((adev), (l)))
2325
2326 #define amdgpu_dpm_powergate_uvd(adev, g) \
2327 ((adev)->pp_enabled ? \
2328 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2329 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2330
2331 #define amdgpu_dpm_powergate_vce(adev, g) \
2332 ((adev)->pp_enabled ? \
2333 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2334 (adev)->pm.funcs->powergate_vce((adev), (g)))
2335
2336 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2337 ((adev)->pp_enabled ? \
2338 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2339 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2340
2341 #define amdgpu_dpm_get_current_power_state(adev) \
2342 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2343
2344 #define amdgpu_dpm_get_performance_level(adev) \
2345 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2346
2347 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2348 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2349
2350 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2351
2352 /* Common functions */
2353 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2354 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2355 bool amdgpu_card_posted(struct amdgpu_device *adev);
2356 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2357 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2358
2359 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2360 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2361 u32 ip_instance, u32 ring,
2362 struct amdgpu_ring **out_ring);
2363 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2364 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2365 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2366 uint32_t flags);
2367 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2368 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2369 unsigned long end);
2370 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2371 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2372 struct ttm_mem_reg *mem);
2373 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2374 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2375 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2376 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2377 const u32 *registers,
2378 const u32 array_size);
2379
2380 bool amdgpu_device_is_px(struct drm_device *dev);
2381 /* atpx handler */
2382 #if defined(CONFIG_VGA_SWITCHEROO)
2383 void amdgpu_register_atpx_handler(void);
2384 void amdgpu_unregister_atpx_handler(void);
2385 #else
2386 static inline void amdgpu_register_atpx_handler(void) {}
2387 static inline void amdgpu_unregister_atpx_handler(void) {}
2388 #endif
2389
2390 /*
2391 * KMS
2392 */
2393 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2394 extern int amdgpu_max_kms_ioctl;
2395
2396 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2397 int amdgpu_driver_unload_kms(struct drm_device *dev);
2398 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2399 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2400 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2401 struct drm_file *file_priv);
2402 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2403 struct drm_file *file_priv);
2404 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2405 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2406 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2407 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2408 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2409 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2410 int *max_error,
2411 struct timeval *vblank_time,
2412 unsigned flags);
2413 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2414 unsigned long arg);
2415
2416 /*
2417 * functions used by amdgpu_encoder.c
2418 */
2419 struct amdgpu_afmt_acr {
2420 u32 clock;
2421
2422 int n_32khz;
2423 int cts_32khz;
2424
2425 int n_44_1khz;
2426 int cts_44_1khz;
2427
2428 int n_48khz;
2429 int cts_48khz;
2430
2431 };
2432
2433 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2434
2435 /* amdgpu_acpi.c */
2436 #if defined(CONFIG_ACPI)
2437 int amdgpu_acpi_init(struct amdgpu_device *adev);
2438 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2439 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2440 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2441 u8 perf_req, bool advertise);
2442 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2443 #else
2444 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2445 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2446 #endif
2447
2448 struct amdgpu_bo_va_mapping *
2449 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2450 uint64_t addr, struct amdgpu_bo **bo);
2451
2452 #include "amdgpu_object.h"
2453
2454 #endif
Linux kernel - Deliverables
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