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drm/amdgpu: grab VMID before submitting job v5
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56
57 #include "gpu_scheduler.h"
58
59 /*
60 * Modules parameters.
61 */
62 extern int amdgpu_modeset;
63 extern int amdgpu_vram_limit;
64 extern int amdgpu_gart_size;
65 extern int amdgpu_benchmarking;
66 extern int amdgpu_testing;
67 extern int amdgpu_audio;
68 extern int amdgpu_disp_priority;
69 extern int amdgpu_hw_i2c;
70 extern int amdgpu_pcie_gen2;
71 extern int amdgpu_msi;
72 extern int amdgpu_lockup_timeout;
73 extern int amdgpu_dpm;
74 extern int amdgpu_smc_load_fw;
75 extern int amdgpu_aspm;
76 extern int amdgpu_runtime_pm;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_vm_fault_stop;
83 extern int amdgpu_vm_debug;
84 extern int amdgpu_sched_jobs;
85 extern int amdgpu_sched_hw_submission;
86 extern int amdgpu_powerplay;
87
88 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
89 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
90 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
91 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
92 #define AMDGPU_IB_POOL_SIZE 16
93 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
94 #define AMDGPUFB_CONN_LIMIT 4
95 #define AMDGPU_BIOS_NUM_SCRATCH 8
96
97 /* max number of rings */
98 #define AMDGPU_MAX_RINGS 16
99 #define AMDGPU_MAX_GFX_RINGS 1
100 #define AMDGPU_MAX_COMPUTE_RINGS 8
101 #define AMDGPU_MAX_VCE_RINGS 2
102
103 /* max number of IP instances */
104 #define AMDGPU_MAX_SDMA_INSTANCES 2
105
106 /* number of hw syncs before falling back on blocking */
107 #define AMDGPU_NUM_SYNCS 4
108
109 /* hardcode that limit for now */
110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112 /* hard reset data */
113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115 /* reset flags */
116 #define AMDGPU_RESET_GFX (1 << 0)
117 #define AMDGPU_RESET_COMPUTE (1 << 1)
118 #define AMDGPU_RESET_DMA (1 << 2)
119 #define AMDGPU_RESET_CP (1 << 3)
120 #define AMDGPU_RESET_GRBM (1 << 4)
121 #define AMDGPU_RESET_DMA1 (1 << 5)
122 #define AMDGPU_RESET_RLC (1 << 6)
123 #define AMDGPU_RESET_SEM (1 << 7)
124 #define AMDGPU_RESET_IH (1 << 8)
125 #define AMDGPU_RESET_VMC (1 << 9)
126 #define AMDGPU_RESET_MC (1 << 10)
127 #define AMDGPU_RESET_DISPLAY (1 << 11)
128 #define AMDGPU_RESET_UVD (1 << 12)
129 #define AMDGPU_RESET_VCE (1 << 13)
130 #define AMDGPU_RESET_VCE1 (1 << 14)
131
132 /* CG block flags */
133 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
134 #define AMDGPU_CG_BLOCK_MC (1 << 1)
135 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
136 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
137 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
138 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
139 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
140
141 /* CG flags */
142 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
143 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
144 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
145 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
146 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
148 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
149 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
150 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
151 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
152 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
153 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
154 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
155 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
156 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
157 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
158 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
159
160 /* PG flags */
161 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
162 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
163 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
164 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
165 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
166 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
167 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
168 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
169 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
170 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
171 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
172
173 /* GFX current status */
174 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
175 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
176 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
177 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
178 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
179
180 /* max cursor sizes (in pixels) */
181 #define CIK_CURSOR_WIDTH 128
182 #define CIK_CURSOR_HEIGHT 128
183
184 struct amdgpu_device;
185 struct amdgpu_fence;
186 struct amdgpu_ib;
187 struct amdgpu_vm;
188 struct amdgpu_ring;
189 struct amdgpu_cs_parser;
190 struct amdgpu_job;
191 struct amdgpu_irq_src;
192 struct amdgpu_fpriv;
193
194 enum amdgpu_cp_irq {
195 AMDGPU_CP_IRQ_GFX_EOP = 0,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
204
205 AMDGPU_CP_IRQ_LAST
206 };
207
208 enum amdgpu_sdma_irq {
209 AMDGPU_SDMA_IRQ_TRAP0 = 0,
210 AMDGPU_SDMA_IRQ_TRAP1,
211
212 AMDGPU_SDMA_IRQ_LAST
213 };
214
215 enum amdgpu_thermal_irq {
216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
218
219 AMDGPU_THERMAL_IRQ_LAST
220 };
221
222 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
223 enum amd_ip_block_type block_type,
224 enum amd_clockgating_state state);
225 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
226 enum amd_ip_block_type block_type,
227 enum amd_powergating_state state);
228
229 struct amdgpu_ip_block_version {
230 enum amd_ip_block_type type;
231 u32 major;
232 u32 minor;
233 u32 rev;
234 const struct amd_ip_funcs *funcs;
235 };
236
237 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
238 enum amd_ip_block_type type,
239 u32 major, u32 minor);
240
241 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
242 struct amdgpu_device *adev,
243 enum amd_ip_block_type type);
244
245 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
246 struct amdgpu_buffer_funcs {
247 /* maximum bytes in a single operation */
248 uint32_t copy_max_bytes;
249
250 /* number of dw to reserve per operation */
251 unsigned copy_num_dw;
252
253 /* used for buffer migration */
254 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
255 /* src addr in bytes */
256 uint64_t src_offset,
257 /* dst addr in bytes */
258 uint64_t dst_offset,
259 /* number of byte to transfer */
260 uint32_t byte_count);
261
262 /* maximum bytes in a single operation */
263 uint32_t fill_max_bytes;
264
265 /* number of dw to reserve per operation */
266 unsigned fill_num_dw;
267
268 /* used for buffer clearing */
269 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
270 /* value to write to memory */
271 uint32_t src_data,
272 /* dst addr in bytes */
273 uint64_t dst_offset,
274 /* number of byte to fill */
275 uint32_t byte_count);
276 };
277
278 /* provided by hw blocks that can write ptes, e.g., sdma */
279 struct amdgpu_vm_pte_funcs {
280 /* copy pte entries from GART */
281 void (*copy_pte)(struct amdgpu_ib *ib,
282 uint64_t pe, uint64_t src,
283 unsigned count);
284 /* write pte one entry at a time with addr mapping */
285 void (*write_pte)(struct amdgpu_ib *ib,
286 uint64_t pe,
287 uint64_t addr, unsigned count,
288 uint32_t incr, uint32_t flags);
289 /* for linear pte/pde updates without addr mapping */
290 void (*set_pte_pde)(struct amdgpu_ib *ib,
291 uint64_t pe,
292 uint64_t addr, unsigned count,
293 uint32_t incr, uint32_t flags);
294 /* pad the indirect buffer to the necessary number of dw */
295 void (*pad_ib)(struct amdgpu_ib *ib);
296 };
297
298 /* provided by the gmc block */
299 struct amdgpu_gart_funcs {
300 /* flush the vm tlb via mmio */
301 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
302 uint32_t vmid);
303 /* write pte/pde updates using the cpu */
304 int (*set_pte_pde)(struct amdgpu_device *adev,
305 void *cpu_pt_addr, /* cpu addr of page table */
306 uint32_t gpu_page_idx, /* pte/pde to update */
307 uint64_t addr, /* addr to write into pte/pde */
308 uint32_t flags); /* access flags */
309 };
310
311 /* provided by the ih block */
312 struct amdgpu_ih_funcs {
313 /* ring read/write ptr handling, called from interrupt context */
314 u32 (*get_wptr)(struct amdgpu_device *adev);
315 void (*decode_iv)(struct amdgpu_device *adev,
316 struct amdgpu_iv_entry *entry);
317 void (*set_rptr)(struct amdgpu_device *adev);
318 };
319
320 /* provided by hw blocks that expose a ring buffer for commands */
321 struct amdgpu_ring_funcs {
322 /* ring read/write ptr handling */
323 u32 (*get_rptr)(struct amdgpu_ring *ring);
324 u32 (*get_wptr)(struct amdgpu_ring *ring);
325 void (*set_wptr)(struct amdgpu_ring *ring);
326 /* validating and patching of IBs */
327 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
328 /* command emit functions */
329 void (*emit_ib)(struct amdgpu_ring *ring,
330 struct amdgpu_ib *ib);
331 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
332 uint64_t seq, unsigned flags);
333 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
334 uint64_t pd_addr);
335 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
336 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
337 uint32_t gds_base, uint32_t gds_size,
338 uint32_t gws_base, uint32_t gws_size,
339 uint32_t oa_base, uint32_t oa_size);
340 /* testing functions */
341 int (*test_ring)(struct amdgpu_ring *ring);
342 int (*test_ib)(struct amdgpu_ring *ring);
343 /* insert NOP packets */
344 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
345 };
346
347 /*
348 * BIOS.
349 */
350 bool amdgpu_get_bios(struct amdgpu_device *adev);
351 bool amdgpu_read_bios(struct amdgpu_device *adev);
352
353 /*
354 * Dummy page
355 */
356 struct amdgpu_dummy_page {
357 struct page *page;
358 dma_addr_t addr;
359 };
360 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
361 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
362
363
364 /*
365 * Clocks
366 */
367
368 #define AMDGPU_MAX_PPLL 3
369
370 struct amdgpu_clock {
371 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
372 struct amdgpu_pll spll;
373 struct amdgpu_pll mpll;
374 /* 10 Khz units */
375 uint32_t default_mclk;
376 uint32_t default_sclk;
377 uint32_t default_dispclk;
378 uint32_t current_dispclk;
379 uint32_t dp_extclk;
380 uint32_t max_pixel_clock;
381 };
382
383 /*
384 * Fences.
385 */
386 struct amdgpu_fence_driver {
387 uint64_t gpu_addr;
388 volatile uint32_t *cpu_addr;
389 /* sync_seq is protected by ring emission lock */
390 uint64_t sync_seq;
391 atomic64_t last_seq;
392 bool initialized;
393 struct amdgpu_irq_src *irq_src;
394 unsigned irq_type;
395 struct timer_list fallback_timer;
396 wait_queue_head_t fence_queue;
397 };
398
399 /* some special values for the owner field */
400 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
401 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
402
403 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
404 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
405
406 struct amdgpu_fence {
407 struct fence base;
408
409 /* RB, DMA, etc. */
410 struct amdgpu_ring *ring;
411 uint64_t seq;
412
413 /* filp or special value for fence creator */
414 void *owner;
415
416 wait_queue_t fence_wake;
417 };
418
419 struct amdgpu_user_fence {
420 /* write-back bo */
421 struct amdgpu_bo *bo;
422 /* write-back address offset to bo start */
423 uint32_t offset;
424 };
425
426 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
427 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
428 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
429
430 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
431 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
432 struct amdgpu_irq_src *irq_src,
433 unsigned irq_type);
434 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
435 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
436 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
437 struct amdgpu_fence **fence);
438 void amdgpu_fence_process(struct amdgpu_ring *ring);
439 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
440 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
441 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
442
443 /*
444 * TTM.
445 */
446 struct amdgpu_mman {
447 struct ttm_bo_global_ref bo_global_ref;
448 struct drm_global_reference mem_global_ref;
449 struct ttm_bo_device bdev;
450 bool mem_global_referenced;
451 bool initialized;
452
453 #if defined(CONFIG_DEBUG_FS)
454 struct dentry *vram;
455 struct dentry *gtt;
456 #endif
457
458 /* buffer handling */
459 const struct amdgpu_buffer_funcs *buffer_funcs;
460 struct amdgpu_ring *buffer_funcs_ring;
461 };
462
463 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
464 uint64_t src_offset,
465 uint64_t dst_offset,
466 uint32_t byte_count,
467 struct reservation_object *resv,
468 struct fence **fence);
469 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
470
471 struct amdgpu_bo_list_entry {
472 struct amdgpu_bo *robj;
473 struct ttm_validate_buffer tv;
474 struct amdgpu_bo_va *bo_va;
475 uint32_t priority;
476 };
477
478 struct amdgpu_bo_va_mapping {
479 struct list_head list;
480 struct interval_tree_node it;
481 uint64_t offset;
482 uint32_t flags;
483 };
484
485 /* bo virtual addresses in a specific vm */
486 struct amdgpu_bo_va {
487 struct mutex mutex;
488 /* protected by bo being reserved */
489 struct list_head bo_list;
490 struct fence *last_pt_update;
491 unsigned ref_count;
492
493 /* protected by vm mutex and spinlock */
494 struct list_head vm_status;
495
496 /* mappings for this bo_va */
497 struct list_head invalids;
498 struct list_head valids;
499
500 /* constant after initialization */
501 struct amdgpu_vm *vm;
502 struct amdgpu_bo *bo;
503 };
504
505 #define AMDGPU_GEM_DOMAIN_MAX 0x3
506
507 struct amdgpu_bo {
508 /* Protected by gem.mutex */
509 struct list_head list;
510 /* Protected by tbo.reserved */
511 u32 prefered_domains;
512 u32 allowed_domains;
513 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
514 struct ttm_placement placement;
515 struct ttm_buffer_object tbo;
516 struct ttm_bo_kmap_obj kmap;
517 u64 flags;
518 unsigned pin_count;
519 void *kptr;
520 u64 tiling_flags;
521 u64 metadata_flags;
522 void *metadata;
523 u32 metadata_size;
524 /* list of all virtual address to which this bo
525 * is associated to
526 */
527 struct list_head va;
528 /* Constant after initialization */
529 struct amdgpu_device *adev;
530 struct drm_gem_object gem_base;
531 struct amdgpu_bo *parent;
532
533 struct ttm_bo_kmap_obj dma_buf_vmap;
534 pid_t pid;
535 struct amdgpu_mn *mn;
536 struct list_head mn_list;
537 };
538 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
539
540 void amdgpu_gem_object_free(struct drm_gem_object *obj);
541 int amdgpu_gem_object_open(struct drm_gem_object *obj,
542 struct drm_file *file_priv);
543 void amdgpu_gem_object_close(struct drm_gem_object *obj,
544 struct drm_file *file_priv);
545 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
546 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
547 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
548 struct dma_buf_attachment *attach,
549 struct sg_table *sg);
550 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
551 struct drm_gem_object *gobj,
552 int flags);
553 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
554 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
555 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
556 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
557 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
558 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
559
560 /* sub-allocation manager, it has to be protected by another lock.
561 * By conception this is an helper for other part of the driver
562 * like the indirect buffer or semaphore, which both have their
563 * locking.
564 *
565 * Principe is simple, we keep a list of sub allocation in offset
566 * order (first entry has offset == 0, last entry has the highest
567 * offset).
568 *
569 * When allocating new object we first check if there is room at
570 * the end total_size - (last_object_offset + last_object_size) >=
571 * alloc_size. If so we allocate new object there.
572 *
573 * When there is not enough room at the end, we start waiting for
574 * each sub object until we reach object_offset+object_size >=
575 * alloc_size, this object then become the sub object we return.
576 *
577 * Alignment can't be bigger than page size.
578 *
579 * Hole are not considered for allocation to keep things simple.
580 * Assumption is that there won't be hole (all object on same
581 * alignment).
582 */
583 struct amdgpu_sa_manager {
584 wait_queue_head_t wq;
585 struct amdgpu_bo *bo;
586 struct list_head *hole;
587 struct list_head flist[AMDGPU_MAX_RINGS];
588 struct list_head olist;
589 unsigned size;
590 uint64_t gpu_addr;
591 void *cpu_ptr;
592 uint32_t domain;
593 uint32_t align;
594 };
595
596 struct amdgpu_sa_bo;
597
598 /* sub-allocation buffer */
599 struct amdgpu_sa_bo {
600 struct list_head olist;
601 struct list_head flist;
602 struct amdgpu_sa_manager *manager;
603 unsigned soffset;
604 unsigned eoffset;
605 struct fence *fence;
606 };
607
608 /*
609 * GEM objects.
610 */
611 struct amdgpu_gem {
612 struct mutex mutex;
613 struct list_head objects;
614 };
615
616 int amdgpu_gem_init(struct amdgpu_device *adev);
617 void amdgpu_gem_fini(struct amdgpu_device *adev);
618 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
619 int alignment, u32 initial_domain,
620 u64 flags, bool kernel,
621 struct drm_gem_object **obj);
622
623 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
624 struct drm_device *dev,
625 struct drm_mode_create_dumb *args);
626 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
627 struct drm_device *dev,
628 uint32_t handle, uint64_t *offset_p);
629 /*
630 * Synchronization
631 */
632 struct amdgpu_sync {
633 DECLARE_HASHTABLE(fences, 4);
634 struct fence *last_vm_update;
635 };
636
637 void amdgpu_sync_create(struct amdgpu_sync *sync);
638 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
639 struct fence *f);
640 int amdgpu_sync_resv(struct amdgpu_device *adev,
641 struct amdgpu_sync *sync,
642 struct reservation_object *resv,
643 void *owner);
644 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
645 int amdgpu_sync_wait(struct amdgpu_sync *sync);
646 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
647 struct fence *fence);
648
649 /*
650 * GART structures, functions & helpers
651 */
652 struct amdgpu_mc;
653
654 #define AMDGPU_GPU_PAGE_SIZE 4096
655 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
656 #define AMDGPU_GPU_PAGE_SHIFT 12
657 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
658
659 struct amdgpu_gart {
660 dma_addr_t table_addr;
661 struct amdgpu_bo *robj;
662 void *ptr;
663 unsigned num_gpu_pages;
664 unsigned num_cpu_pages;
665 unsigned table_size;
666 struct page **pages;
667 dma_addr_t *pages_addr;
668 bool ready;
669 const struct amdgpu_gart_funcs *gart_funcs;
670 };
671
672 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
673 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
674 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
675 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
676 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
677 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
678 int amdgpu_gart_init(struct amdgpu_device *adev);
679 void amdgpu_gart_fini(struct amdgpu_device *adev);
680 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
681 int pages);
682 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
683 int pages, struct page **pagelist,
684 dma_addr_t *dma_addr, uint32_t flags);
685
686 /*
687 * GPU MC structures, functions & helpers
688 */
689 struct amdgpu_mc {
690 resource_size_t aper_size;
691 resource_size_t aper_base;
692 resource_size_t agp_base;
693 /* for some chips with <= 32MB we need to lie
694 * about vram size near mc fb location */
695 u64 mc_vram_size;
696 u64 visible_vram_size;
697 u64 gtt_size;
698 u64 gtt_start;
699 u64 gtt_end;
700 u64 vram_start;
701 u64 vram_end;
702 unsigned vram_width;
703 u64 real_vram_size;
704 int vram_mtrr;
705 u64 gtt_base_align;
706 u64 mc_mask;
707 const struct firmware *fw; /* MC firmware */
708 uint32_t fw_version;
709 struct amdgpu_irq_src vm_fault;
710 uint32_t vram_type;
711 };
712
713 /*
714 * GPU doorbell structures, functions & helpers
715 */
716 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
717 {
718 AMDGPU_DOORBELL_KIQ = 0x000,
719 AMDGPU_DOORBELL_HIQ = 0x001,
720 AMDGPU_DOORBELL_DIQ = 0x002,
721 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
722 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
723 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
724 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
725 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
726 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
727 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
728 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
729 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
730 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
731 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
732 AMDGPU_DOORBELL_IH = 0x1E8,
733 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
734 AMDGPU_DOORBELL_INVALID = 0xFFFF
735 } AMDGPU_DOORBELL_ASSIGNMENT;
736
737 struct amdgpu_doorbell {
738 /* doorbell mmio */
739 resource_size_t base;
740 resource_size_t size;
741 u32 __iomem *ptr;
742 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
743 };
744
745 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
746 phys_addr_t *aperture_base,
747 size_t *aperture_size,
748 size_t *start_offset);
749
750 /*
751 * IRQS.
752 */
753
754 struct amdgpu_flip_work {
755 struct work_struct flip_work;
756 struct work_struct unpin_work;
757 struct amdgpu_device *adev;
758 int crtc_id;
759 uint64_t base;
760 struct drm_pending_vblank_event *event;
761 struct amdgpu_bo *old_rbo;
762 struct fence *excl;
763 unsigned shared_count;
764 struct fence **shared;
765 };
766
767
768 /*
769 * CP & rings.
770 */
771
772 struct amdgpu_ib {
773 struct amdgpu_sa_bo *sa_bo;
774 uint32_t length_dw;
775 uint64_t gpu_addr;
776 uint32_t *ptr;
777 struct amdgpu_ring *ring;
778 struct amdgpu_fence *fence;
779 struct amdgpu_user_fence *user;
780 bool grabbed_vmid;
781 struct amdgpu_vm *vm;
782 struct amdgpu_ctx *ctx;
783 struct amdgpu_sync sync;
784 uint32_t gds_base, gds_size;
785 uint32_t gws_base, gws_size;
786 uint32_t oa_base, oa_size;
787 uint32_t flags;
788 /* resulting sequence number */
789 uint64_t sequence;
790 };
791
792 enum amdgpu_ring_type {
793 AMDGPU_RING_TYPE_GFX,
794 AMDGPU_RING_TYPE_COMPUTE,
795 AMDGPU_RING_TYPE_SDMA,
796 AMDGPU_RING_TYPE_UVD,
797 AMDGPU_RING_TYPE_VCE
798 };
799
800 extern struct amd_sched_backend_ops amdgpu_sched_ops;
801
802 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
803 struct amdgpu_ring *ring,
804 struct amdgpu_ib *ibs,
805 unsigned num_ibs,
806 int (*free_job)(struct amdgpu_job *),
807 void *owner,
808 struct fence **fence);
809
810 struct amdgpu_ring {
811 struct amdgpu_device *adev;
812 const struct amdgpu_ring_funcs *funcs;
813 struct amdgpu_fence_driver fence_drv;
814 struct amd_gpu_scheduler sched;
815
816 spinlock_t fence_lock;
817 struct mutex *ring_lock;
818 struct amdgpu_bo *ring_obj;
819 volatile uint32_t *ring;
820 unsigned rptr_offs;
821 u64 next_rptr_gpu_addr;
822 volatile u32 *next_rptr_cpu_addr;
823 unsigned wptr;
824 unsigned wptr_old;
825 unsigned ring_size;
826 unsigned ring_free_dw;
827 int count_dw;
828 uint64_t gpu_addr;
829 uint32_t align_mask;
830 uint32_t ptr_mask;
831 bool ready;
832 u32 nop;
833 u32 idx;
834 u32 me;
835 u32 pipe;
836 u32 queue;
837 struct amdgpu_bo *mqd_obj;
838 u32 doorbell_index;
839 bool use_doorbell;
840 unsigned wptr_offs;
841 unsigned next_rptr_offs;
842 unsigned fence_offs;
843 struct amdgpu_ctx *current_ctx;
844 enum amdgpu_ring_type type;
845 char name[16];
846 bool is_pte_ring;
847 };
848
849 /*
850 * VM
851 */
852
853 /* maximum number of VMIDs */
854 #define AMDGPU_NUM_VM 16
855
856 /* number of entries in page table */
857 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
858
859 /* PTBs (Page Table Blocks) need to be aligned to 32K */
860 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
861 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
862 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
863
864 #define AMDGPU_PTE_VALID (1 << 0)
865 #define AMDGPU_PTE_SYSTEM (1 << 1)
866 #define AMDGPU_PTE_SNOOPED (1 << 2)
867
868 /* VI only */
869 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
870
871 #define AMDGPU_PTE_READABLE (1 << 5)
872 #define AMDGPU_PTE_WRITEABLE (1 << 6)
873
874 /* PTE (Page Table Entry) fragment field for different page sizes */
875 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
876 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
877 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
878
879 /* How to programm VM fault handling */
880 #define AMDGPU_VM_FAULT_STOP_NEVER 0
881 #define AMDGPU_VM_FAULT_STOP_FIRST 1
882 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
883
884 struct amdgpu_vm_pt {
885 struct amdgpu_bo_list_entry entry;
886 uint64_t addr;
887 };
888
889 struct amdgpu_vm_id {
890 unsigned id;
891 uint64_t pd_gpu_addr;
892 /* last flushed PD/PT update */
893 struct fence *flushed_updates;
894 };
895
896 struct amdgpu_vm {
897 /* tree of virtual addresses mapped */
898 spinlock_t it_lock;
899 struct rb_root va;
900
901 /* protecting invalidated */
902 spinlock_t status_lock;
903
904 /* BOs moved, but not yet updated in the PT */
905 struct list_head invalidated;
906
907 /* BOs cleared in the PT because of a move */
908 struct list_head cleared;
909
910 /* BO mappings freed, but not yet updated in the PT */
911 struct list_head freed;
912
913 /* contains the page directory */
914 struct amdgpu_bo *page_directory;
915 unsigned max_pde_used;
916 struct fence *page_directory_fence;
917
918 /* array of page tables, one for each page directory entry */
919 struct amdgpu_vm_pt *page_tables;
920
921 /* for id and flush management per ring */
922 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
923
924 /* protecting freed */
925 spinlock_t freed_lock;
926 };
927
928 struct amdgpu_vm_manager {
929 /* protecting IDs */
930 struct mutex lock;
931
932 struct {
933 struct fence *active;
934 atomic_long_t owner;
935 } ids[AMDGPU_NUM_VM];
936
937 uint32_t max_pfn;
938 /* number of VMIDs */
939 unsigned nvm;
940 /* vram base address for page table entry */
941 u64 vram_base_offset;
942 /* is vm enabled? */
943 bool enabled;
944 /* vm pte handling */
945 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
946 struct amdgpu_ring *vm_pte_funcs_ring;
947 };
948
949 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
950 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
951 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
952 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
953 struct list_head *validated,
954 struct amdgpu_bo_list_entry *entry);
955 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
956 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
957 struct amdgpu_vm *vm);
958 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
959 struct amdgpu_sync *sync);
960 void amdgpu_vm_flush(struct amdgpu_ring *ring,
961 struct amdgpu_vm *vm,
962 struct fence *updates);
963 void amdgpu_vm_fence(struct amdgpu_device *adev,
964 struct amdgpu_vm *vm,
965 struct fence *fence);
966 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
967 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
968 struct amdgpu_vm *vm);
969 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
970 struct amdgpu_vm *vm);
971 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
972 struct amdgpu_sync *sync);
973 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
974 struct amdgpu_bo_va *bo_va,
975 struct ttm_mem_reg *mem);
976 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
977 struct amdgpu_bo *bo);
978 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
979 struct amdgpu_bo *bo);
980 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
981 struct amdgpu_vm *vm,
982 struct amdgpu_bo *bo);
983 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
984 struct amdgpu_bo_va *bo_va,
985 uint64_t addr, uint64_t offset,
986 uint64_t size, uint32_t flags);
987 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
988 struct amdgpu_bo_va *bo_va,
989 uint64_t addr);
990 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
991 struct amdgpu_bo_va *bo_va);
992 int amdgpu_vm_free_job(struct amdgpu_job *job);
993
994 /*
995 * context related structures
996 */
997
998 struct amdgpu_ctx_ring {
999 uint64_t sequence;
1000 struct fence **fences;
1001 struct amd_sched_entity entity;
1002 };
1003
1004 struct amdgpu_ctx {
1005 struct kref refcount;
1006 struct amdgpu_device *adev;
1007 unsigned reset_counter;
1008 spinlock_t ring_lock;
1009 struct fence **fences;
1010 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1011 };
1012
1013 struct amdgpu_ctx_mgr {
1014 struct amdgpu_device *adev;
1015 struct mutex lock;
1016 /* protected by lock */
1017 struct idr ctx_handles;
1018 };
1019
1020 int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
1021 struct amdgpu_ctx *ctx);
1022 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
1023
1024 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1025 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1026
1027 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1028 struct fence *fence);
1029 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1030 struct amdgpu_ring *ring, uint64_t seq);
1031
1032 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1033 struct drm_file *filp);
1034
1035 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1036 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1037
1038 /*
1039 * file private structure
1040 */
1041
1042 struct amdgpu_fpriv {
1043 struct amdgpu_vm vm;
1044 struct mutex bo_list_lock;
1045 struct idr bo_list_handles;
1046 struct amdgpu_ctx_mgr ctx_mgr;
1047 };
1048
1049 /*
1050 * residency list
1051 */
1052
1053 struct amdgpu_bo_list {
1054 struct mutex lock;
1055 struct amdgpu_bo *gds_obj;
1056 struct amdgpu_bo *gws_obj;
1057 struct amdgpu_bo *oa_obj;
1058 bool has_userptr;
1059 unsigned num_entries;
1060 struct amdgpu_bo_list_entry *array;
1061 };
1062
1063 struct amdgpu_bo_list *
1064 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1065 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1066 struct list_head *validated);
1067 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1068 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1069
1070 /*
1071 * GFX stuff
1072 */
1073 #include "clearstate_defs.h"
1074
1075 struct amdgpu_rlc {
1076 /* for power gating */
1077 struct amdgpu_bo *save_restore_obj;
1078 uint64_t save_restore_gpu_addr;
1079 volatile uint32_t *sr_ptr;
1080 const u32 *reg_list;
1081 u32 reg_list_size;
1082 /* for clear state */
1083 struct amdgpu_bo *clear_state_obj;
1084 uint64_t clear_state_gpu_addr;
1085 volatile uint32_t *cs_ptr;
1086 const struct cs_section_def *cs_data;
1087 u32 clear_state_size;
1088 /* for cp tables */
1089 struct amdgpu_bo *cp_table_obj;
1090 uint64_t cp_table_gpu_addr;
1091 volatile uint32_t *cp_table_ptr;
1092 u32 cp_table_size;
1093 };
1094
1095 struct amdgpu_mec {
1096 struct amdgpu_bo *hpd_eop_obj;
1097 u64 hpd_eop_gpu_addr;
1098 u32 num_pipe;
1099 u32 num_mec;
1100 u32 num_queue;
1101 };
1102
1103 /*
1104 * GPU scratch registers structures, functions & helpers
1105 */
1106 struct amdgpu_scratch {
1107 unsigned num_reg;
1108 uint32_t reg_base;
1109 bool free[32];
1110 uint32_t reg[32];
1111 };
1112
1113 /*
1114 * GFX configurations
1115 */
1116 struct amdgpu_gca_config {
1117 unsigned max_shader_engines;
1118 unsigned max_tile_pipes;
1119 unsigned max_cu_per_sh;
1120 unsigned max_sh_per_se;
1121 unsigned max_backends_per_se;
1122 unsigned max_texture_channel_caches;
1123 unsigned max_gprs;
1124 unsigned max_gs_threads;
1125 unsigned max_hw_contexts;
1126 unsigned sc_prim_fifo_size_frontend;
1127 unsigned sc_prim_fifo_size_backend;
1128 unsigned sc_hiz_tile_fifo_size;
1129 unsigned sc_earlyz_tile_fifo_size;
1130
1131 unsigned num_tile_pipes;
1132 unsigned backend_enable_mask;
1133 unsigned mem_max_burst_length_bytes;
1134 unsigned mem_row_size_in_kb;
1135 unsigned shader_engine_tile_size;
1136 unsigned num_gpus;
1137 unsigned multi_gpu_tile_size;
1138 unsigned mc_arb_ramcfg;
1139 unsigned gb_addr_config;
1140
1141 uint32_t tile_mode_array[32];
1142 uint32_t macrotile_mode_array[16];
1143 };
1144
1145 struct amdgpu_gfx {
1146 struct mutex gpu_clock_mutex;
1147 struct amdgpu_gca_config config;
1148 struct amdgpu_rlc rlc;
1149 struct amdgpu_mec mec;
1150 struct amdgpu_scratch scratch;
1151 const struct firmware *me_fw; /* ME firmware */
1152 uint32_t me_fw_version;
1153 const struct firmware *pfp_fw; /* PFP firmware */
1154 uint32_t pfp_fw_version;
1155 const struct firmware *ce_fw; /* CE firmware */
1156 uint32_t ce_fw_version;
1157 const struct firmware *rlc_fw; /* RLC firmware */
1158 uint32_t rlc_fw_version;
1159 const struct firmware *mec_fw; /* MEC firmware */
1160 uint32_t mec_fw_version;
1161 const struct firmware *mec2_fw; /* MEC2 firmware */
1162 uint32_t mec2_fw_version;
1163 uint32_t me_feature_version;
1164 uint32_t ce_feature_version;
1165 uint32_t pfp_feature_version;
1166 uint32_t rlc_feature_version;
1167 uint32_t mec_feature_version;
1168 uint32_t mec2_feature_version;
1169 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1170 unsigned num_gfx_rings;
1171 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1172 unsigned num_compute_rings;
1173 struct amdgpu_irq_src eop_irq;
1174 struct amdgpu_irq_src priv_reg_irq;
1175 struct amdgpu_irq_src priv_inst_irq;
1176 /* gfx status */
1177 uint32_t gfx_current_status;
1178 /* ce ram size*/
1179 unsigned ce_ram_size;
1180 };
1181
1182 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1183 unsigned size, struct amdgpu_ib *ib);
1184 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1185 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1186 struct amdgpu_ib *ib, void *owner);
1187 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1188 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1189 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1190 /* Ring access between begin & end cannot sleep */
1191 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1192 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1193 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1194 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1195 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1196 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1197 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1198 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1199 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1200 uint32_t **data);
1201 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1202 unsigned size, uint32_t *data);
1203 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1204 unsigned ring_size, u32 nop, u32 align_mask,
1205 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1206 enum amdgpu_ring_type ring_type);
1207 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1208 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
1209
1210 /*
1211 * CS.
1212 */
1213 struct amdgpu_cs_chunk {
1214 uint32_t chunk_id;
1215 uint32_t length_dw;
1216 uint32_t *kdata;
1217 };
1218
1219 struct amdgpu_cs_parser {
1220 struct amdgpu_device *adev;
1221 struct drm_file *filp;
1222 struct amdgpu_ctx *ctx;
1223
1224 /* chunks */
1225 unsigned nchunks;
1226 struct amdgpu_cs_chunk *chunks;
1227
1228 /* indirect buffers */
1229 uint32_t num_ibs;
1230 struct amdgpu_ib *ibs;
1231
1232 /* buffer objects */
1233 struct ww_acquire_ctx ticket;
1234 struct amdgpu_bo_list *bo_list;
1235 struct amdgpu_bo_list_entry vm_pd;
1236 struct list_head validated;
1237 struct fence *fence;
1238 uint64_t bytes_moved_threshold;
1239 uint64_t bytes_moved;
1240
1241 /* user fence */
1242 struct amdgpu_user_fence uf;
1243 struct amdgpu_bo_list_entry uf_entry;
1244 };
1245
1246 struct amdgpu_job {
1247 struct amd_sched_job base;
1248 struct amdgpu_device *adev;
1249 struct amdgpu_ib *ibs;
1250 uint32_t num_ibs;
1251 void *owner;
1252 struct amdgpu_user_fence uf;
1253 int (*free_job)(struct amdgpu_job *job);
1254 };
1255 #define to_amdgpu_job(sched_job) \
1256 container_of((sched_job), struct amdgpu_job, base)
1257
1258 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1259 {
1260 return p->ibs[ib_idx].ptr[idx];
1261 }
1262
1263 /*
1264 * Writeback
1265 */
1266 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1267
1268 struct amdgpu_wb {
1269 struct amdgpu_bo *wb_obj;
1270 volatile uint32_t *wb;
1271 uint64_t gpu_addr;
1272 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1273 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1274 };
1275
1276 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1277 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1278
1279
1280
1281 enum amdgpu_int_thermal_type {
1282 THERMAL_TYPE_NONE,
1283 THERMAL_TYPE_EXTERNAL,
1284 THERMAL_TYPE_EXTERNAL_GPIO,
1285 THERMAL_TYPE_RV6XX,
1286 THERMAL_TYPE_RV770,
1287 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1288 THERMAL_TYPE_EVERGREEN,
1289 THERMAL_TYPE_SUMO,
1290 THERMAL_TYPE_NI,
1291 THERMAL_TYPE_SI,
1292 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1293 THERMAL_TYPE_CI,
1294 THERMAL_TYPE_KV,
1295 };
1296
1297 enum amdgpu_dpm_auto_throttle_src {
1298 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1299 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1300 };
1301
1302 enum amdgpu_dpm_event_src {
1303 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1304 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1305 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1306 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1307 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1308 };
1309
1310 #define AMDGPU_MAX_VCE_LEVELS 6
1311
1312 enum amdgpu_vce_level {
1313 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1314 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1315 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1316 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1317 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1318 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1319 };
1320
1321 struct amdgpu_ps {
1322 u32 caps; /* vbios flags */
1323 u32 class; /* vbios flags */
1324 u32 class2; /* vbios flags */
1325 /* UVD clocks */
1326 u32 vclk;
1327 u32 dclk;
1328 /* VCE clocks */
1329 u32 evclk;
1330 u32 ecclk;
1331 bool vce_active;
1332 enum amdgpu_vce_level vce_level;
1333 /* asic priv */
1334 void *ps_priv;
1335 };
1336
1337 struct amdgpu_dpm_thermal {
1338 /* thermal interrupt work */
1339 struct work_struct work;
1340 /* low temperature threshold */
1341 int min_temp;
1342 /* high temperature threshold */
1343 int max_temp;
1344 /* was last interrupt low to high or high to low */
1345 bool high_to_low;
1346 /* interrupt source */
1347 struct amdgpu_irq_src irq;
1348 };
1349
1350 enum amdgpu_clk_action
1351 {
1352 AMDGPU_SCLK_UP = 1,
1353 AMDGPU_SCLK_DOWN
1354 };
1355
1356 struct amdgpu_blacklist_clocks
1357 {
1358 u32 sclk;
1359 u32 mclk;
1360 enum amdgpu_clk_action action;
1361 };
1362
1363 struct amdgpu_clock_and_voltage_limits {
1364 u32 sclk;
1365 u32 mclk;
1366 u16 vddc;
1367 u16 vddci;
1368 };
1369
1370 struct amdgpu_clock_array {
1371 u32 count;
1372 u32 *values;
1373 };
1374
1375 struct amdgpu_clock_voltage_dependency_entry {
1376 u32 clk;
1377 u16 v;
1378 };
1379
1380 struct amdgpu_clock_voltage_dependency_table {
1381 u32 count;
1382 struct amdgpu_clock_voltage_dependency_entry *entries;
1383 };
1384
1385 union amdgpu_cac_leakage_entry {
1386 struct {
1387 u16 vddc;
1388 u32 leakage;
1389 };
1390 struct {
1391 u16 vddc1;
1392 u16 vddc2;
1393 u16 vddc3;
1394 };
1395 };
1396
1397 struct amdgpu_cac_leakage_table {
1398 u32 count;
1399 union amdgpu_cac_leakage_entry *entries;
1400 };
1401
1402 struct amdgpu_phase_shedding_limits_entry {
1403 u16 voltage;
1404 u32 sclk;
1405 u32 mclk;
1406 };
1407
1408 struct amdgpu_phase_shedding_limits_table {
1409 u32 count;
1410 struct amdgpu_phase_shedding_limits_entry *entries;
1411 };
1412
1413 struct amdgpu_uvd_clock_voltage_dependency_entry {
1414 u32 vclk;
1415 u32 dclk;
1416 u16 v;
1417 };
1418
1419 struct amdgpu_uvd_clock_voltage_dependency_table {
1420 u8 count;
1421 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1422 };
1423
1424 struct amdgpu_vce_clock_voltage_dependency_entry {
1425 u32 ecclk;
1426 u32 evclk;
1427 u16 v;
1428 };
1429
1430 struct amdgpu_vce_clock_voltage_dependency_table {
1431 u8 count;
1432 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1433 };
1434
1435 struct amdgpu_ppm_table {
1436 u8 ppm_design;
1437 u16 cpu_core_number;
1438 u32 platform_tdp;
1439 u32 small_ac_platform_tdp;
1440 u32 platform_tdc;
1441 u32 small_ac_platform_tdc;
1442 u32 apu_tdp;
1443 u32 dgpu_tdp;
1444 u32 dgpu_ulv_power;
1445 u32 tj_max;
1446 };
1447
1448 struct amdgpu_cac_tdp_table {
1449 u16 tdp;
1450 u16 configurable_tdp;
1451 u16 tdc;
1452 u16 battery_power_limit;
1453 u16 small_power_limit;
1454 u16 low_cac_leakage;
1455 u16 high_cac_leakage;
1456 u16 maximum_power_delivery_limit;
1457 };
1458
1459 struct amdgpu_dpm_dynamic_state {
1460 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1461 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1462 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1463 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1464 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1465 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1466 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1467 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1468 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1469 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1470 struct amdgpu_clock_array valid_sclk_values;
1471 struct amdgpu_clock_array valid_mclk_values;
1472 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1473 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1474 u32 mclk_sclk_ratio;
1475 u32 sclk_mclk_delta;
1476 u16 vddc_vddci_delta;
1477 u16 min_vddc_for_pcie_gen2;
1478 struct amdgpu_cac_leakage_table cac_leakage_table;
1479 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1480 struct amdgpu_ppm_table *ppm_table;
1481 struct amdgpu_cac_tdp_table *cac_tdp_table;
1482 };
1483
1484 struct amdgpu_dpm_fan {
1485 u16 t_min;
1486 u16 t_med;
1487 u16 t_high;
1488 u16 pwm_min;
1489 u16 pwm_med;
1490 u16 pwm_high;
1491 u8 t_hyst;
1492 u32 cycle_delay;
1493 u16 t_max;
1494 u8 control_mode;
1495 u16 default_max_fan_pwm;
1496 u16 default_fan_output_sensitivity;
1497 u16 fan_output_sensitivity;
1498 bool ucode_fan_control;
1499 };
1500
1501 enum amdgpu_pcie_gen {
1502 AMDGPU_PCIE_GEN1 = 0,
1503 AMDGPU_PCIE_GEN2 = 1,
1504 AMDGPU_PCIE_GEN3 = 2,
1505 AMDGPU_PCIE_GEN_INVALID = 0xffff
1506 };
1507
1508 enum amdgpu_dpm_forced_level {
1509 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1510 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1511 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1512 };
1513
1514 struct amdgpu_vce_state {
1515 /* vce clocks */
1516 u32 evclk;
1517 u32 ecclk;
1518 /* gpu clocks */
1519 u32 sclk;
1520 u32 mclk;
1521 u8 clk_idx;
1522 u8 pstate;
1523 };
1524
1525 struct amdgpu_dpm_funcs {
1526 int (*get_temperature)(struct amdgpu_device *adev);
1527 int (*pre_set_power_state)(struct amdgpu_device *adev);
1528 int (*set_power_state)(struct amdgpu_device *adev);
1529 void (*post_set_power_state)(struct amdgpu_device *adev);
1530 void (*display_configuration_changed)(struct amdgpu_device *adev);
1531 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1532 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1533 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1534 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1535 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1536 bool (*vblank_too_short)(struct amdgpu_device *adev);
1537 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1538 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1539 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1540 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1541 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1542 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1543 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1544 };
1545
1546 struct amdgpu_dpm {
1547 struct amdgpu_ps *ps;
1548 /* number of valid power states */
1549 int num_ps;
1550 /* current power state that is active */
1551 struct amdgpu_ps *current_ps;
1552 /* requested power state */
1553 struct amdgpu_ps *requested_ps;
1554 /* boot up power state */
1555 struct amdgpu_ps *boot_ps;
1556 /* default uvd power state */
1557 struct amdgpu_ps *uvd_ps;
1558 /* vce requirements */
1559 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1560 enum amdgpu_vce_level vce_level;
1561 enum amd_pm_state_type state;
1562 enum amd_pm_state_type user_state;
1563 u32 platform_caps;
1564 u32 voltage_response_time;
1565 u32 backbias_response_time;
1566 void *priv;
1567 u32 new_active_crtcs;
1568 int new_active_crtc_count;
1569 u32 current_active_crtcs;
1570 int current_active_crtc_count;
1571 struct amdgpu_dpm_dynamic_state dyn_state;
1572 struct amdgpu_dpm_fan fan;
1573 u32 tdp_limit;
1574 u32 near_tdp_limit;
1575 u32 near_tdp_limit_adjusted;
1576 u32 sq_ramping_threshold;
1577 u32 cac_leakage;
1578 u16 tdp_od_limit;
1579 u32 tdp_adjustment;
1580 u16 load_line_slope;
1581 bool power_control;
1582 bool ac_power;
1583 /* special states active */
1584 bool thermal_active;
1585 bool uvd_active;
1586 bool vce_active;
1587 /* thermal handling */
1588 struct amdgpu_dpm_thermal thermal;
1589 /* forced levels */
1590 enum amdgpu_dpm_forced_level forced_level;
1591 };
1592
1593 struct amdgpu_pm {
1594 struct mutex mutex;
1595 u32 current_sclk;
1596 u32 current_mclk;
1597 u32 default_sclk;
1598 u32 default_mclk;
1599 struct amdgpu_i2c_chan *i2c_bus;
1600 /* internal thermal controller on rv6xx+ */
1601 enum amdgpu_int_thermal_type int_thermal_type;
1602 struct device *int_hwmon_dev;
1603 /* fan control parameters */
1604 bool no_fan;
1605 u8 fan_pulses_per_revolution;
1606 u8 fan_min_rpm;
1607 u8 fan_max_rpm;
1608 /* dpm */
1609 bool dpm_enabled;
1610 bool sysfs_initialized;
1611 struct amdgpu_dpm dpm;
1612 const struct firmware *fw; /* SMC firmware */
1613 uint32_t fw_version;
1614 const struct amdgpu_dpm_funcs *funcs;
1615 uint32_t pcie_gen_mask;
1616 uint32_t pcie_mlw_mask;
1617 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1618 };
1619
1620 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1621
1622 /*
1623 * UVD
1624 */
1625 #define AMDGPU_MAX_UVD_HANDLES 10
1626 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1627 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1628 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1629
1630 struct amdgpu_uvd {
1631 struct amdgpu_bo *vcpu_bo;
1632 void *cpu_addr;
1633 uint64_t gpu_addr;
1634 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1635 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1636 struct delayed_work idle_work;
1637 const struct firmware *fw; /* UVD firmware */
1638 struct amdgpu_ring ring;
1639 struct amdgpu_irq_src irq;
1640 bool address_64_bit;
1641 };
1642
1643 /*
1644 * VCE
1645 */
1646 #define AMDGPU_MAX_VCE_HANDLES 16
1647 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1648
1649 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1650 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1651
1652 struct amdgpu_vce {
1653 struct amdgpu_bo *vcpu_bo;
1654 uint64_t gpu_addr;
1655 unsigned fw_version;
1656 unsigned fb_version;
1657 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1658 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1659 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1660 struct delayed_work idle_work;
1661 const struct firmware *fw; /* VCE firmware */
1662 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1663 struct amdgpu_irq_src irq;
1664 unsigned harvest_config;
1665 };
1666
1667 /*
1668 * SDMA
1669 */
1670 struct amdgpu_sdma_instance {
1671 /* SDMA firmware */
1672 const struct firmware *fw;
1673 uint32_t fw_version;
1674 uint32_t feature_version;
1675
1676 struct amdgpu_ring ring;
1677 bool burst_nop;
1678 };
1679
1680 struct amdgpu_sdma {
1681 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1682 struct amdgpu_irq_src trap_irq;
1683 struct amdgpu_irq_src illegal_inst_irq;
1684 int num_instances;
1685 };
1686
1687 /*
1688 * Firmware
1689 */
1690 struct amdgpu_firmware {
1691 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1692 bool smu_load;
1693 struct amdgpu_bo *fw_buf;
1694 unsigned int fw_size;
1695 };
1696
1697 /*
1698 * Benchmarking
1699 */
1700 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1701
1702
1703 /*
1704 * Testing
1705 */
1706 void amdgpu_test_moves(struct amdgpu_device *adev);
1707 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1708 struct amdgpu_ring *cpA,
1709 struct amdgpu_ring *cpB);
1710 void amdgpu_test_syncing(struct amdgpu_device *adev);
1711
1712 /*
1713 * MMU Notifier
1714 */
1715 #if defined(CONFIG_MMU_NOTIFIER)
1716 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1717 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1718 #else
1719 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1720 {
1721 return -ENODEV;
1722 }
1723 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1724 #endif
1725
1726 /*
1727 * Debugfs
1728 */
1729 struct amdgpu_debugfs {
1730 struct drm_info_list *files;
1731 unsigned num_files;
1732 };
1733
1734 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1735 struct drm_info_list *files,
1736 unsigned nfiles);
1737 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1738
1739 #if defined(CONFIG_DEBUG_FS)
1740 int amdgpu_debugfs_init(struct drm_minor *minor);
1741 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1742 #endif
1743
1744 /*
1745 * amdgpu smumgr functions
1746 */
1747 struct amdgpu_smumgr_funcs {
1748 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1749 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1750 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1751 };
1752
1753 /*
1754 * amdgpu smumgr
1755 */
1756 struct amdgpu_smumgr {
1757 struct amdgpu_bo *toc_buf;
1758 struct amdgpu_bo *smu_buf;
1759 /* asic priv smu data */
1760 void *priv;
1761 spinlock_t smu_lock;
1762 /* smumgr functions */
1763 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1764 /* ucode loading complete flag */
1765 uint32_t fw_flags;
1766 };
1767
1768 /*
1769 * ASIC specific register table accessible by UMD
1770 */
1771 struct amdgpu_allowed_register_entry {
1772 uint32_t reg_offset;
1773 bool untouched;
1774 bool grbm_indexed;
1775 };
1776
1777 struct amdgpu_cu_info {
1778 uint32_t number; /* total active CU number */
1779 uint32_t ao_cu_mask;
1780 uint32_t bitmap[4][4];
1781 };
1782
1783
1784 /*
1785 * ASIC specific functions.
1786 */
1787 struct amdgpu_asic_funcs {
1788 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1789 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1790 u8 *bios, u32 length_bytes);
1791 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1792 u32 sh_num, u32 reg_offset, u32 *value);
1793 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1794 int (*reset)(struct amdgpu_device *adev);
1795 /* wait for mc_idle */
1796 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1797 /* get the reference clock */
1798 u32 (*get_xclk)(struct amdgpu_device *adev);
1799 /* get the gpu clock counter */
1800 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1801 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1802 /* MM block clocks */
1803 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1804 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1805 };
1806
1807 /*
1808 * IOCTL.
1809 */
1810 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1811 struct drm_file *filp);
1812 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1813 struct drm_file *filp);
1814
1815 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *filp);
1817 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1820 struct drm_file *filp);
1821 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1822 struct drm_file *filp);
1823 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1824 struct drm_file *filp);
1825 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1826 struct drm_file *filp);
1827 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1828 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1829
1830 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1831 struct drm_file *filp);
1832
1833 /* VRAM scratch page for HDP bug, default vram page */
1834 struct amdgpu_vram_scratch {
1835 struct amdgpu_bo *robj;
1836 volatile uint32_t *ptr;
1837 u64 gpu_addr;
1838 };
1839
1840 /*
1841 * ACPI
1842 */
1843 struct amdgpu_atif_notification_cfg {
1844 bool enabled;
1845 int command_code;
1846 };
1847
1848 struct amdgpu_atif_notifications {
1849 bool display_switch;
1850 bool expansion_mode_change;
1851 bool thermal_state;
1852 bool forced_power_state;
1853 bool system_power_state;
1854 bool display_conf_change;
1855 bool px_gfx_switch;
1856 bool brightness_change;
1857 bool dgpu_display_event;
1858 };
1859
1860 struct amdgpu_atif_functions {
1861 bool system_params;
1862 bool sbios_requests;
1863 bool select_active_disp;
1864 bool lid_state;
1865 bool get_tv_standard;
1866 bool set_tv_standard;
1867 bool get_panel_expansion_mode;
1868 bool set_panel_expansion_mode;
1869 bool temperature_change;
1870 bool graphics_device_types;
1871 };
1872
1873 struct amdgpu_atif {
1874 struct amdgpu_atif_notifications notifications;
1875 struct amdgpu_atif_functions functions;
1876 struct amdgpu_atif_notification_cfg notification_cfg;
1877 struct amdgpu_encoder *encoder_for_bl;
1878 };
1879
1880 struct amdgpu_atcs_functions {
1881 bool get_ext_state;
1882 bool pcie_perf_req;
1883 bool pcie_dev_rdy;
1884 bool pcie_bus_width;
1885 };
1886
1887 struct amdgpu_atcs {
1888 struct amdgpu_atcs_functions functions;
1889 };
1890
1891 /*
1892 * CGS
1893 */
1894 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1895 void amdgpu_cgs_destroy_device(void *cgs_device);
1896
1897
1898 /*
1899 * Core structure, functions and helpers.
1900 */
1901 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1902 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1903
1904 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1905 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1906
1907 struct amdgpu_ip_block_status {
1908 bool valid;
1909 bool sw;
1910 bool hw;
1911 };
1912
1913 struct amdgpu_device {
1914 struct device *dev;
1915 struct drm_device *ddev;
1916 struct pci_dev *pdev;
1917
1918 /* ASIC */
1919 enum amd_asic_type asic_type;
1920 uint32_t family;
1921 uint32_t rev_id;
1922 uint32_t external_rev_id;
1923 unsigned long flags;
1924 int usec_timeout;
1925 const struct amdgpu_asic_funcs *asic_funcs;
1926 bool shutdown;
1927 bool suspend;
1928 bool need_dma32;
1929 bool accel_working;
1930 struct work_struct reset_work;
1931 struct notifier_block acpi_nb;
1932 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1933 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1934 unsigned debugfs_count;
1935 #if defined(CONFIG_DEBUG_FS)
1936 struct dentry *debugfs_regs;
1937 #endif
1938 struct amdgpu_atif atif;
1939 struct amdgpu_atcs atcs;
1940 struct mutex srbm_mutex;
1941 /* GRBM index mutex. Protects concurrent access to GRBM index */
1942 struct mutex grbm_idx_mutex;
1943 struct dev_pm_domain vga_pm_domain;
1944 bool have_disp_power_ref;
1945
1946 /* BIOS */
1947 uint8_t *bios;
1948 bool is_atom_bios;
1949 uint16_t bios_header_start;
1950 struct amdgpu_bo *stollen_vga_memory;
1951 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1952
1953 /* Register/doorbell mmio */
1954 resource_size_t rmmio_base;
1955 resource_size_t rmmio_size;
1956 void __iomem *rmmio;
1957 /* protects concurrent MM_INDEX/DATA based register access */
1958 spinlock_t mmio_idx_lock;
1959 /* protects concurrent SMC based register access */
1960 spinlock_t smc_idx_lock;
1961 amdgpu_rreg_t smc_rreg;
1962 amdgpu_wreg_t smc_wreg;
1963 /* protects concurrent PCIE register access */
1964 spinlock_t pcie_idx_lock;
1965 amdgpu_rreg_t pcie_rreg;
1966 amdgpu_wreg_t pcie_wreg;
1967 /* protects concurrent UVD register access */
1968 spinlock_t uvd_ctx_idx_lock;
1969 amdgpu_rreg_t uvd_ctx_rreg;
1970 amdgpu_wreg_t uvd_ctx_wreg;
1971 /* protects concurrent DIDT register access */
1972 spinlock_t didt_idx_lock;
1973 amdgpu_rreg_t didt_rreg;
1974 amdgpu_wreg_t didt_wreg;
1975 /* protects concurrent ENDPOINT (audio) register access */
1976 spinlock_t audio_endpt_idx_lock;
1977 amdgpu_block_rreg_t audio_endpt_rreg;
1978 amdgpu_block_wreg_t audio_endpt_wreg;
1979 void __iomem *rio_mem;
1980 resource_size_t rio_mem_size;
1981 struct amdgpu_doorbell doorbell;
1982
1983 /* clock/pll info */
1984 struct amdgpu_clock clock;
1985
1986 /* MC */
1987 struct amdgpu_mc mc;
1988 struct amdgpu_gart gart;
1989 struct amdgpu_dummy_page dummy_page;
1990 struct amdgpu_vm_manager vm_manager;
1991
1992 /* memory management */
1993 struct amdgpu_mman mman;
1994 struct amdgpu_gem gem;
1995 struct amdgpu_vram_scratch vram_scratch;
1996 struct amdgpu_wb wb;
1997 atomic64_t vram_usage;
1998 atomic64_t vram_vis_usage;
1999 atomic64_t gtt_usage;
2000 atomic64_t num_bytes_moved;
2001 atomic_t gpu_reset_counter;
2002
2003 /* display */
2004 struct amdgpu_mode_info mode_info;
2005 struct work_struct hotplug_work;
2006 struct amdgpu_irq_src crtc_irq;
2007 struct amdgpu_irq_src pageflip_irq;
2008 struct amdgpu_irq_src hpd_irq;
2009
2010 /* rings */
2011 unsigned fence_context;
2012 struct mutex ring_lock;
2013 unsigned num_rings;
2014 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2015 bool ib_pool_ready;
2016 struct amdgpu_sa_manager ring_tmp_bo;
2017
2018 /* interrupts */
2019 struct amdgpu_irq irq;
2020
2021 /* powerplay */
2022 struct amd_powerplay powerplay;
2023 bool pp_enabled;
2024
2025 /* dpm */
2026 struct amdgpu_pm pm;
2027 u32 cg_flags;
2028 u32 pg_flags;
2029
2030 /* amdgpu smumgr */
2031 struct amdgpu_smumgr smu;
2032
2033 /* gfx */
2034 struct amdgpu_gfx gfx;
2035
2036 /* sdma */
2037 struct amdgpu_sdma sdma;
2038
2039 /* uvd */
2040 bool has_uvd;
2041 struct amdgpu_uvd uvd;
2042
2043 /* vce */
2044 struct amdgpu_vce vce;
2045
2046 /* firmwares */
2047 struct amdgpu_firmware firmware;
2048
2049 /* GDS */
2050 struct amdgpu_gds gds;
2051
2052 const struct amdgpu_ip_block_version *ip_blocks;
2053 int num_ip_blocks;
2054 struct amdgpu_ip_block_status *ip_block_status;
2055 struct mutex mn_lock;
2056 DECLARE_HASHTABLE(mn_hash, 7);
2057
2058 /* tracking pinned memory */
2059 u64 vram_pin_size;
2060 u64 gart_pin_size;
2061
2062 /* amdkfd interface */
2063 struct kfd_dev *kfd;
2064
2065 /* kernel conext for IB submission */
2066 struct amdgpu_ctx kernel_ctx;
2067 };
2068
2069 bool amdgpu_device_is_px(struct drm_device *dev);
2070 int amdgpu_device_init(struct amdgpu_device *adev,
2071 struct drm_device *ddev,
2072 struct pci_dev *pdev,
2073 uint32_t flags);
2074 void amdgpu_device_fini(struct amdgpu_device *adev);
2075 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2076
2077 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2078 bool always_indirect);
2079 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2080 bool always_indirect);
2081 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2082 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2083
2084 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2085 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2086
2087 /*
2088 * Cast helper
2089 */
2090 extern const struct fence_ops amdgpu_fence_ops;
2091 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2092 {
2093 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2094
2095 if (__f->base.ops == &amdgpu_fence_ops)
2096 return __f;
2097
2098 return NULL;
2099 }
2100
2101 /*
2102 * Registers read & write functions.
2103 */
2104 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2105 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2106 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2107 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2108 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2109 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2110 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2111 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2112 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2113 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2114 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2115 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2116 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2117 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2118 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2119 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2120 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2121 #define WREG32_P(reg, val, mask) \
2122 do { \
2123 uint32_t tmp_ = RREG32(reg); \
2124 tmp_ &= (mask); \
2125 tmp_ |= ((val) & ~(mask)); \
2126 WREG32(reg, tmp_); \
2127 } while (0)
2128 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2129 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2130 #define WREG32_PLL_P(reg, val, mask) \
2131 do { \
2132 uint32_t tmp_ = RREG32_PLL(reg); \
2133 tmp_ &= (mask); \
2134 tmp_ |= ((val) & ~(mask)); \
2135 WREG32_PLL(reg, tmp_); \
2136 } while (0)
2137 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2138 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2139 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2140
2141 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2142 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2143
2144 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2145 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2146
2147 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2148 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2149 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2150
2151 #define REG_GET_FIELD(value, reg, field) \
2152 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2153
2154 /*
2155 * BIOS helpers.
2156 */
2157 #define RBIOS8(i) (adev->bios[i])
2158 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2159 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2160
2161 /*
2162 * RING helpers.
2163 */
2164 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2165 {
2166 if (ring->count_dw <= 0)
2167 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2168 ring->ring[ring->wptr++] = v;
2169 ring->wptr &= ring->ptr_mask;
2170 ring->count_dw--;
2171 ring->ring_free_dw--;
2172 }
2173
2174 static inline struct amdgpu_sdma_instance *
2175 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2176 {
2177 struct amdgpu_device *adev = ring->adev;
2178 int i;
2179
2180 for (i = 0; i < adev->sdma.num_instances; i++)
2181 if (&adev->sdma.instance[i].ring == ring)
2182 break;
2183
2184 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2185 return &adev->sdma.instance[i];
2186 else
2187 return NULL;
2188 }
2189
2190 /*
2191 * ASICs macro.
2192 */
2193 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2194 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2195 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2196 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2197 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2198 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2199 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2200 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2201 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2202 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2203 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2204 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2205 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2206 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2207 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2208 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2209 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2210 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2211 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2212 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2213 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2214 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2215 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2216 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2217 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2218 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2219 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2220 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2221 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2222 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2223 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2224 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2225 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2226 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2227 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2228 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2229 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2230 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2231 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2232 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2233 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2234 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2235 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2236 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2237 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2238 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2239 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2240 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2241 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2242 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2243 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2244 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2245 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2246 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2247 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2248 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2249
2250 #define amdgpu_dpm_get_temperature(adev) \
2251 ((adev)->pp_enabled ? \
2252 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2253 (adev)->pm.funcs->get_temperature((adev)))
2254
2255 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2256 ((adev)->pp_enabled ? \
2257 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2258 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2259
2260 #define amdgpu_dpm_get_fan_control_mode(adev) \
2261 ((adev)->pp_enabled ? \
2262 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2263 (adev)->pm.funcs->get_fan_control_mode((adev)))
2264
2265 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2266 ((adev)->pp_enabled ? \
2267 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2268 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2269
2270 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2271 ((adev)->pp_enabled ? \
2272 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2273 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2274
2275 #define amdgpu_dpm_get_sclk(adev, l) \
2276 ((adev)->pp_enabled ? \
2277 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2278 (adev)->pm.funcs->get_sclk((adev), (l)))
2279
2280 #define amdgpu_dpm_get_mclk(adev, l) \
2281 ((adev)->pp_enabled ? \
2282 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2283 (adev)->pm.funcs->get_mclk((adev), (l)))
2284
2285
2286 #define amdgpu_dpm_force_performance_level(adev, l) \
2287 ((adev)->pp_enabled ? \
2288 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2289 (adev)->pm.funcs->force_performance_level((adev), (l)))
2290
2291 #define amdgpu_dpm_powergate_uvd(adev, g) \
2292 ((adev)->pp_enabled ? \
2293 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2294 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2295
2296 #define amdgpu_dpm_powergate_vce(adev, g) \
2297 ((adev)->pp_enabled ? \
2298 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2299 (adev)->pm.funcs->powergate_vce((adev), (g)))
2300
2301 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2302 ((adev)->pp_enabled ? \
2303 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2304 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2305
2306 #define amdgpu_dpm_get_current_power_state(adev) \
2307 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2308
2309 #define amdgpu_dpm_get_performance_level(adev) \
2310 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2311
2312 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2313 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2314
2315 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2316
2317 /* Common functions */
2318 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2319 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2320 bool amdgpu_card_posted(struct amdgpu_device *adev);
2321 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2322 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2323
2324 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2325 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2326 u32 ip_instance, u32 ring,
2327 struct amdgpu_ring **out_ring);
2328 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2329 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2330 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2331 uint32_t flags);
2332 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2333 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2334 unsigned long end);
2335 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2336 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2337 struct ttm_mem_reg *mem);
2338 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2339 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2340 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2341 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2342 const u32 *registers,
2343 const u32 array_size);
2344
2345 bool amdgpu_device_is_px(struct drm_device *dev);
2346 /* atpx handler */
2347 #if defined(CONFIG_VGA_SWITCHEROO)
2348 void amdgpu_register_atpx_handler(void);
2349 void amdgpu_unregister_atpx_handler(void);
2350 #else
2351 static inline void amdgpu_register_atpx_handler(void) {}
2352 static inline void amdgpu_unregister_atpx_handler(void) {}
2353 #endif
2354
2355 /*
2356 * KMS
2357 */
2358 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2359 extern int amdgpu_max_kms_ioctl;
2360
2361 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2362 int amdgpu_driver_unload_kms(struct drm_device *dev);
2363 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2364 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2365 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2366 struct drm_file *file_priv);
2367 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2368 struct drm_file *file_priv);
2369 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2370 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2371 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2372 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2373 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2374 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2375 int *max_error,
2376 struct timeval *vblank_time,
2377 unsigned flags);
2378 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2379 unsigned long arg);
2380
2381 /*
2382 * functions used by amdgpu_encoder.c
2383 */
2384 struct amdgpu_afmt_acr {
2385 u32 clock;
2386
2387 int n_32khz;
2388 int cts_32khz;
2389
2390 int n_44_1khz;
2391 int cts_44_1khz;
2392
2393 int n_48khz;
2394 int cts_48khz;
2395
2396 };
2397
2398 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2399
2400 /* amdgpu_acpi.c */
2401 #if defined(CONFIG_ACPI)
2402 int amdgpu_acpi_init(struct amdgpu_device *adev);
2403 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2404 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2405 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2406 u8 perf_req, bool advertise);
2407 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2408 #else
2409 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2410 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2411 #endif
2412
2413 struct amdgpu_bo_va_mapping *
2414 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2415 uint64_t addr, struct amdgpu_bo **bo);
2416
2417 #include "amdgpu_object.h"
2418
2419 #endif
Linux kernel - Deliverables
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