2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
57 #include "gpu_scheduler.h"
62 extern int amdgpu_modeset
;
63 extern int amdgpu_vram_limit
;
64 extern int amdgpu_gart_size
;
65 extern int amdgpu_benchmarking
;
66 extern int amdgpu_testing
;
67 extern int amdgpu_audio
;
68 extern int amdgpu_disp_priority
;
69 extern int amdgpu_hw_i2c
;
70 extern int amdgpu_pcie_gen2
;
71 extern int amdgpu_msi
;
72 extern int amdgpu_lockup_timeout
;
73 extern int amdgpu_dpm
;
74 extern int amdgpu_smc_load_fw
;
75 extern int amdgpu_aspm
;
76 extern int amdgpu_runtime_pm
;
77 extern unsigned amdgpu_ip_block_mask
;
78 extern int amdgpu_bapm
;
79 extern int amdgpu_deep_color
;
80 extern int amdgpu_vm_size
;
81 extern int amdgpu_vm_block_size
;
82 extern int amdgpu_vm_fault_stop
;
83 extern int amdgpu_vm_debug
;
84 extern int amdgpu_sched_jobs
;
85 extern int amdgpu_sched_hw_submission
;
86 extern int amdgpu_powerplay
;
88 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
89 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
90 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
91 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
92 #define AMDGPU_IB_POOL_SIZE 16
93 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
94 #define AMDGPUFB_CONN_LIMIT 4
95 #define AMDGPU_BIOS_NUM_SCRATCH 8
97 /* max number of rings */
98 #define AMDGPU_MAX_RINGS 16
99 #define AMDGPU_MAX_GFX_RINGS 1
100 #define AMDGPU_MAX_COMPUTE_RINGS 8
101 #define AMDGPU_MAX_VCE_RINGS 2
103 /* max number of IP instances */
104 #define AMDGPU_MAX_SDMA_INSTANCES 2
106 /* number of hw syncs before falling back on blocking */
107 #define AMDGPU_NUM_SYNCS 4
109 /* hardcode that limit for now */
110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
112 /* hard reset data */
113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
116 #define AMDGPU_RESET_GFX (1 << 0)
117 #define AMDGPU_RESET_COMPUTE (1 << 1)
118 #define AMDGPU_RESET_DMA (1 << 2)
119 #define AMDGPU_RESET_CP (1 << 3)
120 #define AMDGPU_RESET_GRBM (1 << 4)
121 #define AMDGPU_RESET_DMA1 (1 << 5)
122 #define AMDGPU_RESET_RLC (1 << 6)
123 #define AMDGPU_RESET_SEM (1 << 7)
124 #define AMDGPU_RESET_IH (1 << 8)
125 #define AMDGPU_RESET_VMC (1 << 9)
126 #define AMDGPU_RESET_MC (1 << 10)
127 #define AMDGPU_RESET_DISPLAY (1 << 11)
128 #define AMDGPU_RESET_UVD (1 << 12)
129 #define AMDGPU_RESET_VCE (1 << 13)
130 #define AMDGPU_RESET_VCE1 (1 << 14)
133 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
134 #define AMDGPU_CG_BLOCK_MC (1 << 1)
135 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
136 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
137 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
138 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
139 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
142 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
143 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
144 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
145 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
146 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
147 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
148 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
149 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
150 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
151 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
152 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
153 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
154 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
155 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
156 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
157 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
158 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
161 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
162 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
163 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
164 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
165 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
166 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
167 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
168 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
169 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
170 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
171 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
173 /* GFX current status */
174 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
175 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
176 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
177 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
178 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
180 /* max cursor sizes (in pixels) */
181 #define CIK_CURSOR_WIDTH 128
182 #define CIK_CURSOR_HEIGHT 128
184 struct amdgpu_device
;
189 struct amdgpu_cs_parser
;
191 struct amdgpu_irq_src
;
195 AMDGPU_CP_IRQ_GFX_EOP
= 0,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
208 enum amdgpu_sdma_irq
{
209 AMDGPU_SDMA_IRQ_TRAP0
= 0,
210 AMDGPU_SDMA_IRQ_TRAP1
,
215 enum amdgpu_thermal_irq
{
216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
219 AMDGPU_THERMAL_IRQ_LAST
222 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
223 enum amd_ip_block_type block_type
,
224 enum amd_clockgating_state state
);
225 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
226 enum amd_ip_block_type block_type
,
227 enum amd_powergating_state state
);
229 struct amdgpu_ip_block_version
{
230 enum amd_ip_block_type type
;
234 const struct amd_ip_funcs
*funcs
;
237 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
238 enum amd_ip_block_type type
,
239 u32 major
, u32 minor
);
241 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
242 struct amdgpu_device
*adev
,
243 enum amd_ip_block_type type
);
245 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
246 struct amdgpu_buffer_funcs
{
247 /* maximum bytes in a single operation */
248 uint32_t copy_max_bytes
;
250 /* number of dw to reserve per operation */
251 unsigned copy_num_dw
;
253 /* used for buffer migration */
254 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
255 /* src addr in bytes */
257 /* dst addr in bytes */
259 /* number of byte to transfer */
260 uint32_t byte_count
);
262 /* maximum bytes in a single operation */
263 uint32_t fill_max_bytes
;
265 /* number of dw to reserve per operation */
266 unsigned fill_num_dw
;
268 /* used for buffer clearing */
269 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
270 /* value to write to memory */
272 /* dst addr in bytes */
274 /* number of byte to fill */
275 uint32_t byte_count
);
278 /* provided by hw blocks that can write ptes, e.g., sdma */
279 struct amdgpu_vm_pte_funcs
{
280 /* copy pte entries from GART */
281 void (*copy_pte
)(struct amdgpu_ib
*ib
,
282 uint64_t pe
, uint64_t src
,
284 /* write pte one entry at a time with addr mapping */
285 void (*write_pte
)(struct amdgpu_ib
*ib
,
287 uint64_t addr
, unsigned count
,
288 uint32_t incr
, uint32_t flags
);
289 /* for linear pte/pde updates without addr mapping */
290 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
292 uint64_t addr
, unsigned count
,
293 uint32_t incr
, uint32_t flags
);
294 /* pad the indirect buffer to the necessary number of dw */
295 void (*pad_ib
)(struct amdgpu_ib
*ib
);
298 /* provided by the gmc block */
299 struct amdgpu_gart_funcs
{
300 /* flush the vm tlb via mmio */
301 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
303 /* write pte/pde updates using the cpu */
304 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
305 void *cpu_pt_addr
, /* cpu addr of page table */
306 uint32_t gpu_page_idx
, /* pte/pde to update */
307 uint64_t addr
, /* addr to write into pte/pde */
308 uint32_t flags
); /* access flags */
311 /* provided by the ih block */
312 struct amdgpu_ih_funcs
{
313 /* ring read/write ptr handling, called from interrupt context */
314 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
315 void (*decode_iv
)(struct amdgpu_device
*adev
,
316 struct amdgpu_iv_entry
*entry
);
317 void (*set_rptr
)(struct amdgpu_device
*adev
);
320 /* provided by hw blocks that expose a ring buffer for commands */
321 struct amdgpu_ring_funcs
{
322 /* ring read/write ptr handling */
323 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
324 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
325 void (*set_wptr
)(struct amdgpu_ring
*ring
);
326 /* validating and patching of IBs */
327 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
328 /* command emit functions */
329 void (*emit_ib
)(struct amdgpu_ring
*ring
,
330 struct amdgpu_ib
*ib
);
331 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
332 uint64_t seq
, unsigned flags
);
333 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
335 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
336 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
337 uint32_t gds_base
, uint32_t gds_size
,
338 uint32_t gws_base
, uint32_t gws_size
,
339 uint32_t oa_base
, uint32_t oa_size
);
340 /* testing functions */
341 int (*test_ring
)(struct amdgpu_ring
*ring
);
342 int (*test_ib
)(struct amdgpu_ring
*ring
);
343 /* insert NOP packets */
344 void (*insert_nop
)(struct amdgpu_ring
*ring
, uint32_t count
);
350 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
351 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
356 struct amdgpu_dummy_page
{
360 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
361 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
368 #define AMDGPU_MAX_PPLL 3
370 struct amdgpu_clock
{
371 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
372 struct amdgpu_pll spll
;
373 struct amdgpu_pll mpll
;
375 uint32_t default_mclk
;
376 uint32_t default_sclk
;
377 uint32_t default_dispclk
;
378 uint32_t current_dispclk
;
380 uint32_t max_pixel_clock
;
386 struct amdgpu_fence_driver
{
388 volatile uint32_t *cpu_addr
;
389 /* sync_seq is protected by ring emission lock */
393 struct amdgpu_irq_src
*irq_src
;
395 struct timer_list fallback_timer
;
396 wait_queue_head_t fence_queue
;
399 /* some special values for the owner field */
400 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
401 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
403 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
404 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
406 struct amdgpu_fence
{
410 struct amdgpu_ring
*ring
;
413 /* filp or special value for fence creator */
416 wait_queue_t fence_wake
;
419 struct amdgpu_user_fence
{
421 struct amdgpu_bo
*bo
;
422 /* write-back address offset to bo start */
426 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
427 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
428 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
430 int amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
);
431 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
432 struct amdgpu_irq_src
*irq_src
,
434 void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev
);
435 void amdgpu_fence_driver_resume(struct amdgpu_device
*adev
);
436 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, void *owner
,
437 struct amdgpu_fence
**fence
);
438 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
439 int amdgpu_fence_wait_next(struct amdgpu_ring
*ring
);
440 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
441 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
447 struct ttm_bo_global_ref bo_global_ref
;
448 struct drm_global_reference mem_global_ref
;
449 struct ttm_bo_device bdev
;
450 bool mem_global_referenced
;
453 #if defined(CONFIG_DEBUG_FS)
458 /* buffer handling */
459 const struct amdgpu_buffer_funcs
*buffer_funcs
;
460 struct amdgpu_ring
*buffer_funcs_ring
;
463 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
467 struct reservation_object
*resv
,
468 struct fence
**fence
);
469 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
471 struct amdgpu_bo_list_entry
{
472 struct amdgpu_bo
*robj
;
473 struct ttm_validate_buffer tv
;
474 struct amdgpu_bo_va
*bo_va
;
478 struct amdgpu_bo_va_mapping
{
479 struct list_head list
;
480 struct interval_tree_node it
;
485 /* bo virtual addresses in a specific vm */
486 struct amdgpu_bo_va
{
488 /* protected by bo being reserved */
489 struct list_head bo_list
;
490 struct fence
*last_pt_update
;
493 /* protected by vm mutex and spinlock */
494 struct list_head vm_status
;
496 /* mappings for this bo_va */
497 struct list_head invalids
;
498 struct list_head valids
;
500 /* constant after initialization */
501 struct amdgpu_vm
*vm
;
502 struct amdgpu_bo
*bo
;
505 #define AMDGPU_GEM_DOMAIN_MAX 0x3
508 /* Protected by gem.mutex */
509 struct list_head list
;
510 /* Protected by tbo.reserved */
511 u32 prefered_domains
;
513 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
514 struct ttm_placement placement
;
515 struct ttm_buffer_object tbo
;
516 struct ttm_bo_kmap_obj kmap
;
524 /* list of all virtual address to which this bo
528 /* Constant after initialization */
529 struct amdgpu_device
*adev
;
530 struct drm_gem_object gem_base
;
531 struct amdgpu_bo
*parent
;
533 struct ttm_bo_kmap_obj dma_buf_vmap
;
535 struct amdgpu_mn
*mn
;
536 struct list_head mn_list
;
538 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
540 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
541 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
542 struct drm_file
*file_priv
);
543 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
544 struct drm_file
*file_priv
);
545 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
546 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
547 struct drm_gem_object
*amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
548 struct dma_buf_attachment
*attach
,
549 struct sg_table
*sg
);
550 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
551 struct drm_gem_object
*gobj
,
553 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
554 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
555 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
556 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
557 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
558 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
560 /* sub-allocation manager, it has to be protected by another lock.
561 * By conception this is an helper for other part of the driver
562 * like the indirect buffer or semaphore, which both have their
565 * Principe is simple, we keep a list of sub allocation in offset
566 * order (first entry has offset == 0, last entry has the highest
569 * When allocating new object we first check if there is room at
570 * the end total_size - (last_object_offset + last_object_size) >=
571 * alloc_size. If so we allocate new object there.
573 * When there is not enough room at the end, we start waiting for
574 * each sub object until we reach object_offset+object_size >=
575 * alloc_size, this object then become the sub object we return.
577 * Alignment can't be bigger than page size.
579 * Hole are not considered for allocation to keep things simple.
580 * Assumption is that there won't be hole (all object on same
583 struct amdgpu_sa_manager
{
584 wait_queue_head_t wq
;
585 struct amdgpu_bo
*bo
;
586 struct list_head
*hole
;
587 struct list_head flist
[AMDGPU_MAX_RINGS
];
588 struct list_head olist
;
598 /* sub-allocation buffer */
599 struct amdgpu_sa_bo
{
600 struct list_head olist
;
601 struct list_head flist
;
602 struct amdgpu_sa_manager
*manager
;
613 struct list_head objects
;
616 int amdgpu_gem_init(struct amdgpu_device
*adev
);
617 void amdgpu_gem_fini(struct amdgpu_device
*adev
);
618 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
619 int alignment
, u32 initial_domain
,
620 u64 flags
, bool kernel
,
621 struct drm_gem_object
**obj
);
623 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
624 struct drm_device
*dev
,
625 struct drm_mode_create_dumb
*args
);
626 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
627 struct drm_device
*dev
,
628 uint32_t handle
, uint64_t *offset_p
);
633 DECLARE_HASHTABLE(fences
, 4);
634 struct fence
*last_vm_update
;
637 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
638 int amdgpu_sync_fence(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
640 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
641 struct amdgpu_sync
*sync
,
642 struct reservation_object
*resv
,
644 struct fence
*amdgpu_sync_get_fence(struct amdgpu_sync
*sync
);
645 int amdgpu_sync_wait(struct amdgpu_sync
*sync
);
646 void amdgpu_sync_free(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
647 struct fence
*fence
);
650 * GART structures, functions & helpers
654 #define AMDGPU_GPU_PAGE_SIZE 4096
655 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
656 #define AMDGPU_GPU_PAGE_SHIFT 12
657 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
660 dma_addr_t table_addr
;
661 struct amdgpu_bo
*robj
;
663 unsigned num_gpu_pages
;
664 unsigned num_cpu_pages
;
667 dma_addr_t
*pages_addr
;
669 const struct amdgpu_gart_funcs
*gart_funcs
;
672 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
673 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
674 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
675 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
676 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
677 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
678 int amdgpu_gart_init(struct amdgpu_device
*adev
);
679 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
680 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, unsigned offset
,
682 int amdgpu_gart_bind(struct amdgpu_device
*adev
, unsigned offset
,
683 int pages
, struct page
**pagelist
,
684 dma_addr_t
*dma_addr
, uint32_t flags
);
687 * GPU MC structures, functions & helpers
690 resource_size_t aper_size
;
691 resource_size_t aper_base
;
692 resource_size_t agp_base
;
693 /* for some chips with <= 32MB we need to lie
694 * about vram size near mc fb location */
696 u64 visible_vram_size
;
707 const struct firmware
*fw
; /* MC firmware */
709 struct amdgpu_irq_src vm_fault
;
714 * GPU doorbell structures, functions & helpers
716 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
718 AMDGPU_DOORBELL_KIQ
= 0x000,
719 AMDGPU_DOORBELL_HIQ
= 0x001,
720 AMDGPU_DOORBELL_DIQ
= 0x002,
721 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
722 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
723 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
724 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
725 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
726 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
727 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
728 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
729 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
730 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
731 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
732 AMDGPU_DOORBELL_IH
= 0x1E8,
733 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
734 AMDGPU_DOORBELL_INVALID
= 0xFFFF
735 } AMDGPU_DOORBELL_ASSIGNMENT
;
737 struct amdgpu_doorbell
{
739 resource_size_t base
;
740 resource_size_t size
;
742 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
745 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
746 phys_addr_t
*aperture_base
,
747 size_t *aperture_size
,
748 size_t *start_offset
);
754 struct amdgpu_flip_work
{
755 struct work_struct flip_work
;
756 struct work_struct unpin_work
;
757 struct amdgpu_device
*adev
;
760 struct drm_pending_vblank_event
*event
;
761 struct amdgpu_bo
*old_rbo
;
763 unsigned shared_count
;
764 struct fence
**shared
;
773 struct amdgpu_sa_bo
*sa_bo
;
777 struct amdgpu_ring
*ring
;
778 struct amdgpu_fence
*fence
;
779 struct amdgpu_user_fence
*user
;
781 struct amdgpu_vm
*vm
;
782 struct amdgpu_ctx
*ctx
;
783 struct amdgpu_sync sync
;
784 uint32_t gds_base
, gds_size
;
785 uint32_t gws_base
, gws_size
;
786 uint32_t oa_base
, oa_size
;
788 /* resulting sequence number */
792 enum amdgpu_ring_type
{
793 AMDGPU_RING_TYPE_GFX
,
794 AMDGPU_RING_TYPE_COMPUTE
,
795 AMDGPU_RING_TYPE_SDMA
,
796 AMDGPU_RING_TYPE_UVD
,
800 extern struct amd_sched_backend_ops amdgpu_sched_ops
;
802 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device
*adev
,
803 struct amdgpu_ring
*ring
,
804 struct amdgpu_ib
*ibs
,
806 int (*free_job
)(struct amdgpu_job
*),
808 struct fence
**fence
);
811 struct amdgpu_device
*adev
;
812 const struct amdgpu_ring_funcs
*funcs
;
813 struct amdgpu_fence_driver fence_drv
;
814 struct amd_gpu_scheduler sched
;
816 spinlock_t fence_lock
;
817 struct mutex
*ring_lock
;
818 struct amdgpu_bo
*ring_obj
;
819 volatile uint32_t *ring
;
821 u64 next_rptr_gpu_addr
;
822 volatile u32
*next_rptr_cpu_addr
;
826 unsigned ring_free_dw
;
837 struct amdgpu_bo
*mqd_obj
;
841 unsigned next_rptr_offs
;
843 struct amdgpu_ctx
*current_ctx
;
844 enum amdgpu_ring_type type
;
853 /* maximum number of VMIDs */
854 #define AMDGPU_NUM_VM 16
856 /* number of entries in page table */
857 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
859 /* PTBs (Page Table Blocks) need to be aligned to 32K */
860 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
861 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
862 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
864 #define AMDGPU_PTE_VALID (1 << 0)
865 #define AMDGPU_PTE_SYSTEM (1 << 1)
866 #define AMDGPU_PTE_SNOOPED (1 << 2)
869 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
871 #define AMDGPU_PTE_READABLE (1 << 5)
872 #define AMDGPU_PTE_WRITEABLE (1 << 6)
874 /* PTE (Page Table Entry) fragment field for different page sizes */
875 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
876 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
877 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
879 /* How to programm VM fault handling */
880 #define AMDGPU_VM_FAULT_STOP_NEVER 0
881 #define AMDGPU_VM_FAULT_STOP_FIRST 1
882 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
884 struct amdgpu_vm_pt
{
885 struct amdgpu_bo_list_entry entry
;
889 struct amdgpu_vm_id
{
891 uint64_t pd_gpu_addr
;
892 /* last flushed PD/PT update */
893 struct fence
*flushed_updates
;
897 /* tree of virtual addresses mapped */
901 /* protecting invalidated */
902 spinlock_t status_lock
;
904 /* BOs moved, but not yet updated in the PT */
905 struct list_head invalidated
;
907 /* BOs cleared in the PT because of a move */
908 struct list_head cleared
;
910 /* BO mappings freed, but not yet updated in the PT */
911 struct list_head freed
;
913 /* contains the page directory */
914 struct amdgpu_bo
*page_directory
;
915 unsigned max_pde_used
;
916 struct fence
*page_directory_fence
;
918 /* array of page tables, one for each page directory entry */
919 struct amdgpu_vm_pt
*page_tables
;
921 /* for id and flush management per ring */
922 struct amdgpu_vm_id ids
[AMDGPU_MAX_RINGS
];
924 /* protecting freed */
925 spinlock_t freed_lock
;
928 struct amdgpu_vm_manager
{
933 struct fence
*active
;
935 } ids
[AMDGPU_NUM_VM
];
938 /* number of VMIDs */
940 /* vram base address for page table entry */
941 u64 vram_base_offset
;
944 /* vm pte handling */
945 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
946 struct amdgpu_ring
*vm_pte_funcs_ring
;
949 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
);
950 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
951 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
952 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
953 struct list_head
*validated
,
954 struct amdgpu_bo_list_entry
*entry
);
955 void amdgpu_vm_get_pt_bos(struct amdgpu_vm
*vm
, struct list_head
*duplicates
);
956 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
957 struct amdgpu_vm
*vm
);
958 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
959 struct amdgpu_sync
*sync
, struct fence
*fence
);
960 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
961 struct amdgpu_vm
*vm
,
962 struct fence
*updates
);
963 uint64_t amdgpu_vm_map_gart(struct amdgpu_device
*adev
, uint64_t addr
);
964 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
965 struct amdgpu_vm
*vm
);
966 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
967 struct amdgpu_vm
*vm
);
968 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
969 struct amdgpu_sync
*sync
);
970 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
971 struct amdgpu_bo_va
*bo_va
,
972 struct ttm_mem_reg
*mem
);
973 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
974 struct amdgpu_bo
*bo
);
975 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
976 struct amdgpu_bo
*bo
);
977 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
978 struct amdgpu_vm
*vm
,
979 struct amdgpu_bo
*bo
);
980 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
981 struct amdgpu_bo_va
*bo_va
,
982 uint64_t addr
, uint64_t offset
,
983 uint64_t size
, uint32_t flags
);
984 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
985 struct amdgpu_bo_va
*bo_va
,
987 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
988 struct amdgpu_bo_va
*bo_va
);
989 int amdgpu_vm_free_job(struct amdgpu_job
*job
);
992 * context related structures
995 struct amdgpu_ctx_ring
{
997 struct fence
**fences
;
998 struct amd_sched_entity entity
;
1002 struct kref refcount
;
1003 struct amdgpu_device
*adev
;
1004 unsigned reset_counter
;
1005 spinlock_t ring_lock
;
1006 struct fence
**fences
;
1007 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
1010 struct amdgpu_ctx_mgr
{
1011 struct amdgpu_device
*adev
;
1013 /* protected by lock */
1014 struct idr ctx_handles
;
1017 int amdgpu_ctx_init(struct amdgpu_device
*adev
, enum amd_sched_priority pri
,
1018 struct amdgpu_ctx
*ctx
);
1019 void amdgpu_ctx_fini(struct amdgpu_ctx
*ctx
);
1021 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
1022 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
1024 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
1025 struct fence
*fence
);
1026 struct fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
1027 struct amdgpu_ring
*ring
, uint64_t seq
);
1029 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
1030 struct drm_file
*filp
);
1032 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
1033 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
1036 * file private structure
1039 struct amdgpu_fpriv
{
1040 struct amdgpu_vm vm
;
1041 struct mutex bo_list_lock
;
1042 struct idr bo_list_handles
;
1043 struct amdgpu_ctx_mgr ctx_mgr
;
1050 struct amdgpu_bo_list
{
1052 struct amdgpu_bo
*gds_obj
;
1053 struct amdgpu_bo
*gws_obj
;
1054 struct amdgpu_bo
*oa_obj
;
1056 unsigned num_entries
;
1057 struct amdgpu_bo_list_entry
*array
;
1060 struct amdgpu_bo_list
*
1061 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1062 void amdgpu_bo_list_get_list(struct amdgpu_bo_list
*list
,
1063 struct list_head
*validated
);
1064 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1065 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1070 #include "clearstate_defs.h"
1073 /* for power gating */
1074 struct amdgpu_bo
*save_restore_obj
;
1075 uint64_t save_restore_gpu_addr
;
1076 volatile uint32_t *sr_ptr
;
1077 const u32
*reg_list
;
1079 /* for clear state */
1080 struct amdgpu_bo
*clear_state_obj
;
1081 uint64_t clear_state_gpu_addr
;
1082 volatile uint32_t *cs_ptr
;
1083 const struct cs_section_def
*cs_data
;
1084 u32 clear_state_size
;
1086 struct amdgpu_bo
*cp_table_obj
;
1087 uint64_t cp_table_gpu_addr
;
1088 volatile uint32_t *cp_table_ptr
;
1093 struct amdgpu_bo
*hpd_eop_obj
;
1094 u64 hpd_eop_gpu_addr
;
1101 * GPU scratch registers structures, functions & helpers
1103 struct amdgpu_scratch
{
1111 * GFX configurations
1113 struct amdgpu_gca_config
{
1114 unsigned max_shader_engines
;
1115 unsigned max_tile_pipes
;
1116 unsigned max_cu_per_sh
;
1117 unsigned max_sh_per_se
;
1118 unsigned max_backends_per_se
;
1119 unsigned max_texture_channel_caches
;
1121 unsigned max_gs_threads
;
1122 unsigned max_hw_contexts
;
1123 unsigned sc_prim_fifo_size_frontend
;
1124 unsigned sc_prim_fifo_size_backend
;
1125 unsigned sc_hiz_tile_fifo_size
;
1126 unsigned sc_earlyz_tile_fifo_size
;
1128 unsigned num_tile_pipes
;
1129 unsigned backend_enable_mask
;
1130 unsigned mem_max_burst_length_bytes
;
1131 unsigned mem_row_size_in_kb
;
1132 unsigned shader_engine_tile_size
;
1134 unsigned multi_gpu_tile_size
;
1135 unsigned mc_arb_ramcfg
;
1136 unsigned gb_addr_config
;
1138 uint32_t tile_mode_array
[32];
1139 uint32_t macrotile_mode_array
[16];
1143 struct mutex gpu_clock_mutex
;
1144 struct amdgpu_gca_config config
;
1145 struct amdgpu_rlc rlc
;
1146 struct amdgpu_mec mec
;
1147 struct amdgpu_scratch scratch
;
1148 const struct firmware
*me_fw
; /* ME firmware */
1149 uint32_t me_fw_version
;
1150 const struct firmware
*pfp_fw
; /* PFP firmware */
1151 uint32_t pfp_fw_version
;
1152 const struct firmware
*ce_fw
; /* CE firmware */
1153 uint32_t ce_fw_version
;
1154 const struct firmware
*rlc_fw
; /* RLC firmware */
1155 uint32_t rlc_fw_version
;
1156 const struct firmware
*mec_fw
; /* MEC firmware */
1157 uint32_t mec_fw_version
;
1158 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1159 uint32_t mec2_fw_version
;
1160 uint32_t me_feature_version
;
1161 uint32_t ce_feature_version
;
1162 uint32_t pfp_feature_version
;
1163 uint32_t rlc_feature_version
;
1164 uint32_t mec_feature_version
;
1165 uint32_t mec2_feature_version
;
1166 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1167 unsigned num_gfx_rings
;
1168 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1169 unsigned num_compute_rings
;
1170 struct amdgpu_irq_src eop_irq
;
1171 struct amdgpu_irq_src priv_reg_irq
;
1172 struct amdgpu_irq_src priv_inst_irq
;
1174 uint32_t gfx_current_status
;
1176 unsigned ce_ram_size
;
1179 int amdgpu_ib_get(struct amdgpu_ring
*ring
, struct amdgpu_vm
*vm
,
1180 unsigned size
, struct amdgpu_ib
*ib
);
1181 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
);
1182 int amdgpu_ib_schedule(struct amdgpu_device
*adev
, unsigned num_ibs
,
1183 struct amdgpu_ib
*ib
, void *owner
);
1184 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1185 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1186 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1187 /* Ring access between begin & end cannot sleep */
1188 void amdgpu_ring_free_size(struct amdgpu_ring
*ring
);
1189 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1190 int amdgpu_ring_lock(struct amdgpu_ring
*ring
, unsigned ndw
);
1191 void amdgpu_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
);
1192 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1193 void amdgpu_ring_unlock_commit(struct amdgpu_ring
*ring
);
1194 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1195 void amdgpu_ring_unlock_undo(struct amdgpu_ring
*ring
);
1196 unsigned amdgpu_ring_backup(struct amdgpu_ring
*ring
,
1198 int amdgpu_ring_restore(struct amdgpu_ring
*ring
,
1199 unsigned size
, uint32_t *data
);
1200 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1201 unsigned ring_size
, u32 nop
, u32 align_mask
,
1202 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1203 enum amdgpu_ring_type ring_type
);
1204 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1205 struct amdgpu_ring
*amdgpu_ring_from_fence(struct fence
*f
);
1210 struct amdgpu_cs_chunk
{
1216 struct amdgpu_cs_parser
{
1217 struct amdgpu_device
*adev
;
1218 struct drm_file
*filp
;
1219 struct amdgpu_ctx
*ctx
;
1223 struct amdgpu_cs_chunk
*chunks
;
1225 /* indirect buffers */
1227 struct amdgpu_ib
*ibs
;
1229 /* buffer objects */
1230 struct ww_acquire_ctx ticket
;
1231 struct amdgpu_bo_list
*bo_list
;
1232 struct amdgpu_bo_list_entry vm_pd
;
1233 struct list_head validated
;
1234 struct fence
*fence
;
1235 uint64_t bytes_moved_threshold
;
1236 uint64_t bytes_moved
;
1239 struct amdgpu_user_fence uf
;
1240 struct amdgpu_bo_list_entry uf_entry
;
1244 struct amd_sched_job base
;
1245 struct amdgpu_device
*adev
;
1246 struct amdgpu_ib
*ibs
;
1249 struct amdgpu_user_fence uf
;
1250 int (*free_job
)(struct amdgpu_job
*job
);
1252 #define to_amdgpu_job(sched_job) \
1253 container_of((sched_job), struct amdgpu_job, base)
1255 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
, int idx
)
1257 return p
->ibs
[ib_idx
].ptr
[idx
];
1263 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1266 struct amdgpu_bo
*wb_obj
;
1267 volatile uint32_t *wb
;
1269 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1270 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1273 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1274 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1278 enum amdgpu_int_thermal_type
{
1280 THERMAL_TYPE_EXTERNAL
,
1281 THERMAL_TYPE_EXTERNAL_GPIO
,
1284 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1285 THERMAL_TYPE_EVERGREEN
,
1289 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1294 enum amdgpu_dpm_auto_throttle_src
{
1295 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1296 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1299 enum amdgpu_dpm_event_src
{
1300 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1301 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1302 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1303 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1304 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1307 #define AMDGPU_MAX_VCE_LEVELS 6
1309 enum amdgpu_vce_level
{
1310 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1311 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1312 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1313 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1314 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1315 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1319 u32 caps
; /* vbios flags */
1320 u32
class; /* vbios flags */
1321 u32 class2
; /* vbios flags */
1329 enum amdgpu_vce_level vce_level
;
1334 struct amdgpu_dpm_thermal
{
1335 /* thermal interrupt work */
1336 struct work_struct work
;
1337 /* low temperature threshold */
1339 /* high temperature threshold */
1341 /* was last interrupt low to high or high to low */
1343 /* interrupt source */
1344 struct amdgpu_irq_src irq
;
1347 enum amdgpu_clk_action
1353 struct amdgpu_blacklist_clocks
1357 enum amdgpu_clk_action action
;
1360 struct amdgpu_clock_and_voltage_limits
{
1367 struct amdgpu_clock_array
{
1372 struct amdgpu_clock_voltage_dependency_entry
{
1377 struct amdgpu_clock_voltage_dependency_table
{
1379 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1382 union amdgpu_cac_leakage_entry
{
1394 struct amdgpu_cac_leakage_table
{
1396 union amdgpu_cac_leakage_entry
*entries
;
1399 struct amdgpu_phase_shedding_limits_entry
{
1405 struct amdgpu_phase_shedding_limits_table
{
1407 struct amdgpu_phase_shedding_limits_entry
*entries
;
1410 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1416 struct amdgpu_uvd_clock_voltage_dependency_table
{
1418 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1421 struct amdgpu_vce_clock_voltage_dependency_entry
{
1427 struct amdgpu_vce_clock_voltage_dependency_table
{
1429 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1432 struct amdgpu_ppm_table
{
1434 u16 cpu_core_number
;
1436 u32 small_ac_platform_tdp
;
1438 u32 small_ac_platform_tdc
;
1445 struct amdgpu_cac_tdp_table
{
1447 u16 configurable_tdp
;
1449 u16 battery_power_limit
;
1450 u16 small_power_limit
;
1451 u16 low_cac_leakage
;
1452 u16 high_cac_leakage
;
1453 u16 maximum_power_delivery_limit
;
1456 struct amdgpu_dpm_dynamic_state
{
1457 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1458 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1459 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1460 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1461 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1462 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1463 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1464 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1465 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1466 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1467 struct amdgpu_clock_array valid_sclk_values
;
1468 struct amdgpu_clock_array valid_mclk_values
;
1469 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1470 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1471 u32 mclk_sclk_ratio
;
1472 u32 sclk_mclk_delta
;
1473 u16 vddc_vddci_delta
;
1474 u16 min_vddc_for_pcie_gen2
;
1475 struct amdgpu_cac_leakage_table cac_leakage_table
;
1476 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1477 struct amdgpu_ppm_table
*ppm_table
;
1478 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1481 struct amdgpu_dpm_fan
{
1492 u16 default_max_fan_pwm
;
1493 u16 default_fan_output_sensitivity
;
1494 u16 fan_output_sensitivity
;
1495 bool ucode_fan_control
;
1498 enum amdgpu_pcie_gen
{
1499 AMDGPU_PCIE_GEN1
= 0,
1500 AMDGPU_PCIE_GEN2
= 1,
1501 AMDGPU_PCIE_GEN3
= 2,
1502 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1505 enum amdgpu_dpm_forced_level
{
1506 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1507 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1508 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1511 struct amdgpu_vce_state
{
1522 struct amdgpu_dpm_funcs
{
1523 int (*get_temperature
)(struct amdgpu_device
*adev
);
1524 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1525 int (*set_power_state
)(struct amdgpu_device
*adev
);
1526 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1527 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1528 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1529 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1530 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1531 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1532 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1533 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1534 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1535 void (*powergate_vce
)(struct amdgpu_device
*adev
, bool gate
);
1536 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1537 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1538 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1539 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1540 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1544 struct amdgpu_ps
*ps
;
1545 /* number of valid power states */
1547 /* current power state that is active */
1548 struct amdgpu_ps
*current_ps
;
1549 /* requested power state */
1550 struct amdgpu_ps
*requested_ps
;
1551 /* boot up power state */
1552 struct amdgpu_ps
*boot_ps
;
1553 /* default uvd power state */
1554 struct amdgpu_ps
*uvd_ps
;
1555 /* vce requirements */
1556 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1557 enum amdgpu_vce_level vce_level
;
1558 enum amd_pm_state_type state
;
1559 enum amd_pm_state_type user_state
;
1561 u32 voltage_response_time
;
1562 u32 backbias_response_time
;
1564 u32 new_active_crtcs
;
1565 int new_active_crtc_count
;
1566 u32 current_active_crtcs
;
1567 int current_active_crtc_count
;
1568 struct amdgpu_dpm_dynamic_state dyn_state
;
1569 struct amdgpu_dpm_fan fan
;
1572 u32 near_tdp_limit_adjusted
;
1573 u32 sq_ramping_threshold
;
1577 u16 load_line_slope
;
1580 /* special states active */
1581 bool thermal_active
;
1584 /* thermal handling */
1585 struct amdgpu_dpm_thermal thermal
;
1587 enum amdgpu_dpm_forced_level forced_level
;
1596 struct amdgpu_i2c_chan
*i2c_bus
;
1597 /* internal thermal controller on rv6xx+ */
1598 enum amdgpu_int_thermal_type int_thermal_type
;
1599 struct device
*int_hwmon_dev
;
1600 /* fan control parameters */
1602 u8 fan_pulses_per_revolution
;
1607 bool sysfs_initialized
;
1608 struct amdgpu_dpm dpm
;
1609 const struct firmware
*fw
; /* SMC firmware */
1610 uint32_t fw_version
;
1611 const struct amdgpu_dpm_funcs
*funcs
;
1612 uint32_t pcie_gen_mask
;
1613 uint32_t pcie_mlw_mask
;
1614 struct amd_pp_display_configuration pm_display_cfg
;/* set by DAL */
1617 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
);
1622 #define AMDGPU_MAX_UVD_HANDLES 10
1623 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1624 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1625 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1628 struct amdgpu_bo
*vcpu_bo
;
1631 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1632 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1633 struct delayed_work idle_work
;
1634 const struct firmware
*fw
; /* UVD firmware */
1635 struct amdgpu_ring ring
;
1636 struct amdgpu_irq_src irq
;
1637 bool address_64_bit
;
1643 #define AMDGPU_MAX_VCE_HANDLES 16
1644 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1646 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1647 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1650 struct amdgpu_bo
*vcpu_bo
;
1652 unsigned fw_version
;
1653 unsigned fb_version
;
1654 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1655 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1656 uint32_t img_size
[AMDGPU_MAX_VCE_HANDLES
];
1657 struct delayed_work idle_work
;
1658 const struct firmware
*fw
; /* VCE firmware */
1659 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1660 struct amdgpu_irq_src irq
;
1661 unsigned harvest_config
;
1667 struct amdgpu_sdma_instance
{
1669 const struct firmware
*fw
;
1670 uint32_t fw_version
;
1671 uint32_t feature_version
;
1673 struct amdgpu_ring ring
;
1677 struct amdgpu_sdma
{
1678 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1679 struct amdgpu_irq_src trap_irq
;
1680 struct amdgpu_irq_src illegal_inst_irq
;
1687 struct amdgpu_firmware
{
1688 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1690 struct amdgpu_bo
*fw_buf
;
1691 unsigned int fw_size
;
1697 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1703 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1704 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1705 struct amdgpu_ring
*cpA
,
1706 struct amdgpu_ring
*cpB
);
1707 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1712 #if defined(CONFIG_MMU_NOTIFIER)
1713 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1714 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1716 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1720 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1726 struct amdgpu_debugfs
{
1727 struct drm_info_list
*files
;
1731 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1732 struct drm_info_list
*files
,
1734 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1736 #if defined(CONFIG_DEBUG_FS)
1737 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1738 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1742 * amdgpu smumgr functions
1744 struct amdgpu_smumgr_funcs
{
1745 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1746 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1747 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1753 struct amdgpu_smumgr
{
1754 struct amdgpu_bo
*toc_buf
;
1755 struct amdgpu_bo
*smu_buf
;
1756 /* asic priv smu data */
1758 spinlock_t smu_lock
;
1759 /* smumgr functions */
1760 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1761 /* ucode loading complete flag */
1766 * ASIC specific register table accessible by UMD
1768 struct amdgpu_allowed_register_entry
{
1769 uint32_t reg_offset
;
1774 struct amdgpu_cu_info
{
1775 uint32_t number
; /* total active CU number */
1776 uint32_t ao_cu_mask
;
1777 uint32_t bitmap
[4][4];
1782 * ASIC specific functions.
1784 struct amdgpu_asic_funcs
{
1785 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1786 bool (*read_bios_from_rom
)(struct amdgpu_device
*adev
,
1787 u8
*bios
, u32 length_bytes
);
1788 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1789 u32 sh_num
, u32 reg_offset
, u32
*value
);
1790 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1791 int (*reset
)(struct amdgpu_device
*adev
);
1792 /* wait for mc_idle */
1793 int (*wait_for_mc_idle
)(struct amdgpu_device
*adev
);
1794 /* get the reference clock */
1795 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1796 /* get the gpu clock counter */
1797 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1798 int (*get_cu_info
)(struct amdgpu_device
*adev
, struct amdgpu_cu_info
*info
);
1799 /* MM block clocks */
1800 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1801 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1807 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1808 struct drm_file
*filp
);
1809 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1810 struct drm_file
*filp
);
1812 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1813 struct drm_file
*filp
);
1814 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1815 struct drm_file
*filp
);
1816 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1817 struct drm_file
*filp
);
1818 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1819 struct drm_file
*filp
);
1820 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1821 struct drm_file
*filp
);
1822 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1823 struct drm_file
*filp
);
1824 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1825 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1827 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1828 struct drm_file
*filp
);
1830 /* VRAM scratch page for HDP bug, default vram page */
1831 struct amdgpu_vram_scratch
{
1832 struct amdgpu_bo
*robj
;
1833 volatile uint32_t *ptr
;
1840 struct amdgpu_atif_notification_cfg
{
1845 struct amdgpu_atif_notifications
{
1846 bool display_switch
;
1847 bool expansion_mode_change
;
1849 bool forced_power_state
;
1850 bool system_power_state
;
1851 bool display_conf_change
;
1853 bool brightness_change
;
1854 bool dgpu_display_event
;
1857 struct amdgpu_atif_functions
{
1859 bool sbios_requests
;
1860 bool select_active_disp
;
1862 bool get_tv_standard
;
1863 bool set_tv_standard
;
1864 bool get_panel_expansion_mode
;
1865 bool set_panel_expansion_mode
;
1866 bool temperature_change
;
1867 bool graphics_device_types
;
1870 struct amdgpu_atif
{
1871 struct amdgpu_atif_notifications notifications
;
1872 struct amdgpu_atif_functions functions
;
1873 struct amdgpu_atif_notification_cfg notification_cfg
;
1874 struct amdgpu_encoder
*encoder_for_bl
;
1877 struct amdgpu_atcs_functions
{
1881 bool pcie_bus_width
;
1884 struct amdgpu_atcs
{
1885 struct amdgpu_atcs_functions functions
;
1891 void *amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1892 void amdgpu_cgs_destroy_device(void *cgs_device
);
1896 * Core structure, functions and helpers.
1898 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1899 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1901 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1902 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1904 struct amdgpu_ip_block_status
{
1910 struct amdgpu_device
{
1912 struct drm_device
*ddev
;
1913 struct pci_dev
*pdev
;
1916 enum amd_asic_type asic_type
;
1919 uint32_t external_rev_id
;
1920 unsigned long flags
;
1922 const struct amdgpu_asic_funcs
*asic_funcs
;
1927 struct work_struct reset_work
;
1928 struct notifier_block acpi_nb
;
1929 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1930 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1931 unsigned debugfs_count
;
1932 #if defined(CONFIG_DEBUG_FS)
1933 struct dentry
*debugfs_regs
;
1935 struct amdgpu_atif atif
;
1936 struct amdgpu_atcs atcs
;
1937 struct mutex srbm_mutex
;
1938 /* GRBM index mutex. Protects concurrent access to GRBM index */
1939 struct mutex grbm_idx_mutex
;
1940 struct dev_pm_domain vga_pm_domain
;
1941 bool have_disp_power_ref
;
1946 uint16_t bios_header_start
;
1947 struct amdgpu_bo
*stollen_vga_memory
;
1948 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1950 /* Register/doorbell mmio */
1951 resource_size_t rmmio_base
;
1952 resource_size_t rmmio_size
;
1953 void __iomem
*rmmio
;
1954 /* protects concurrent MM_INDEX/DATA based register access */
1955 spinlock_t mmio_idx_lock
;
1956 /* protects concurrent SMC based register access */
1957 spinlock_t smc_idx_lock
;
1958 amdgpu_rreg_t smc_rreg
;
1959 amdgpu_wreg_t smc_wreg
;
1960 /* protects concurrent PCIE register access */
1961 spinlock_t pcie_idx_lock
;
1962 amdgpu_rreg_t pcie_rreg
;
1963 amdgpu_wreg_t pcie_wreg
;
1964 /* protects concurrent UVD register access */
1965 spinlock_t uvd_ctx_idx_lock
;
1966 amdgpu_rreg_t uvd_ctx_rreg
;
1967 amdgpu_wreg_t uvd_ctx_wreg
;
1968 /* protects concurrent DIDT register access */
1969 spinlock_t didt_idx_lock
;
1970 amdgpu_rreg_t didt_rreg
;
1971 amdgpu_wreg_t didt_wreg
;
1972 /* protects concurrent ENDPOINT (audio) register access */
1973 spinlock_t audio_endpt_idx_lock
;
1974 amdgpu_block_rreg_t audio_endpt_rreg
;
1975 amdgpu_block_wreg_t audio_endpt_wreg
;
1976 void __iomem
*rio_mem
;
1977 resource_size_t rio_mem_size
;
1978 struct amdgpu_doorbell doorbell
;
1980 /* clock/pll info */
1981 struct amdgpu_clock clock
;
1984 struct amdgpu_mc mc
;
1985 struct amdgpu_gart gart
;
1986 struct amdgpu_dummy_page dummy_page
;
1987 struct amdgpu_vm_manager vm_manager
;
1989 /* memory management */
1990 struct amdgpu_mman mman
;
1991 struct amdgpu_gem gem
;
1992 struct amdgpu_vram_scratch vram_scratch
;
1993 struct amdgpu_wb wb
;
1994 atomic64_t vram_usage
;
1995 atomic64_t vram_vis_usage
;
1996 atomic64_t gtt_usage
;
1997 atomic64_t num_bytes_moved
;
1998 atomic_t gpu_reset_counter
;
2001 struct amdgpu_mode_info mode_info
;
2002 struct work_struct hotplug_work
;
2003 struct amdgpu_irq_src crtc_irq
;
2004 struct amdgpu_irq_src pageflip_irq
;
2005 struct amdgpu_irq_src hpd_irq
;
2008 unsigned fence_context
;
2009 struct mutex ring_lock
;
2011 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
2013 struct amdgpu_sa_manager ring_tmp_bo
;
2016 struct amdgpu_irq irq
;
2019 struct amd_powerplay powerplay
;
2023 struct amdgpu_pm pm
;
2028 struct amdgpu_smumgr smu
;
2031 struct amdgpu_gfx gfx
;
2034 struct amdgpu_sdma sdma
;
2038 struct amdgpu_uvd uvd
;
2041 struct amdgpu_vce vce
;
2044 struct amdgpu_firmware firmware
;
2047 struct amdgpu_gds gds
;
2049 const struct amdgpu_ip_block_version
*ip_blocks
;
2051 struct amdgpu_ip_block_status
*ip_block_status
;
2052 struct mutex mn_lock
;
2053 DECLARE_HASHTABLE(mn_hash
, 7);
2055 /* tracking pinned memory */
2059 /* amdkfd interface */
2060 struct kfd_dev
*kfd
;
2062 /* kernel conext for IB submission */
2063 struct amdgpu_ctx kernel_ctx
;
2066 bool amdgpu_device_is_px(struct drm_device
*dev
);
2067 int amdgpu_device_init(struct amdgpu_device
*adev
,
2068 struct drm_device
*ddev
,
2069 struct pci_dev
*pdev
,
2071 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2072 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2074 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2075 bool always_indirect
);
2076 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2077 bool always_indirect
);
2078 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2079 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2081 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2082 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2087 extern const struct fence_ops amdgpu_fence_ops
;
2088 static inline struct amdgpu_fence
*to_amdgpu_fence(struct fence
*f
)
2090 struct amdgpu_fence
*__f
= container_of(f
, struct amdgpu_fence
, base
);
2092 if (__f
->base
.ops
== &amdgpu_fence_ops
)
2099 * Registers read & write functions.
2101 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2102 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2103 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2104 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2105 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2106 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2107 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2108 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2109 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2110 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2111 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2112 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2113 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2114 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2115 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2116 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2117 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2118 #define WREG32_P(reg, val, mask) \
2120 uint32_t tmp_ = RREG32(reg); \
2122 tmp_ |= ((val) & ~(mask)); \
2123 WREG32(reg, tmp_); \
2125 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2126 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2127 #define WREG32_PLL_P(reg, val, mask) \
2129 uint32_t tmp_ = RREG32_PLL(reg); \
2131 tmp_ |= ((val) & ~(mask)); \
2132 WREG32_PLL(reg, tmp_); \
2134 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2135 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2136 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2138 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2139 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2141 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2142 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2144 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2145 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2146 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2148 #define REG_GET_FIELD(value, reg, field) \
2149 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2154 #define RBIOS8(i) (adev->bios[i])
2155 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2156 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2161 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2163 if (ring
->count_dw
<= 0)
2164 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2165 ring
->ring
[ring
->wptr
++] = v
;
2166 ring
->wptr
&= ring
->ptr_mask
;
2168 ring
->ring_free_dw
--;
2171 static inline struct amdgpu_sdma_instance
*
2172 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
2174 struct amdgpu_device
*adev
= ring
->adev
;
2177 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
2178 if (&adev
->sdma
.instance
[i
].ring
== ring
)
2181 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
2182 return &adev
->sdma
.instance
[i
];
2190 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2191 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2192 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2193 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2194 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2195 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2196 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2197 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2198 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2199 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2200 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2201 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2202 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2203 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2204 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2205 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2206 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2207 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2208 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2209 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2210 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2211 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2212 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2213 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2214 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2215 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2216 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2217 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2218 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2219 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2220 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2221 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2222 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2223 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2224 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2225 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2226 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2227 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2228 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2229 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2230 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2231 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2232 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2233 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2234 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2235 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2236 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2237 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2238 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2239 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2240 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2241 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2242 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2243 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2244 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2245 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2247 #define amdgpu_dpm_get_temperature(adev) \
2248 ((adev)->pp_enabled ? \
2249 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2250 (adev)->pm.funcs->get_temperature((adev)))
2252 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2253 ((adev)->pp_enabled ? \
2254 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2255 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2257 #define amdgpu_dpm_get_fan_control_mode(adev) \
2258 ((adev)->pp_enabled ? \
2259 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2260 (adev)->pm.funcs->get_fan_control_mode((adev)))
2262 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2263 ((adev)->pp_enabled ? \
2264 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2265 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2267 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2268 ((adev)->pp_enabled ? \
2269 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2270 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2272 #define amdgpu_dpm_get_sclk(adev, l) \
2273 ((adev)->pp_enabled ? \
2274 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2275 (adev)->pm.funcs->get_sclk((adev), (l)))
2277 #define amdgpu_dpm_get_mclk(adev, l) \
2278 ((adev)->pp_enabled ? \
2279 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2280 (adev)->pm.funcs->get_mclk((adev), (l)))
2283 #define amdgpu_dpm_force_performance_level(adev, l) \
2284 ((adev)->pp_enabled ? \
2285 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2286 (adev)->pm.funcs->force_performance_level((adev), (l)))
2288 #define amdgpu_dpm_powergate_uvd(adev, g) \
2289 ((adev)->pp_enabled ? \
2290 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2291 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2293 #define amdgpu_dpm_powergate_vce(adev, g) \
2294 ((adev)->pp_enabled ? \
2295 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2296 (adev)->pm.funcs->powergate_vce((adev), (g)))
2298 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2299 ((adev)->pp_enabled ? \
2300 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2301 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2303 #define amdgpu_dpm_get_current_power_state(adev) \
2304 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2306 #define amdgpu_dpm_get_performance_level(adev) \
2307 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2309 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2310 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2312 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2314 /* Common functions */
2315 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2316 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2317 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2318 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2319 bool amdgpu_boot_test_post_card(struct amdgpu_device
*adev
);
2321 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2322 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2323 u32 ip_instance
, u32 ring
,
2324 struct amdgpu_ring
**out_ring
);
2325 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2326 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2327 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2329 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
2330 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
2332 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2333 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2334 struct ttm_mem_reg
*mem
);
2335 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2336 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2337 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2338 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2339 const u32
*registers
,
2340 const u32 array_size
);
2342 bool amdgpu_device_is_px(struct drm_device
*dev
);
2344 #if defined(CONFIG_VGA_SWITCHEROO)
2345 void amdgpu_register_atpx_handler(void);
2346 void amdgpu_unregister_atpx_handler(void);
2348 static inline void amdgpu_register_atpx_handler(void) {}
2349 static inline void amdgpu_unregister_atpx_handler(void) {}
2355 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2356 extern int amdgpu_max_kms_ioctl
;
2358 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2359 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2360 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2361 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2362 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2363 struct drm_file
*file_priv
);
2364 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2365 struct drm_file
*file_priv
);
2366 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2367 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2368 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
2369 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2370 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2371 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, unsigned int pipe
,
2373 struct timeval
*vblank_time
,
2375 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2379 * functions used by amdgpu_encoder.c
2381 struct amdgpu_afmt_acr
{
2395 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2398 #if defined(CONFIG_ACPI)
2399 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2400 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2401 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2402 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2403 u8 perf_req
, bool advertise
);
2404 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2406 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2407 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2410 struct amdgpu_bo_va_mapping
*
2411 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2412 uint64_t addr
, struct amdgpu_bo
**bo
);
2414 #include "amdgpu_object.h"