2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/amdgpu_drm.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_i2c.h"
33 #include "atom-bits.h"
34 #include "atombios_encoders.h"
35 #include "bif/bif_4_1_d.h"
37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device
*adev
,
38 ATOM_GPIO_I2C_ASSIGMENT
*gpio
,
44 static struct amdgpu_i2c_bus_rec
amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT
*gpio
)
46 struct amdgpu_i2c_bus_rec i2c
;
48 memset(&i2c
, 0, sizeof(struct amdgpu_i2c_bus_rec
));
50 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
);
51 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
);
52 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
);
53 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
);
54 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
);
55 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
);
56 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
);
57 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
);
58 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
59 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
60 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
61 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
62 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
63 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
64 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
65 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
67 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
68 i2c
.hw_capable
= true;
70 i2c
.hw_capable
= false;
72 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
77 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
87 struct amdgpu_i2c_bus_rec
amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device
*adev
,
90 struct atom_context
*ctx
= adev
->mode_info
.atom_context
;
91 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
92 struct amdgpu_i2c_bus_rec i2c
;
93 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
94 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
95 uint16_t data_offset
, size
;
98 memset(&i2c
, 0, sizeof(struct amdgpu_i2c_bus_rec
));
101 if (amdgpu_atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
102 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
104 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
105 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
107 gpio
= &i2c_info
->asGPIO_Info
[0];
108 for (i
= 0; i
< num_indices
; i
++) {
110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev
, gpio
, i
);
112 if (gpio
->sucI2cId
.ucAccess
== id
) {
113 i2c
= amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio
);
116 gpio
= (ATOM_GPIO_I2C_ASSIGMENT
*)
117 ((u8
*)gpio
+ sizeof(ATOM_GPIO_I2C_ASSIGMENT
));
124 void amdgpu_atombios_i2c_init(struct amdgpu_device
*adev
)
126 struct atom_context
*ctx
= adev
->mode_info
.atom_context
;
127 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
128 struct amdgpu_i2c_bus_rec i2c
;
129 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
130 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
131 uint16_t data_offset
, size
;
135 if (amdgpu_atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
136 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
138 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
139 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
141 gpio
= &i2c_info
->asGPIO_Info
[0];
142 for (i
= 0; i
< num_indices
; i
++) {
143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev
, gpio
, i
);
145 i2c
= amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio
);
148 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
149 adev
->i2c_bus
[i
] = amdgpu_i2c_create(adev
->ddev
, &i2c
, stmp
);
151 gpio
= (ATOM_GPIO_I2C_ASSIGMENT
*)
152 ((u8
*)gpio
+ sizeof(ATOM_GPIO_I2C_ASSIGMENT
));
157 struct amdgpu_gpio_rec
158 amdgpu_atombios_lookup_gpio(struct amdgpu_device
*adev
,
161 struct atom_context
*ctx
= adev
->mode_info
.atom_context
;
162 struct amdgpu_gpio_rec gpio
;
163 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
164 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
165 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
166 u16 data_offset
, size
;
169 memset(&gpio
, 0, sizeof(struct amdgpu_gpio_rec
));
172 if (amdgpu_atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
173 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
175 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
178 pin
= gpio_info
->asGPIO_Pin
;
179 for (i
= 0; i
< num_indices
; i
++) {
180 if (id
== pin
->ucGPIO_ID
) {
181 gpio
.id
= pin
->ucGPIO_ID
;
182 gpio
.reg
= le16_to_cpu(pin
->usGpioPin_AIndex
);
183 gpio
.shift
= pin
->ucGpioPinBitShift
;
184 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
188 pin
= (ATOM_GPIO_PIN_ASSIGNMENT
*)
189 ((u8
*)pin
+ sizeof(ATOM_GPIO_PIN_ASSIGNMENT
));
196 static struct amdgpu_hpd
197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device
*adev
,
198 struct amdgpu_gpio_rec
*gpio
)
200 struct amdgpu_hpd hpd
;
203 memset(&hpd
, 0, sizeof(struct amdgpu_hpd
));
205 reg
= amdgpu_display_hpd_get_gpio_reg(adev
);
208 if (gpio
->reg
== reg
) {
211 hpd
.hpd
= AMDGPU_HPD_1
;
214 hpd
.hpd
= AMDGPU_HPD_2
;
217 hpd
.hpd
= AMDGPU_HPD_3
;
220 hpd
.hpd
= AMDGPU_HPD_4
;
223 hpd
.hpd
= AMDGPU_HPD_5
;
226 hpd
.hpd
= AMDGPU_HPD_6
;
229 hpd
.hpd
= AMDGPU_HPD_NONE
;
233 hpd
.hpd
= AMDGPU_HPD_NONE
;
237 static const int object_connector_convert
[] = {
238 DRM_MODE_CONNECTOR_Unknown
,
239 DRM_MODE_CONNECTOR_DVII
,
240 DRM_MODE_CONNECTOR_DVII
,
241 DRM_MODE_CONNECTOR_DVID
,
242 DRM_MODE_CONNECTOR_DVID
,
243 DRM_MODE_CONNECTOR_VGA
,
244 DRM_MODE_CONNECTOR_Composite
,
245 DRM_MODE_CONNECTOR_SVIDEO
,
246 DRM_MODE_CONNECTOR_Unknown
,
247 DRM_MODE_CONNECTOR_Unknown
,
248 DRM_MODE_CONNECTOR_9PinDIN
,
249 DRM_MODE_CONNECTOR_Unknown
,
250 DRM_MODE_CONNECTOR_HDMIA
,
251 DRM_MODE_CONNECTOR_HDMIB
,
252 DRM_MODE_CONNECTOR_LVDS
,
253 DRM_MODE_CONNECTOR_9PinDIN
,
254 DRM_MODE_CONNECTOR_Unknown
,
255 DRM_MODE_CONNECTOR_Unknown
,
256 DRM_MODE_CONNECTOR_Unknown
,
257 DRM_MODE_CONNECTOR_DisplayPort
,
258 DRM_MODE_CONNECTOR_eDP
,
259 DRM_MODE_CONNECTOR_Unknown
262 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device
*adev
)
264 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
265 struct atom_context
*ctx
= mode_info
->atom_context
;
266 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
267 u16 size
, data_offset
;
269 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
270 ATOM_OBJECT_HEADER
*obj_header
;
272 if (!amdgpu_atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
278 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
279 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
280 (ctx
->bios
+ data_offset
+
281 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
283 if (path_obj
->ucNumOfDispPath
)
289 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device
*adev
)
291 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
292 struct atom_context
*ctx
= mode_info
->atom_context
;
293 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
294 u16 size
, data_offset
;
296 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
297 ATOM_ENCODER_OBJECT_TABLE
*enc_obj
;
298 ATOM_OBJECT_TABLE
*router_obj
;
299 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
300 ATOM_OBJECT_HEADER
*obj_header
;
301 int i
, j
, k
, path_size
, device_support
;
303 u16 conn_id
, connector_object_id
;
304 struct amdgpu_i2c_bus_rec ddc_bus
;
305 struct amdgpu_router router
;
306 struct amdgpu_gpio_rec gpio
;
307 struct amdgpu_hpd hpd
;
309 if (!amdgpu_atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
315 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
316 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
317 (ctx
->bios
+ data_offset
+
318 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
319 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
320 (ctx
->bios
+ data_offset
+
321 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
322 enc_obj
= (ATOM_ENCODER_OBJECT_TABLE
*)
323 (ctx
->bios
+ data_offset
+
324 le16_to_cpu(obj_header
->usEncoderObjectTableOffset
));
325 router_obj
= (ATOM_OBJECT_TABLE
*)
326 (ctx
->bios
+ data_offset
+
327 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
328 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
331 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
332 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
333 ATOM_DISPLAY_OBJECT_PATH
*path
;
335 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
336 path_size
+= le16_to_cpu(path
->usSize
);
338 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
339 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
342 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
345 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
348 (le16_to_cpu(path
->usConnObjectId
) &
349 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
351 /* Skip TV/CV support */
352 if ((le16_to_cpu(path
->usDeviceTag
) ==
353 ATOM_DEVICE_TV1_SUPPORT
) ||
354 (le16_to_cpu(path
->usDeviceTag
) ==
355 ATOM_DEVICE_CV_SUPPORT
))
358 if (con_obj_id
>= ARRAY_SIZE(object_connector_convert
)) {
359 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
360 con_obj_id
, le16_to_cpu(path
->usDeviceTag
));
365 object_connector_convert
[con_obj_id
];
366 connector_object_id
= con_obj_id
;
368 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
371 router
.ddc_valid
= false;
372 router
.cd_valid
= false;
373 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
374 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
377 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
378 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
380 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
381 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
383 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
384 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
386 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
387 for (k
= 0; k
< enc_obj
->ucNumberOfObjects
; k
++) {
388 u16 encoder_obj
= le16_to_cpu(enc_obj
->asObjects
[k
].usObjectID
);
389 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == encoder_obj
) {
390 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
391 (ctx
->bios
+ data_offset
+
392 le16_to_cpu(enc_obj
->asObjects
[k
].usRecordOffset
));
393 ATOM_ENCODER_CAP_RECORD
*cap_record
;
396 while (record
->ucRecordSize
> 0 &&
397 record
->ucRecordType
> 0 &&
398 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
399 switch (record
->ucRecordType
) {
400 case ATOM_ENCODER_CAP_RECORD_TYPE
:
401 cap_record
=(ATOM_ENCODER_CAP_RECORD
*)
403 caps
= le16_to_cpu(cap_record
->usEncoderCap
);
406 record
= (ATOM_COMMON_RECORD_HEADER
*)
407 ((char *)record
+ record
->ucRecordSize
);
409 amdgpu_display_add_encoder(adev
, encoder_obj
,
410 le16_to_cpu(path
->usDeviceTag
),
414 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
415 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
416 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[k
].usObjectID
);
417 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
418 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
419 (ctx
->bios
+ data_offset
+
420 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
421 ATOM_I2C_RECORD
*i2c_record
;
422 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
423 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
424 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*cd_path
;
425 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
426 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
427 (ctx
->bios
+ data_offset
+
428 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
429 u8
*num_dst_objs
= (u8
*)
430 ((u8
*)router_src_dst_table
+ 1 +
431 (router_src_dst_table
->ucNumberOfSrc
* 2));
432 u16
*dst_objs
= (u16
*)(num_dst_objs
+ 1);
435 router
.router_id
= router_obj_id
;
436 for (enum_id
= 0; enum_id
< (*num_dst_objs
); enum_id
++) {
437 if (le16_to_cpu(path
->usConnObjectId
) ==
438 le16_to_cpu(dst_objs
[enum_id
]))
442 while (record
->ucRecordSize
> 0 &&
443 record
->ucRecordType
> 0 &&
444 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
445 switch (record
->ucRecordType
) {
446 case ATOM_I2C_RECORD_TYPE
:
451 (ATOM_I2C_ID_CONFIG_ACCESS
*)
452 &i2c_record
->sucI2cId
;
454 amdgpu_atombios_lookup_i2c_gpio(adev
,
457 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
459 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
460 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
462 router
.ddc_valid
= true;
463 router
.ddc_mux_type
= ddc_path
->ucMuxType
;
464 router
.ddc_mux_control_pin
= ddc_path
->ucMuxControlPin
;
465 router
.ddc_mux_state
= ddc_path
->ucMuxState
[enum_id
];
467 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
:
468 cd_path
= (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*)
470 router
.cd_valid
= true;
471 router
.cd_mux_type
= cd_path
->ucMuxType
;
472 router
.cd_mux_control_pin
= cd_path
->ucMuxControlPin
;
473 router
.cd_mux_state
= cd_path
->ucMuxState
[enum_id
];
476 record
= (ATOM_COMMON_RECORD_HEADER
*)
477 ((char *)record
+ record
->ucRecordSize
);
484 /* look up gpio for ddc, hpd */
485 ddc_bus
.valid
= false;
486 hpd
.hpd
= AMDGPU_HPD_NONE
;
487 if ((le16_to_cpu(path
->usDeviceTag
) &
488 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
489 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
490 if (le16_to_cpu(path
->usConnObjectId
) ==
491 le16_to_cpu(con_obj
->asObjects
[j
].
493 ATOM_COMMON_RECORD_HEADER
495 (ATOM_COMMON_RECORD_HEADER
497 (ctx
->bios
+ data_offset
+
498 le16_to_cpu(con_obj
->
501 ATOM_I2C_RECORD
*i2c_record
;
502 ATOM_HPD_INT_RECORD
*hpd_record
;
503 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
505 while (record
->ucRecordSize
> 0 &&
506 record
->ucRecordType
> 0 &&
507 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
508 switch (record
->ucRecordType
) {
509 case ATOM_I2C_RECORD_TYPE
:
514 (ATOM_I2C_ID_CONFIG_ACCESS
*)
515 &i2c_record
->sucI2cId
;
516 ddc_bus
= amdgpu_atombios_lookup_i2c_gpio(adev
,
520 case ATOM_HPD_INT_RECORD_TYPE
:
522 (ATOM_HPD_INT_RECORD
*)
524 gpio
= amdgpu_atombios_lookup_gpio(adev
,
525 hpd_record
->ucHPDIntGPIOID
);
526 hpd
= amdgpu_atombios_get_hpd_info_from_gpio(adev
, &gpio
);
527 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
531 (ATOM_COMMON_RECORD_HEADER
542 /* needed for aux chan transactions */
543 ddc_bus
.hpd
= hpd
.hpd
;
545 conn_id
= le16_to_cpu(path
->usConnObjectId
);
547 amdgpu_display_add_connector(adev
,
549 le16_to_cpu(path
->usDeviceTag
),
550 connector_type
, &ddc_bus
,
558 amdgpu_link_encoder_connector(adev
->ddev
);
563 union firmware_info
{
564 ATOM_FIRMWARE_INFO info
;
565 ATOM_FIRMWARE_INFO_V1_2 info_12
;
566 ATOM_FIRMWARE_INFO_V1_3 info_13
;
567 ATOM_FIRMWARE_INFO_V1_4 info_14
;
568 ATOM_FIRMWARE_INFO_V2_1 info_21
;
569 ATOM_FIRMWARE_INFO_V2_2 info_22
;
572 int amdgpu_atombios_get_clock_info(struct amdgpu_device
*adev
)
574 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
575 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
577 uint16_t data_offset
;
580 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
581 &frev
, &crev
, &data_offset
)) {
583 struct amdgpu_pll
*ppll
= &adev
->clock
.ppll
[0];
584 struct amdgpu_pll
*spll
= &adev
->clock
.spll
;
585 struct amdgpu_pll
*mpll
= &adev
->clock
.mpll
;
586 union firmware_info
*firmware_info
=
587 (union firmware_info
*)(mode_info
->atom_context
->bios
+
590 ppll
->reference_freq
=
591 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
592 ppll
->reference_div
= 0;
595 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
597 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
599 ppll
->lcd_pll_out_min
=
600 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
601 if (ppll
->lcd_pll_out_min
== 0)
602 ppll
->lcd_pll_out_min
= ppll
->pll_out_min
;
603 ppll
->lcd_pll_out_max
=
604 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
605 if (ppll
->lcd_pll_out_max
== 0)
606 ppll
->lcd_pll_out_max
= ppll
->pll_out_max
;
608 if (ppll
->pll_out_min
== 0)
609 ppll
->pll_out_min
= 64800;
612 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
614 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
616 ppll
->min_post_div
= 2;
617 ppll
->max_post_div
= 0x7f;
618 ppll
->min_frac_feedback_div
= 0;
619 ppll
->max_frac_feedback_div
= 9;
620 ppll
->min_ref_div
= 2;
621 ppll
->max_ref_div
= 0x3ff;
622 ppll
->min_feedback_div
= 4;
623 ppll
->max_feedback_div
= 0xfff;
626 for (i
= 1; i
< AMDGPU_MAX_PPLL
; i
++)
627 adev
->clock
.ppll
[i
] = *ppll
;
630 spll
->reference_freq
=
631 le16_to_cpu(firmware_info
->info_21
.usCoreReferenceClock
);
632 spll
->reference_div
= 0;
635 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
637 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
640 if (spll
->pll_out_min
== 0)
641 spll
->pll_out_min
= 64800;
644 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
646 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
648 spll
->min_post_div
= 1;
649 spll
->max_post_div
= 1;
650 spll
->min_ref_div
= 2;
651 spll
->max_ref_div
= 0xff;
652 spll
->min_feedback_div
= 4;
653 spll
->max_feedback_div
= 0xff;
657 mpll
->reference_freq
=
658 le16_to_cpu(firmware_info
->info_21
.usMemoryReferenceClock
);
659 mpll
->reference_div
= 0;
662 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
664 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
667 if (mpll
->pll_out_min
== 0)
668 mpll
->pll_out_min
= 64800;
671 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
673 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
675 adev
->clock
.default_sclk
=
676 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
677 adev
->clock
.default_mclk
=
678 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
680 mpll
->min_post_div
= 1;
681 mpll
->max_post_div
= 1;
682 mpll
->min_ref_div
= 2;
683 mpll
->max_ref_div
= 0xff;
684 mpll
->min_feedback_div
= 4;
685 mpll
->max_feedback_div
= 0xff;
689 adev
->clock
.default_dispclk
=
690 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
691 /* set a reasonable default for DP */
692 if (adev
->clock
.default_dispclk
< 53900) {
693 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
694 adev
->clock
.default_dispclk
/ 100);
695 adev
->clock
.default_dispclk
= 60000;
697 adev
->clock
.dp_extclk
=
698 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
699 adev
->clock
.current_dispclk
= adev
->clock
.default_dispclk
;
701 adev
->clock
.max_pixel_clock
= le16_to_cpu(firmware_info
->info
.usMaxPixelClock
);
702 if (adev
->clock
.max_pixel_clock
== 0)
703 adev
->clock
.max_pixel_clock
= 40000;
705 /* not technically a clock, but... */
706 adev
->mode_info
.firmware_flags
=
707 le16_to_cpu(firmware_info
->info
.usFirmwareCapability
.susAccess
);
712 adev
->pm
.current_sclk
= adev
->clock
.default_sclk
;
713 adev
->pm
.current_mclk
= adev
->clock
.default_mclk
;
719 ATOM_GFX_INFO_V2_1 info
;
722 int amdgpu_atombios_get_gfx_info(struct amdgpu_device
*adev
)
724 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
725 int index
= GetIndexIntoMasterTable(DATA
, GFX_Info
);
727 uint16_t data_offset
;
730 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
731 &frev
, &crev
, &data_offset
)) {
732 union gfx_info
*gfx_info
= (union gfx_info
*)
733 (mode_info
->atom_context
->bios
+ data_offset
);
735 adev
->gfx
.config
.max_shader_engines
= gfx_info
->info
.max_shader_engines
;
736 adev
->gfx
.config
.max_tile_pipes
= gfx_info
->info
.max_tile_pipes
;
737 adev
->gfx
.config
.max_cu_per_sh
= gfx_info
->info
.max_cu_per_sh
;
738 adev
->gfx
.config
.max_sh_per_se
= gfx_info
->info
.max_sh_per_se
;
739 adev
->gfx
.config
.max_backends_per_se
= gfx_info
->info
.max_backends_per_se
;
740 adev
->gfx
.config
.max_texture_channel_caches
=
741 gfx_info
->info
.max_texture_channel_caches
;
749 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
750 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
751 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6
;
752 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7
;
753 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8
;
754 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9
;
757 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device
*adev
,
758 struct amdgpu_atom_ss
*ss
,
761 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
762 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
763 u16 data_offset
, size
;
764 union igp_info
*igp_info
;
766 u16 percentage
= 0, rate
= 0;
768 /* get any igp specific overrides */
769 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
770 &frev
, &crev
, &data_offset
)) {
771 igp_info
= (union igp_info
*)
772 (mode_info
->atom_context
->bios
+ data_offset
);
776 case ASIC_INTERNAL_SS_ON_TMDS
:
777 percentage
= le16_to_cpu(igp_info
->info_6
.usDVISSPercentage
);
778 rate
= le16_to_cpu(igp_info
->info_6
.usDVISSpreadRateIn10Hz
);
780 case ASIC_INTERNAL_SS_ON_HDMI
:
781 percentage
= le16_to_cpu(igp_info
->info_6
.usHDMISSPercentage
);
782 rate
= le16_to_cpu(igp_info
->info_6
.usHDMISSpreadRateIn10Hz
);
784 case ASIC_INTERNAL_SS_ON_LVDS
:
785 percentage
= le16_to_cpu(igp_info
->info_6
.usLvdsSSPercentage
);
786 rate
= le16_to_cpu(igp_info
->info_6
.usLvdsSSpreadRateIn10Hz
);
792 case ASIC_INTERNAL_SS_ON_TMDS
:
793 percentage
= le16_to_cpu(igp_info
->info_7
.usDVISSPercentage
);
794 rate
= le16_to_cpu(igp_info
->info_7
.usDVISSpreadRateIn10Hz
);
796 case ASIC_INTERNAL_SS_ON_HDMI
:
797 percentage
= le16_to_cpu(igp_info
->info_7
.usHDMISSPercentage
);
798 rate
= le16_to_cpu(igp_info
->info_7
.usHDMISSpreadRateIn10Hz
);
800 case ASIC_INTERNAL_SS_ON_LVDS
:
801 percentage
= le16_to_cpu(igp_info
->info_7
.usLvdsSSPercentage
);
802 rate
= le16_to_cpu(igp_info
->info_7
.usLvdsSSpreadRateIn10Hz
);
808 case ASIC_INTERNAL_SS_ON_TMDS
:
809 percentage
= le16_to_cpu(igp_info
->info_8
.usDVISSPercentage
);
810 rate
= le16_to_cpu(igp_info
->info_8
.usDVISSpreadRateIn10Hz
);
812 case ASIC_INTERNAL_SS_ON_HDMI
:
813 percentage
= le16_to_cpu(igp_info
->info_8
.usHDMISSPercentage
);
814 rate
= le16_to_cpu(igp_info
->info_8
.usHDMISSpreadRateIn10Hz
);
816 case ASIC_INTERNAL_SS_ON_LVDS
:
817 percentage
= le16_to_cpu(igp_info
->info_8
.usLvdsSSPercentage
);
818 rate
= le16_to_cpu(igp_info
->info_8
.usLvdsSSpreadRateIn10Hz
);
824 case ASIC_INTERNAL_SS_ON_TMDS
:
825 percentage
= le16_to_cpu(igp_info
->info_9
.usDVISSPercentage
);
826 rate
= le16_to_cpu(igp_info
->info_9
.usDVISSpreadRateIn10Hz
);
828 case ASIC_INTERNAL_SS_ON_HDMI
:
829 percentage
= le16_to_cpu(igp_info
->info_9
.usHDMISSPercentage
);
830 rate
= le16_to_cpu(igp_info
->info_9
.usHDMISSpreadRateIn10Hz
);
832 case ASIC_INTERNAL_SS_ON_LVDS
:
833 percentage
= le16_to_cpu(igp_info
->info_9
.usLvdsSSPercentage
);
834 rate
= le16_to_cpu(igp_info
->info_9
.usLvdsSSpreadRateIn10Hz
);
839 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
843 ss
->percentage
= percentage
;
850 struct _ATOM_ASIC_INTERNAL_SS_INFO info
;
851 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2
;
852 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3
;
855 union asic_ss_assignment
{
856 struct _ATOM_ASIC_SS_ASSIGNMENT v1
;
857 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2
;
858 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3
;
861 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device
*adev
,
862 struct amdgpu_atom_ss
*ss
,
865 struct amdgpu_mode_info
*mode_info
= &adev
->mode_info
;
866 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
867 uint16_t data_offset
, size
;
868 union asic_ss_info
*ss_info
;
869 union asic_ss_assignment
*ss_assign
;
873 if (id
== ASIC_INTERNAL_MEMORY_SS
) {
874 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT
))
877 if (id
== ASIC_INTERNAL_ENGINE_SS
) {
878 if (!(adev
->mode_info
.firmware_flags
& ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT
))
882 memset(ss
, 0, sizeof(struct amdgpu_atom_ss
));
883 if (amdgpu_atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
884 &frev
, &crev
, &data_offset
)) {
887 (union asic_ss_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
891 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
892 sizeof(ATOM_ASIC_SS_ASSIGNMENT
);
894 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info
.asSpreadSpectrum
[0]);
895 for (i
= 0; i
< num_indices
; i
++) {
896 if ((ss_assign
->v1
.ucClockIndication
== id
) &&
897 (clock
<= le32_to_cpu(ss_assign
->v1
.ulTargetClockRange
))) {
899 le16_to_cpu(ss_assign
->v1
.usSpreadSpectrumPercentage
);
900 ss
->type
= ss_assign
->v1
.ucSpreadSpectrumMode
;
901 ss
->rate
= le16_to_cpu(ss_assign
->v1
.usSpreadRateInKhz
);
902 ss
->percentage_divider
= 100;
905 ss_assign
= (union asic_ss_assignment
*)
906 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT
));
910 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
911 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
);
912 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info_2
.asSpreadSpectrum
[0]);
913 for (i
= 0; i
< num_indices
; i
++) {
914 if ((ss_assign
->v2
.ucClockIndication
== id
) &&
915 (clock
<= le32_to_cpu(ss_assign
->v2
.ulTargetClockRange
))) {
917 le16_to_cpu(ss_assign
->v2
.usSpreadSpectrumPercentage
);
918 ss
->type
= ss_assign
->v2
.ucSpreadSpectrumMode
;
919 ss
->rate
= le16_to_cpu(ss_assign
->v2
.usSpreadRateIn10Hz
);
920 ss
->percentage_divider
= 100;
922 ((id
== ASIC_INTERNAL_ENGINE_SS
) ||
923 (id
== ASIC_INTERNAL_MEMORY_SS
)))
927 ss_assign
= (union asic_ss_assignment
*)
928 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
));
932 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
933 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
);
934 ss_assign
= (union asic_ss_assignment
*)((u8
*)&ss_info
->info_3
.asSpreadSpectrum
[0]);
935 for (i
= 0; i
< num_indices
; i
++) {
936 if ((ss_assign
->v3
.ucClockIndication
== id
) &&
937 (clock
<= le32_to_cpu(ss_assign
->v3
.ulTargetClockRange
))) {
939 le16_to_cpu(ss_assign
->v3
.usSpreadSpectrumPercentage
);
940 ss
->type
= ss_assign
->v3
.ucSpreadSpectrumMode
;
941 ss
->rate
= le16_to_cpu(ss_assign
->v3
.usSpreadRateIn10Hz
);
942 if (ss_assign
->v3
.ucSpreadSpectrumMode
&
943 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK
)
944 ss
->percentage_divider
= 1000;
946 ss
->percentage_divider
= 100;
947 if ((id
== ASIC_INTERNAL_ENGINE_SS
) ||
948 (id
== ASIC_INTERNAL_MEMORY_SS
))
950 if (adev
->flags
& AMD_IS_APU
)
951 amdgpu_atombios_get_igp_ss_overrides(adev
, ss
, id
);
954 ss_assign
= (union asic_ss_assignment
*)
955 ((u8
*)ss_assign
+ sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
));
959 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev
, crev
);
967 union get_clock_dividers
{
968 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1
;
969 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2
;
970 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3
;
971 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4
;
972 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5
;
973 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in
;
974 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out
;
977 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device
*adev
,
981 struct atom_clock_dividers
*dividers
)
983 union get_clock_dividers args
;
984 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryEnginePLL
);
987 memset(&args
, 0, sizeof(args
));
988 memset(dividers
, 0, sizeof(struct atom_clock_dividers
));
990 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
996 args
.v4
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
998 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1000 dividers
->post_divider
= dividers
->post_div
= args
.v4
.ucPostDiv
;
1001 dividers
->real_clock
= le32_to_cpu(args
.v4
.ulClock
);
1005 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1006 args
.v6_in
.ulClock
.ulComputeClockFlag
= clock_type
;
1007 args
.v6_in
.ulClock
.ulClockFreq
= cpu_to_le32(clock
); /* 10 khz */
1009 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1011 dividers
->whole_fb_div
= le16_to_cpu(args
.v6_out
.ulFbDiv
.usFbDiv
);
1012 dividers
->frac_fb_div
= le16_to_cpu(args
.v6_out
.ulFbDiv
.usFbDivFrac
);
1013 dividers
->ref_div
= args
.v6_out
.ucPllRefDiv
;
1014 dividers
->post_div
= args
.v6_out
.ucPllPostDiv
;
1015 dividers
->flags
= args
.v6_out
.ucPllCntlFlag
;
1016 dividers
->real_clock
= le32_to_cpu(args
.v6_out
.ulClock
.ulClock
);
1017 dividers
->post_divider
= args
.v6_out
.ulClock
.ucPostDiv
;
1025 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device
*adev
,
1028 struct atom_mpll_param
*mpll_param
)
1030 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args
;
1031 int index
= GetIndexIntoMasterTable(COMMAND
, ComputeMemoryClockParam
);
1034 memset(&args
, 0, sizeof(args
));
1035 memset(mpll_param
, 0, sizeof(struct atom_mpll_param
));
1037 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1045 args
.ulClock
= cpu_to_le32(clock
); /* 10 khz */
1046 args
.ucInputFlag
= 0;
1048 args
.ucInputFlag
|= MPLL_INPUT_FLAG_STROBE_MODE_EN
;
1050 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1052 mpll_param
->clkfrac
= le16_to_cpu(args
.ulFbDiv
.usFbDivFrac
);
1053 mpll_param
->clkf
= le16_to_cpu(args
.ulFbDiv
.usFbDiv
);
1054 mpll_param
->post_div
= args
.ucPostDiv
;
1055 mpll_param
->dll_speed
= args
.ucDllSpeed
;
1056 mpll_param
->bwcntl
= args
.ucBWCntl
;
1057 mpll_param
->vco_mode
=
1058 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_VCO_MODE_MASK
);
1059 mpll_param
->yclk_sel
=
1060 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_BYPASS_DQ_PLL
) ? 1 : 0;
1062 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_QDR_ENABLE
) ? 1 : 0;
1063 mpll_param
->half_rate
=
1064 (args
.ucPllCntlFlag
& MPLL_CNTL_FLAG_AD_HALF_RATE
) ? 1 : 0;
1076 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device
*adev
)
1078 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
1079 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
1081 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1082 return le32_to_cpu(args
.ulReturnEngineClock
);
1085 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device
*adev
)
1087 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
1088 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
1090 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1091 return le32_to_cpu(args
.ulReturnMemoryClock
);
1094 void amdgpu_atombios_set_engine_clock(struct amdgpu_device
*adev
,
1097 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1098 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
1100 args
.ulTargetEngineClock
= cpu_to_le32(eng_clock
); /* 10 khz */
1102 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1105 void amdgpu_atombios_set_memory_clock(struct amdgpu_device
*adev
,
1108 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
1109 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
1111 if (adev
->flags
& AMD_IS_APU
)
1114 args
.ulTargetMemoryClock
= cpu_to_le32(mem_clock
); /* 10 khz */
1116 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1119 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device
*adev
,
1120 u32 eng_clock
, u32 mem_clock
)
1122 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1123 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicMemorySettings
);
1126 memset(&args
, 0, sizeof(args
));
1128 tmp
= eng_clock
& SET_CLOCK_FREQ_MASK
;
1129 tmp
|= (COMPUTE_ENGINE_PLL_PARAM
<< 24);
1131 args
.ulTargetEngineClock
= cpu_to_le32(tmp
);
1133 args
.sReserved
.ulClock
= cpu_to_le32(mem_clock
& SET_CLOCK_FREQ_MASK
);
1135 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1139 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
1140 struct _SET_VOLTAGE_PARAMETERS v1
;
1141 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
1142 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3
;
1145 void amdgpu_atombios_set_voltage(struct amdgpu_device
*adev
,
1149 union set_voltage args
;
1150 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
1151 u8 frev
, crev
, volt_index
= voltage_level
;
1153 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1156 /* 0xff01 is a flag rather then an actual voltage */
1157 if (voltage_level
== 0xff01)
1162 args
.v1
.ucVoltageType
= voltage_type
;
1163 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
1164 args
.v1
.ucVoltageIndex
= volt_index
;
1167 args
.v2
.ucVoltageType
= voltage_type
;
1168 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
1169 args
.v2
.usVoltageLevel
= cpu_to_le16(voltage_level
);
1172 args
.v3
.ucVoltageType
= voltage_type
;
1173 args
.v3
.ucVoltageMode
= ATOM_SET_VOLTAGE
;
1174 args
.v3
.usVoltageLevel
= cpu_to_le16(voltage_level
);
1177 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1181 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1184 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device
*adev
,
1187 union set_voltage args
;
1188 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
1191 if (!amdgpu_atom_parse_cmd_header(adev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1197 args
.v3
.ucVoltageType
= 0;
1198 args
.v3
.ucVoltageMode
= ATOM_GET_LEAKAGE_ID
;
1199 args
.v3
.usVoltageLevel
= 0;
1201 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1203 *leakage_id
= le16_to_cpu(args
.v3
.usVoltageLevel
);
1206 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1213 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device
*adev
,
1214 u16
*vddc
, u16
*vddci
,
1215 u16 virtual_voltage_id
,
1216 u16 vbios_voltage_id
)
1218 int index
= GetIndexIntoMasterTable(DATA
, ASIC_ProfilingInfo
);
1220 u16 data_offset
, size
;
1222 ATOM_ASIC_PROFILING_INFO_V2_1
*profile
;
1223 u16
*leakage_bin
, *vddc_id_buf
, *vddc_buf
, *vddci_id_buf
, *vddci_buf
;
1228 if (!amdgpu_atom_parse_data_header(adev
->mode_info
.atom_context
, index
, &size
,
1229 &frev
, &crev
, &data_offset
))
1232 profile
= (ATOM_ASIC_PROFILING_INFO_V2_1
*)
1233 (adev
->mode_info
.atom_context
->bios
+ data_offset
);
1241 if (size
< sizeof(ATOM_ASIC_PROFILING_INFO_V2_1
))
1243 leakage_bin
= (u16
*)
1244 (adev
->mode_info
.atom_context
->bios
+ data_offset
+
1245 le16_to_cpu(profile
->usLeakageBinArrayOffset
));
1246 vddc_id_buf
= (u16
*)
1247 (adev
->mode_info
.atom_context
->bios
+ data_offset
+
1248 le16_to_cpu(profile
->usElbVDDC_IdArrayOffset
));
1250 (adev
->mode_info
.atom_context
->bios
+ data_offset
+
1251 le16_to_cpu(profile
->usElbVDDC_LevelArrayOffset
));
1252 vddci_id_buf
= (u16
*)
1253 (adev
->mode_info
.atom_context
->bios
+ data_offset
+
1254 le16_to_cpu(profile
->usElbVDDCI_IdArrayOffset
));
1256 (adev
->mode_info
.atom_context
->bios
+ data_offset
+
1257 le16_to_cpu(profile
->usElbVDDCI_LevelArrayOffset
));
1259 if (profile
->ucElbVDDC_Num
> 0) {
1260 for (i
= 0; i
< profile
->ucElbVDDC_Num
; i
++) {
1261 if (vddc_id_buf
[i
] == virtual_voltage_id
) {
1262 for (j
= 0; j
< profile
->ucLeakageBinNum
; j
++) {
1263 if (vbios_voltage_id
<= leakage_bin
[j
]) {
1264 *vddc
= vddc_buf
[j
* profile
->ucElbVDDC_Num
+ i
];
1272 if (profile
->ucElbVDDCI_Num
> 0) {
1273 for (i
= 0; i
< profile
->ucElbVDDCI_Num
; i
++) {
1274 if (vddci_id_buf
[i
] == virtual_voltage_id
) {
1275 for (j
= 0; j
< profile
->ucLeakageBinNum
; j
++) {
1276 if (vbios_voltage_id
<= leakage_bin
[j
]) {
1277 *vddci
= vddci_buf
[j
* profile
->ucElbVDDCI_Num
+ i
];
1287 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1292 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1299 union get_voltage_info
{
1300 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in
;
1301 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out
;
1304 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device
*adev
,
1305 u16 virtual_voltage_id
,
1308 int index
= GetIndexIntoMasterTable(COMMAND
, GetVoltageInfo
);
1310 u32 count
= adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.count
;
1311 union get_voltage_info args
;
1313 for (entry_id
= 0; entry_id
< count
; entry_id
++) {
1314 if (adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[entry_id
].v
==
1319 if (entry_id
>= count
)
1322 args
.in
.ucVoltageType
= VOLTAGE_TYPE_VDDC
;
1323 args
.in
.ucVoltageMode
= ATOM_GET_VOLTAGE_EVV_VOLTAGE
;
1324 args
.in
.usVoltageLevel
= cpu_to_le16(virtual_voltage_id
);
1325 args
.in
.ulSCLKFreq
=
1326 cpu_to_le32(adev
->pm
.dpm
.dyn_state
.vddc_dependency_on_sclk
.entries
[entry_id
].clk
);
1328 amdgpu_atom_execute_table(adev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1330 *voltage
= le16_to_cpu(args
.evv_out
.usVoltageLevel
);
1335 union voltage_object_info
{
1336 struct _ATOM_VOLTAGE_OBJECT_INFO v1
;
1337 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2
;
1338 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3
;
1341 union voltage_object
{
1342 struct _ATOM_VOLTAGE_OBJECT v1
;
1343 struct _ATOM_VOLTAGE_OBJECT_V2 v2
;
1344 union _ATOM_VOLTAGE_OBJECT_V3 v3
;
1348 static ATOM_VOLTAGE_OBJECT_V3
*amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1
*v3
,
1349 u8 voltage_type
, u8 voltage_mode
)
1351 u32 size
= le16_to_cpu(v3
->sHeader
.usStructureSize
);
1352 u32 offset
= offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1
, asVoltageObj
[0]);
1353 u8
*start
= (u8
*)v3
;
1355 while (offset
< size
) {
1356 ATOM_VOLTAGE_OBJECT_V3
*vo
= (ATOM_VOLTAGE_OBJECT_V3
*)(start
+ offset
);
1357 if ((vo
->asGpioVoltageObj
.sHeader
.ucVoltageType
== voltage_type
) &&
1358 (vo
->asGpioVoltageObj
.sHeader
.ucVoltageMode
== voltage_mode
))
1360 offset
+= le16_to_cpu(vo
->asGpioVoltageObj
.sHeader
.usSize
);
1366 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device
*adev
,
1367 u8 voltage_type
, u8 voltage_mode
)
1369 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
1371 u16 data_offset
, size
;
1372 union voltage_object_info
*voltage_info
;
1374 if (amdgpu_atom_parse_data_header(adev
->mode_info
.atom_context
, index
, &size
,
1375 &frev
, &crev
, &data_offset
)) {
1376 voltage_info
= (union voltage_object_info
*)
1377 (adev
->mode_info
.atom_context
->bios
+ data_offset
);
1383 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info
->v3
,
1384 voltage_type
, voltage_mode
))
1388 DRM_ERROR("unknown voltage object table\n");
1393 DRM_ERROR("unknown voltage object table\n");
1401 int amdgpu_atombios_get_voltage_table(struct amdgpu_device
*adev
,
1402 u8 voltage_type
, u8 voltage_mode
,
1403 struct atom_voltage_table
*voltage_table
)
1405 int index
= GetIndexIntoMasterTable(DATA
, VoltageObjectInfo
);
1407 u16 data_offset
, size
;
1409 union voltage_object_info
*voltage_info
;
1410 union voltage_object
*voltage_object
= NULL
;
1412 if (amdgpu_atom_parse_data_header(adev
->mode_info
.atom_context
, index
, &size
,
1413 &frev
, &crev
, &data_offset
)) {
1414 voltage_info
= (union voltage_object_info
*)
1415 (adev
->mode_info
.atom_context
->bios
+ data_offset
);
1421 voltage_object
= (union voltage_object
*)
1422 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info
->v3
,
1423 voltage_type
, voltage_mode
);
1424 if (voltage_object
) {
1425 ATOM_GPIO_VOLTAGE_OBJECT_V3
*gpio
=
1426 &voltage_object
->v3
.asGpioVoltageObj
;
1427 VOLTAGE_LUT_ENTRY_V2
*lut
;
1428 if (gpio
->ucGpioEntryNum
> MAX_VOLTAGE_ENTRIES
)
1430 lut
= &gpio
->asVolGpioLut
[0];
1431 for (i
= 0; i
< gpio
->ucGpioEntryNum
; i
++) {
1432 voltage_table
->entries
[i
].value
=
1433 le16_to_cpu(lut
->usVoltageValue
);
1434 voltage_table
->entries
[i
].smio_low
=
1435 le32_to_cpu(lut
->ulVoltageId
);
1436 lut
= (VOLTAGE_LUT_ENTRY_V2
*)
1437 ((u8
*)lut
+ sizeof(VOLTAGE_LUT_ENTRY_V2
));
1439 voltage_table
->mask_low
= le32_to_cpu(gpio
->ulGpioMaskVal
);
1440 voltage_table
->count
= gpio
->ucGpioEntryNum
;
1441 voltage_table
->phase_delay
= gpio
->ucPhaseDelay
;
1446 DRM_ERROR("unknown voltage object table\n");
1451 DRM_ERROR("unknown voltage object table\n");
1459 struct _ATOM_VRAM_INFO_V3 v1_3
;
1460 struct _ATOM_VRAM_INFO_V4 v1_4
;
1461 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1
;
1464 #define MEM_ID_MASK 0xff000000
1465 #define MEM_ID_SHIFT 24
1466 #define CLOCK_RANGE_MASK 0x00ffffff
1467 #define CLOCK_RANGE_SHIFT 0
1468 #define LOW_NIBBLE_MASK 0xf
1469 #define DATA_EQU_PREV 0
1470 #define DATA_FROM_TABLE 4
1472 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device
*adev
,
1474 struct atom_mc_reg_table
*reg_table
)
1476 int index
= GetIndexIntoMasterTable(DATA
, VRAM_Info
);
1477 u8 frev
, crev
, num_entries
, t_mem_id
, num_ranges
= 0;
1479 u16 data_offset
, size
;
1480 union vram_info
*vram_info
;
1482 memset(reg_table
, 0, sizeof(struct atom_mc_reg_table
));
1484 if (amdgpu_atom_parse_data_header(adev
->mode_info
.atom_context
, index
, &size
,
1485 &frev
, &crev
, &data_offset
)) {
1486 vram_info
= (union vram_info
*)
1487 (adev
->mode_info
.atom_context
->bios
+ data_offset
);
1490 DRM_ERROR("old table version %d, %d\n", frev
, crev
);
1495 if (module_index
< vram_info
->v2_1
.ucNumOfVRAMModule
) {
1496 ATOM_INIT_REG_BLOCK
*reg_block
=
1497 (ATOM_INIT_REG_BLOCK
*)
1498 ((u8
*)vram_info
+ le16_to_cpu(vram_info
->v2_1
.usMemClkPatchTblOffset
));
1499 ATOM_MEMORY_SETTING_DATA_BLOCK
*reg_data
=
1500 (ATOM_MEMORY_SETTING_DATA_BLOCK
*)
1501 ((u8
*)reg_block
+ (2 * sizeof(u16
)) +
1502 le16_to_cpu(reg_block
->usRegIndexTblSize
));
1503 ATOM_INIT_REG_INDEX_FORMAT
*format
= ®_block
->asRegIndexBuf
[0];
1504 num_entries
= (u8
)((le16_to_cpu(reg_block
->usRegIndexTblSize
)) /
1505 sizeof(ATOM_INIT_REG_INDEX_FORMAT
)) - 1;
1506 if (num_entries
> VBIOS_MC_REGISTER_ARRAY_SIZE
)
1508 while (i
< num_entries
) {
1509 if (format
->ucPreRegDataLength
& ACCESS_PLACEHOLDER
)
1511 reg_table
->mc_reg_address
[i
].s1
=
1512 (u16
)(le16_to_cpu(format
->usRegIndex
));
1513 reg_table
->mc_reg_address
[i
].pre_reg_data
=
1514 (u8
)(format
->ucPreRegDataLength
);
1516 format
= (ATOM_INIT_REG_INDEX_FORMAT
*)
1517 ((u8
*)format
+ sizeof(ATOM_INIT_REG_INDEX_FORMAT
));
1519 reg_table
->last
= i
;
1520 while ((le32_to_cpu(*(u32
*)reg_data
) != END_OF_REG_DATA_BLOCK
) &&
1521 (num_ranges
< VBIOS_MAX_AC_TIMING_ENTRIES
)) {
1522 t_mem_id
= (u8
)((le32_to_cpu(*(u32
*)reg_data
) & MEM_ID_MASK
)
1524 if (module_index
== t_mem_id
) {
1525 reg_table
->mc_reg_table_entry
[num_ranges
].mclk_max
=
1526 (u32
)((le32_to_cpu(*(u32
*)reg_data
) & CLOCK_RANGE_MASK
)
1527 >> CLOCK_RANGE_SHIFT
);
1528 for (i
= 0, j
= 1; i
< reg_table
->last
; i
++) {
1529 if ((reg_table
->mc_reg_address
[i
].pre_reg_data
& LOW_NIBBLE_MASK
) == DATA_FROM_TABLE
) {
1530 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
] =
1531 (u32
)le32_to_cpu(*((u32
*)reg_data
+ j
));
1533 } else if ((reg_table
->mc_reg_address
[i
].pre_reg_data
& LOW_NIBBLE_MASK
) == DATA_EQU_PREV
) {
1534 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
] =
1535 reg_table
->mc_reg_table_entry
[num_ranges
].mc_data
[i
- 1];
1540 reg_data
= (ATOM_MEMORY_SETTING_DATA_BLOCK
*)
1541 ((u8
*)reg_data
+ le16_to_cpu(reg_block
->usRegDataBlkSize
));
1543 if (le32_to_cpu(*(u32
*)reg_data
) != END_OF_REG_DATA_BLOCK
)
1545 reg_table
->num_entries
= num_ranges
;
1550 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1555 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
1563 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device
*adev
)
1565 int index
= GetIndexIntoMasterTable(DATA
, GPUVirtualizationInfo
);
1567 u16 data_offset
, size
;
1569 if (amdgpu_atom_parse_data_header(adev
->mode_info
.atom_context
, index
, &size
,
1570 &frev
, &crev
, &data_offset
))
1576 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device
*adev
, bool lock
)
1578 uint32_t bios_6_scratch
;
1580 bios_6_scratch
= RREG32(mmBIOS_SCRATCH_6
);
1583 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
1584 bios_6_scratch
&= ~ATOM_S6_ACC_MODE
;
1586 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
1587 bios_6_scratch
|= ATOM_S6_ACC_MODE
;
1590 WREG32(mmBIOS_SCRATCH_6
, bios_6_scratch
);
1593 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device
*adev
)
1595 uint32_t bios_2_scratch
, bios_6_scratch
;
1597 bios_2_scratch
= RREG32(mmBIOS_SCRATCH_2
);
1598 bios_6_scratch
= RREG32(mmBIOS_SCRATCH_6
);
1600 /* let the bios control the backlight */
1601 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
1603 /* tell the bios not to handle mode switching */
1604 bios_6_scratch
|= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
;
1606 /* clear the vbios dpms state */
1607 bios_2_scratch
&= ~ATOM_S2_DEVICE_DPMS_STATE
;
1609 WREG32(mmBIOS_SCRATCH_2
, bios_2_scratch
);
1610 WREG32(mmBIOS_SCRATCH_6
, bios_6_scratch
);
1613 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device
*adev
)
1617 for (i
= 0; i
< AMDGPU_BIOS_NUM_SCRATCH
; i
++)
1618 adev
->bios_scratch
[i
] = RREG32(mmBIOS_SCRATCH_0
+ i
);
1621 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device
*adev
)
1625 for (i
= 0; i
< AMDGPU_BIOS_NUM_SCRATCH
; i
++)
1626 WREG32(mmBIOS_SCRATCH_0
+ i
, adev
->bios_scratch
[i
]);
1629 /* Atom needs data in little endian format
1630 * so swap as appropriate when copying data to
1631 * or from atom. Note that atom operates on
1634 void amdgpu_atombios_copy_swap(u8
*dst
, u8
*src
, u8 num_bytes
, bool to_le
)
1637 u8 src_tmp
[20], dst_tmp
[20]; /* used for byteswapping */
1641 memcpy(src_tmp
, src
, num_bytes
);
1642 src32
= (u32
*)src_tmp
;
1643 dst32
= (u32
*)dst_tmp
;
1645 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
1646 dst32
[i
] = cpu_to_le32(src32
[i
]);
1647 memcpy(dst
, dst_tmp
, num_bytes
);
1649 u8 dws
= num_bytes
& ~3;
1650 for (i
= 0; i
< ((num_bytes
+ 3) / 4); i
++)
1651 dst32
[i
] = le32_to_cpu(src32
[i
]);
1652 memcpy(dst
, dst_tmp
, dws
);
1653 if (num_bytes
% 4) {
1654 for (i
= 0; i
< (num_bytes
% 4); i
++)
1655 dst
[dws
+i
] = dst_tmp
[dws
+i
];
1659 memcpy(dst
, src
, num_bytes
);