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drm/i915: Update DRIVER_DATE to 20160214
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_atombios.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_i2c.h"
31
32 #include "atom.h"
33 #include "atom-bits.h"
34 #include "atombios_encoders.h"
35 #include "bif/bif_4_1_d.h"
36
37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
38 ATOM_GPIO_I2C_ASSIGMENT *gpio,
39 u8 index)
40 {
41
42 }
43
44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
45 {
46 struct amdgpu_i2c_bus_rec i2c;
47
48 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
49
50 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
51 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
52 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
53 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
54 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
55 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
56 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
57 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
58 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
59 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
60 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
61 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
62 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
63 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
64 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
65 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
66
67 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
68 i2c.hw_capable = true;
69 else
70 i2c.hw_capable = false;
71
72 if (gpio->sucI2cId.ucAccess == 0xa0)
73 i2c.mm_i2c = true;
74 else
75 i2c.mm_i2c = false;
76
77 i2c.i2c_id = gpio->sucI2cId.ucAccess;
78
79 if (i2c.mask_clk_reg)
80 i2c.valid = true;
81 else
82 i2c.valid = false;
83
84 return i2c;
85 }
86
87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
88 uint8_t id)
89 {
90 struct atom_context *ctx = adev->mode_info.atom_context;
91 ATOM_GPIO_I2C_ASSIGMENT *gpio;
92 struct amdgpu_i2c_bus_rec i2c;
93 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
94 struct _ATOM_GPIO_I2C_INFO *i2c_info;
95 uint16_t data_offset, size;
96 int i, num_indices;
97
98 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
99 i2c.valid = false;
100
101 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
102 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
103
104 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
105 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
106
107 gpio = &i2c_info->asGPIO_Info[0];
108 for (i = 0; i < num_indices; i++) {
109
110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
111
112 if (gpio->sucI2cId.ucAccess == id) {
113 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
114 break;
115 }
116 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
117 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
118 }
119 }
120
121 return i2c;
122 }
123
124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
125 {
126 struct atom_context *ctx = adev->mode_info.atom_context;
127 ATOM_GPIO_I2C_ASSIGMENT *gpio;
128 struct amdgpu_i2c_bus_rec i2c;
129 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
130 struct _ATOM_GPIO_I2C_INFO *i2c_info;
131 uint16_t data_offset, size;
132 int i, num_indices;
133 char stmp[32];
134
135 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
137
138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
139 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
140
141 gpio = &i2c_info->asGPIO_Info[0];
142 for (i = 0; i < num_indices; i++) {
143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
144
145 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
146
147 if (i2c.valid) {
148 sprintf(stmp, "0x%x", i2c.i2c_id);
149 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
150 }
151 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
152 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
153 }
154 }
155 }
156
157 struct amdgpu_gpio_rec
158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
159 u8 id)
160 {
161 struct atom_context *ctx = adev->mode_info.atom_context;
162 struct amdgpu_gpio_rec gpio;
163 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
164 struct _ATOM_GPIO_PIN_LUT *gpio_info;
165 ATOM_GPIO_PIN_ASSIGNMENT *pin;
166 u16 data_offset, size;
167 int i, num_indices;
168
169 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
170 gpio.valid = false;
171
172 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
173 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
174
175 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
177
178 pin = gpio_info->asGPIO_Pin;
179 for (i = 0; i < num_indices; i++) {
180 if (id == pin->ucGPIO_ID) {
181 gpio.id = pin->ucGPIO_ID;
182 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
183 gpio.shift = pin->ucGpioPinBitShift;
184 gpio.mask = (1 << pin->ucGpioPinBitShift);
185 gpio.valid = true;
186 break;
187 }
188 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
189 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
190 }
191 }
192
193 return gpio;
194 }
195
196 static struct amdgpu_hpd
197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
198 struct amdgpu_gpio_rec *gpio)
199 {
200 struct amdgpu_hpd hpd;
201 u32 reg;
202
203 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
204
205 reg = amdgpu_display_hpd_get_gpio_reg(adev);
206
207 hpd.gpio = *gpio;
208 if (gpio->reg == reg) {
209 switch(gpio->mask) {
210 case (1 << 0):
211 hpd.hpd = AMDGPU_HPD_1;
212 break;
213 case (1 << 8):
214 hpd.hpd = AMDGPU_HPD_2;
215 break;
216 case (1 << 16):
217 hpd.hpd = AMDGPU_HPD_3;
218 break;
219 case (1 << 24):
220 hpd.hpd = AMDGPU_HPD_4;
221 break;
222 case (1 << 26):
223 hpd.hpd = AMDGPU_HPD_5;
224 break;
225 case (1 << 28):
226 hpd.hpd = AMDGPU_HPD_6;
227 break;
228 default:
229 hpd.hpd = AMDGPU_HPD_NONE;
230 break;
231 }
232 } else
233 hpd.hpd = AMDGPU_HPD_NONE;
234 return hpd;
235 }
236
237 static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev,
238 uint32_t supported_device,
239 int *connector_type,
240 struct amdgpu_i2c_bus_rec *i2c_bus,
241 uint16_t *line_mux,
242 struct amdgpu_hpd *hpd)
243 {
244 return true;
245 }
246
247 static const int object_connector_convert[] = {
248 DRM_MODE_CONNECTOR_Unknown,
249 DRM_MODE_CONNECTOR_DVII,
250 DRM_MODE_CONNECTOR_DVII,
251 DRM_MODE_CONNECTOR_DVID,
252 DRM_MODE_CONNECTOR_DVID,
253 DRM_MODE_CONNECTOR_VGA,
254 DRM_MODE_CONNECTOR_Composite,
255 DRM_MODE_CONNECTOR_SVIDEO,
256 DRM_MODE_CONNECTOR_Unknown,
257 DRM_MODE_CONNECTOR_Unknown,
258 DRM_MODE_CONNECTOR_9PinDIN,
259 DRM_MODE_CONNECTOR_Unknown,
260 DRM_MODE_CONNECTOR_HDMIA,
261 DRM_MODE_CONNECTOR_HDMIB,
262 DRM_MODE_CONNECTOR_LVDS,
263 DRM_MODE_CONNECTOR_9PinDIN,
264 DRM_MODE_CONNECTOR_Unknown,
265 DRM_MODE_CONNECTOR_Unknown,
266 DRM_MODE_CONNECTOR_Unknown,
267 DRM_MODE_CONNECTOR_DisplayPort,
268 DRM_MODE_CONNECTOR_eDP,
269 DRM_MODE_CONNECTOR_Unknown
270 };
271
272 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
273 {
274 struct amdgpu_mode_info *mode_info = &adev->mode_info;
275 struct atom_context *ctx = mode_info->atom_context;
276 int index = GetIndexIntoMasterTable(DATA, Object_Header);
277 u16 size, data_offset;
278 u8 frev, crev;
279 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
280 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
281 ATOM_OBJECT_TABLE *router_obj;
282 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
283 ATOM_OBJECT_HEADER *obj_header;
284 int i, j, k, path_size, device_support;
285 int connector_type;
286 u16 conn_id, connector_object_id;
287 struct amdgpu_i2c_bus_rec ddc_bus;
288 struct amdgpu_router router;
289 struct amdgpu_gpio_rec gpio;
290 struct amdgpu_hpd hpd;
291
292 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
293 return false;
294
295 if (crev < 2)
296 return false;
297
298 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
299 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
300 (ctx->bios + data_offset +
301 le16_to_cpu(obj_header->usDisplayPathTableOffset));
302 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
303 (ctx->bios + data_offset +
304 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
305 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
306 (ctx->bios + data_offset +
307 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
308 router_obj = (ATOM_OBJECT_TABLE *)
309 (ctx->bios + data_offset +
310 le16_to_cpu(obj_header->usRouterObjectTableOffset));
311 device_support = le16_to_cpu(obj_header->usDeviceSupport);
312
313 path_size = 0;
314 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
315 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
316 ATOM_DISPLAY_OBJECT_PATH *path;
317 addr += path_size;
318 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
319 path_size += le16_to_cpu(path->usSize);
320
321 if (device_support & le16_to_cpu(path->usDeviceTag)) {
322 uint8_t con_obj_id, con_obj_num, con_obj_type;
323
324 con_obj_id =
325 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
326 >> OBJECT_ID_SHIFT;
327 con_obj_num =
328 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
329 >> ENUM_ID_SHIFT;
330 con_obj_type =
331 (le16_to_cpu(path->usConnObjectId) &
332 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
333
334 connector_type =
335 object_connector_convert[con_obj_id];
336 connector_object_id = con_obj_id;
337
338 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
339 continue;
340
341 router.ddc_valid = false;
342 router.cd_valid = false;
343 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
344 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
345
346 grph_obj_id =
347 (le16_to_cpu(path->usGraphicObjIds[j]) &
348 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
349 grph_obj_num =
350 (le16_to_cpu(path->usGraphicObjIds[j]) &
351 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
352 grph_obj_type =
353 (le16_to_cpu(path->usGraphicObjIds[j]) &
354 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
355
356 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
357 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
358 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
359 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
360 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
361 (ctx->bios + data_offset +
362 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
363 ATOM_ENCODER_CAP_RECORD *cap_record;
364 u16 caps = 0;
365
366 while (record->ucRecordSize > 0 &&
367 record->ucRecordType > 0 &&
368 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
369 switch (record->ucRecordType) {
370 case ATOM_ENCODER_CAP_RECORD_TYPE:
371 cap_record =(ATOM_ENCODER_CAP_RECORD *)
372 record;
373 caps = le16_to_cpu(cap_record->usEncoderCap);
374 break;
375 }
376 record = (ATOM_COMMON_RECORD_HEADER *)
377 ((char *)record + record->ucRecordSize);
378 }
379 amdgpu_display_add_encoder(adev, encoder_obj,
380 le16_to_cpu(path->usDeviceTag),
381 caps);
382 }
383 }
384 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
385 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
386 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
387 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
388 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
389 (ctx->bios + data_offset +
390 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
391 ATOM_I2C_RECORD *i2c_record;
392 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
393 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
394 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
395 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
396 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
397 (ctx->bios + data_offset +
398 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
399 u8 *num_dst_objs = (u8 *)
400 ((u8 *)router_src_dst_table + 1 +
401 (router_src_dst_table->ucNumberOfSrc * 2));
402 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
403 int enum_id;
404
405 router.router_id = router_obj_id;
406 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
407 if (le16_to_cpu(path->usConnObjectId) ==
408 le16_to_cpu(dst_objs[enum_id]))
409 break;
410 }
411
412 while (record->ucRecordSize > 0 &&
413 record->ucRecordType > 0 &&
414 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
415 switch (record->ucRecordType) {
416 case ATOM_I2C_RECORD_TYPE:
417 i2c_record =
418 (ATOM_I2C_RECORD *)
419 record;
420 i2c_config =
421 (ATOM_I2C_ID_CONFIG_ACCESS *)
422 &i2c_record->sucI2cId;
423 router.i2c_info =
424 amdgpu_atombios_lookup_i2c_gpio(adev,
425 i2c_config->
426 ucAccess);
427 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
428 break;
429 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
430 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
431 record;
432 router.ddc_valid = true;
433 router.ddc_mux_type = ddc_path->ucMuxType;
434 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
435 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
436 break;
437 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
438 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
439 record;
440 router.cd_valid = true;
441 router.cd_mux_type = cd_path->ucMuxType;
442 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
443 router.cd_mux_state = cd_path->ucMuxState[enum_id];
444 break;
445 }
446 record = (ATOM_COMMON_RECORD_HEADER *)
447 ((char *)record + record->ucRecordSize);
448 }
449 }
450 }
451 }
452 }
453
454 /* look up gpio for ddc, hpd */
455 ddc_bus.valid = false;
456 hpd.hpd = AMDGPU_HPD_NONE;
457 if ((le16_to_cpu(path->usDeviceTag) &
458 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
459 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
460 if (le16_to_cpu(path->usConnObjectId) ==
461 le16_to_cpu(con_obj->asObjects[j].
462 usObjectID)) {
463 ATOM_COMMON_RECORD_HEADER
464 *record =
465 (ATOM_COMMON_RECORD_HEADER
466 *)
467 (ctx->bios + data_offset +
468 le16_to_cpu(con_obj->
469 asObjects[j].
470 usRecordOffset));
471 ATOM_I2C_RECORD *i2c_record;
472 ATOM_HPD_INT_RECORD *hpd_record;
473 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
474
475 while (record->ucRecordSize > 0 &&
476 record->ucRecordType > 0 &&
477 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
478 switch (record->ucRecordType) {
479 case ATOM_I2C_RECORD_TYPE:
480 i2c_record =
481 (ATOM_I2C_RECORD *)
482 record;
483 i2c_config =
484 (ATOM_I2C_ID_CONFIG_ACCESS *)
485 &i2c_record->sucI2cId;
486 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
487 i2c_config->
488 ucAccess);
489 break;
490 case ATOM_HPD_INT_RECORD_TYPE:
491 hpd_record =
492 (ATOM_HPD_INT_RECORD *)
493 record;
494 gpio = amdgpu_atombios_lookup_gpio(adev,
495 hpd_record->ucHPDIntGPIOID);
496 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
497 hpd.plugged_state = hpd_record->ucPlugged_PinState;
498 break;
499 }
500 record =
501 (ATOM_COMMON_RECORD_HEADER
502 *) ((char *)record
503 +
504 record->
505 ucRecordSize);
506 }
507 break;
508 }
509 }
510 }
511
512 /* needed for aux chan transactions */
513 ddc_bus.hpd = hpd.hpd;
514
515 conn_id = le16_to_cpu(path->usConnObjectId);
516
517 if (!amdgpu_atombios_apply_quirks
518 (adev, le16_to_cpu(path->usDeviceTag), &connector_type,
519 &ddc_bus, &conn_id, &hpd))
520 continue;
521
522 amdgpu_display_add_connector(adev,
523 conn_id,
524 le16_to_cpu(path->usDeviceTag),
525 connector_type, &ddc_bus,
526 connector_object_id,
527 &hpd,
528 &router);
529
530 }
531 }
532
533 amdgpu_link_encoder_connector(adev->ddev);
534
535 return true;
536 }
537
538 union firmware_info {
539 ATOM_FIRMWARE_INFO info;
540 ATOM_FIRMWARE_INFO_V1_2 info_12;
541 ATOM_FIRMWARE_INFO_V1_3 info_13;
542 ATOM_FIRMWARE_INFO_V1_4 info_14;
543 ATOM_FIRMWARE_INFO_V2_1 info_21;
544 ATOM_FIRMWARE_INFO_V2_2 info_22;
545 };
546
547 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
548 {
549 struct amdgpu_mode_info *mode_info = &adev->mode_info;
550 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
551 uint8_t frev, crev;
552 uint16_t data_offset;
553 int ret = -EINVAL;
554
555 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
556 &frev, &crev, &data_offset)) {
557 int i;
558 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
559 struct amdgpu_pll *spll = &adev->clock.spll;
560 struct amdgpu_pll *mpll = &adev->clock.mpll;
561 union firmware_info *firmware_info =
562 (union firmware_info *)(mode_info->atom_context->bios +
563 data_offset);
564 /* pixel clocks */
565 ppll->reference_freq =
566 le16_to_cpu(firmware_info->info.usReferenceClock);
567 ppll->reference_div = 0;
568
569 if (crev < 2)
570 ppll->pll_out_min =
571 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
572 else
573 ppll->pll_out_min =
574 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
575 ppll->pll_out_max =
576 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
577
578 if (crev >= 4) {
579 ppll->lcd_pll_out_min =
580 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
581 if (ppll->lcd_pll_out_min == 0)
582 ppll->lcd_pll_out_min = ppll->pll_out_min;
583 ppll->lcd_pll_out_max =
584 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
585 if (ppll->lcd_pll_out_max == 0)
586 ppll->lcd_pll_out_max = ppll->pll_out_max;
587 } else {
588 ppll->lcd_pll_out_min = ppll->pll_out_min;
589 ppll->lcd_pll_out_max = ppll->pll_out_max;
590 }
591
592 if (ppll->pll_out_min == 0)
593 ppll->pll_out_min = 64800;
594
595 ppll->pll_in_min =
596 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
597 ppll->pll_in_max =
598 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
599
600 ppll->min_post_div = 2;
601 ppll->max_post_div = 0x7f;
602 ppll->min_frac_feedback_div = 0;
603 ppll->max_frac_feedback_div = 9;
604 ppll->min_ref_div = 2;
605 ppll->max_ref_div = 0x3ff;
606 ppll->min_feedback_div = 4;
607 ppll->max_feedback_div = 0xfff;
608 ppll->best_vco = 0;
609
610 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
611 adev->clock.ppll[i] = *ppll;
612
613 /* system clock */
614 spll->reference_freq =
615 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
616 spll->reference_div = 0;
617
618 spll->pll_out_min =
619 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
620 spll->pll_out_max =
621 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
622
623 /* ??? */
624 if (spll->pll_out_min == 0)
625 spll->pll_out_min = 64800;
626
627 spll->pll_in_min =
628 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
629 spll->pll_in_max =
630 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
631
632 spll->min_post_div = 1;
633 spll->max_post_div = 1;
634 spll->min_ref_div = 2;
635 spll->max_ref_div = 0xff;
636 spll->min_feedback_div = 4;
637 spll->max_feedback_div = 0xff;
638 spll->best_vco = 0;
639
640 /* memory clock */
641 mpll->reference_freq =
642 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
643 mpll->reference_div = 0;
644
645 mpll->pll_out_min =
646 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
647 mpll->pll_out_max =
648 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
649
650 /* ??? */
651 if (mpll->pll_out_min == 0)
652 mpll->pll_out_min = 64800;
653
654 mpll->pll_in_min =
655 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
656 mpll->pll_in_max =
657 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
658
659 adev->clock.default_sclk =
660 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
661 adev->clock.default_mclk =
662 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
663
664 mpll->min_post_div = 1;
665 mpll->max_post_div = 1;
666 mpll->min_ref_div = 2;
667 mpll->max_ref_div = 0xff;
668 mpll->min_feedback_div = 4;
669 mpll->max_feedback_div = 0xff;
670 mpll->best_vco = 0;
671
672 /* disp clock */
673 adev->clock.default_dispclk =
674 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
675 /* set a reasonable default for DP */
676 if (adev->clock.default_dispclk < 53900) {
677 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
678 adev->clock.default_dispclk / 100);
679 adev->clock.default_dispclk = 60000;
680 }
681 adev->clock.dp_extclk =
682 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
683 adev->clock.current_dispclk = adev->clock.default_dispclk;
684
685 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
686 if (adev->clock.max_pixel_clock == 0)
687 adev->clock.max_pixel_clock = 40000;
688
689 /* not technically a clock, but... */
690 adev->mode_info.firmware_flags =
691 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
692
693 ret = 0;
694 }
695
696 adev->pm.current_sclk = adev->clock.default_sclk;
697 adev->pm.current_mclk = adev->clock.default_mclk;
698
699 return ret;
700 }
701
702 union igp_info {
703 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
704 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
705 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
706 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
707 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
708 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
709 };
710
711 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
712 struct amdgpu_atom_ss *ss,
713 int id)
714 {
715 struct amdgpu_mode_info *mode_info = &adev->mode_info;
716 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
717 u16 data_offset, size;
718 union igp_info *igp_info;
719 u8 frev, crev;
720 u16 percentage = 0, rate = 0;
721
722 /* get any igp specific overrides */
723 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
724 &frev, &crev, &data_offset)) {
725 igp_info = (union igp_info *)
726 (mode_info->atom_context->bios + data_offset);
727 switch (crev) {
728 case 6:
729 switch (id) {
730 case ASIC_INTERNAL_SS_ON_TMDS:
731 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
732 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
733 break;
734 case ASIC_INTERNAL_SS_ON_HDMI:
735 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
736 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
737 break;
738 case ASIC_INTERNAL_SS_ON_LVDS:
739 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
740 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
741 break;
742 }
743 break;
744 case 7:
745 switch (id) {
746 case ASIC_INTERNAL_SS_ON_TMDS:
747 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
748 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
749 break;
750 case ASIC_INTERNAL_SS_ON_HDMI:
751 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
752 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
753 break;
754 case ASIC_INTERNAL_SS_ON_LVDS:
755 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
756 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
757 break;
758 }
759 break;
760 case 8:
761 switch (id) {
762 case ASIC_INTERNAL_SS_ON_TMDS:
763 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
764 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
765 break;
766 case ASIC_INTERNAL_SS_ON_HDMI:
767 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
768 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
769 break;
770 case ASIC_INTERNAL_SS_ON_LVDS:
771 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
772 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
773 break;
774 }
775 break;
776 case 9:
777 switch (id) {
778 case ASIC_INTERNAL_SS_ON_TMDS:
779 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
780 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
781 break;
782 case ASIC_INTERNAL_SS_ON_HDMI:
783 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
784 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
785 break;
786 case ASIC_INTERNAL_SS_ON_LVDS:
787 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
788 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
789 break;
790 }
791 break;
792 default:
793 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
794 break;
795 }
796 if (percentage)
797 ss->percentage = percentage;
798 if (rate)
799 ss->rate = rate;
800 }
801 }
802
803 union asic_ss_info {
804 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
805 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
806 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
807 };
808
809 union asic_ss_assignment {
810 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
811 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
812 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
813 };
814
815 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
816 struct amdgpu_atom_ss *ss,
817 int id, u32 clock)
818 {
819 struct amdgpu_mode_info *mode_info = &adev->mode_info;
820 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
821 uint16_t data_offset, size;
822 union asic_ss_info *ss_info;
823 union asic_ss_assignment *ss_assign;
824 uint8_t frev, crev;
825 int i, num_indices;
826
827 if (id == ASIC_INTERNAL_MEMORY_SS) {
828 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
829 return false;
830 }
831 if (id == ASIC_INTERNAL_ENGINE_SS) {
832 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
833 return false;
834 }
835
836 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
837 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
838 &frev, &crev, &data_offset)) {
839
840 ss_info =
841 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
842
843 switch (frev) {
844 case 1:
845 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
846 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
847
848 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
849 for (i = 0; i < num_indices; i++) {
850 if ((ss_assign->v1.ucClockIndication == id) &&
851 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
852 ss->percentage =
853 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
854 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
855 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
856 ss->percentage_divider = 100;
857 return true;
858 }
859 ss_assign = (union asic_ss_assignment *)
860 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
861 }
862 break;
863 case 2:
864 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
865 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
866 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
867 for (i = 0; i < num_indices; i++) {
868 if ((ss_assign->v2.ucClockIndication == id) &&
869 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
870 ss->percentage =
871 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
872 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
873 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
874 ss->percentage_divider = 100;
875 if ((crev == 2) &&
876 ((id == ASIC_INTERNAL_ENGINE_SS) ||
877 (id == ASIC_INTERNAL_MEMORY_SS)))
878 ss->rate /= 100;
879 return true;
880 }
881 ss_assign = (union asic_ss_assignment *)
882 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
883 }
884 break;
885 case 3:
886 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
887 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
888 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
889 for (i = 0; i < num_indices; i++) {
890 if ((ss_assign->v3.ucClockIndication == id) &&
891 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
892 ss->percentage =
893 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
894 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
895 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
896 if (ss_assign->v3.ucSpreadSpectrumMode &
897 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
898 ss->percentage_divider = 1000;
899 else
900 ss->percentage_divider = 100;
901 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
902 (id == ASIC_INTERNAL_MEMORY_SS))
903 ss->rate /= 100;
904 if (adev->flags & AMD_IS_APU)
905 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
906 return true;
907 }
908 ss_assign = (union asic_ss_assignment *)
909 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
910 }
911 break;
912 default:
913 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
914 break;
915 }
916
917 }
918 return false;
919 }
920
921 union get_clock_dividers {
922 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
923 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
924 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
925 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
926 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
927 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
928 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
929 };
930
931 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
932 u8 clock_type,
933 u32 clock,
934 bool strobe_mode,
935 struct atom_clock_dividers *dividers)
936 {
937 union get_clock_dividers args;
938 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
939 u8 frev, crev;
940
941 memset(&args, 0, sizeof(args));
942 memset(dividers, 0, sizeof(struct atom_clock_dividers));
943
944 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
945 return -EINVAL;
946
947 switch (crev) {
948 case 4:
949 /* fusion */
950 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
951
952 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
953
954 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
955 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
956 break;
957 case 6:
958 /* CI */
959 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
960 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
961 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
962
963 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
964
965 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
966 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
967 dividers->ref_div = args.v6_out.ucPllRefDiv;
968 dividers->post_div = args.v6_out.ucPllPostDiv;
969 dividers->flags = args.v6_out.ucPllCntlFlag;
970 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
971 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
972 break;
973 default:
974 return -EINVAL;
975 }
976 return 0;
977 }
978
979 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
980 u32 clock,
981 bool strobe_mode,
982 struct atom_mpll_param *mpll_param)
983 {
984 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
985 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
986 u8 frev, crev;
987
988 memset(&args, 0, sizeof(args));
989 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
990
991 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
992 return -EINVAL;
993
994 switch (frev) {
995 case 2:
996 switch (crev) {
997 case 1:
998 /* SI */
999 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1000 args.ucInputFlag = 0;
1001 if (strobe_mode)
1002 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1003
1004 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1005
1006 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1007 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1008 mpll_param->post_div = args.ucPostDiv;
1009 mpll_param->dll_speed = args.ucDllSpeed;
1010 mpll_param->bwcntl = args.ucBWCntl;
1011 mpll_param->vco_mode =
1012 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1013 mpll_param->yclk_sel =
1014 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1015 mpll_param->qdr =
1016 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1017 mpll_param->half_rate =
1018 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1019 break;
1020 default:
1021 return -EINVAL;
1022 }
1023 break;
1024 default:
1025 return -EINVAL;
1026 }
1027 return 0;
1028 }
1029
1030 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev)
1031 {
1032 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1033 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1034
1035 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1036 return le32_to_cpu(args.ulReturnEngineClock);
1037 }
1038
1039 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev)
1040 {
1041 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1042 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1043
1044 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1045 return le32_to_cpu(args.ulReturnMemoryClock);
1046 }
1047
1048 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev,
1049 uint32_t eng_clock)
1050 {
1051 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1052 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1053
1054 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
1055
1056 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1057 }
1058
1059 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1060 uint32_t mem_clock)
1061 {
1062 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1063 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1064
1065 if (adev->flags & AMD_IS_APU)
1066 return;
1067
1068 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
1069
1070 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1071 }
1072
1073 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1074 u32 eng_clock, u32 mem_clock)
1075 {
1076 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1077 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1078 u32 tmp;
1079
1080 memset(&args, 0, sizeof(args));
1081
1082 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1083 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1084
1085 args.ulTargetEngineClock = cpu_to_le32(tmp);
1086 if (mem_clock)
1087 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1088
1089 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1090 }
1091
1092 union set_voltage {
1093 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1094 struct _SET_VOLTAGE_PARAMETERS v1;
1095 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1096 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1097 };
1098
1099 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,
1100 u16 voltage_level,
1101 u8 voltage_type)
1102 {
1103 union set_voltage args;
1104 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1105 u8 frev, crev, volt_index = voltage_level;
1106
1107 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1108 return;
1109
1110 /* 0xff01 is a flag rather then an actual voltage */
1111 if (voltage_level == 0xff01)
1112 return;
1113
1114 switch (crev) {
1115 case 1:
1116 args.v1.ucVoltageType = voltage_type;
1117 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
1118 args.v1.ucVoltageIndex = volt_index;
1119 break;
1120 case 2:
1121 args.v2.ucVoltageType = voltage_type;
1122 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
1123 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
1124 break;
1125 case 3:
1126 args.v3.ucVoltageType = voltage_type;
1127 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
1128 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
1129 break;
1130 default:
1131 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1132 return;
1133 }
1134
1135 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1136 }
1137
1138 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1139 u16 *leakage_id)
1140 {
1141 union set_voltage args;
1142 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1143 u8 frev, crev;
1144
1145 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1146 return -EINVAL;
1147
1148 switch (crev) {
1149 case 3:
1150 case 4:
1151 args.v3.ucVoltageType = 0;
1152 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1153 args.v3.usVoltageLevel = 0;
1154
1155 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1156
1157 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1158 break;
1159 default:
1160 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1161 return -EINVAL;
1162 }
1163
1164 return 0;
1165 }
1166
1167 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1168 u16 *vddc, u16 *vddci,
1169 u16 virtual_voltage_id,
1170 u16 vbios_voltage_id)
1171 {
1172 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1173 u8 frev, crev;
1174 u16 data_offset, size;
1175 int i, j;
1176 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1177 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1178
1179 *vddc = 0;
1180 *vddci = 0;
1181
1182 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1183 &frev, &crev, &data_offset))
1184 return -EINVAL;
1185
1186 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1187 (adev->mode_info.atom_context->bios + data_offset);
1188
1189 switch (frev) {
1190 case 1:
1191 return -EINVAL;
1192 case 2:
1193 switch (crev) {
1194 case 1:
1195 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1196 return -EINVAL;
1197 leakage_bin = (u16 *)
1198 (adev->mode_info.atom_context->bios + data_offset +
1199 le16_to_cpu(profile->usLeakageBinArrayOffset));
1200 vddc_id_buf = (u16 *)
1201 (adev->mode_info.atom_context->bios + data_offset +
1202 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1203 vddc_buf = (u16 *)
1204 (adev->mode_info.atom_context->bios + data_offset +
1205 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1206 vddci_id_buf = (u16 *)
1207 (adev->mode_info.atom_context->bios + data_offset +
1208 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1209 vddci_buf = (u16 *)
1210 (adev->mode_info.atom_context->bios + data_offset +
1211 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1212
1213 if (profile->ucElbVDDC_Num > 0) {
1214 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1215 if (vddc_id_buf[i] == virtual_voltage_id) {
1216 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1217 if (vbios_voltage_id <= leakage_bin[j]) {
1218 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1219 break;
1220 }
1221 }
1222 break;
1223 }
1224 }
1225 }
1226 if (profile->ucElbVDDCI_Num > 0) {
1227 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1228 if (vddci_id_buf[i] == virtual_voltage_id) {
1229 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1230 if (vbios_voltage_id <= leakage_bin[j]) {
1231 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1232 break;
1233 }
1234 }
1235 break;
1236 }
1237 }
1238 }
1239 break;
1240 default:
1241 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1242 return -EINVAL;
1243 }
1244 break;
1245 default:
1246 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1247 return -EINVAL;
1248 }
1249
1250 return 0;
1251 }
1252
1253 union get_voltage_info {
1254 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1255 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1256 };
1257
1258 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1259 u16 virtual_voltage_id,
1260 u16 *voltage)
1261 {
1262 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1263 u32 entry_id;
1264 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1265 union get_voltage_info args;
1266
1267 for (entry_id = 0; entry_id < count; entry_id++) {
1268 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1269 virtual_voltage_id)
1270 break;
1271 }
1272
1273 if (entry_id >= count)
1274 return -EINVAL;
1275
1276 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1277 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1278 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1279 args.in.ulSCLKFreq =
1280 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1281
1282 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1283
1284 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1285
1286 return 0;
1287 }
1288
1289 union voltage_object_info {
1290 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1291 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1292 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1293 };
1294
1295 union voltage_object {
1296 struct _ATOM_VOLTAGE_OBJECT v1;
1297 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1298 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1299 };
1300
1301
1302 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1303 u8 voltage_type, u8 voltage_mode)
1304 {
1305 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1306 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1307 u8 *start = (u8*)v3;
1308
1309 while (offset < size) {
1310 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1311 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1312 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1313 return vo;
1314 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1315 }
1316 return NULL;
1317 }
1318
1319 bool
1320 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1321 u8 voltage_type, u8 voltage_mode)
1322 {
1323 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1324 u8 frev, crev;
1325 u16 data_offset, size;
1326 union voltage_object_info *voltage_info;
1327
1328 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1329 &frev, &crev, &data_offset)) {
1330 voltage_info = (union voltage_object_info *)
1331 (adev->mode_info.atom_context->bios + data_offset);
1332
1333 switch (frev) {
1334 case 3:
1335 switch (crev) {
1336 case 1:
1337 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1338 voltage_type, voltage_mode))
1339 return true;
1340 break;
1341 default:
1342 DRM_ERROR("unknown voltage object table\n");
1343 return false;
1344 }
1345 break;
1346 default:
1347 DRM_ERROR("unknown voltage object table\n");
1348 return false;
1349 }
1350
1351 }
1352 return false;
1353 }
1354
1355 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1356 u8 voltage_type, u8 voltage_mode,
1357 struct atom_voltage_table *voltage_table)
1358 {
1359 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1360 u8 frev, crev;
1361 u16 data_offset, size;
1362 int i;
1363 union voltage_object_info *voltage_info;
1364 union voltage_object *voltage_object = NULL;
1365
1366 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1367 &frev, &crev, &data_offset)) {
1368 voltage_info = (union voltage_object_info *)
1369 (adev->mode_info.atom_context->bios + data_offset);
1370
1371 switch (frev) {
1372 case 3:
1373 switch (crev) {
1374 case 1:
1375 voltage_object = (union voltage_object *)
1376 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1377 voltage_type, voltage_mode);
1378 if (voltage_object) {
1379 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1380 &voltage_object->v3.asGpioVoltageObj;
1381 VOLTAGE_LUT_ENTRY_V2 *lut;
1382 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1383 return -EINVAL;
1384 lut = &gpio->asVolGpioLut[0];
1385 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1386 voltage_table->entries[i].value =
1387 le16_to_cpu(lut->usVoltageValue);
1388 voltage_table->entries[i].smio_low =
1389 le32_to_cpu(lut->ulVoltageId);
1390 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1391 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1392 }
1393 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1394 voltage_table->count = gpio->ucGpioEntryNum;
1395 voltage_table->phase_delay = gpio->ucPhaseDelay;
1396 return 0;
1397 }
1398 break;
1399 default:
1400 DRM_ERROR("unknown voltage object table\n");
1401 return -EINVAL;
1402 }
1403 break;
1404 default:
1405 DRM_ERROR("unknown voltage object table\n");
1406 return -EINVAL;
1407 }
1408 }
1409 return -EINVAL;
1410 }
1411
1412 union vram_info {
1413 struct _ATOM_VRAM_INFO_V3 v1_3;
1414 struct _ATOM_VRAM_INFO_V4 v1_4;
1415 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1416 };
1417
1418 #define MEM_ID_MASK 0xff000000
1419 #define MEM_ID_SHIFT 24
1420 #define CLOCK_RANGE_MASK 0x00ffffff
1421 #define CLOCK_RANGE_SHIFT 0
1422 #define LOW_NIBBLE_MASK 0xf
1423 #define DATA_EQU_PREV 0
1424 #define DATA_FROM_TABLE 4
1425
1426 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1427 u8 module_index,
1428 struct atom_mc_reg_table *reg_table)
1429 {
1430 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1431 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1432 u32 i = 0, j;
1433 u16 data_offset, size;
1434 union vram_info *vram_info;
1435
1436 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1437
1438 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1439 &frev, &crev, &data_offset)) {
1440 vram_info = (union vram_info *)
1441 (adev->mode_info.atom_context->bios + data_offset);
1442 switch (frev) {
1443 case 1:
1444 DRM_ERROR("old table version %d, %d\n", frev, crev);
1445 return -EINVAL;
1446 case 2:
1447 switch (crev) {
1448 case 1:
1449 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1450 ATOM_INIT_REG_BLOCK *reg_block =
1451 (ATOM_INIT_REG_BLOCK *)
1452 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1453 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1454 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1455 ((u8 *)reg_block + (2 * sizeof(u16)) +
1456 le16_to_cpu(reg_block->usRegIndexTblSize));
1457 ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1458 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1459 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1460 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1461 return -EINVAL;
1462 while (i < num_entries) {
1463 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1464 break;
1465 reg_table->mc_reg_address[i].s1 =
1466 (u16)(le16_to_cpu(format->usRegIndex));
1467 reg_table->mc_reg_address[i].pre_reg_data =
1468 (u8)(format->ucPreRegDataLength);
1469 i++;
1470 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1471 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1472 }
1473 reg_table->last = i;
1474 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1475 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1476 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1477 >> MEM_ID_SHIFT);
1478 if (module_index == t_mem_id) {
1479 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1480 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1481 >> CLOCK_RANGE_SHIFT);
1482 for (i = 0, j = 1; i < reg_table->last; i++) {
1483 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1484 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1485 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1486 j++;
1487 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1488 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1489 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1490 }
1491 }
1492 num_ranges++;
1493 }
1494 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1495 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1496 }
1497 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1498 return -EINVAL;
1499 reg_table->num_entries = num_ranges;
1500 } else
1501 return -EINVAL;
1502 break;
1503 default:
1504 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1505 return -EINVAL;
1506 }
1507 break;
1508 default:
1509 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1510 return -EINVAL;
1511 }
1512 return 0;
1513 }
1514 return -EINVAL;
1515 }
1516
1517 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1518 {
1519 uint32_t bios_6_scratch;
1520
1521 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1522
1523 if (lock) {
1524 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1525 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1526 } else {
1527 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1528 bios_6_scratch |= ATOM_S6_ACC_MODE;
1529 }
1530
1531 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1532 }
1533
1534 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1535 {
1536 uint32_t bios_2_scratch, bios_6_scratch;
1537
1538 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
1539 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
1540
1541 /* let the bios control the backlight */
1542 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1543
1544 /* tell the bios not to handle mode switching */
1545 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1546
1547 /* clear the vbios dpms state */
1548 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1549
1550 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);
1551 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);
1552 }
1553
1554 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1555 {
1556 int i;
1557
1558 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1559 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i);
1560 }
1561
1562 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1563 {
1564 int i;
1565
1566 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1567 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
1568 }
1569
1570 /* Atom needs data in little endian format
1571 * so swap as appropriate when copying data to
1572 * or from atom. Note that atom operates on
1573 * dw units.
1574 */
1575 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1576 {
1577 #ifdef __BIG_ENDIAN
1578 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1579 u32 *dst32, *src32;
1580 int i;
1581
1582 memcpy(src_tmp, src, num_bytes);
1583 src32 = (u32 *)src_tmp;
1584 dst32 = (u32 *)dst_tmp;
1585 if (to_le) {
1586 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1587 dst32[i] = cpu_to_le32(src32[i]);
1588 memcpy(dst, dst_tmp, num_bytes);
1589 } else {
1590 u8 dws = num_bytes & ~3;
1591 for (i = 0; i < ((num_bytes + 3) / 4); i++)
1592 dst32[i] = le32_to_cpu(src32[i]);
1593 memcpy(dst, dst_tmp, dws);
1594 if (num_bytes % 4) {
1595 for (i = 0; i < (num_bytes % 4); i++)
1596 dst[dws+i] = dst_tmp[dws+i];
1597 }
1598 }
1599 #else
1600 memcpy(dst, src, num_bytes);
1601 #endif
1602 }
Linux kernel - Deliverables
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