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[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cs.c
1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27 #include <linux/pagemap.h>
28 #include <drm/drmP.h>
29 #include <drm/amdgpu_drm.h>
30 #include "amdgpu.h"
31 #include "amdgpu_trace.h"
32
33 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
34 u32 ip_instance, u32 ring,
35 struct amdgpu_ring **out_ring)
36 {
37 /* Right now all IPs have only one instance - multiple rings. */
38 if (ip_instance != 0) {
39 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
40 return -EINVAL;
41 }
42
43 switch (ip_type) {
44 default:
45 DRM_ERROR("unknown ip type: %d\n", ip_type);
46 return -EINVAL;
47 case AMDGPU_HW_IP_GFX:
48 if (ring < adev->gfx.num_gfx_rings) {
49 *out_ring = &adev->gfx.gfx_ring[ring];
50 } else {
51 DRM_ERROR("only %d gfx rings are supported now\n",
52 adev->gfx.num_gfx_rings);
53 return -EINVAL;
54 }
55 break;
56 case AMDGPU_HW_IP_COMPUTE:
57 if (ring < adev->gfx.num_compute_rings) {
58 *out_ring = &adev->gfx.compute_ring[ring];
59 } else {
60 DRM_ERROR("only %d compute rings are supported now\n",
61 adev->gfx.num_compute_rings);
62 return -EINVAL;
63 }
64 break;
65 case AMDGPU_HW_IP_DMA:
66 if (ring < adev->sdma.num_instances) {
67 *out_ring = &adev->sdma.instance[ring].ring;
68 } else {
69 DRM_ERROR("only %d SDMA rings are supported\n",
70 adev->sdma.num_instances);
71 return -EINVAL;
72 }
73 break;
74 case AMDGPU_HW_IP_UVD:
75 *out_ring = &adev->uvd.ring;
76 break;
77 case AMDGPU_HW_IP_VCE:
78 if (ring < 2){
79 *out_ring = &adev->vce.ring[ring];
80 } else {
81 DRM_ERROR("only two VCE rings are supported\n");
82 return -EINVAL;
83 }
84 break;
85 }
86 return 0;
87 }
88
89 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
90 struct drm_amdgpu_cs_chunk_fence *data,
91 uint32_t *offset)
92 {
93 struct drm_gem_object *gobj;
94
95 gobj = drm_gem_object_lookup(p->filp, data->handle);
96 if (gobj == NULL)
97 return -EINVAL;
98
99 p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
100 p->uf_entry.priority = 0;
101 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
102 p->uf_entry.tv.shared = true;
103 p->uf_entry.user_pages = NULL;
104 *offset = data->offset;
105
106 drm_gem_object_unreference_unlocked(gobj);
107
108 if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
109 amdgpu_bo_unref(&p->uf_entry.robj);
110 return -EINVAL;
111 }
112
113 return 0;
114 }
115
116 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
117 {
118 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
119 struct amdgpu_vm *vm = &fpriv->vm;
120 union drm_amdgpu_cs *cs = data;
121 uint64_t *chunk_array_user;
122 uint64_t *chunk_array;
123 unsigned size, num_ibs = 0;
124 uint32_t uf_offset = 0;
125 int i;
126 int ret;
127
128 if (cs->in.num_chunks == 0)
129 return 0;
130
131 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
132 if (!chunk_array)
133 return -ENOMEM;
134
135 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
136 if (!p->ctx) {
137 ret = -EINVAL;
138 goto free_chunk;
139 }
140
141 /* get chunks */
142 chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
143 if (copy_from_user(chunk_array, chunk_array_user,
144 sizeof(uint64_t)*cs->in.num_chunks)) {
145 ret = -EFAULT;
146 goto put_ctx;
147 }
148
149 p->nchunks = cs->in.num_chunks;
150 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
151 GFP_KERNEL);
152 if (!p->chunks) {
153 ret = -ENOMEM;
154 goto put_ctx;
155 }
156
157 for (i = 0; i < p->nchunks; i++) {
158 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
159 struct drm_amdgpu_cs_chunk user_chunk;
160 uint32_t __user *cdata;
161
162 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
163 if (copy_from_user(&user_chunk, chunk_ptr,
164 sizeof(struct drm_amdgpu_cs_chunk))) {
165 ret = -EFAULT;
166 i--;
167 goto free_partial_kdata;
168 }
169 p->chunks[i].chunk_id = user_chunk.chunk_id;
170 p->chunks[i].length_dw = user_chunk.length_dw;
171
172 size = p->chunks[i].length_dw;
173 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
174
175 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
176 if (p->chunks[i].kdata == NULL) {
177 ret = -ENOMEM;
178 i--;
179 goto free_partial_kdata;
180 }
181 size *= sizeof(uint32_t);
182 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
183 ret = -EFAULT;
184 goto free_partial_kdata;
185 }
186
187 switch (p->chunks[i].chunk_id) {
188 case AMDGPU_CHUNK_ID_IB:
189 ++num_ibs;
190 break;
191
192 case AMDGPU_CHUNK_ID_FENCE:
193 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
194 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
195 ret = -EINVAL;
196 goto free_partial_kdata;
197 }
198
199 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
200 &uf_offset);
201 if (ret)
202 goto free_partial_kdata;
203
204 break;
205
206 case AMDGPU_CHUNK_ID_DEPENDENCIES:
207 break;
208
209 default:
210 ret = -EINVAL;
211 goto free_partial_kdata;
212 }
213 }
214
215 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
216 if (ret)
217 goto free_all_kdata;
218
219 if (p->uf_entry.robj)
220 p->job->uf_addr = uf_offset;
221 kfree(chunk_array);
222 return 0;
223
224 free_all_kdata:
225 i = p->nchunks - 1;
226 free_partial_kdata:
227 for (; i >= 0; i--)
228 drm_free_large(p->chunks[i].kdata);
229 kfree(p->chunks);
230 put_ctx:
231 amdgpu_ctx_put(p->ctx);
232 free_chunk:
233 kfree(chunk_array);
234
235 return ret;
236 }
237
238 /* Returns how many bytes TTM can move per IB.
239 */
240 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
241 {
242 u64 real_vram_size = adev->mc.real_vram_size;
243 u64 vram_usage = atomic64_read(&adev->vram_usage);
244
245 /* This function is based on the current VRAM usage.
246 *
247 * - If all of VRAM is free, allow relocating the number of bytes that
248 * is equal to 1/4 of the size of VRAM for this IB.
249
250 * - If more than one half of VRAM is occupied, only allow relocating
251 * 1 MB of data for this IB.
252 *
253 * - From 0 to one half of used VRAM, the threshold decreases
254 * linearly.
255 * __________________
256 * 1/4 of -|\ |
257 * VRAM | \ |
258 * | \ |
259 * | \ |
260 * | \ |
261 * | \ |
262 * | \ |
263 * | \________|1 MB
264 * |----------------|
265 * VRAM 0 % 100 %
266 * used used
267 *
268 * Note: It's a threshold, not a limit. The threshold must be crossed
269 * for buffer relocations to stop, so any buffer of an arbitrary size
270 * can be moved as long as the threshold isn't crossed before
271 * the relocation takes place. We don't want to disable buffer
272 * relocations completely.
273 *
274 * The idea is that buffers should be placed in VRAM at creation time
275 * and TTM should only do a minimum number of relocations during
276 * command submission. In practice, you need to submit at least
277 * a dozen IBs to move all buffers to VRAM if they are in GTT.
278 *
279 * Also, things can get pretty crazy under memory pressure and actual
280 * VRAM usage can change a lot, so playing safe even at 50% does
281 * consistently increase performance.
282 */
283
284 u64 half_vram = real_vram_size >> 1;
285 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
286 u64 bytes_moved_threshold = half_free_vram >> 1;
287 return max(bytes_moved_threshold, 1024*1024ull);
288 }
289
290 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
291 struct list_head *validated)
292 {
293 struct amdgpu_bo_list_entry *lobj;
294 u64 initial_bytes_moved;
295 int r;
296
297 list_for_each_entry(lobj, validated, tv.head) {
298 struct amdgpu_bo *bo = lobj->robj;
299 bool binding_userptr = false;
300 struct mm_struct *usermm;
301 uint32_t domain;
302
303 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
304 if (usermm && usermm != current->mm)
305 return -EPERM;
306
307 /* Check if we have user pages and nobody bound the BO already */
308 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
309 size_t size = sizeof(struct page *);
310
311 size *= bo->tbo.ttm->num_pages;
312 memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
313 binding_userptr = true;
314 }
315
316 if (bo->pin_count)
317 continue;
318
319 /* Avoid moving this one if we have moved too many buffers
320 * for this IB already.
321 *
322 * Note that this allows moving at least one buffer of
323 * any size, because it doesn't take the current "bo"
324 * into account. We don't want to disallow buffer moves
325 * completely.
326 */
327 if (p->bytes_moved <= p->bytes_moved_threshold)
328 domain = bo->prefered_domains;
329 else
330 domain = bo->allowed_domains;
331
332 retry:
333 amdgpu_ttm_placement_from_domain(bo, domain);
334 initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
335 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
336 p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
337 initial_bytes_moved;
338
339 if (unlikely(r)) {
340 if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
341 domain = bo->allowed_domains;
342 goto retry;
343 }
344 return r;
345 }
346
347 if (binding_userptr) {
348 drm_free_large(lobj->user_pages);
349 lobj->user_pages = NULL;
350 }
351 }
352 return 0;
353 }
354
355 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
356 union drm_amdgpu_cs *cs)
357 {
358 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
359 struct amdgpu_bo_list_entry *e;
360 struct list_head duplicates;
361 bool need_mmap_lock = false;
362 unsigned i, tries = 10;
363 int r;
364
365 INIT_LIST_HEAD(&p->validated);
366
367 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
368 if (p->bo_list) {
369 need_mmap_lock = p->bo_list->first_userptr !=
370 p->bo_list->num_entries;
371 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
372 }
373
374 INIT_LIST_HEAD(&duplicates);
375 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
376
377 if (p->uf_entry.robj)
378 list_add(&p->uf_entry.tv.head, &p->validated);
379
380 if (need_mmap_lock)
381 down_read(&current->mm->mmap_sem);
382
383 while (1) {
384 struct list_head need_pages;
385 unsigned i;
386
387 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
388 &duplicates);
389 if (unlikely(r != 0))
390 goto error_free_pages;
391
392 /* Without a BO list we don't have userptr BOs */
393 if (!p->bo_list)
394 break;
395
396 INIT_LIST_HEAD(&need_pages);
397 for (i = p->bo_list->first_userptr;
398 i < p->bo_list->num_entries; ++i) {
399
400 e = &p->bo_list->array[i];
401
402 if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
403 &e->user_invalidated) && e->user_pages) {
404
405 /* We acquired a page array, but somebody
406 * invalidated it. Free it an try again
407 */
408 release_pages(e->user_pages,
409 e->robj->tbo.ttm->num_pages,
410 false);
411 drm_free_large(e->user_pages);
412 e->user_pages = NULL;
413 }
414
415 if (e->robj->tbo.ttm->state != tt_bound &&
416 !e->user_pages) {
417 list_del(&e->tv.head);
418 list_add(&e->tv.head, &need_pages);
419
420 amdgpu_bo_unreserve(e->robj);
421 }
422 }
423
424 if (list_empty(&need_pages))
425 break;
426
427 /* Unreserve everything again. */
428 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
429
430 /* We tried to often, just abort */
431 if (!--tries) {
432 r = -EDEADLK;
433 goto error_free_pages;
434 }
435
436 /* Fill the page arrays for all useptrs. */
437 list_for_each_entry(e, &need_pages, tv.head) {
438 struct ttm_tt *ttm = e->robj->tbo.ttm;
439
440 e->user_pages = drm_calloc_large(ttm->num_pages,
441 sizeof(struct page*));
442 if (!e->user_pages) {
443 r = -ENOMEM;
444 goto error_free_pages;
445 }
446
447 r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
448 if (r) {
449 drm_free_large(e->user_pages);
450 e->user_pages = NULL;
451 goto error_free_pages;
452 }
453 }
454
455 /* And try again. */
456 list_splice(&need_pages, &p->validated);
457 }
458
459 amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates);
460
461 p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
462 p->bytes_moved = 0;
463
464 r = amdgpu_cs_list_validate(p, &duplicates);
465 if (r)
466 goto error_validate;
467
468 r = amdgpu_cs_list_validate(p, &p->validated);
469 if (r)
470 goto error_validate;
471
472 fpriv->vm.last_eviction_counter =
473 atomic64_read(&p->adev->num_evictions);
474
475 if (p->bo_list) {
476 struct amdgpu_bo *gds = p->bo_list->gds_obj;
477 struct amdgpu_bo *gws = p->bo_list->gws_obj;
478 struct amdgpu_bo *oa = p->bo_list->oa_obj;
479 struct amdgpu_vm *vm = &fpriv->vm;
480 unsigned i;
481
482 for (i = 0; i < p->bo_list->num_entries; i++) {
483 struct amdgpu_bo *bo = p->bo_list->array[i].robj;
484
485 p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
486 }
487
488 if (gds) {
489 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
490 p->job->gds_size = amdgpu_bo_size(gds);
491 }
492 if (gws) {
493 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
494 p->job->gws_size = amdgpu_bo_size(gws);
495 }
496 if (oa) {
497 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
498 p->job->oa_size = amdgpu_bo_size(oa);
499 }
500 }
501
502 if (p->uf_entry.robj)
503 p->job->uf_addr += amdgpu_bo_gpu_offset(p->uf_entry.robj);
504
505 error_validate:
506 if (r) {
507 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
508 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
509 }
510
511 error_free_pages:
512
513 if (need_mmap_lock)
514 up_read(&current->mm->mmap_sem);
515
516 if (p->bo_list) {
517 for (i = p->bo_list->first_userptr;
518 i < p->bo_list->num_entries; ++i) {
519 e = &p->bo_list->array[i];
520
521 if (!e->user_pages)
522 continue;
523
524 release_pages(e->user_pages,
525 e->robj->tbo.ttm->num_pages,
526 false);
527 drm_free_large(e->user_pages);
528 }
529 }
530
531 return r;
532 }
533
534 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
535 {
536 struct amdgpu_bo_list_entry *e;
537 int r;
538
539 list_for_each_entry(e, &p->validated, tv.head) {
540 struct reservation_object *resv = e->robj->tbo.resv;
541 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
542
543 if (r)
544 return r;
545 }
546 return 0;
547 }
548
549 /**
550 * cs_parser_fini() - clean parser states
551 * @parser: parser structure holding parsing context.
552 * @error: error number
553 *
554 * If error is set than unvalidate buffer, otherwise just free memory
555 * used by parsing context.
556 **/
557 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
558 {
559 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
560 unsigned i;
561
562 if (!error) {
563 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
564
565 ttm_eu_fence_buffer_objects(&parser->ticket,
566 &parser->validated,
567 parser->fence);
568 } else if (backoff) {
569 ttm_eu_backoff_reservation(&parser->ticket,
570 &parser->validated);
571 }
572 fence_put(parser->fence);
573
574 if (parser->ctx)
575 amdgpu_ctx_put(parser->ctx);
576 if (parser->bo_list)
577 amdgpu_bo_list_put(parser->bo_list);
578
579 for (i = 0; i < parser->nchunks; i++)
580 drm_free_large(parser->chunks[i].kdata);
581 kfree(parser->chunks);
582 if (parser->job)
583 amdgpu_job_free(parser->job);
584 amdgpu_bo_unref(&parser->uf_entry.robj);
585 }
586
587 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
588 struct amdgpu_vm *vm)
589 {
590 struct amdgpu_device *adev = p->adev;
591 struct amdgpu_bo_va *bo_va;
592 struct amdgpu_bo *bo;
593 int i, r;
594
595 r = amdgpu_vm_update_page_directory(adev, vm);
596 if (r)
597 return r;
598
599 r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
600 if (r)
601 return r;
602
603 r = amdgpu_vm_clear_freed(adev, vm);
604 if (r)
605 return r;
606
607 if (p->bo_list) {
608 for (i = 0; i < p->bo_list->num_entries; i++) {
609 struct fence *f;
610
611 /* ignore duplicates */
612 bo = p->bo_list->array[i].robj;
613 if (!bo)
614 continue;
615
616 bo_va = p->bo_list->array[i].bo_va;
617 if (bo_va == NULL)
618 continue;
619
620 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
621 if (r)
622 return r;
623
624 f = bo_va->last_pt_update;
625 r = amdgpu_sync_fence(adev, &p->job->sync, f);
626 if (r)
627 return r;
628 }
629
630 }
631
632 r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
633
634 if (amdgpu_vm_debug && p->bo_list) {
635 /* Invalidate all BOs to test for userspace bugs */
636 for (i = 0; i < p->bo_list->num_entries; i++) {
637 /* ignore duplicates */
638 bo = p->bo_list->array[i].robj;
639 if (!bo)
640 continue;
641
642 amdgpu_vm_bo_invalidate(adev, bo);
643 }
644 }
645
646 return r;
647 }
648
649 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
650 struct amdgpu_cs_parser *p)
651 {
652 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
653 struct amdgpu_vm *vm = &fpriv->vm;
654 struct amdgpu_ring *ring = p->job->ring;
655 int i, r;
656
657 /* Only for UVD/VCE VM emulation */
658 if (ring->funcs->parse_cs) {
659 p->job->vm = NULL;
660 for (i = 0; i < p->job->num_ibs; i++) {
661 r = amdgpu_ring_parse_cs(ring, p, i);
662 if (r)
663 return r;
664 }
665 } else {
666 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
667
668 r = amdgpu_bo_vm_update_pte(p, vm);
669 if (r)
670 return r;
671 }
672
673 return amdgpu_cs_sync_rings(p);
674 }
675
676 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
677 {
678 if (r == -EDEADLK) {
679 r = amdgpu_gpu_reset(adev);
680 if (!r)
681 r = -EAGAIN;
682 }
683 return r;
684 }
685
686 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
687 struct amdgpu_cs_parser *parser)
688 {
689 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
690 struct amdgpu_vm *vm = &fpriv->vm;
691 int i, j;
692 int r;
693
694 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
695 struct amdgpu_cs_chunk *chunk;
696 struct amdgpu_ib *ib;
697 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
698 struct amdgpu_ring *ring;
699
700 chunk = &parser->chunks[i];
701 ib = &parser->job->ibs[j];
702 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
703
704 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
705 continue;
706
707 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
708 chunk_ib->ip_instance, chunk_ib->ring,
709 &ring);
710 if (r)
711 return r;
712
713 if (parser->job->ring && parser->job->ring != ring)
714 return -EINVAL;
715
716 parser->job->ring = ring;
717
718 if (ring->funcs->parse_cs) {
719 struct amdgpu_bo_va_mapping *m;
720 struct amdgpu_bo *aobj = NULL;
721 uint64_t offset;
722 uint8_t *kptr;
723
724 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
725 &aobj);
726 if (!aobj) {
727 DRM_ERROR("IB va_start is invalid\n");
728 return -EINVAL;
729 }
730
731 if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
732 (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
733 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
734 return -EINVAL;
735 }
736
737 /* the IB should be reserved at this point */
738 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
739 if (r) {
740 return r;
741 }
742
743 offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
744 kptr += chunk_ib->va_start - offset;
745
746 r = amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
747 if (r) {
748 DRM_ERROR("Failed to get ib !\n");
749 return r;
750 }
751
752 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
753 amdgpu_bo_kunmap(aobj);
754 } else {
755 r = amdgpu_ib_get(adev, vm, 0, ib);
756 if (r) {
757 DRM_ERROR("Failed to get ib !\n");
758 return r;
759 }
760
761 ib->gpu_addr = chunk_ib->va_start;
762 }
763
764 ib->length_dw = chunk_ib->ib_bytes / 4;
765 ib->flags = chunk_ib->flags;
766 j++;
767 }
768
769 /* UVD & VCE fw doesn't support user fences */
770 if (parser->job->uf_addr && (
771 parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
772 parser->job->ring->type == AMDGPU_RING_TYPE_VCE))
773 return -EINVAL;
774
775 return 0;
776 }
777
778 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
779 struct amdgpu_cs_parser *p)
780 {
781 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
782 int i, j, r;
783
784 for (i = 0; i < p->nchunks; ++i) {
785 struct drm_amdgpu_cs_chunk_dep *deps;
786 struct amdgpu_cs_chunk *chunk;
787 unsigned num_deps;
788
789 chunk = &p->chunks[i];
790
791 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
792 continue;
793
794 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
795 num_deps = chunk->length_dw * 4 /
796 sizeof(struct drm_amdgpu_cs_chunk_dep);
797
798 for (j = 0; j < num_deps; ++j) {
799 struct amdgpu_ring *ring;
800 struct amdgpu_ctx *ctx;
801 struct fence *fence;
802
803 r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
804 deps[j].ip_instance,
805 deps[j].ring, &ring);
806 if (r)
807 return r;
808
809 ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
810 if (ctx == NULL)
811 return -EINVAL;
812
813 fence = amdgpu_ctx_get_fence(ctx, ring,
814 deps[j].handle);
815 if (IS_ERR(fence)) {
816 r = PTR_ERR(fence);
817 amdgpu_ctx_put(ctx);
818 return r;
819
820 } else if (fence) {
821 r = amdgpu_sync_fence(adev, &p->job->sync,
822 fence);
823 fence_put(fence);
824 amdgpu_ctx_put(ctx);
825 if (r)
826 return r;
827 }
828 }
829 }
830
831 return 0;
832 }
833
834 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
835 union drm_amdgpu_cs *cs)
836 {
837 struct amdgpu_ring *ring = p->job->ring;
838 struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
839 struct amdgpu_job *job;
840 int r;
841
842 job = p->job;
843 p->job = NULL;
844
845 r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
846 if (r) {
847 amdgpu_job_free(job);
848 return r;
849 }
850
851 job->owner = p->filp;
852 job->ctx = entity->fence_context;
853 p->fence = fence_get(&job->base.s_fence->finished);
854 cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
855 job->uf_sequence = cs->out.handle;
856 amdgpu_job_free_resources(job);
857
858 trace_amdgpu_cs_ioctl(job);
859 amd_sched_entity_push_job(&job->base);
860
861 return 0;
862 }
863
864 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
865 {
866 struct amdgpu_device *adev = dev->dev_private;
867 union drm_amdgpu_cs *cs = data;
868 struct amdgpu_cs_parser parser = {};
869 bool reserved_buffers = false;
870 int i, r;
871
872 if (!adev->accel_working)
873 return -EBUSY;
874
875 parser.adev = adev;
876 parser.filp = filp;
877
878 r = amdgpu_cs_parser_init(&parser, data);
879 if (r) {
880 DRM_ERROR("Failed to initialize parser !\n");
881 amdgpu_cs_parser_fini(&parser, r, false);
882 r = amdgpu_cs_handle_lockup(adev, r);
883 return r;
884 }
885 r = amdgpu_cs_parser_bos(&parser, data);
886 if (r == -ENOMEM)
887 DRM_ERROR("Not enough memory for command submission!\n");
888 else if (r && r != -ERESTARTSYS)
889 DRM_ERROR("Failed to process the buffer list %d!\n", r);
890 else if (!r) {
891 reserved_buffers = true;
892 r = amdgpu_cs_ib_fill(adev, &parser);
893 }
894
895 if (!r) {
896 r = amdgpu_cs_dependencies(adev, &parser);
897 if (r)
898 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
899 }
900
901 if (r)
902 goto out;
903
904 for (i = 0; i < parser.job->num_ibs; i++)
905 trace_amdgpu_cs(&parser, i);
906
907 r = amdgpu_cs_ib_vm_chunk(adev, &parser);
908 if (r)
909 goto out;
910
911 r = amdgpu_cs_submit(&parser, cs);
912
913 out:
914 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
915 r = amdgpu_cs_handle_lockup(adev, r);
916 return r;
917 }
918
919 /**
920 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
921 *
922 * @dev: drm device
923 * @data: data from userspace
924 * @filp: file private
925 *
926 * Wait for the command submission identified by handle to finish.
927 */
928 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
929 struct drm_file *filp)
930 {
931 union drm_amdgpu_wait_cs *wait = data;
932 struct amdgpu_device *adev = dev->dev_private;
933 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
934 struct amdgpu_ring *ring = NULL;
935 struct amdgpu_ctx *ctx;
936 struct fence *fence;
937 long r;
938
939 r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
940 wait->in.ring, &ring);
941 if (r)
942 return r;
943
944 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
945 if (ctx == NULL)
946 return -EINVAL;
947
948 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
949 if (IS_ERR(fence))
950 r = PTR_ERR(fence);
951 else if (fence) {
952 r = fence_wait_timeout(fence, true, timeout);
953 fence_put(fence);
954 } else
955 r = 1;
956
957 amdgpu_ctx_put(ctx);
958 if (r < 0)
959 return r;
960
961 memset(wait, 0, sizeof(*wait));
962 wait->out.status = (r == 0);
963
964 return 0;
965 }
966
967 /**
968 * amdgpu_cs_find_bo_va - find bo_va for VM address
969 *
970 * @parser: command submission parser context
971 * @addr: VM address
972 * @bo: resulting BO of the mapping found
973 *
974 * Search the buffer objects in the command submission context for a certain
975 * virtual memory address. Returns allocation structure when found, NULL
976 * otherwise.
977 */
978 struct amdgpu_bo_va_mapping *
979 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
980 uint64_t addr, struct amdgpu_bo **bo)
981 {
982 struct amdgpu_bo_va_mapping *mapping;
983 unsigned i;
984
985 if (!parser->bo_list)
986 return NULL;
987
988 addr /= AMDGPU_GPU_PAGE_SIZE;
989
990 for (i = 0; i < parser->bo_list->num_entries; i++) {
991 struct amdgpu_bo_list_entry *lobj;
992
993 lobj = &parser->bo_list->array[i];
994 if (!lobj->bo_va)
995 continue;
996
997 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
998 if (mapping->it.start > addr ||
999 addr > mapping->it.last)
1000 continue;
1001
1002 *bo = lobj->bo_va->bo;
1003 return mapping;
1004 }
1005
1006 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1007 if (mapping->it.start > addr ||
1008 addr > mapping->it.last)
1009 continue;
1010
1011 *bo = lobj->bo_va->bo;
1012 return mapping;
1013 }
1014 }
1015
1016 return NULL;
1017 }
Linux kernel - Deliverables
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