5 * \author Gareth Hughes <gareth@valinux.com>
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_gem.h>
35 #include "amdgpu_drv.h"
37 #include <drm/drm_pciids.h>
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include "drm_crtc_helper.h"
45 #include "amdgpu_irq.h"
47 #include "amdgpu_amdkfd.h"
51 * - 3.0.0 - initial driver
52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
55 * - 3.3.0 - Add VM support for UVD on supported hardware.
57 #define KMS_DRIVER_MAJOR 3
58 #define KMS_DRIVER_MINOR 3
59 #define KMS_DRIVER_PATCHLEVEL 0
61 int amdgpu_vram_limit
= 0;
62 int amdgpu_gart_size
= -1; /* auto */
63 int amdgpu_benchmarking
= 0;
64 int amdgpu_testing
= 0;
65 int amdgpu_audio
= -1;
66 int amdgpu_disp_priority
= 0;
67 int amdgpu_hw_i2c
= 0;
68 int amdgpu_pcie_gen2
= -1;
70 int amdgpu_lockup_timeout
= 0;
72 int amdgpu_smc_load_fw
= 1;
74 int amdgpu_runtime_pm
= -1;
75 unsigned amdgpu_ip_block_mask
= 0xffffffff;
77 int amdgpu_deep_color
= 0;
78 int amdgpu_vm_size
= 64;
79 int amdgpu_vm_block_size
= -1;
80 int amdgpu_vm_fault_stop
= 0;
81 int amdgpu_vm_debug
= 0;
82 int amdgpu_exp_hw_support
= 0;
83 int amdgpu_sched_jobs
= 32;
84 int amdgpu_sched_hw_submission
= 2;
85 int amdgpu_powerplay
= -1;
86 int amdgpu_powercontainment
= 1;
87 unsigned amdgpu_pcie_gen_cap
= 0;
88 unsigned amdgpu_pcie_lane_cap
= 0;
89 unsigned amdgpu_cg_mask
= 0xffffffff;
90 unsigned amdgpu_pg_mask
= 0xffffffff;
91 char *amdgpu_disable_cu
= NULL
;
93 MODULE_PARM_DESC(vramlimit
, "Restrict VRAM for testing, in megabytes");
94 module_param_named(vramlimit
, amdgpu_vram_limit
, int, 0600);
96 MODULE_PARM_DESC(gartsize
, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
97 module_param_named(gartsize
, amdgpu_gart_size
, int, 0600);
99 MODULE_PARM_DESC(benchmark
, "Run benchmark");
100 module_param_named(benchmark
, amdgpu_benchmarking
, int, 0444);
102 MODULE_PARM_DESC(test
, "Run tests");
103 module_param_named(test
, amdgpu_testing
, int, 0444);
105 MODULE_PARM_DESC(audio
, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
106 module_param_named(audio
, amdgpu_audio
, int, 0444);
108 MODULE_PARM_DESC(disp_priority
, "Display Priority (0 = auto, 1 = normal, 2 = high)");
109 module_param_named(disp_priority
, amdgpu_disp_priority
, int, 0444);
111 MODULE_PARM_DESC(hw_i2c
, "hw i2c engine enable (0 = disable)");
112 module_param_named(hw_i2c
, amdgpu_hw_i2c
, int, 0444);
114 MODULE_PARM_DESC(pcie_gen2
, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
115 module_param_named(pcie_gen2
, amdgpu_pcie_gen2
, int, 0444);
117 MODULE_PARM_DESC(msi
, "MSI support (1 = enable, 0 = disable, -1 = auto)");
118 module_param_named(msi
, amdgpu_msi
, int, 0444);
120 MODULE_PARM_DESC(lockup_timeout
, "GPU lockup timeout in ms (default 0 = disable)");
121 module_param_named(lockup_timeout
, amdgpu_lockup_timeout
, int, 0444);
123 MODULE_PARM_DESC(dpm
, "DPM support (1 = enable, 0 = disable, -1 = auto)");
124 module_param_named(dpm
, amdgpu_dpm
, int, 0444);
126 MODULE_PARM_DESC(smc_load_fw
, "SMC firmware loading(1 = enable, 0 = disable)");
127 module_param_named(smc_load_fw
, amdgpu_smc_load_fw
, int, 0444);
129 MODULE_PARM_DESC(aspm
, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
130 module_param_named(aspm
, amdgpu_aspm
, int, 0444);
132 MODULE_PARM_DESC(runpm
, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
133 module_param_named(runpm
, amdgpu_runtime_pm
, int, 0444);
135 MODULE_PARM_DESC(ip_block_mask
, "IP Block Mask (all blocks enabled (default))");
136 module_param_named(ip_block_mask
, amdgpu_ip_block_mask
, uint
, 0444);
138 MODULE_PARM_DESC(bapm
, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
139 module_param_named(bapm
, amdgpu_bapm
, int, 0444);
141 MODULE_PARM_DESC(deep_color
, "Deep Color support (1 = enable, 0 = disable (default))");
142 module_param_named(deep_color
, amdgpu_deep_color
, int, 0444);
144 MODULE_PARM_DESC(vm_size
, "VM address space size in gigabytes (default 64GB)");
145 module_param_named(vm_size
, amdgpu_vm_size
, int, 0444);
147 MODULE_PARM_DESC(vm_block_size
, "VM page table size in bits (default depending on vm_size)");
148 module_param_named(vm_block_size
, amdgpu_vm_block_size
, int, 0444);
150 MODULE_PARM_DESC(vm_fault_stop
, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
151 module_param_named(vm_fault_stop
, amdgpu_vm_fault_stop
, int, 0444);
153 MODULE_PARM_DESC(vm_debug
, "Debug VM handling (0 = disabled (default), 1 = enabled)");
154 module_param_named(vm_debug
, amdgpu_vm_debug
, int, 0644);
156 MODULE_PARM_DESC(exp_hw_support
, "experimental hw support (1 = enable, 0 = disable (default))");
157 module_param_named(exp_hw_support
, amdgpu_exp_hw_support
, int, 0444);
159 MODULE_PARM_DESC(sched_jobs
, "the max number of jobs supported in the sw queue (default 32)");
160 module_param_named(sched_jobs
, amdgpu_sched_jobs
, int, 0444);
162 MODULE_PARM_DESC(sched_hw_submission
, "the max number of HW submissions (default 2)");
163 module_param_named(sched_hw_submission
, amdgpu_sched_hw_submission
, int, 0444);
165 #ifdef CONFIG_DRM_AMD_POWERPLAY
166 MODULE_PARM_DESC(powerplay
, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
167 module_param_named(powerplay
, amdgpu_powerplay
, int, 0444);
169 MODULE_PARM_DESC(powercontainment
, "Power Containment (1 = enable (default), 0 = disable)");
170 module_param_named(powercontainment
, amdgpu_powercontainment
, int, 0444);
173 MODULE_PARM_DESC(pcie_gen_cap
, "PCIE Gen Caps (0: autodetect (default))");
174 module_param_named(pcie_gen_cap
, amdgpu_pcie_gen_cap
, uint
, 0444);
176 MODULE_PARM_DESC(pcie_lane_cap
, "PCIE Lane Caps (0: autodetect (default))");
177 module_param_named(pcie_lane_cap
, amdgpu_pcie_lane_cap
, uint
, 0444);
179 MODULE_PARM_DESC(cg_mask
, "Clockgating flags mask (0 = disable clock gating)");
180 module_param_named(cg_mask
, amdgpu_cg_mask
, uint
, 0444);
182 MODULE_PARM_DESC(pg_mask
, "Powergating flags mask (0 = disable power gating)");
183 module_param_named(pg_mask
, amdgpu_pg_mask
, uint
, 0444);
185 MODULE_PARM_DESC(disable_cu
, "Disable CUs (se.sh.cu,...)");
186 module_param_named(disable_cu
, amdgpu_disable_cu
, charp
, 0444);
188 static const struct pci_device_id pciidlist
[] = {
189 #ifdef CONFIG_DRM_AMDGPU_CIK
191 {0x1002, 0x1304, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
192 {0x1002, 0x1305, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
193 {0x1002, 0x1306, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
194 {0x1002, 0x1307, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
195 {0x1002, 0x1309, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
196 {0x1002, 0x130A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
197 {0x1002, 0x130B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
198 {0x1002, 0x130C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
199 {0x1002, 0x130D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
200 {0x1002, 0x130E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
201 {0x1002, 0x130F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
202 {0x1002, 0x1310, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
203 {0x1002, 0x1311, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
204 {0x1002, 0x1312, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
205 {0x1002, 0x1313, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
206 {0x1002, 0x1315, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
207 {0x1002, 0x1316, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
208 {0x1002, 0x1317, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
209 {0x1002, 0x1318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
210 {0x1002, 0x131B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
211 {0x1002, 0x131C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
212 {0x1002, 0x131D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KAVERI
|AMD_IS_APU
},
214 {0x1002, 0x6640, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
215 {0x1002, 0x6641, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
216 {0x1002, 0x6646, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
217 {0x1002, 0x6647, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
|AMD_IS_MOBILITY
},
218 {0x1002, 0x6649, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
219 {0x1002, 0x6650, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
220 {0x1002, 0x6651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
221 {0x1002, 0x6658, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
222 {0x1002, 0x665c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
223 {0x1002, 0x665d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
224 {0x1002, 0x665f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_BONAIRE
},
226 {0x1002, 0x67A0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
227 {0x1002, 0x67A1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
228 {0x1002, 0x67A2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
229 {0x1002, 0x67A8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
230 {0x1002, 0x67A9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
231 {0x1002, 0x67AA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
232 {0x1002, 0x67B0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
233 {0x1002, 0x67B1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
234 {0x1002, 0x67B8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
235 {0x1002, 0x67B9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
236 {0x1002, 0x67BA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
237 {0x1002, 0x67BE, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_HAWAII
},
239 {0x1002, 0x9830, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
240 {0x1002, 0x9831, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
241 {0x1002, 0x9832, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
242 {0x1002, 0x9833, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
243 {0x1002, 0x9834, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
244 {0x1002, 0x9835, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
245 {0x1002, 0x9836, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
246 {0x1002, 0x9837, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
247 {0x1002, 0x9838, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
248 {0x1002, 0x9839, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
249 {0x1002, 0x983a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
250 {0x1002, 0x983b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_MOBILITY
|AMD_IS_APU
},
251 {0x1002, 0x983c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
252 {0x1002, 0x983d, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
253 {0x1002, 0x983e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
254 {0x1002, 0x983f, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_KABINI
|AMD_IS_APU
},
256 {0x1002, 0x9850, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
257 {0x1002, 0x9851, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
258 {0x1002, 0x9852, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
259 {0x1002, 0x9853, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
260 {0x1002, 0x9854, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
261 {0x1002, 0x9855, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
262 {0x1002, 0x9856, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
263 {0x1002, 0x9857, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
264 {0x1002, 0x9858, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
265 {0x1002, 0x9859, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
266 {0x1002, 0x985A, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
267 {0x1002, 0x985B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
268 {0x1002, 0x985C, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
269 {0x1002, 0x985D, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
270 {0x1002, 0x985E, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
271 {0x1002, 0x985F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_MULLINS
|AMD_IS_MOBILITY
|AMD_IS_APU
},
274 {0x1002, 0x6900, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
275 {0x1002, 0x6901, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
276 {0x1002, 0x6902, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
277 {0x1002, 0x6903, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
278 {0x1002, 0x6907, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TOPAZ
},
280 {0x1002, 0x6920, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
281 {0x1002, 0x6921, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
282 {0x1002, 0x6928, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
283 {0x1002, 0x6929, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
284 {0x1002, 0x692B, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
285 {0x1002, 0x692F, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
286 {0x1002, 0x6930, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
287 {0x1002, 0x6938, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
288 {0x1002, 0x6939, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_TONGA
},
290 {0x1002, 0x7300, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_FIJI
},
292 {0x1002, 0x9870, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
293 {0x1002, 0x9874, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
294 {0x1002, 0x9875, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
295 {0x1002, 0x9876, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
296 {0x1002, 0x9877, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_CARRIZO
|AMD_IS_APU
},
298 {0x1002, 0x98E4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_STONEY
|AMD_IS_APU
},
300 {0x1002, 0x67E0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
301 {0x1002, 0x67E3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
302 {0x1002, 0x67E8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
303 {0x1002, 0x67EB, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
304 {0x1002, 0x67EF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
305 {0x1002, 0x67FF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
306 {0x1002, 0x67E1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
307 {0x1002, 0x67E7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
308 {0x1002, 0x67E9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS11
},
310 {0x1002, 0x67C0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
311 {0x1002, 0x67C1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
312 {0x1002, 0x67C2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
313 {0x1002, 0x67C4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
314 {0x1002, 0x67C7, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
315 {0x1002, 0x67DF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
316 {0x1002, 0x67C8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
317 {0x1002, 0x67C9, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
318 {0x1002, 0x67CA, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
319 {0x1002, 0x67CC, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
320 {0x1002, 0x67CF, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, CHIP_POLARIS10
},
325 MODULE_DEVICE_TABLE(pci
, pciidlist
);
327 static struct drm_driver kms_driver
;
329 static int amdgpu_kick_out_firmware_fb(struct pci_dev
*pdev
)
331 struct apertures_struct
*ap
;
332 bool primary
= false;
334 ap
= alloc_apertures(1);
338 ap
->ranges
[0].base
= pci_resource_start(pdev
, 0);
339 ap
->ranges
[0].size
= pci_resource_len(pdev
, 0);
342 primary
= pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
344 remove_conflicting_framebuffers(ap
, "amdgpudrmfb", primary
);
350 static int amdgpu_pci_probe(struct pci_dev
*pdev
,
351 const struct pci_device_id
*ent
)
353 unsigned long flags
= ent
->driver_data
;
356 if ((flags
& AMD_EXP_HW_SUPPORT
) && !amdgpu_exp_hw_support
) {
357 DRM_INFO("This hardware requires experimental hardware support.\n"
358 "See modparam exp_hw_support\n");
363 * Initialize amdkfd before starting radeon. If it was not loaded yet,
364 * defer radeon probing
366 ret
= amdgpu_amdkfd_init();
367 if (ret
== -EPROBE_DEFER
)
370 /* Get rid of things like offb */
371 ret
= amdgpu_kick_out_firmware_fb(pdev
);
375 return drm_get_pci_dev(pdev
, ent
, &kms_driver
);
379 amdgpu_pci_remove(struct pci_dev
*pdev
)
381 struct drm_device
*dev
= pci_get_drvdata(pdev
);
386 static int amdgpu_pmops_suspend(struct device
*dev
)
388 struct pci_dev
*pdev
= to_pci_dev(dev
);
389 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
390 return amdgpu_suspend_kms(drm_dev
, true, true);
393 static int amdgpu_pmops_resume(struct device
*dev
)
395 struct pci_dev
*pdev
= to_pci_dev(dev
);
396 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
397 return amdgpu_resume_kms(drm_dev
, true, true);
400 static int amdgpu_pmops_freeze(struct device
*dev
)
402 struct pci_dev
*pdev
= to_pci_dev(dev
);
403 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
404 return amdgpu_suspend_kms(drm_dev
, false, true);
407 static int amdgpu_pmops_thaw(struct device
*dev
)
409 struct pci_dev
*pdev
= to_pci_dev(dev
);
410 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
411 return amdgpu_resume_kms(drm_dev
, false, true);
414 static int amdgpu_pmops_runtime_suspend(struct device
*dev
)
416 struct pci_dev
*pdev
= to_pci_dev(dev
);
417 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
420 if (!amdgpu_device_is_px(drm_dev
)) {
421 pm_runtime_forbid(dev
);
425 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
426 drm_kms_helper_poll_disable(drm_dev
);
427 vga_switcheroo_set_dynamic_switch(pdev
, VGA_SWITCHEROO_OFF
);
429 ret
= amdgpu_suspend_kms(drm_dev
, false, false);
430 pci_save_state(pdev
);
431 pci_disable_device(pdev
);
432 pci_ignore_hotplug(pdev
);
433 if (amdgpu_is_atpx_hybrid())
434 pci_set_power_state(pdev
, PCI_D3cold
);
435 else if (!amdgpu_has_atpx_dgpu_power_cntl())
436 pci_set_power_state(pdev
, PCI_D3hot
);
437 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_DYNAMIC_OFF
;
442 static int amdgpu_pmops_runtime_resume(struct device
*dev
)
444 struct pci_dev
*pdev
= to_pci_dev(dev
);
445 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
448 if (!amdgpu_device_is_px(drm_dev
))
451 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
453 if (amdgpu_is_atpx_hybrid() ||
454 !amdgpu_has_atpx_dgpu_power_cntl())
455 pci_set_power_state(pdev
, PCI_D0
);
456 pci_restore_state(pdev
);
457 ret
= pci_enable_device(pdev
);
460 pci_set_master(pdev
);
462 ret
= amdgpu_resume_kms(drm_dev
, false, false);
463 drm_kms_helper_poll_enable(drm_dev
);
464 vga_switcheroo_set_dynamic_switch(pdev
, VGA_SWITCHEROO_ON
);
465 drm_dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
469 static int amdgpu_pmops_runtime_idle(struct device
*dev
)
471 struct pci_dev
*pdev
= to_pci_dev(dev
);
472 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
473 struct drm_crtc
*crtc
;
475 if (!amdgpu_device_is_px(drm_dev
)) {
476 pm_runtime_forbid(dev
);
480 list_for_each_entry(crtc
, &drm_dev
->mode_config
.crtc_list
, head
) {
482 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
487 pm_runtime_mark_last_busy(dev
);
488 pm_runtime_autosuspend(dev
);
489 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
493 long amdgpu_drm_ioctl(struct file
*filp
,
494 unsigned int cmd
, unsigned long arg
)
496 struct drm_file
*file_priv
= filp
->private_data
;
497 struct drm_device
*dev
;
499 dev
= file_priv
->minor
->dev
;
500 ret
= pm_runtime_get_sync(dev
->dev
);
504 ret
= drm_ioctl(filp
, cmd
, arg
);
506 pm_runtime_mark_last_busy(dev
->dev
);
507 pm_runtime_put_autosuspend(dev
->dev
);
511 static const struct dev_pm_ops amdgpu_pm_ops
= {
512 .suspend
= amdgpu_pmops_suspend
,
513 .resume
= amdgpu_pmops_resume
,
514 .freeze
= amdgpu_pmops_freeze
,
515 .thaw
= amdgpu_pmops_thaw
,
516 .poweroff
= amdgpu_pmops_freeze
,
517 .restore
= amdgpu_pmops_resume
,
518 .runtime_suspend
= amdgpu_pmops_runtime_suspend
,
519 .runtime_resume
= amdgpu_pmops_runtime_resume
,
520 .runtime_idle
= amdgpu_pmops_runtime_idle
,
523 static const struct file_operations amdgpu_driver_kms_fops
= {
524 .owner
= THIS_MODULE
,
526 .release
= drm_release
,
527 .unlocked_ioctl
= amdgpu_drm_ioctl
,
532 .compat_ioctl
= amdgpu_kms_compat_ioctl
,
536 static struct drm_driver kms_driver
= {
539 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
|
540 DRIVER_PRIME
| DRIVER_RENDER
| DRIVER_MODESET
,
542 .load
= amdgpu_driver_load_kms
,
543 .open
= amdgpu_driver_open_kms
,
544 .preclose
= amdgpu_driver_preclose_kms
,
545 .postclose
= amdgpu_driver_postclose_kms
,
546 .lastclose
= amdgpu_driver_lastclose_kms
,
547 .set_busid
= drm_pci_set_busid
,
548 .unload
= amdgpu_driver_unload_kms
,
549 .get_vblank_counter
= amdgpu_get_vblank_counter_kms
,
550 .enable_vblank
= amdgpu_enable_vblank_kms
,
551 .disable_vblank
= amdgpu_disable_vblank_kms
,
552 .get_vblank_timestamp
= amdgpu_get_vblank_timestamp_kms
,
553 .get_scanout_position
= amdgpu_get_crtc_scanoutpos
,
554 #if defined(CONFIG_DEBUG_FS)
555 .debugfs_init
= amdgpu_debugfs_init
,
556 .debugfs_cleanup
= amdgpu_debugfs_cleanup
,
558 .irq_preinstall
= amdgpu_irq_preinstall
,
559 .irq_postinstall
= amdgpu_irq_postinstall
,
560 .irq_uninstall
= amdgpu_irq_uninstall
,
561 .irq_handler
= amdgpu_irq_handler
,
562 .ioctls
= amdgpu_ioctls_kms
,
563 .gem_free_object_unlocked
= amdgpu_gem_object_free
,
564 .gem_open_object
= amdgpu_gem_object_open
,
565 .gem_close_object
= amdgpu_gem_object_close
,
566 .dumb_create
= amdgpu_mode_dumb_create
,
567 .dumb_map_offset
= amdgpu_mode_dumb_mmap
,
568 .dumb_destroy
= drm_gem_dumb_destroy
,
569 .fops
= &amdgpu_driver_kms_fops
,
571 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
572 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
573 .gem_prime_export
= amdgpu_gem_prime_export
,
574 .gem_prime_import
= drm_gem_prime_import
,
575 .gem_prime_pin
= amdgpu_gem_prime_pin
,
576 .gem_prime_unpin
= amdgpu_gem_prime_unpin
,
577 .gem_prime_res_obj
= amdgpu_gem_prime_res_obj
,
578 .gem_prime_get_sg_table
= amdgpu_gem_prime_get_sg_table
,
579 .gem_prime_import_sg_table
= amdgpu_gem_prime_import_sg_table
,
580 .gem_prime_vmap
= amdgpu_gem_prime_vmap
,
581 .gem_prime_vunmap
= amdgpu_gem_prime_vunmap
,
586 .major
= KMS_DRIVER_MAJOR
,
587 .minor
= KMS_DRIVER_MINOR
,
588 .patchlevel
= KMS_DRIVER_PATCHLEVEL
,
591 static struct drm_driver
*driver
;
592 static struct pci_driver
*pdriver
;
594 static struct pci_driver amdgpu_kms_pci_driver
= {
596 .id_table
= pciidlist
,
597 .probe
= amdgpu_pci_probe
,
598 .remove
= amdgpu_pci_remove
,
599 .driver
.pm
= &amdgpu_pm_ops
,
604 static int __init
amdgpu_init(void)
607 amdgpu_fence_slab_init();
608 if (vgacon_text_force()) {
609 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
612 DRM_INFO("amdgpu kernel modesetting enabled.\n");
613 driver
= &kms_driver
;
614 pdriver
= &amdgpu_kms_pci_driver
;
615 driver
->num_ioctls
= amdgpu_max_kms_ioctl
;
616 amdgpu_register_atpx_handler();
617 /* let modprobe override vga console setting */
618 return drm_pci_init(driver
, pdriver
);
621 static void __exit
amdgpu_exit(void)
623 amdgpu_amdkfd_fini();
624 drm_pci_exit(driver
, pdriver
);
625 amdgpu_unregister_atpx_handler();
627 amdgpu_fence_slab_fini();
630 module_init(amdgpu_init
);
631 module_exit(amdgpu_exit
);
633 MODULE_AUTHOR(DRIVER_AUTHOR
);
634 MODULE_DESCRIPTION(DRIVER_DESC
);
635 MODULE_LICENSE("GPL and additional rights");