Merge remote-tracking branch 'vfio/next'
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ib.c
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <drm/drmP.h>
32 #include <drm/amdgpu_drm.h>
33 #include "amdgpu.h"
34 #include "atom.h"
35
36 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
37
38 /*
39 * IB
40 * IBs (Indirect Buffers) and areas of GPU accessible memory where
41 * commands are stored. You can put a pointer to the IB in the
42 * command ring and the hw will fetch the commands from the IB
43 * and execute them. Generally userspace acceleration drivers
44 * produce command buffers which are send to the kernel and
45 * put in IBs for execution by the requested ring.
46 */
47 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
48
49 /**
50 * amdgpu_ib_get - request an IB (Indirect Buffer)
51 *
52 * @ring: ring index the IB is associated with
53 * @size: requested IB size
54 * @ib: IB object returned
55 *
56 * Request an IB (all asics). IBs are allocated using the
57 * suballocator.
58 * Returns 0 on success, error on failure.
59 */
60 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
61 unsigned size, struct amdgpu_ib *ib)
62 {
63 int r;
64
65 if (size) {
66 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
67 &ib->sa_bo, size, 256);
68 if (r) {
69 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
70 return r;
71 }
72
73 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
74
75 if (!vm)
76 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
77 }
78
79 return 0;
80 }
81
82 /**
83 * amdgpu_ib_free - free an IB (Indirect Buffer)
84 *
85 * @adev: amdgpu_device pointer
86 * @ib: IB object to free
87 * @f: the fence SA bo need wait on for the ib alloation
88 *
89 * Free an IB (all asics).
90 */
91 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
92 struct fence *f)
93 {
94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
95 }
96
97 /**
98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
99 *
100 * @adev: amdgpu_device pointer
101 * @num_ibs: number of IBs to schedule
102 * @ibs: IB objects to schedule
103 * @f: fence created during this submission
104 *
105 * Schedule an IB on the associated ring (all asics).
106 * Returns 0 on success, error on failure.
107 *
108 * On SI, there are two parallel engines fed from the primary ring,
109 * the CE (Constant Engine) and the DE (Drawing Engine). Since
110 * resource descriptors have moved to memory, the CE allows you to
111 * prime the caches while the DE is updating register state so that
112 * the resource descriptors will be already in cache when the draw is
113 * processed. To accomplish this, the userspace driver submits two
114 * IBs, one for the CE and one for the DE. If there is a CE IB (called
115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
116 * to SI there was just a DE IB.
117 */
118 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
119 struct amdgpu_ib *ibs, struct fence *last_vm_update,
120 struct amdgpu_job *job, struct fence **f)
121 {
122 struct amdgpu_device *adev = ring->adev;
123 struct amdgpu_ib *ib = &ibs[0];
124 bool skip_preamble, need_ctx_switch;
125 unsigned patch_offset = ~0;
126 struct amdgpu_vm *vm;
127 uint64_t ctx;
128
129 unsigned i;
130 int r = 0;
131
132 if (num_ibs == 0)
133 return -EINVAL;
134
135 /* ring tests don't use a job */
136 if (job) {
137 vm = job->vm;
138 ctx = job->ctx;
139 } else {
140 vm = NULL;
141 ctx = 0;
142 }
143
144 if (!ring->ready) {
145 dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
146 return -EINVAL;
147 }
148
149 if (vm && !job->vm_id) {
150 dev_err(adev->dev, "VM IB without ID\n");
151 return -EINVAL;
152 }
153
154 r = amdgpu_ring_alloc(ring, 256 * num_ibs);
155 if (r) {
156 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
157 return r;
158 }
159
160 if (ring->type == AMDGPU_RING_TYPE_SDMA && ring->funcs->init_cond_exec)
161 patch_offset = amdgpu_ring_init_cond_exec(ring);
162
163 if (vm) {
164 r = amdgpu_vm_flush(ring, job);
165 if (r) {
166 amdgpu_ring_undo(ring);
167 return r;
168 }
169 }
170
171 if (ring->funcs->emit_hdp_flush)
172 amdgpu_ring_emit_hdp_flush(ring);
173
174 /* always set cond_exec_polling to CONTINUE */
175 *ring->cond_exe_cpu_addr = 1;
176
177 skip_preamble = ring->current_ctx == ctx;
178 need_ctx_switch = ring->current_ctx != ctx;
179 for (i = 0; i < num_ibs; ++i) {
180 ib = &ibs[i];
181
182 /* drop preamble IBs if we don't have a context switch */
183 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble)
184 continue;
185
186 amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
187 need_ctx_switch);
188 need_ctx_switch = false;
189 }
190
191 if (ring->funcs->emit_hdp_invalidate)
192 amdgpu_ring_emit_hdp_invalidate(ring);
193
194 r = amdgpu_fence_emit(ring, f);
195 if (r) {
196 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
197 if (job && job->vm_id)
198 amdgpu_vm_reset_id(adev, job->vm_id);
199 amdgpu_ring_undo(ring);
200 return r;
201 }
202
203 /* wrap the last IB with fence */
204 if (job && job->uf_addr) {
205 amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
206 AMDGPU_FENCE_FLAG_64BIT);
207 }
208
209 if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
210 amdgpu_ring_patch_cond_exec(ring, patch_offset);
211
212 ring->current_ctx = ctx;
213 amdgpu_ring_commit(ring);
214 return 0;
215 }
216
217 /**
218 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
219 *
220 * @adev: amdgpu_device pointer
221 *
222 * Initialize the suballocator to manage a pool of memory
223 * for use as IBs (all asics).
224 * Returns 0 on success, error on failure.
225 */
226 int amdgpu_ib_pool_init(struct amdgpu_device *adev)
227 {
228 int r;
229
230 if (adev->ib_pool_ready) {
231 return 0;
232 }
233 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
234 AMDGPU_IB_POOL_SIZE*64*1024,
235 AMDGPU_GPU_PAGE_SIZE,
236 AMDGPU_GEM_DOMAIN_GTT);
237 if (r) {
238 return r;
239 }
240
241 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
242 if (r) {
243 return r;
244 }
245
246 adev->ib_pool_ready = true;
247 if (amdgpu_debugfs_sa_init(adev)) {
248 dev_err(adev->dev, "failed to register debugfs file for SA\n");
249 }
250 return 0;
251 }
252
253 /**
254 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
255 *
256 * @adev: amdgpu_device pointer
257 *
258 * Tear down the suballocator managing the pool of memory
259 * for use as IBs (all asics).
260 */
261 void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
262 {
263 if (adev->ib_pool_ready) {
264 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
265 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
266 adev->ib_pool_ready = false;
267 }
268 }
269
270 /**
271 * amdgpu_ib_ring_tests - test IBs on the rings
272 *
273 * @adev: amdgpu_device pointer
274 *
275 * Test an IB (Indirect Buffer) on each ring.
276 * If the test fails, disable the ring.
277 * Returns 0 on success, error if the primary GFX ring
278 * IB test fails.
279 */
280 int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
281 {
282 unsigned i;
283 int r, ret = 0;
284
285 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
286 struct amdgpu_ring *ring = adev->rings[i];
287
288 if (!ring || !ring->ready)
289 continue;
290
291 r = amdgpu_ring_test_ib(ring, AMDGPU_IB_TEST_TIMEOUT);
292 if (r) {
293 ring->ready = false;
294
295 if (ring == &adev->gfx.gfx_ring[0]) {
296 /* oh, oh, that's really bad */
297 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
298 adev->accel_working = false;
299 return r;
300
301 } else {
302 /* still not good, but we can live with it */
303 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
304 ret = r;
305 }
306 }
307 }
308 return ret;
309 }
310
311 /*
312 * Debugfs info
313 */
314 #if defined(CONFIG_DEBUG_FS)
315
316 static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
317 {
318 struct drm_info_node *node = (struct drm_info_node *) m->private;
319 struct drm_device *dev = node->minor->dev;
320 struct amdgpu_device *adev = dev->dev_private;
321
322 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
323
324 return 0;
325
326 }
327
328 static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
329 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
330 };
331
332 #endif
333
334 static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
335 {
336 #if defined(CONFIG_DEBUG_FS)
337 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
338 #else
339 return 0;
340 #endif
341 }
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