Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ih.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <drm/drmP.h>
25 #include "amdgpu.h"
26 #include "amdgpu_ih.h"
27 #include "amdgpu_amdkfd.h"
28
29 /**
30 * amdgpu_ih_ring_alloc - allocate memory for the IH ring
31 *
32 * @adev: amdgpu_device pointer
33 *
34 * Allocate a ring buffer for the interrupt controller.
35 * Returns 0 for success, errors for failure.
36 */
37 static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
38 {
39 int r;
40
41 /* Allocate ring buffer */
42 if (adev->irq.ih.ring_obj == NULL) {
43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size,
44 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
45 &adev->irq.ih.ring_obj,
46 &adev->irq.ih.gpu_addr,
47 (void **)&adev->irq.ih.ring);
48 if (r) {
49 DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
50 return r;
51 }
52 }
53 return 0;
54 }
55
56 /**
57 * amdgpu_ih_ring_init - initialize the IH state
58 *
59 * @adev: amdgpu_device pointer
60 *
61 * Initializes the IH state and allocates a buffer
62 * for the IH ring buffer.
63 * Returns 0 for success, errors for failure.
64 */
65 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
66 bool use_bus_addr)
67 {
68 u32 rb_bufsz;
69 int r;
70
71 /* Align ring size */
72 rb_bufsz = order_base_2(ring_size / 4);
73 ring_size = (1 << rb_bufsz) * 4;
74 adev->irq.ih.ring_size = ring_size;
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
76 adev->irq.ih.rptr = 0;
77 adev->irq.ih.use_bus_addr = use_bus_addr;
78
79 if (adev->irq.ih.use_bus_addr) {
80 if (!adev->irq.ih.ring) {
81 /* add 8 bytes for the rptr/wptr shadows and
82 * add them to the end of the ring allocation.
83 */
84 adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
85 adev->irq.ih.ring_size + 8,
86 &adev->irq.ih.rb_dma_addr);
87 if (adev->irq.ih.ring == NULL)
88 return -ENOMEM;
89 memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
90 adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
91 adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
92 }
93 return 0;
94 } else {
95 r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
96 if (r) {
97 dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
98 return r;
99 }
100
101 r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
102 if (r) {
103 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
104 dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
105 return r;
106 }
107
108 return amdgpu_ih_ring_alloc(adev);
109 }
110 }
111
112 /**
113 * amdgpu_ih_ring_fini - tear down the IH state
114 *
115 * @adev: amdgpu_device pointer
116 *
117 * Tears down the IH state and frees buffer
118 * used for the IH ring buffer.
119 */
120 void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
121 {
122 int r;
123
124 if (adev->irq.ih.use_bus_addr) {
125 if (adev->irq.ih.ring) {
126 /* add 8 bytes for the rptr/wptr shadows and
127 * add them to the end of the ring allocation.
128 */
129 pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
130 (void *)adev->irq.ih.ring,
131 adev->irq.ih.rb_dma_addr);
132 adev->irq.ih.ring = NULL;
133 }
134 } else {
135 if (adev->irq.ih.ring_obj) {
136 r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
137 if (likely(r == 0)) {
138 amdgpu_bo_kunmap(adev->irq.ih.ring_obj);
139 amdgpu_bo_unpin(adev->irq.ih.ring_obj);
140 amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
141 }
142 amdgpu_bo_unref(&adev->irq.ih.ring_obj);
143 adev->irq.ih.ring = NULL;
144 adev->irq.ih.ring_obj = NULL;
145 }
146 amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
147 amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
148 }
149 }
150
151 /**
152 * amdgpu_ih_process - interrupt handler
153 *
154 * @adev: amdgpu_device pointer
155 *
156 * Interrupt hander (VI), walk the IH ring.
157 * Returns irq process return code.
158 */
159 int amdgpu_ih_process(struct amdgpu_device *adev)
160 {
161 struct amdgpu_iv_entry entry;
162 u32 wptr;
163
164 if (!adev->irq.ih.enabled || adev->shutdown)
165 return IRQ_NONE;
166
167 wptr = amdgpu_ih_get_wptr(adev);
168
169 restart_ih:
170 /* is somebody else already processing irqs? */
171 if (atomic_xchg(&adev->irq.ih.lock, 1))
172 return IRQ_NONE;
173
174 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
175
176 /* Order reading of wptr vs. reading of IH ring data */
177 rmb();
178
179 while (adev->irq.ih.rptr != wptr) {
180 u32 ring_index = adev->irq.ih.rptr >> 2;
181
182 /* Before dispatching irq to IP blocks, send it to amdkfd */
183 amdgpu_amdkfd_interrupt(adev,
184 (const void *) &adev->irq.ih.ring[ring_index]);
185
186 entry.iv_entry = (const uint32_t *)
187 &adev->irq.ih.ring[ring_index];
188 amdgpu_ih_decode_iv(adev, &entry);
189 adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
190
191 amdgpu_irq_dispatch(adev, &entry);
192 }
193 amdgpu_ih_set_rptr(adev);
194 atomic_set(&adev->irq.ih.lock, 0);
195
196 /* make sure wptr hasn't changed while processing */
197 wptr = amdgpu_ih_get_wptr(adev);
198 if (wptr != adev->irq.ih.rptr)
199 goto restart_ih;
200
201 return IRQ_HANDLED;
202 }
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