2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
34 #include <linux/vga_switcheroo.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
37 #include "amdgpu_amdkfd.h"
39 #if defined(CONFIG_VGA_SWITCHEROO)
40 bool amdgpu_has_atpx(void);
42 static inline bool amdgpu_has_atpx(void) { return false; }
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
48 * @dev: drm dev pointer
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
53 int amdgpu_driver_unload_kms(struct drm_device
*dev
)
55 struct amdgpu_device
*adev
= dev
->dev_private
;
60 if (adev
->rmmio
== NULL
)
63 if (amdgpu_device_is_px(dev
)) {
64 pm_runtime_get_sync(dev
->dev
);
65 pm_runtime_forbid(dev
->dev
);
68 amdgpu_amdkfd_device_fini(adev
);
70 amdgpu_acpi_fini(adev
);
72 amdgpu_device_fini(adev
);
76 dev
->dev_private
= NULL
;
81 * amdgpu_driver_load_kms - Main load function for KMS.
83 * @dev: drm dev pointer
84 * @flags: device flags
86 * This is the main load function for KMS (all asics).
87 * Returns 0 on success, error on failure.
89 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
91 struct amdgpu_device
*adev
;
94 adev
= kzalloc(sizeof(struct amdgpu_device
), GFP_KERNEL
);
98 dev
->dev_private
= (void *)adev
;
100 if ((amdgpu_runtime_pm
!= 0) &&
102 ((flags
& AMD_IS_APU
) == 0))
105 /* amdgpu_device_init should report only fatal error
106 * like memory allocation failure or iomapping failure,
107 * or memory manager initialization failure, it must
108 * properly initialize the GPU MC controller and permit
111 r
= amdgpu_device_init(adev
, dev
, dev
->pdev
, flags
);
113 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
117 /* Call ACPI methods: require modeset init
118 * but failure is not fatal
121 acpi_status
= amdgpu_acpi_init(adev
);
123 dev_dbg(&dev
->pdev
->dev
,
124 "Error during ACPI methods call\n");
127 amdgpu_amdkfd_load_interface(adev
);
128 amdgpu_amdkfd_device_probe(adev
);
129 amdgpu_amdkfd_device_init(adev
);
131 if (amdgpu_device_is_px(dev
)) {
132 pm_runtime_use_autosuspend(dev
->dev
);
133 pm_runtime_set_autosuspend_delay(dev
->dev
, 5000);
134 pm_runtime_set_active(dev
->dev
);
135 pm_runtime_allow(dev
->dev
);
136 pm_runtime_mark_last_busy(dev
->dev
);
137 pm_runtime_put_autosuspend(dev
->dev
);
142 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
143 if (adev
->rmmio
&& amdgpu_device_is_px(dev
))
144 pm_runtime_put_noidle(dev
->dev
);
145 amdgpu_driver_unload_kms(dev
);
151 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware
*fw_info
,
152 struct drm_amdgpu_query_fw
*query_fw
,
153 struct amdgpu_device
*adev
)
155 switch (query_fw
->fw_type
) {
156 case AMDGPU_INFO_FW_VCE
:
157 fw_info
->ver
= adev
->vce
.fw_version
;
158 fw_info
->feature
= adev
->vce
.fb_version
;
160 case AMDGPU_INFO_FW_UVD
:
161 fw_info
->ver
= adev
->uvd
.fw_version
;
162 fw_info
->feature
= 0;
164 case AMDGPU_INFO_FW_GMC
:
165 fw_info
->ver
= adev
->mc
.fw_version
;
166 fw_info
->feature
= 0;
168 case AMDGPU_INFO_FW_GFX_ME
:
169 fw_info
->ver
= adev
->gfx
.me_fw_version
;
170 fw_info
->feature
= adev
->gfx
.me_feature_version
;
172 case AMDGPU_INFO_FW_GFX_PFP
:
173 fw_info
->ver
= adev
->gfx
.pfp_fw_version
;
174 fw_info
->feature
= adev
->gfx
.pfp_feature_version
;
176 case AMDGPU_INFO_FW_GFX_CE
:
177 fw_info
->ver
= adev
->gfx
.ce_fw_version
;
178 fw_info
->feature
= adev
->gfx
.ce_feature_version
;
180 case AMDGPU_INFO_FW_GFX_RLC
:
181 fw_info
->ver
= adev
->gfx
.rlc_fw_version
;
182 fw_info
->feature
= adev
->gfx
.rlc_feature_version
;
184 case AMDGPU_INFO_FW_GFX_MEC
:
185 if (query_fw
->index
== 0) {
186 fw_info
->ver
= adev
->gfx
.mec_fw_version
;
187 fw_info
->feature
= adev
->gfx
.mec_feature_version
;
188 } else if (query_fw
->index
== 1) {
189 fw_info
->ver
= adev
->gfx
.mec2_fw_version
;
190 fw_info
->feature
= adev
->gfx
.mec2_feature_version
;
194 case AMDGPU_INFO_FW_SMC
:
195 fw_info
->ver
= adev
->pm
.fw_version
;
196 fw_info
->feature
= 0;
198 case AMDGPU_INFO_FW_SDMA
:
199 if (query_fw
->index
>= adev
->sdma
.num_instances
)
201 fw_info
->ver
= adev
->sdma
.instance
[query_fw
->index
].fw_version
;
202 fw_info
->feature
= adev
->sdma
.instance
[query_fw
->index
].feature_version
;
211 * Userspace get information ioctl
214 * amdgpu_info_ioctl - answer a device specific request.
216 * @adev: amdgpu device pointer
217 * @data: request object
220 * This function is used to pass device specific parameters to the userspace
221 * drivers. Examples include: pci device id, pipeline parms, tiling params,
223 * Returns 0 on success, -EINVAL on failure.
225 static int amdgpu_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
227 struct amdgpu_device
*adev
= dev
->dev_private
;
228 struct drm_amdgpu_info
*info
= data
;
229 struct amdgpu_mode_info
*minfo
= &adev
->mode_info
;
230 void __user
*out
= (void __user
*)(long)info
->return_pointer
;
231 uint32_t size
= info
->return_size
;
232 struct drm_crtc
*crtc
;
237 if (!info
->return_size
|| !info
->return_pointer
)
240 switch (info
->query
) {
241 case AMDGPU_INFO_ACCEL_WORKING
:
242 ui32
= adev
->accel_working
;
243 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
244 case AMDGPU_INFO_CRTC_FROM_ID
:
245 for (i
= 0, found
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
246 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
247 if (crtc
&& crtc
->base
.id
== info
->mode_crtc
.id
) {
248 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
249 ui32
= amdgpu_crtc
->crtc_id
;
255 DRM_DEBUG_KMS("unknown crtc id %d\n", info
->mode_crtc
.id
);
258 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
259 case AMDGPU_INFO_HW_IP_INFO
: {
260 struct drm_amdgpu_info_hw_ip ip
= {};
261 enum amd_ip_block_type type
;
262 uint32_t ring_mask
= 0;
263 uint32_t ib_start_alignment
= 0;
264 uint32_t ib_size_alignment
= 0;
266 if (info
->query_hw_ip
.ip_instance
>= AMDGPU_HW_IP_INSTANCE_MAX_COUNT
)
269 switch (info
->query_hw_ip
.type
) {
270 case AMDGPU_HW_IP_GFX
:
271 type
= AMD_IP_BLOCK_TYPE_GFX
;
272 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
273 ring_mask
|= ((adev
->gfx
.gfx_ring
[i
].ready
? 1 : 0) << i
);
274 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
275 ib_size_alignment
= 8;
277 case AMDGPU_HW_IP_COMPUTE
:
278 type
= AMD_IP_BLOCK_TYPE_GFX
;
279 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
280 ring_mask
|= ((adev
->gfx
.compute_ring
[i
].ready
? 1 : 0) << i
);
281 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
282 ib_size_alignment
= 8;
284 case AMDGPU_HW_IP_DMA
:
285 type
= AMD_IP_BLOCK_TYPE_SDMA
;
286 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
287 ring_mask
|= ((adev
->sdma
.instance
[i
].ring
.ready
? 1 : 0) << i
);
288 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
289 ib_size_alignment
= 1;
291 case AMDGPU_HW_IP_UVD
:
292 type
= AMD_IP_BLOCK_TYPE_UVD
;
293 ring_mask
= adev
->uvd
.ring
.ready
? 1 : 0;
294 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
295 ib_size_alignment
= 8;
297 case AMDGPU_HW_IP_VCE
:
298 type
= AMD_IP_BLOCK_TYPE_VCE
;
299 for (i
= 0; i
< AMDGPU_MAX_VCE_RINGS
; i
++)
300 ring_mask
|= ((adev
->vce
.ring
[i
].ready
? 1 : 0) << i
);
301 ib_start_alignment
= AMDGPU_GPU_PAGE_SIZE
;
302 ib_size_alignment
= 8;
308 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
309 if (adev
->ip_blocks
[i
].type
== type
&&
310 adev
->ip_block_status
[i
].valid
) {
311 ip
.hw_ip_version_major
= adev
->ip_blocks
[i
].major
;
312 ip
.hw_ip_version_minor
= adev
->ip_blocks
[i
].minor
;
313 ip
.capabilities_flags
= 0;
314 ip
.available_rings
= ring_mask
;
315 ip
.ib_start_alignment
= ib_start_alignment
;
316 ip
.ib_size_alignment
= ib_size_alignment
;
320 return copy_to_user(out
, &ip
,
321 min((size_t)size
, sizeof(ip
))) ? -EFAULT
: 0;
323 case AMDGPU_INFO_HW_IP_COUNT
: {
324 enum amd_ip_block_type type
;
327 switch (info
->query_hw_ip
.type
) {
328 case AMDGPU_HW_IP_GFX
:
329 type
= AMD_IP_BLOCK_TYPE_GFX
;
331 case AMDGPU_HW_IP_COMPUTE
:
332 type
= AMD_IP_BLOCK_TYPE_GFX
;
334 case AMDGPU_HW_IP_DMA
:
335 type
= AMD_IP_BLOCK_TYPE_SDMA
;
337 case AMDGPU_HW_IP_UVD
:
338 type
= AMD_IP_BLOCK_TYPE_UVD
;
340 case AMDGPU_HW_IP_VCE
:
341 type
= AMD_IP_BLOCK_TYPE_VCE
;
347 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
348 if (adev
->ip_blocks
[i
].type
== type
&&
349 adev
->ip_block_status
[i
].valid
&&
350 count
< AMDGPU_HW_IP_INSTANCE_MAX_COUNT
)
353 return copy_to_user(out
, &count
, min(size
, 4u)) ? -EFAULT
: 0;
355 case AMDGPU_INFO_TIMESTAMP
:
356 ui64
= amdgpu_gfx_get_gpu_clock_counter(adev
);
357 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
358 case AMDGPU_INFO_FW_VERSION
: {
359 struct drm_amdgpu_info_firmware fw_info
;
362 /* We only support one instance of each IP block right now. */
363 if (info
->query_fw
.ip_instance
!= 0)
366 ret
= amdgpu_firmware_info(&fw_info
, &info
->query_fw
, adev
);
370 return copy_to_user(out
, &fw_info
,
371 min((size_t)size
, sizeof(fw_info
))) ? -EFAULT
: 0;
373 case AMDGPU_INFO_NUM_BYTES_MOVED
:
374 ui64
= atomic64_read(&adev
->num_bytes_moved
);
375 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
376 case AMDGPU_INFO_VRAM_USAGE
:
377 ui64
= atomic64_read(&adev
->vram_usage
);
378 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
379 case AMDGPU_INFO_VIS_VRAM_USAGE
:
380 ui64
= atomic64_read(&adev
->vram_vis_usage
);
381 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
382 case AMDGPU_INFO_GTT_USAGE
:
383 ui64
= atomic64_read(&adev
->gtt_usage
);
384 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
385 case AMDGPU_INFO_GDS_CONFIG
: {
386 struct drm_amdgpu_info_gds gds_info
;
388 memset(&gds_info
, 0, sizeof(gds_info
));
389 gds_info
.gds_gfx_partition_size
= adev
->gds
.mem
.gfx_partition_size
>> AMDGPU_GDS_SHIFT
;
390 gds_info
.compute_partition_size
= adev
->gds
.mem
.cs_partition_size
>> AMDGPU_GDS_SHIFT
;
391 gds_info
.gds_total_size
= adev
->gds
.mem
.total_size
>> AMDGPU_GDS_SHIFT
;
392 gds_info
.gws_per_gfx_partition
= adev
->gds
.gws
.gfx_partition_size
>> AMDGPU_GWS_SHIFT
;
393 gds_info
.gws_per_compute_partition
= adev
->gds
.gws
.cs_partition_size
>> AMDGPU_GWS_SHIFT
;
394 gds_info
.oa_per_gfx_partition
= adev
->gds
.oa
.gfx_partition_size
>> AMDGPU_OA_SHIFT
;
395 gds_info
.oa_per_compute_partition
= adev
->gds
.oa
.cs_partition_size
>> AMDGPU_OA_SHIFT
;
396 return copy_to_user(out
, &gds_info
,
397 min((size_t)size
, sizeof(gds_info
))) ? -EFAULT
: 0;
399 case AMDGPU_INFO_VRAM_GTT
: {
400 struct drm_amdgpu_info_vram_gtt vram_gtt
;
402 vram_gtt
.vram_size
= adev
->mc
.real_vram_size
;
403 vram_gtt
.vram_size
-= adev
->vram_pin_size
;
404 vram_gtt
.vram_cpu_accessible_size
= adev
->mc
.visible_vram_size
;
405 vram_gtt
.vram_cpu_accessible_size
-= (adev
->vram_pin_size
- adev
->invisible_pin_size
);
406 vram_gtt
.gtt_size
= adev
->mc
.gtt_size
;
407 vram_gtt
.gtt_size
-= adev
->gart_pin_size
;
408 return copy_to_user(out
, &vram_gtt
,
409 min((size_t)size
, sizeof(vram_gtt
))) ? -EFAULT
: 0;
411 case AMDGPU_INFO_READ_MMR_REG
: {
412 unsigned n
, alloc_size
;
414 unsigned se_num
= (info
->read_mmr_reg
.instance
>>
415 AMDGPU_INFO_MMR_SE_INDEX_SHIFT
) &
416 AMDGPU_INFO_MMR_SE_INDEX_MASK
;
417 unsigned sh_num
= (info
->read_mmr_reg
.instance
>>
418 AMDGPU_INFO_MMR_SH_INDEX_SHIFT
) &
419 AMDGPU_INFO_MMR_SH_INDEX_MASK
;
421 /* set full masks if the userspace set all bits
422 * in the bitfields */
423 if (se_num
== AMDGPU_INFO_MMR_SE_INDEX_MASK
)
425 if (sh_num
== AMDGPU_INFO_MMR_SH_INDEX_MASK
)
428 regs
= kmalloc_array(info
->read_mmr_reg
.count
, sizeof(*regs
), GFP_KERNEL
);
431 alloc_size
= info
->read_mmr_reg
.count
* sizeof(*regs
);
433 for (i
= 0; i
< info
->read_mmr_reg
.count
; i
++)
434 if (amdgpu_asic_read_register(adev
, se_num
, sh_num
,
435 info
->read_mmr_reg
.dword_offset
+ i
,
437 DRM_DEBUG_KMS("unallowed offset %#x\n",
438 info
->read_mmr_reg
.dword_offset
+ i
);
442 n
= copy_to_user(out
, regs
, min(size
, alloc_size
));
444 return n
? -EFAULT
: 0;
446 case AMDGPU_INFO_DEV_INFO
: {
447 struct drm_amdgpu_info_device dev_info
= {};
449 dev_info
.device_id
= dev
->pdev
->device
;
450 dev_info
.chip_rev
= adev
->rev_id
;
451 dev_info
.external_rev
= adev
->external_rev_id
;
452 dev_info
.pci_rev
= dev
->pdev
->revision
;
453 dev_info
.family
= adev
->family
;
454 dev_info
.num_shader_engines
= adev
->gfx
.config
.max_shader_engines
;
455 dev_info
.num_shader_arrays_per_engine
= adev
->gfx
.config
.max_sh_per_se
;
456 /* return all clocks in KHz */
457 dev_info
.gpu_counter_freq
= amdgpu_asic_get_xclk(adev
) * 10;
458 if (adev
->pm
.dpm_enabled
) {
459 dev_info
.max_engine_clock
=
460 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.sclk
* 10;
461 dev_info
.max_memory_clock
=
462 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.mclk
* 10;
464 dev_info
.max_engine_clock
= adev
->pm
.default_sclk
* 10;
465 dev_info
.max_memory_clock
= adev
->pm
.default_mclk
* 10;
467 dev_info
.enabled_rb_pipes_mask
= adev
->gfx
.config
.backend_enable_mask
;
468 dev_info
.num_rb_pipes
= adev
->gfx
.config
.max_backends_per_se
*
469 adev
->gfx
.config
.max_shader_engines
;
470 dev_info
.num_hw_gfx_contexts
= adev
->gfx
.config
.max_hw_contexts
;
472 dev_info
.ids_flags
= 0;
473 if (adev
->flags
& AMD_IS_APU
)
474 dev_info
.ids_flags
|= AMDGPU_IDS_FLAGS_FUSION
;
475 dev_info
.virtual_address_offset
= AMDGPU_VA_RESERVED_SIZE
;
476 dev_info
.virtual_address_max
= (uint64_t)adev
->vm_manager
.max_pfn
* AMDGPU_GPU_PAGE_SIZE
;
477 dev_info
.virtual_address_alignment
= max((int)PAGE_SIZE
, AMDGPU_GPU_PAGE_SIZE
);
478 dev_info
.pte_fragment_size
= (1 << AMDGPU_LOG2_PAGES_PER_FRAG
) *
479 AMDGPU_GPU_PAGE_SIZE
;
480 dev_info
.gart_page_size
= AMDGPU_GPU_PAGE_SIZE
;
482 dev_info
.cu_active_number
= adev
->gfx
.cu_info
.number
;
483 dev_info
.cu_ao_mask
= adev
->gfx
.cu_info
.ao_cu_mask
;
484 dev_info
.ce_ram_size
= adev
->gfx
.ce_ram_size
;
485 memcpy(&dev_info
.cu_bitmap
[0], &adev
->gfx
.cu_info
.bitmap
[0],
486 sizeof(adev
->gfx
.cu_info
.bitmap
));
487 dev_info
.vram_type
= adev
->mc
.vram_type
;
488 dev_info
.vram_bit_width
= adev
->mc
.vram_width
;
489 dev_info
.vce_harvest_config
= adev
->vce
.harvest_config
;
491 return copy_to_user(out
, &dev_info
,
492 min((size_t)size
, sizeof(dev_info
))) ? -EFAULT
: 0;
495 DRM_DEBUG_KMS("Invalid request %d\n", info
->query
);
503 * Outdated mess for old drm with Xorg being in charge (void function now).
506 * amdgpu_driver_lastclose_kms - drm callback for last close
508 * @dev: drm dev pointer
510 * Switch vga_switcheroo state after last close (all asics).
512 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
)
514 struct amdgpu_device
*adev
= dev
->dev_private
;
516 amdgpu_fbdev_restore_mode(adev
);
517 vga_switcheroo_process_delayed_switch();
521 * amdgpu_driver_open_kms - drm callback for open
523 * @dev: drm dev pointer
524 * @file_priv: drm file
526 * On device open, init vm on cayman+ (all asics).
527 * Returns 0 on success, error on failure.
529 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
531 struct amdgpu_device
*adev
= dev
->dev_private
;
532 struct amdgpu_fpriv
*fpriv
;
535 file_priv
->driver_priv
= NULL
;
537 r
= pm_runtime_get_sync(dev
->dev
);
541 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
542 if (unlikely(!fpriv
))
545 r
= amdgpu_vm_init(adev
, &fpriv
->vm
);
549 mutex_init(&fpriv
->bo_list_lock
);
550 idr_init(&fpriv
->bo_list_handles
);
552 amdgpu_ctx_mgr_init(&fpriv
->ctx_mgr
);
554 file_priv
->driver_priv
= fpriv
;
556 pm_runtime_mark_last_busy(dev
->dev
);
557 pm_runtime_put_autosuspend(dev
->dev
);
567 * amdgpu_driver_postclose_kms - drm callback for post close
569 * @dev: drm dev pointer
570 * @file_priv: drm file
572 * On device post close, tear down vm on cayman+ (all asics).
574 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
575 struct drm_file
*file_priv
)
577 struct amdgpu_device
*adev
= dev
->dev_private
;
578 struct amdgpu_fpriv
*fpriv
= file_priv
->driver_priv
;
579 struct amdgpu_bo_list
*list
;
585 amdgpu_ctx_mgr_fini(&fpriv
->ctx_mgr
);
587 amdgpu_uvd_free_handles(adev
, file_priv
);
588 amdgpu_vce_free_handles(adev
, file_priv
);
590 amdgpu_vm_fini(adev
, &fpriv
->vm
);
592 idr_for_each_entry(&fpriv
->bo_list_handles
, list
, handle
)
593 amdgpu_bo_list_free(list
);
595 idr_destroy(&fpriv
->bo_list_handles
);
596 mutex_destroy(&fpriv
->bo_list_lock
);
599 file_priv
->driver_priv
= NULL
;
603 * amdgpu_driver_preclose_kms - drm callback for pre close
605 * @dev: drm dev pointer
606 * @file_priv: drm file
608 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
611 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
612 struct drm_file
*file_priv
)
617 * VBlank related functions.
620 * amdgpu_get_vblank_counter_kms - get frame count
622 * @dev: drm dev pointer
623 * @pipe: crtc to get the frame count from
625 * Gets the frame count on the requested crtc (all asics).
626 * Returns frame count on success, -EINVAL on failure.
628 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
)
630 struct amdgpu_device
*adev
= dev
->dev_private
;
631 int vpos
, hpos
, stat
;
634 if (pipe
>= adev
->mode_info
.num_crtc
) {
635 DRM_ERROR("Invalid crtc %u\n", pipe
);
639 /* The hw increments its frame counter at start of vsync, not at start
640 * of vblank, as is required by DRM core vblank counter handling.
641 * Cook the hw count here to make it appear to the caller as if it
642 * incremented at start of vblank. We measure distance to start of
643 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
644 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
645 * result by 1 to give the proper appearance to caller.
647 if (adev
->mode_info
.crtcs
[pipe
]) {
648 /* Repeat readout if needed to provide stable result if
649 * we cross start of vsync during the queries.
652 count
= amdgpu_display_vblank_get_counter(adev
, pipe
);
653 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
654 * distance to start of vblank, instead of regular
655 * vertical scanout pos.
657 stat
= amdgpu_get_crtc_scanoutpos(
658 dev
, pipe
, GET_DISTANCE_TO_VBLANKSTART
,
659 &vpos
, &hpos
, NULL
, NULL
,
660 &adev
->mode_info
.crtcs
[pipe
]->base
.hwmode
);
661 } while (count
!= amdgpu_display_vblank_get_counter(adev
, pipe
));
663 if (((stat
& (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
)) !=
664 (DRM_SCANOUTPOS_VALID
| DRM_SCANOUTPOS_ACCURATE
))) {
665 DRM_DEBUG_VBL("Query failed! stat %d\n", stat
);
667 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
670 /* Bump counter if we are at >= leading edge of vblank,
671 * but before vsync where vpos would turn negative and
672 * the hw counter really increments.
678 /* Fallback to use value as is. */
679 count
= amdgpu_display_vblank_get_counter(adev
, pipe
);
680 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
687 * amdgpu_enable_vblank_kms - enable vblank interrupt
689 * @dev: drm dev pointer
690 * @pipe: crtc to enable vblank interrupt for
692 * Enable the interrupt on the requested crtc (all asics).
693 * Returns 0 on success, -EINVAL on failure.
695 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
)
697 struct amdgpu_device
*adev
= dev
->dev_private
;
698 int idx
= amdgpu_crtc_idx_to_irq_type(adev
, pipe
);
700 return amdgpu_irq_get(adev
, &adev
->crtc_irq
, idx
);
704 * amdgpu_disable_vblank_kms - disable vblank interrupt
706 * @dev: drm dev pointer
707 * @pipe: crtc to disable vblank interrupt for
709 * Disable the interrupt on the requested crtc (all asics).
711 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
)
713 struct amdgpu_device
*adev
= dev
->dev_private
;
714 int idx
= amdgpu_crtc_idx_to_irq_type(adev
, pipe
);
716 amdgpu_irq_put(adev
, &adev
->crtc_irq
, idx
);
720 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
722 * @dev: drm dev pointer
723 * @crtc: crtc to get the timestamp for
724 * @max_error: max error
725 * @vblank_time: time value
726 * @flags: flags passed to the driver
728 * Gets the timestamp on the requested crtc based on the
729 * scanout position. (all asics).
730 * Returns postive status flags on success, negative error on failure.
732 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, unsigned int pipe
,
734 struct timeval
*vblank_time
,
737 struct drm_crtc
*crtc
;
738 struct amdgpu_device
*adev
= dev
->dev_private
;
740 if (pipe
>= dev
->num_crtcs
) {
741 DRM_ERROR("Invalid crtc %u\n", pipe
);
745 /* Get associated drm_crtc: */
746 crtc
= &adev
->mode_info
.crtcs
[pipe
]->base
;
748 /* This can occur on driver load if some component fails to
749 * initialize completely and driver is unloaded */
750 DRM_ERROR("Uninitialized crtc %d\n", pipe
);
754 /* Helper routine in DRM core does all the work: */
755 return drm_calc_vbltimestamp_from_scanoutpos(dev
, pipe
, max_error
,
760 const struct drm_ioctl_desc amdgpu_ioctls_kms
[] = {
761 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE
, amdgpu_gem_create_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
762 DRM_IOCTL_DEF_DRV(AMDGPU_CTX
, amdgpu_ctx_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
763 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST
, amdgpu_bo_list_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
765 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP
, amdgpu_gem_mmap_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
766 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE
, amdgpu_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
767 DRM_IOCTL_DEF_DRV(AMDGPU_CS
, amdgpu_cs_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
768 DRM_IOCTL_DEF_DRV(AMDGPU_INFO
, amdgpu_info_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
769 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS
, amdgpu_cs_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
770 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA
, amdgpu_gem_metadata_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
771 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA
, amdgpu_gem_va_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP
, amdgpu_gem_op_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
773 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR
, amdgpu_gem_userptr_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
775 const int amdgpu_max_kms_ioctl
= ARRAY_SIZE(amdgpu_ioctls_kms
);
780 #if defined(CONFIG_DEBUG_FS)
782 static int amdgpu_debugfs_firmware_info(struct seq_file
*m
, void *data
)
784 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
785 struct drm_device
*dev
= node
->minor
->dev
;
786 struct amdgpu_device
*adev
= dev
->dev_private
;
787 struct drm_amdgpu_info_firmware fw_info
;
788 struct drm_amdgpu_query_fw query_fw
;
792 query_fw
.fw_type
= AMDGPU_INFO_FW_VCE
;
793 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
796 seq_printf(m
, "VCE feature version: %u, firmware version: 0x%08x\n",
797 fw_info
.feature
, fw_info
.ver
);
800 query_fw
.fw_type
= AMDGPU_INFO_FW_UVD
;
801 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
804 seq_printf(m
, "UVD feature version: %u, firmware version: 0x%08x\n",
805 fw_info
.feature
, fw_info
.ver
);
808 query_fw
.fw_type
= AMDGPU_INFO_FW_GMC
;
809 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
812 seq_printf(m
, "MC feature version: %u, firmware version: 0x%08x\n",
813 fw_info
.feature
, fw_info
.ver
);
816 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_ME
;
817 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
820 seq_printf(m
, "ME feature version: %u, firmware version: 0x%08x\n",
821 fw_info
.feature
, fw_info
.ver
);
824 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_PFP
;
825 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
828 seq_printf(m
, "PFP feature version: %u, firmware version: 0x%08x\n",
829 fw_info
.feature
, fw_info
.ver
);
832 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_CE
;
833 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
836 seq_printf(m
, "CE feature version: %u, firmware version: 0x%08x\n",
837 fw_info
.feature
, fw_info
.ver
);
840 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_RLC
;
841 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
844 seq_printf(m
, "RLC feature version: %u, firmware version: 0x%08x\n",
845 fw_info
.feature
, fw_info
.ver
);
848 query_fw
.fw_type
= AMDGPU_INFO_FW_GFX_MEC
;
850 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
853 seq_printf(m
, "MEC feature version: %u, firmware version: 0x%08x\n",
854 fw_info
.feature
, fw_info
.ver
);
857 if (adev
->asic_type
== CHIP_KAVERI
||
858 (adev
->asic_type
> CHIP_TOPAZ
&& adev
->asic_type
!= CHIP_STONEY
)) {
860 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
863 seq_printf(m
, "MEC2 feature version: %u, firmware version: 0x%08x\n",
864 fw_info
.feature
, fw_info
.ver
);
868 query_fw
.fw_type
= AMDGPU_INFO_FW_SMC
;
869 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
872 seq_printf(m
, "SMC feature version: %u, firmware version: 0x%08x\n",
873 fw_info
.feature
, fw_info
.ver
);
876 query_fw
.fw_type
= AMDGPU_INFO_FW_SDMA
;
877 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
879 ret
= amdgpu_firmware_info(&fw_info
, &query_fw
, adev
);
882 seq_printf(m
, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
883 i
, fw_info
.feature
, fw_info
.ver
);
889 static const struct drm_info_list amdgpu_firmware_info_list
[] = {
890 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info
, 0, NULL
},
894 int amdgpu_debugfs_firmware_init(struct amdgpu_device
*adev
)
896 #if defined(CONFIG_DEBUG_FS)
897 return amdgpu_debugfs_add_files(adev
, amdgpu_firmware_info_list
,
898 ARRAY_SIZE(amdgpu_firmware_info_list
));