2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
40 #include "uvd/uvd_4_2_d.h"
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT_MS 1000
46 #ifdef CONFIG_DRM_AMDGPU_CIK
47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
55 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
56 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
59 * amdgpu_uvd_cs_ctx - Command submission parser context
61 * Used for emulating virtual memory support on UVD 4.2.
63 struct amdgpu_uvd_cs_ctx
{
64 struct amdgpu_cs_parser
*parser
;
66 unsigned data0
, data1
;
70 /* does the IB has a msg command */
73 /* minimum buffer sizes */
77 #ifdef CONFIG_DRM_AMDGPU_CIK
78 MODULE_FIRMWARE(FIRMWARE_BONAIRE
);
79 MODULE_FIRMWARE(FIRMWARE_KABINI
);
80 MODULE_FIRMWARE(FIRMWARE_KAVERI
);
81 MODULE_FIRMWARE(FIRMWARE_HAWAII
);
82 MODULE_FIRMWARE(FIRMWARE_MULLINS
);
84 MODULE_FIRMWARE(FIRMWARE_TONGA
);
85 MODULE_FIRMWARE(FIRMWARE_CARRIZO
);
86 MODULE_FIRMWARE(FIRMWARE_FIJI
);
87 MODULE_FIRMWARE(FIRMWARE_STONEY
);
89 static void amdgpu_uvd_note_usage(struct amdgpu_device
*adev
);
90 static void amdgpu_uvd_idle_work_handler(struct work_struct
*work
);
92 int amdgpu_uvd_sw_init(struct amdgpu_device
*adev
)
94 struct amdgpu_ring
*ring
;
95 struct amd_sched_rq
*rq
;
96 unsigned long bo_size
;
98 const struct common_firmware_header
*hdr
;
99 unsigned version_major
, version_minor
, family_id
;
102 INIT_DELAYED_WORK(&adev
->uvd
.idle_work
, amdgpu_uvd_idle_work_handler
);
104 switch (adev
->asic_type
) {
105 #ifdef CONFIG_DRM_AMDGPU_CIK
107 fw_name
= FIRMWARE_BONAIRE
;
110 fw_name
= FIRMWARE_KABINI
;
113 fw_name
= FIRMWARE_KAVERI
;
116 fw_name
= FIRMWARE_HAWAII
;
119 fw_name
= FIRMWARE_MULLINS
;
123 fw_name
= FIRMWARE_TONGA
;
126 fw_name
= FIRMWARE_FIJI
;
129 fw_name
= FIRMWARE_CARRIZO
;
132 fw_name
= FIRMWARE_STONEY
;
138 r
= request_firmware(&adev
->uvd
.fw
, fw_name
, adev
->dev
);
140 dev_err(adev
->dev
, "amdgpu_uvd: Can't load firmware \"%s\"\n",
145 r
= amdgpu_ucode_validate(adev
->uvd
.fw
);
147 dev_err(adev
->dev
, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
149 release_firmware(adev
->uvd
.fw
);
154 hdr
= (const struct common_firmware_header
*)adev
->uvd
.fw
->data
;
155 family_id
= le32_to_cpu(hdr
->ucode_version
) & 0xff;
156 version_major
= (le32_to_cpu(hdr
->ucode_version
) >> 24) & 0xff;
157 version_minor
= (le32_to_cpu(hdr
->ucode_version
) >> 8) & 0xff;
158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
159 version_major
, version_minor
, family_id
);
161 bo_size
= AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr
->ucode_size_bytes
) + 8)
162 + AMDGPU_UVD_STACK_SIZE
+ AMDGPU_UVD_HEAP_SIZE
;
163 r
= amdgpu_bo_create(adev
, bo_size
, PAGE_SIZE
, true,
164 AMDGPU_GEM_DOMAIN_VRAM
,
165 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
166 NULL
, NULL
, &adev
->uvd
.vcpu_bo
);
168 dev_err(adev
->dev
, "(%d) failed to allocate UVD bo\n", r
);
172 r
= amdgpu_bo_reserve(adev
->uvd
.vcpu_bo
, false);
174 amdgpu_bo_unref(&adev
->uvd
.vcpu_bo
);
175 dev_err(adev
->dev
, "(%d) failed to reserve UVD bo\n", r
);
179 r
= amdgpu_bo_pin(adev
->uvd
.vcpu_bo
, AMDGPU_GEM_DOMAIN_VRAM
,
180 &adev
->uvd
.gpu_addr
);
182 amdgpu_bo_unreserve(adev
->uvd
.vcpu_bo
);
183 amdgpu_bo_unref(&adev
->uvd
.vcpu_bo
);
184 dev_err(adev
->dev
, "(%d) UVD bo pin failed\n", r
);
188 r
= amdgpu_bo_kmap(adev
->uvd
.vcpu_bo
, &adev
->uvd
.cpu_addr
);
190 dev_err(adev
->dev
, "(%d) UVD map failed\n", r
);
194 amdgpu_bo_unreserve(adev
->uvd
.vcpu_bo
);
196 ring
= &adev
->uvd
.ring
;
197 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_NORMAL
];
198 r
= amd_sched_entity_init(&ring
->sched
, &adev
->uvd
.entity
,
199 rq
, amdgpu_sched_jobs
);
201 DRM_ERROR("Failed setting up UVD run queue.\n");
205 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
) {
206 atomic_set(&adev
->uvd
.handles
[i
], 0);
207 adev
->uvd
.filp
[i
] = NULL
;
210 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
211 if (!amdgpu_ip_block_version_cmp(adev
, AMD_IP_BLOCK_TYPE_UVD
, 5, 0))
212 adev
->uvd
.address_64_bit
= true;
217 int amdgpu_uvd_sw_fini(struct amdgpu_device
*adev
)
221 if (adev
->uvd
.vcpu_bo
== NULL
)
224 amd_sched_entity_fini(&adev
->uvd
.ring
.sched
, &adev
->uvd
.entity
);
226 r
= amdgpu_bo_reserve(adev
->uvd
.vcpu_bo
, false);
228 amdgpu_bo_kunmap(adev
->uvd
.vcpu_bo
);
229 amdgpu_bo_unpin(adev
->uvd
.vcpu_bo
);
230 amdgpu_bo_unreserve(adev
->uvd
.vcpu_bo
);
233 amdgpu_bo_unref(&adev
->uvd
.vcpu_bo
);
235 amdgpu_ring_fini(&adev
->uvd
.ring
);
237 release_firmware(adev
->uvd
.fw
);
242 int amdgpu_uvd_suspend(struct amdgpu_device
*adev
)
248 if (adev
->uvd
.vcpu_bo
== NULL
)
251 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
)
252 if (atomic_read(&adev
->uvd
.handles
[i
]))
255 if (i
== AMDGPU_MAX_UVD_HANDLES
)
258 size
= amdgpu_bo_size(adev
->uvd
.vcpu_bo
);
259 ptr
= adev
->uvd
.cpu_addr
;
261 adev
->uvd
.saved_bo
= kmalloc(size
, GFP_KERNEL
);
262 if (!adev
->uvd
.saved_bo
)
265 memcpy(adev
->uvd
.saved_bo
, ptr
, size
);
270 int amdgpu_uvd_resume(struct amdgpu_device
*adev
)
275 if (adev
->uvd
.vcpu_bo
== NULL
)
278 size
= amdgpu_bo_size(adev
->uvd
.vcpu_bo
);
279 ptr
= adev
->uvd
.cpu_addr
;
281 if (adev
->uvd
.saved_bo
!= NULL
) {
282 memcpy(ptr
, adev
->uvd
.saved_bo
, size
);
283 kfree(adev
->uvd
.saved_bo
);
284 adev
->uvd
.saved_bo
= NULL
;
286 const struct common_firmware_header
*hdr
;
289 hdr
= (const struct common_firmware_header
*)adev
->uvd
.fw
->data
;
290 offset
= le32_to_cpu(hdr
->ucode_array_offset_bytes
);
291 memcpy(adev
->uvd
.cpu_addr
, (adev
->uvd
.fw
->data
) + offset
,
292 (adev
->uvd
.fw
->size
) - offset
);
293 size
-= le32_to_cpu(hdr
->ucode_size_bytes
);
294 ptr
+= le32_to_cpu(hdr
->ucode_size_bytes
);
295 memset(ptr
, 0, size
);
301 void amdgpu_uvd_free_handles(struct amdgpu_device
*adev
, struct drm_file
*filp
)
303 struct amdgpu_ring
*ring
= &adev
->uvd
.ring
;
306 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
) {
307 uint32_t handle
= atomic_read(&adev
->uvd
.handles
[i
]);
308 if (handle
!= 0 && adev
->uvd
.filp
[i
] == filp
) {
311 amdgpu_uvd_note_usage(adev
);
313 r
= amdgpu_uvd_get_destroy_msg(ring
, handle
,
316 DRM_ERROR("Error destroying UVD (%d)!\n", r
);
320 fence_wait(fence
, false);
323 adev
->uvd
.filp
[i
] = NULL
;
324 atomic_set(&adev
->uvd
.handles
[i
], 0);
329 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo
*rbo
)
332 for (i
= 0; i
< rbo
->placement
.num_placement
; ++i
) {
333 rbo
->placements
[i
].fpfn
= 0 >> PAGE_SHIFT
;
334 rbo
->placements
[i
].lpfn
= (256 * 1024 * 1024) >> PAGE_SHIFT
;
339 * amdgpu_uvd_cs_pass1 - first parsing round
341 * @ctx: UVD parser context
343 * Make sure UVD message and feedback buffers are in VRAM and
344 * nobody is violating an 256MB boundary.
346 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx
*ctx
)
348 struct amdgpu_bo_va_mapping
*mapping
;
349 struct amdgpu_bo
*bo
;
350 uint32_t cmd
, lo
, hi
;
354 lo
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
);
355 hi
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
);
356 addr
= ((uint64_t)lo
) | (((uint64_t)hi
) << 32);
358 mapping
= amdgpu_cs_find_mapping(ctx
->parser
, addr
, &bo
);
359 if (mapping
== NULL
) {
360 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr
);
364 if (!ctx
->parser
->adev
->uvd
.address_64_bit
) {
365 /* check if it's a message or feedback command */
366 cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
) >> 1;
367 if (cmd
== 0x0 || cmd
== 0x3) {
368 /* yes, force it into VRAM */
369 uint32_t domain
= AMDGPU_GEM_DOMAIN_VRAM
;
370 amdgpu_ttm_placement_from_domain(bo
, domain
);
372 amdgpu_uvd_force_into_uvd_segment(bo
);
374 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
381 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
383 * @msg: pointer to message structure
384 * @buf_sizes: returned buffer sizes
386 * Peek into the decode message and calculate the necessary buffer sizes.
388 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg
, unsigned buf_sizes
[])
390 unsigned stream_type
= msg
[4];
391 unsigned width
= msg
[6];
392 unsigned height
= msg
[7];
393 unsigned dpb_size
= msg
[9];
394 unsigned pitch
= msg
[28];
395 unsigned level
= msg
[57];
397 unsigned width_in_mb
= width
/ 16;
398 unsigned height_in_mb
= ALIGN(height
/ 16, 2);
399 unsigned fs_in_mb
= width_in_mb
* height_in_mb
;
401 unsigned image_size
, tmp
, min_dpb_size
, num_dpb_buffer
;
402 unsigned min_ctx_size
= 0;
404 image_size
= width
* height
;
405 image_size
+= image_size
/ 2;
406 image_size
= ALIGN(image_size
, 1024);
408 switch (stream_type
) {
410 case 7: /* H264 Perf */
413 num_dpb_buffer
= 8100 / fs_in_mb
;
416 num_dpb_buffer
= 18000 / fs_in_mb
;
419 num_dpb_buffer
= 20480 / fs_in_mb
;
422 num_dpb_buffer
= 32768 / fs_in_mb
;
425 num_dpb_buffer
= 34816 / fs_in_mb
;
428 num_dpb_buffer
= 110400 / fs_in_mb
;
431 num_dpb_buffer
= 184320 / fs_in_mb
;
434 num_dpb_buffer
= 184320 / fs_in_mb
;
438 if (num_dpb_buffer
> 17)
441 /* reference picture buffer */
442 min_dpb_size
= image_size
* num_dpb_buffer
;
444 /* macroblock context buffer */
445 min_dpb_size
+= width_in_mb
* height_in_mb
* num_dpb_buffer
* 192;
447 /* IT surface buffer */
448 min_dpb_size
+= width_in_mb
* height_in_mb
* 32;
453 /* reference picture buffer */
454 min_dpb_size
= image_size
* 3;
457 min_dpb_size
+= width_in_mb
* height_in_mb
* 128;
459 /* IT surface buffer */
460 min_dpb_size
+= width_in_mb
* 64;
462 /* DB surface buffer */
463 min_dpb_size
+= width_in_mb
* 128;
466 tmp
= max(width_in_mb
, height_in_mb
);
467 min_dpb_size
+= ALIGN(tmp
* 7 * 16, 64);
472 /* reference picture buffer */
473 min_dpb_size
= image_size
* 3;
478 /* reference picture buffer */
479 min_dpb_size
= image_size
* 3;
482 min_dpb_size
+= width_in_mb
* height_in_mb
* 64;
484 /* IT surface buffer */
485 min_dpb_size
+= ALIGN(width_in_mb
* height_in_mb
* 32, 64);
489 image_size
= (ALIGN(width
, 16) * ALIGN(height
, 16) * 3) / 2;
490 image_size
= ALIGN(image_size
, 256);
492 num_dpb_buffer
= (le32_to_cpu(msg
[59]) & 0xff) + 2;
493 min_dpb_size
= image_size
* num_dpb_buffer
;
494 min_ctx_size
= ((width
+ 255) / 16) * ((height
+ 255) / 16)
495 * 16 * num_dpb_buffer
+ 52 * 1024;
499 DRM_ERROR("UVD codec not handled %d!\n", stream_type
);
504 DRM_ERROR("Invalid UVD decoding target pitch!\n");
508 if (dpb_size
< min_dpb_size
) {
509 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
510 dpb_size
, min_dpb_size
);
514 buf_sizes
[0x1] = dpb_size
;
515 buf_sizes
[0x2] = image_size
;
516 buf_sizes
[0x4] = min_ctx_size
;
521 * amdgpu_uvd_cs_msg - handle UVD message
523 * @ctx: UVD parser context
524 * @bo: buffer object containing the message
525 * @offset: offset into the buffer object
527 * Peek into the UVD message and extract the session id.
528 * Make sure that we don't open up to many sessions.
530 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx
*ctx
,
531 struct amdgpu_bo
*bo
, unsigned offset
)
533 struct amdgpu_device
*adev
= ctx
->parser
->adev
;
534 int32_t *msg
, msg_type
, handle
;
540 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
544 r
= amdgpu_bo_kmap(bo
, &ptr
);
546 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r
);
556 DRM_ERROR("Invalid UVD handle!\n");
562 /* it's a create msg, calc image size (width * height) */
563 amdgpu_bo_kunmap(bo
);
565 /* try to alloc a new handle */
566 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
) {
567 if (atomic_read(&adev
->uvd
.handles
[i
]) == handle
) {
568 DRM_ERROR("Handle 0x%x already in use!\n", handle
);
572 if (!atomic_cmpxchg(&adev
->uvd
.handles
[i
], 0, handle
)) {
573 adev
->uvd
.filp
[i
] = ctx
->parser
->filp
;
578 DRM_ERROR("No more free UVD handles!\n");
582 /* it's a decode msg, calc buffer sizes */
583 r
= amdgpu_uvd_cs_msg_decode(msg
, ctx
->buf_sizes
);
584 amdgpu_bo_kunmap(bo
);
588 /* validate the handle */
589 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
) {
590 if (atomic_read(&adev
->uvd
.handles
[i
]) == handle
) {
591 if (adev
->uvd
.filp
[i
] != ctx
->parser
->filp
) {
592 DRM_ERROR("UVD handle collision detected!\n");
599 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle
);
603 /* it's a destroy msg, free the handle */
604 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
)
605 atomic_cmpxchg(&adev
->uvd
.handles
[i
], handle
, 0);
606 amdgpu_bo_kunmap(bo
);
610 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type
);
618 * amdgpu_uvd_cs_pass2 - second parsing round
620 * @ctx: UVD parser context
622 * Patch buffer addresses, make sure buffer sizes are correct.
624 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx
*ctx
)
626 struct amdgpu_bo_va_mapping
*mapping
;
627 struct amdgpu_bo
*bo
;
628 uint32_t cmd
, lo
, hi
;
633 lo
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
);
634 hi
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
);
635 addr
= ((uint64_t)lo
) | (((uint64_t)hi
) << 32);
637 mapping
= amdgpu_cs_find_mapping(ctx
->parser
, addr
, &bo
);
641 start
= amdgpu_bo_gpu_offset(bo
);
643 end
= (mapping
->it
.last
+ 1 - mapping
->it
.start
);
644 end
= end
* AMDGPU_GPU_PAGE_SIZE
+ start
;
646 addr
-= ((uint64_t)mapping
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
649 amdgpu_set_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data0
,
650 lower_32_bits(start
));
651 amdgpu_set_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->data1
,
652 upper_32_bits(start
));
654 cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
) >> 1;
656 if ((end
- start
) < ctx
->buf_sizes
[cmd
]) {
657 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd
,
658 (unsigned)(end
- start
),
659 ctx
->buf_sizes
[cmd
]);
663 } else if (cmd
== 0x206) {
664 if ((end
- start
) < ctx
->buf_sizes
[4]) {
665 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd
,
666 (unsigned)(end
- start
),
670 } else if ((cmd
!= 0x100) && (cmd
!= 0x204)) {
671 DRM_ERROR("invalid UVD command %X!\n", cmd
);
675 if (!ctx
->parser
->adev
->uvd
.address_64_bit
) {
676 if ((start
>> 28) != ((end
- 1) >> 28)) {
677 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
682 if ((cmd
== 0 || cmd
== 0x3) &&
683 (start
>> 28) != (ctx
->parser
->adev
->uvd
.gpu_addr
>> 28)) {
684 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
691 ctx
->has_msg_cmd
= true;
692 r
= amdgpu_uvd_cs_msg(ctx
, bo
, addr
);
695 } else if (!ctx
->has_msg_cmd
) {
696 DRM_ERROR("Message needed before other commands are send!\n");
704 * amdgpu_uvd_cs_reg - parse register writes
706 * @ctx: UVD parser context
707 * @cb: callback function
709 * Parse the register writes, call cb on each complete command.
711 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx
*ctx
,
712 int (*cb
)(struct amdgpu_uvd_cs_ctx
*ctx
))
714 struct amdgpu_ib
*ib
= &ctx
->parser
->job
->ibs
[ctx
->ib_idx
];
718 for (i
= 0; i
<= ctx
->count
; ++i
) {
719 unsigned reg
= ctx
->reg
+ i
;
721 if (ctx
->idx
>= ib
->length_dw
) {
722 DRM_ERROR("Register command after end of CS!\n");
727 case mmUVD_GPCOM_VCPU_DATA0
:
728 ctx
->data0
= ctx
->idx
;
730 case mmUVD_GPCOM_VCPU_DATA1
:
731 ctx
->data1
= ctx
->idx
;
733 case mmUVD_GPCOM_VCPU_CMD
:
738 case mmUVD_ENGINE_CNTL
:
741 DRM_ERROR("Invalid reg 0x%X!\n", reg
);
750 * amdgpu_uvd_cs_packets - parse UVD packets
752 * @ctx: UVD parser context
753 * @cb: callback function
755 * Parse the command stream packets.
757 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx
*ctx
,
758 int (*cb
)(struct amdgpu_uvd_cs_ctx
*ctx
))
760 struct amdgpu_ib
*ib
= &ctx
->parser
->job
->ibs
[ctx
->ib_idx
];
763 for (ctx
->idx
= 0 ; ctx
->idx
< ib
->length_dw
; ) {
764 uint32_t cmd
= amdgpu_get_ib_value(ctx
->parser
, ctx
->ib_idx
, ctx
->idx
);
765 unsigned type
= CP_PACKET_GET_TYPE(cmd
);
768 ctx
->reg
= CP_PACKET0_GET_REG(cmd
);
769 ctx
->count
= CP_PACKET_GET_COUNT(cmd
);
770 r
= amdgpu_uvd_cs_reg(ctx
, cb
);
778 DRM_ERROR("Unknown packet type %d !\n", type
);
786 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
788 * @parser: Command submission parser context
790 * Parse the command stream, patch in addresses as necessary.
792 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser
*parser
, uint32_t ib_idx
)
794 struct amdgpu_uvd_cs_ctx ctx
= {};
795 unsigned buf_sizes
[] = {
797 [0x00000001] = 0xFFFFFFFF,
798 [0x00000002] = 0xFFFFFFFF,
800 [0x00000004] = 0xFFFFFFFF,
802 struct amdgpu_ib
*ib
= &parser
->job
->ibs
[ib_idx
];
805 if (ib
->length_dw
% 16) {
806 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
812 ctx
.buf_sizes
= buf_sizes
;
815 /* first round, make sure the buffers are actually in the UVD segment */
816 r
= amdgpu_uvd_cs_packets(&ctx
, amdgpu_uvd_cs_pass1
);
820 /* second round, patch buffer addresses into the command stream */
821 r
= amdgpu_uvd_cs_packets(&ctx
, amdgpu_uvd_cs_pass2
);
825 if (!ctx
.has_msg_cmd
) {
826 DRM_ERROR("UVD-IBs need a msg command!\n");
830 amdgpu_uvd_note_usage(ctx
.parser
->adev
);
835 static int amdgpu_uvd_send_msg(struct amdgpu_ring
*ring
, struct amdgpu_bo
*bo
,
836 bool direct
, struct fence
**fence
)
838 struct ttm_validate_buffer tv
;
839 struct ww_acquire_ctx ticket
;
840 struct list_head head
;
841 struct amdgpu_job
*job
;
842 struct amdgpu_ib
*ib
;
843 struct fence
*f
= NULL
;
844 struct amdgpu_device
*adev
= ring
->adev
;
848 memset(&tv
, 0, sizeof(tv
));
851 INIT_LIST_HEAD(&head
);
852 list_add(&tv
.head
, &head
);
854 r
= ttm_eu_reserve_buffers(&ticket
, &head
, true, NULL
);
858 if (!bo
->adev
->uvd
.address_64_bit
) {
859 amdgpu_ttm_placement_from_domain(bo
, AMDGPU_GEM_DOMAIN_VRAM
);
860 amdgpu_uvd_force_into_uvd_segment(bo
);
863 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
867 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
872 addr
= amdgpu_bo_gpu_offset(bo
);
873 ib
->ptr
[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0
, 0);
875 ib
->ptr
[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1
, 0);
876 ib
->ptr
[3] = addr
>> 32;
877 ib
->ptr
[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD
, 0);
879 for (i
= 6; i
< 16; ++i
)
880 ib
->ptr
[i
] = PACKET2(0);
884 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, &f
);
889 amdgpu_job_free(job
);
891 r
= amdgpu_job_submit(job
, ring
, &adev
->uvd
.entity
,
892 AMDGPU_FENCE_OWNER_UNDEFINED
, &f
);
897 ttm_eu_fence_buffer_objects(&ticket
, &head
, f
);
900 *fence
= fence_get(f
);
901 amdgpu_bo_unref(&bo
);
907 amdgpu_job_free(job
);
910 ttm_eu_backoff_reservation(&ticket
, &head
);
914 /* multiple fence commands without any stream commands in between can
915 crash the vcpu so just try to emmit a dummy create/destroy msg to
917 int amdgpu_uvd_get_create_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
918 struct fence
**fence
)
920 struct amdgpu_device
*adev
= ring
->adev
;
921 struct amdgpu_bo
*bo
;
925 r
= amdgpu_bo_create(adev
, 1024, PAGE_SIZE
, true,
926 AMDGPU_GEM_DOMAIN_VRAM
,
927 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
932 r
= amdgpu_bo_reserve(bo
, false);
934 amdgpu_bo_unref(&bo
);
938 r
= amdgpu_bo_kmap(bo
, (void **)&msg
);
940 amdgpu_bo_unreserve(bo
);
941 amdgpu_bo_unref(&bo
);
945 /* stitch together an UVD create msg */
946 msg
[0] = cpu_to_le32(0x00000de4);
947 msg
[1] = cpu_to_le32(0x00000000);
948 msg
[2] = cpu_to_le32(handle
);
949 msg
[3] = cpu_to_le32(0x00000000);
950 msg
[4] = cpu_to_le32(0x00000000);
951 msg
[5] = cpu_to_le32(0x00000000);
952 msg
[6] = cpu_to_le32(0x00000000);
953 msg
[7] = cpu_to_le32(0x00000780);
954 msg
[8] = cpu_to_le32(0x00000440);
955 msg
[9] = cpu_to_le32(0x00000000);
956 msg
[10] = cpu_to_le32(0x01b37000);
957 for (i
= 11; i
< 1024; ++i
)
958 msg
[i
] = cpu_to_le32(0x0);
960 amdgpu_bo_kunmap(bo
);
961 amdgpu_bo_unreserve(bo
);
963 return amdgpu_uvd_send_msg(ring
, bo
, true, fence
);
966 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
967 bool direct
, struct fence
**fence
)
969 struct amdgpu_device
*adev
= ring
->adev
;
970 struct amdgpu_bo
*bo
;
974 r
= amdgpu_bo_create(adev
, 1024, PAGE_SIZE
, true,
975 AMDGPU_GEM_DOMAIN_VRAM
,
976 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
981 r
= amdgpu_bo_reserve(bo
, false);
983 amdgpu_bo_unref(&bo
);
987 r
= amdgpu_bo_kmap(bo
, (void **)&msg
);
989 amdgpu_bo_unreserve(bo
);
990 amdgpu_bo_unref(&bo
);
994 /* stitch together an UVD destroy msg */
995 msg
[0] = cpu_to_le32(0x00000de4);
996 msg
[1] = cpu_to_le32(0x00000002);
997 msg
[2] = cpu_to_le32(handle
);
998 msg
[3] = cpu_to_le32(0x00000000);
999 for (i
= 4; i
< 1024; ++i
)
1000 msg
[i
] = cpu_to_le32(0x0);
1002 amdgpu_bo_kunmap(bo
);
1003 amdgpu_bo_unreserve(bo
);
1005 return amdgpu_uvd_send_msg(ring
, bo
, direct
, fence
);
1008 static void amdgpu_uvd_idle_work_handler(struct work_struct
*work
)
1010 struct amdgpu_device
*adev
=
1011 container_of(work
, struct amdgpu_device
, uvd
.idle_work
.work
);
1012 unsigned i
, fences
, handles
= 0;
1014 fences
= amdgpu_fence_count_emitted(&adev
->uvd
.ring
);
1016 for (i
= 0; i
< AMDGPU_MAX_UVD_HANDLES
; ++i
)
1017 if (atomic_read(&adev
->uvd
.handles
[i
]))
1020 if (fences
== 0 && handles
== 0) {
1021 if (adev
->pm
.dpm_enabled
) {
1022 amdgpu_dpm_enable_uvd(adev
, false);
1024 amdgpu_asic_set_uvd_clocks(adev
, 0, 0);
1027 schedule_delayed_work(&adev
->uvd
.idle_work
,
1028 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS
));
1032 static void amdgpu_uvd_note_usage(struct amdgpu_device
*adev
)
1034 bool set_clocks
= !cancel_delayed_work_sync(&adev
->uvd
.idle_work
);
1035 set_clocks
&= schedule_delayed_work(&adev
->uvd
.idle_work
,
1036 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS
));
1039 if (adev
->pm
.dpm_enabled
) {
1040 amdgpu_dpm_enable_uvd(adev
, true);
1042 amdgpu_asic_set_uvd_clocks(adev
, 53300, 40000);