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8d035b65d967b1b5a8337d17116809827206f423
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_uvd.c
1 /*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <drm/drmP.h>
34 #include <drm/drm.h>
35
36 #include "amdgpu.h"
37 #include "amdgpu_pm.h"
38 #include "amdgpu_uvd.h"
39 #include "cikd.h"
40 #include "uvd/uvd_4_2_d.h"
41
42 /* 1 second timeout */
43 #define UVD_IDLE_TIMEOUT_MS 1000
44
45 /* Firmware Names */
46 #ifdef CONFIG_DRM_AMDGPU_CIK
47 #define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48 #define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49 #define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50 #define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51 #define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
52 #endif
53 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
55 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
56 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
57
58 /**
59 * amdgpu_uvd_cs_ctx - Command submission parser context
60 *
61 * Used for emulating virtual memory support on UVD 4.2.
62 */
63 struct amdgpu_uvd_cs_ctx {
64 struct amdgpu_cs_parser *parser;
65 unsigned reg, count;
66 unsigned data0, data1;
67 unsigned idx;
68 unsigned ib_idx;
69
70 /* does the IB has a msg command */
71 bool has_msg_cmd;
72
73 /* minimum buffer sizes */
74 unsigned *buf_sizes;
75 };
76
77 #ifdef CONFIG_DRM_AMDGPU_CIK
78 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
79 MODULE_FIRMWARE(FIRMWARE_KABINI);
80 MODULE_FIRMWARE(FIRMWARE_KAVERI);
81 MODULE_FIRMWARE(FIRMWARE_HAWAII);
82 MODULE_FIRMWARE(FIRMWARE_MULLINS);
83 #endif
84 MODULE_FIRMWARE(FIRMWARE_TONGA);
85 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
86 MODULE_FIRMWARE(FIRMWARE_FIJI);
87 MODULE_FIRMWARE(FIRMWARE_STONEY);
88
89 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
90 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
91
92 int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
93 {
94 struct amdgpu_ring *ring;
95 struct amd_sched_rq *rq;
96 unsigned long bo_size;
97 const char *fw_name;
98 const struct common_firmware_header *hdr;
99 unsigned version_major, version_minor, family_id;
100 int i, r;
101
102 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
103
104 switch (adev->asic_type) {
105 #ifdef CONFIG_DRM_AMDGPU_CIK
106 case CHIP_BONAIRE:
107 fw_name = FIRMWARE_BONAIRE;
108 break;
109 case CHIP_KABINI:
110 fw_name = FIRMWARE_KABINI;
111 break;
112 case CHIP_KAVERI:
113 fw_name = FIRMWARE_KAVERI;
114 break;
115 case CHIP_HAWAII:
116 fw_name = FIRMWARE_HAWAII;
117 break;
118 case CHIP_MULLINS:
119 fw_name = FIRMWARE_MULLINS;
120 break;
121 #endif
122 case CHIP_TONGA:
123 fw_name = FIRMWARE_TONGA;
124 break;
125 case CHIP_FIJI:
126 fw_name = FIRMWARE_FIJI;
127 break;
128 case CHIP_CARRIZO:
129 fw_name = FIRMWARE_CARRIZO;
130 break;
131 case CHIP_STONEY:
132 fw_name = FIRMWARE_STONEY;
133 break;
134 default:
135 return -EINVAL;
136 }
137
138 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
139 if (r) {
140 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
141 fw_name);
142 return r;
143 }
144
145 r = amdgpu_ucode_validate(adev->uvd.fw);
146 if (r) {
147 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
148 fw_name);
149 release_firmware(adev->uvd.fw);
150 adev->uvd.fw = NULL;
151 return r;
152 }
153
154 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
155 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
156 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
157 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
159 version_major, version_minor, family_id);
160
161 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
162 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
163 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
164 AMDGPU_GEM_DOMAIN_VRAM,
165 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
166 NULL, NULL, &adev->uvd.vcpu_bo);
167 if (r) {
168 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
169 return r;
170 }
171
172 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
173 if (r) {
174 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
175 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
176 return r;
177 }
178
179 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
180 &adev->uvd.gpu_addr);
181 if (r) {
182 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
183 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
184 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
185 return r;
186 }
187
188 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
189 if (r) {
190 dev_err(adev->dev, "(%d) UVD map failed\n", r);
191 return r;
192 }
193
194 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
195
196 ring = &adev->uvd.ring;
197 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
198 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
199 rq, amdgpu_sched_jobs);
200 if (r != 0) {
201 DRM_ERROR("Failed setting up UVD run queue.\n");
202 return r;
203 }
204
205 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
206 atomic_set(&adev->uvd.handles[i], 0);
207 adev->uvd.filp[i] = NULL;
208 }
209
210 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
211 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
212 adev->uvd.address_64_bit = true;
213
214 return 0;
215 }
216
217 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
218 {
219 int r;
220
221 if (adev->uvd.vcpu_bo == NULL)
222 return 0;
223
224 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
225
226 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
227 if (!r) {
228 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
229 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
230 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
231 }
232
233 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
234
235 amdgpu_ring_fini(&adev->uvd.ring);
236
237 release_firmware(adev->uvd.fw);
238
239 return 0;
240 }
241
242 int amdgpu_uvd_suspend(struct amdgpu_device *adev)
243 {
244 unsigned size;
245 void *ptr;
246 int i;
247
248 if (adev->uvd.vcpu_bo == NULL)
249 return 0;
250
251 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
252 if (atomic_read(&adev->uvd.handles[i]))
253 break;
254
255 if (i == AMDGPU_MAX_UVD_HANDLES)
256 return 0;
257
258 cancel_delayed_work_sync(&adev->uvd.idle_work);
259
260 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
261 ptr = adev->uvd.cpu_addr;
262
263 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
264 if (!adev->uvd.saved_bo)
265 return -ENOMEM;
266
267 memcpy(adev->uvd.saved_bo, ptr, size);
268
269 return 0;
270 }
271
272 int amdgpu_uvd_resume(struct amdgpu_device *adev)
273 {
274 unsigned size;
275 void *ptr;
276
277 if (adev->uvd.vcpu_bo == NULL)
278 return -EINVAL;
279
280 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
281 ptr = adev->uvd.cpu_addr;
282
283 if (adev->uvd.saved_bo != NULL) {
284 memcpy(ptr, adev->uvd.saved_bo, size);
285 kfree(adev->uvd.saved_bo);
286 adev->uvd.saved_bo = NULL;
287 } else {
288 const struct common_firmware_header *hdr;
289 unsigned offset;
290
291 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
292 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
293 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
294 (adev->uvd.fw->size) - offset);
295 size -= le32_to_cpu(hdr->ucode_size_bytes);
296 ptr += le32_to_cpu(hdr->ucode_size_bytes);
297 memset(ptr, 0, size);
298 }
299
300 return 0;
301 }
302
303 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
304 {
305 struct amdgpu_ring *ring = &adev->uvd.ring;
306 int i, r;
307
308 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
309 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
310 if (handle != 0 && adev->uvd.filp[i] == filp) {
311 struct fence *fence;
312
313 amdgpu_uvd_note_usage(adev);
314
315 r = amdgpu_uvd_get_destroy_msg(ring, handle,
316 false, &fence);
317 if (r) {
318 DRM_ERROR("Error destroying UVD (%d)!\n", r);
319 continue;
320 }
321
322 fence_wait(fence, false);
323 fence_put(fence);
324
325 adev->uvd.filp[i] = NULL;
326 atomic_set(&adev->uvd.handles[i], 0);
327 }
328 }
329 }
330
331 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
332 {
333 int i;
334 for (i = 0; i < rbo->placement.num_placement; ++i) {
335 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
336 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
337 }
338 }
339
340 /**
341 * amdgpu_uvd_cs_pass1 - first parsing round
342 *
343 * @ctx: UVD parser context
344 *
345 * Make sure UVD message and feedback buffers are in VRAM and
346 * nobody is violating an 256MB boundary.
347 */
348 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
349 {
350 struct amdgpu_bo_va_mapping *mapping;
351 struct amdgpu_bo *bo;
352 uint32_t cmd, lo, hi;
353 uint64_t addr;
354 int r = 0;
355
356 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
357 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
358 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
359
360 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
361 if (mapping == NULL) {
362 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
363 return -EINVAL;
364 }
365
366 if (!ctx->parser->adev->uvd.address_64_bit) {
367 /* check if it's a message or feedback command */
368 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
369 if (cmd == 0x0 || cmd == 0x3) {
370 /* yes, force it into VRAM */
371 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
372 amdgpu_ttm_placement_from_domain(bo, domain);
373 }
374 amdgpu_uvd_force_into_uvd_segment(bo);
375
376 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
377 }
378
379 return r;
380 }
381
382 /**
383 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
384 *
385 * @msg: pointer to message structure
386 * @buf_sizes: returned buffer sizes
387 *
388 * Peek into the decode message and calculate the necessary buffer sizes.
389 */
390 static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
391 {
392 unsigned stream_type = msg[4];
393 unsigned width = msg[6];
394 unsigned height = msg[7];
395 unsigned dpb_size = msg[9];
396 unsigned pitch = msg[28];
397 unsigned level = msg[57];
398
399 unsigned width_in_mb = width / 16;
400 unsigned height_in_mb = ALIGN(height / 16, 2);
401 unsigned fs_in_mb = width_in_mb * height_in_mb;
402
403 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
404 unsigned min_ctx_size = 0;
405
406 image_size = width * height;
407 image_size += image_size / 2;
408 image_size = ALIGN(image_size, 1024);
409
410 switch (stream_type) {
411 case 0: /* H264 */
412 case 7: /* H264 Perf */
413 switch(level) {
414 case 30:
415 num_dpb_buffer = 8100 / fs_in_mb;
416 break;
417 case 31:
418 num_dpb_buffer = 18000 / fs_in_mb;
419 break;
420 case 32:
421 num_dpb_buffer = 20480 / fs_in_mb;
422 break;
423 case 41:
424 num_dpb_buffer = 32768 / fs_in_mb;
425 break;
426 case 42:
427 num_dpb_buffer = 34816 / fs_in_mb;
428 break;
429 case 50:
430 num_dpb_buffer = 110400 / fs_in_mb;
431 break;
432 case 51:
433 num_dpb_buffer = 184320 / fs_in_mb;
434 break;
435 default:
436 num_dpb_buffer = 184320 / fs_in_mb;
437 break;
438 }
439 num_dpb_buffer++;
440 if (num_dpb_buffer > 17)
441 num_dpb_buffer = 17;
442
443 /* reference picture buffer */
444 min_dpb_size = image_size * num_dpb_buffer;
445
446 /* macroblock context buffer */
447 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
448
449 /* IT surface buffer */
450 min_dpb_size += width_in_mb * height_in_mb * 32;
451 break;
452
453 case 1: /* VC1 */
454
455 /* reference picture buffer */
456 min_dpb_size = image_size * 3;
457
458 /* CONTEXT_BUFFER */
459 min_dpb_size += width_in_mb * height_in_mb * 128;
460
461 /* IT surface buffer */
462 min_dpb_size += width_in_mb * 64;
463
464 /* DB surface buffer */
465 min_dpb_size += width_in_mb * 128;
466
467 /* BP */
468 tmp = max(width_in_mb, height_in_mb);
469 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
470 break;
471
472 case 3: /* MPEG2 */
473
474 /* reference picture buffer */
475 min_dpb_size = image_size * 3;
476 break;
477
478 case 4: /* MPEG4 */
479
480 /* reference picture buffer */
481 min_dpb_size = image_size * 3;
482
483 /* CM */
484 min_dpb_size += width_in_mb * height_in_mb * 64;
485
486 /* IT surface buffer */
487 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
488 break;
489
490 case 16: /* H265 */
491 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
492 image_size = ALIGN(image_size, 256);
493
494 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
495 min_dpb_size = image_size * num_dpb_buffer;
496 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
497 * 16 * num_dpb_buffer + 52 * 1024;
498 break;
499
500 default:
501 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
502 return -EINVAL;
503 }
504
505 if (width > pitch) {
506 DRM_ERROR("Invalid UVD decoding target pitch!\n");
507 return -EINVAL;
508 }
509
510 if (dpb_size < min_dpb_size) {
511 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
512 dpb_size, min_dpb_size);
513 return -EINVAL;
514 }
515
516 buf_sizes[0x1] = dpb_size;
517 buf_sizes[0x2] = image_size;
518 buf_sizes[0x4] = min_ctx_size;
519 return 0;
520 }
521
522 /**
523 * amdgpu_uvd_cs_msg - handle UVD message
524 *
525 * @ctx: UVD parser context
526 * @bo: buffer object containing the message
527 * @offset: offset into the buffer object
528 *
529 * Peek into the UVD message and extract the session id.
530 * Make sure that we don't open up to many sessions.
531 */
532 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
533 struct amdgpu_bo *bo, unsigned offset)
534 {
535 struct amdgpu_device *adev = ctx->parser->adev;
536 int32_t *msg, msg_type, handle;
537 void *ptr;
538 long r;
539 int i;
540
541 if (offset & 0x3F) {
542 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
543 return -EINVAL;
544 }
545
546 r = amdgpu_bo_kmap(bo, &ptr);
547 if (r) {
548 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
549 return r;
550 }
551
552 msg = ptr + offset;
553
554 msg_type = msg[1];
555 handle = msg[2];
556
557 if (handle == 0) {
558 DRM_ERROR("Invalid UVD handle!\n");
559 return -EINVAL;
560 }
561
562 switch (msg_type) {
563 case 0:
564 /* it's a create msg, calc image size (width * height) */
565 amdgpu_bo_kunmap(bo);
566
567 /* try to alloc a new handle */
568 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
569 if (atomic_read(&adev->uvd.handles[i]) == handle) {
570 DRM_ERROR("Handle 0x%x already in use!\n", handle);
571 return -EINVAL;
572 }
573
574 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
575 adev->uvd.filp[i] = ctx->parser->filp;
576 return 0;
577 }
578 }
579
580 DRM_ERROR("No more free UVD handles!\n");
581 return -EINVAL;
582
583 case 1:
584 /* it's a decode msg, calc buffer sizes */
585 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
586 amdgpu_bo_kunmap(bo);
587 if (r)
588 return r;
589
590 /* validate the handle */
591 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
592 if (atomic_read(&adev->uvd.handles[i]) == handle) {
593 if (adev->uvd.filp[i] != ctx->parser->filp) {
594 DRM_ERROR("UVD handle collision detected!\n");
595 return -EINVAL;
596 }
597 return 0;
598 }
599 }
600
601 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
602 return -ENOENT;
603
604 case 2:
605 /* it's a destroy msg, free the handle */
606 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
607 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
608 amdgpu_bo_kunmap(bo);
609 return 0;
610
611 default:
612 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
613 return -EINVAL;
614 }
615 BUG();
616 return -EINVAL;
617 }
618
619 /**
620 * amdgpu_uvd_cs_pass2 - second parsing round
621 *
622 * @ctx: UVD parser context
623 *
624 * Patch buffer addresses, make sure buffer sizes are correct.
625 */
626 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
627 {
628 struct amdgpu_bo_va_mapping *mapping;
629 struct amdgpu_bo *bo;
630 uint32_t cmd, lo, hi;
631 uint64_t start, end;
632 uint64_t addr;
633 int r;
634
635 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
636 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
637 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
638
639 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
640 if (mapping == NULL)
641 return -EINVAL;
642
643 start = amdgpu_bo_gpu_offset(bo);
644
645 end = (mapping->it.last + 1 - mapping->it.start);
646 end = end * AMDGPU_GPU_PAGE_SIZE + start;
647
648 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
649 start += addr;
650
651 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
652 lower_32_bits(start));
653 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
654 upper_32_bits(start));
655
656 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
657 if (cmd < 0x4) {
658 if ((end - start) < ctx->buf_sizes[cmd]) {
659 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
660 (unsigned)(end - start),
661 ctx->buf_sizes[cmd]);
662 return -EINVAL;
663 }
664
665 } else if (cmd == 0x206) {
666 if ((end - start) < ctx->buf_sizes[4]) {
667 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
668 (unsigned)(end - start),
669 ctx->buf_sizes[4]);
670 return -EINVAL;
671 }
672 } else if ((cmd != 0x100) && (cmd != 0x204)) {
673 DRM_ERROR("invalid UVD command %X!\n", cmd);
674 return -EINVAL;
675 }
676
677 if (!ctx->parser->adev->uvd.address_64_bit) {
678 if ((start >> 28) != ((end - 1) >> 28)) {
679 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
680 start, end);
681 return -EINVAL;
682 }
683
684 if ((cmd == 0 || cmd == 0x3) &&
685 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
686 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
687 start, end);
688 return -EINVAL;
689 }
690 }
691
692 if (cmd == 0) {
693 ctx->has_msg_cmd = true;
694 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
695 if (r)
696 return r;
697 } else if (!ctx->has_msg_cmd) {
698 DRM_ERROR("Message needed before other commands are send!\n");
699 return -EINVAL;
700 }
701
702 return 0;
703 }
704
705 /**
706 * amdgpu_uvd_cs_reg - parse register writes
707 *
708 * @ctx: UVD parser context
709 * @cb: callback function
710 *
711 * Parse the register writes, call cb on each complete command.
712 */
713 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
714 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
715 {
716 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
717 int i, r;
718
719 ctx->idx++;
720 for (i = 0; i <= ctx->count; ++i) {
721 unsigned reg = ctx->reg + i;
722
723 if (ctx->idx >= ib->length_dw) {
724 DRM_ERROR("Register command after end of CS!\n");
725 return -EINVAL;
726 }
727
728 switch (reg) {
729 case mmUVD_GPCOM_VCPU_DATA0:
730 ctx->data0 = ctx->idx;
731 break;
732 case mmUVD_GPCOM_VCPU_DATA1:
733 ctx->data1 = ctx->idx;
734 break;
735 case mmUVD_GPCOM_VCPU_CMD:
736 r = cb(ctx);
737 if (r)
738 return r;
739 break;
740 case mmUVD_ENGINE_CNTL:
741 break;
742 default:
743 DRM_ERROR("Invalid reg 0x%X!\n", reg);
744 return -EINVAL;
745 }
746 ctx->idx++;
747 }
748 return 0;
749 }
750
751 /**
752 * amdgpu_uvd_cs_packets - parse UVD packets
753 *
754 * @ctx: UVD parser context
755 * @cb: callback function
756 *
757 * Parse the command stream packets.
758 */
759 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
760 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
761 {
762 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
763 int r;
764
765 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
766 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
767 unsigned type = CP_PACKET_GET_TYPE(cmd);
768 switch (type) {
769 case PACKET_TYPE0:
770 ctx->reg = CP_PACKET0_GET_REG(cmd);
771 ctx->count = CP_PACKET_GET_COUNT(cmd);
772 r = amdgpu_uvd_cs_reg(ctx, cb);
773 if (r)
774 return r;
775 break;
776 case PACKET_TYPE2:
777 ++ctx->idx;
778 break;
779 default:
780 DRM_ERROR("Unknown packet type %d !\n", type);
781 return -EINVAL;
782 }
783 }
784 return 0;
785 }
786
787 /**
788 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
789 *
790 * @parser: Command submission parser context
791 *
792 * Parse the command stream, patch in addresses as necessary.
793 */
794 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
795 {
796 struct amdgpu_uvd_cs_ctx ctx = {};
797 unsigned buf_sizes[] = {
798 [0x00000000] = 2048,
799 [0x00000001] = 0xFFFFFFFF,
800 [0x00000002] = 0xFFFFFFFF,
801 [0x00000003] = 2048,
802 [0x00000004] = 0xFFFFFFFF,
803 };
804 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
805 int r;
806
807 if (ib->length_dw % 16) {
808 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
809 ib->length_dw);
810 return -EINVAL;
811 }
812
813 ctx.parser = parser;
814 ctx.buf_sizes = buf_sizes;
815 ctx.ib_idx = ib_idx;
816
817 /* first round, make sure the buffers are actually in the UVD segment */
818 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
819 if (r)
820 return r;
821
822 /* second round, patch buffer addresses into the command stream */
823 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
824 if (r)
825 return r;
826
827 if (!ctx.has_msg_cmd) {
828 DRM_ERROR("UVD-IBs need a msg command!\n");
829 return -EINVAL;
830 }
831
832 amdgpu_uvd_note_usage(ctx.parser->adev);
833
834 return 0;
835 }
836
837 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
838 bool direct, struct fence **fence)
839 {
840 struct ttm_validate_buffer tv;
841 struct ww_acquire_ctx ticket;
842 struct list_head head;
843 struct amdgpu_job *job;
844 struct amdgpu_ib *ib;
845 struct fence *f = NULL;
846 struct amdgpu_device *adev = ring->adev;
847 uint64_t addr;
848 int i, r;
849
850 memset(&tv, 0, sizeof(tv));
851 tv.bo = &bo->tbo;
852
853 INIT_LIST_HEAD(&head);
854 list_add(&tv.head, &head);
855
856 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
857 if (r)
858 return r;
859
860 if (!bo->adev->uvd.address_64_bit) {
861 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
862 amdgpu_uvd_force_into_uvd_segment(bo);
863 }
864
865 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
866 if (r)
867 goto err;
868
869 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
870 if (r)
871 goto err;
872
873 ib = &job->ibs[0];
874 addr = amdgpu_bo_gpu_offset(bo);
875 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
876 ib->ptr[1] = addr;
877 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
878 ib->ptr[3] = addr >> 32;
879 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
880 ib->ptr[5] = 0;
881 for (i = 6; i < 16; ++i)
882 ib->ptr[i] = PACKET2(0);
883 ib->length_dw = 16;
884
885 if (direct) {
886 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
887 job->fence = f;
888 if (r)
889 goto err_free;
890
891 amdgpu_job_free(job);
892 } else {
893 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
894 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
895 if (r)
896 goto err_free;
897 }
898
899 ttm_eu_fence_buffer_objects(&ticket, &head, f);
900
901 if (fence)
902 *fence = fence_get(f);
903 amdgpu_bo_unref(&bo);
904 fence_put(f);
905
906 return 0;
907
908 err_free:
909 amdgpu_job_free(job);
910
911 err:
912 ttm_eu_backoff_reservation(&ticket, &head);
913 return r;
914 }
915
916 /* multiple fence commands without any stream commands in between can
917 crash the vcpu so just try to emmit a dummy create/destroy msg to
918 avoid this */
919 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
920 struct fence **fence)
921 {
922 struct amdgpu_device *adev = ring->adev;
923 struct amdgpu_bo *bo;
924 uint32_t *msg;
925 int r, i;
926
927 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
928 AMDGPU_GEM_DOMAIN_VRAM,
929 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
930 NULL, NULL, &bo);
931 if (r)
932 return r;
933
934 r = amdgpu_bo_reserve(bo, false);
935 if (r) {
936 amdgpu_bo_unref(&bo);
937 return r;
938 }
939
940 r = amdgpu_bo_kmap(bo, (void **)&msg);
941 if (r) {
942 amdgpu_bo_unreserve(bo);
943 amdgpu_bo_unref(&bo);
944 return r;
945 }
946
947 /* stitch together an UVD create msg */
948 msg[0] = cpu_to_le32(0x00000de4);
949 msg[1] = cpu_to_le32(0x00000000);
950 msg[2] = cpu_to_le32(handle);
951 msg[3] = cpu_to_le32(0x00000000);
952 msg[4] = cpu_to_le32(0x00000000);
953 msg[5] = cpu_to_le32(0x00000000);
954 msg[6] = cpu_to_le32(0x00000000);
955 msg[7] = cpu_to_le32(0x00000780);
956 msg[8] = cpu_to_le32(0x00000440);
957 msg[9] = cpu_to_le32(0x00000000);
958 msg[10] = cpu_to_le32(0x01b37000);
959 for (i = 11; i < 1024; ++i)
960 msg[i] = cpu_to_le32(0x0);
961
962 amdgpu_bo_kunmap(bo);
963 amdgpu_bo_unreserve(bo);
964
965 return amdgpu_uvd_send_msg(ring, bo, true, fence);
966 }
967
968 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
969 bool direct, struct fence **fence)
970 {
971 struct amdgpu_device *adev = ring->adev;
972 struct amdgpu_bo *bo;
973 uint32_t *msg;
974 int r, i;
975
976 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
977 AMDGPU_GEM_DOMAIN_VRAM,
978 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
979 NULL, NULL, &bo);
980 if (r)
981 return r;
982
983 r = amdgpu_bo_reserve(bo, false);
984 if (r) {
985 amdgpu_bo_unref(&bo);
986 return r;
987 }
988
989 r = amdgpu_bo_kmap(bo, (void **)&msg);
990 if (r) {
991 amdgpu_bo_unreserve(bo);
992 amdgpu_bo_unref(&bo);
993 return r;
994 }
995
996 /* stitch together an UVD destroy msg */
997 msg[0] = cpu_to_le32(0x00000de4);
998 msg[1] = cpu_to_le32(0x00000002);
999 msg[2] = cpu_to_le32(handle);
1000 msg[3] = cpu_to_le32(0x00000000);
1001 for (i = 4; i < 1024; ++i)
1002 msg[i] = cpu_to_le32(0x0);
1003
1004 amdgpu_bo_kunmap(bo);
1005 amdgpu_bo_unreserve(bo);
1006
1007 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
1008 }
1009
1010 static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1011 {
1012 struct amdgpu_device *adev =
1013 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1014 unsigned i, fences, handles = 0;
1015
1016 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1017
1018 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
1019 if (atomic_read(&adev->uvd.handles[i]))
1020 ++handles;
1021
1022 if (fences == 0 && handles == 0) {
1023 if (adev->pm.dpm_enabled) {
1024 amdgpu_dpm_enable_uvd(adev, false);
1025 } else {
1026 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1027 }
1028 } else {
1029 schedule_delayed_work(&adev->uvd.idle_work,
1030 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1031 }
1032 }
1033
1034 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1035 {
1036 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1037 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1038 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1039
1040 if (set_clocks) {
1041 if (adev->pm.dpm_enabled) {
1042 amdgpu_dpm_enable_uvd(adev, true);
1043 } else {
1044 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1045 }
1046 }
1047 }
Linux kernel - Deliverables
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