2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT_MS 1000
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
47 #define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
54 #ifdef CONFIG_DRM_AMDGPU_CIK
55 MODULE_FIRMWARE(FIRMWARE_BONAIRE
);
56 MODULE_FIRMWARE(FIRMWARE_KABINI
);
57 MODULE_FIRMWARE(FIRMWARE_KAVERI
);
58 MODULE_FIRMWARE(FIRMWARE_HAWAII
);
59 MODULE_FIRMWARE(FIRMWARE_MULLINS
);
61 MODULE_FIRMWARE(FIRMWARE_TONGA
);
62 MODULE_FIRMWARE(FIRMWARE_CARRIZO
);
63 MODULE_FIRMWARE(FIRMWARE_FIJI
);
64 MODULE_FIRMWARE(FIRMWARE_STONEY
);
66 static void amdgpu_vce_idle_work_handler(struct work_struct
*work
);
69 * amdgpu_vce_init - allocate memory, load vce firmware
71 * @adev: amdgpu_device pointer
73 * First step to get VCE online, allocate memory and load the firmware
75 int amdgpu_vce_sw_init(struct amdgpu_device
*adev
, unsigned long size
)
77 struct amdgpu_ring
*ring
;
78 struct amd_sched_rq
*rq
;
80 const struct common_firmware_header
*hdr
;
81 unsigned ucode_version
, version_major
, version_minor
, binary_id
;
84 INIT_DELAYED_WORK(&adev
->vce
.idle_work
, amdgpu_vce_idle_work_handler
);
86 switch (adev
->asic_type
) {
87 #ifdef CONFIG_DRM_AMDGPU_CIK
89 fw_name
= FIRMWARE_BONAIRE
;
92 fw_name
= FIRMWARE_KAVERI
;
95 fw_name
= FIRMWARE_KABINI
;
98 fw_name
= FIRMWARE_HAWAII
;
101 fw_name
= FIRMWARE_MULLINS
;
105 fw_name
= FIRMWARE_TONGA
;
108 fw_name
= FIRMWARE_CARRIZO
;
111 fw_name
= FIRMWARE_FIJI
;
114 fw_name
= FIRMWARE_STONEY
;
121 r
= request_firmware(&adev
->vce
.fw
, fw_name
, adev
->dev
);
123 dev_err(adev
->dev
, "amdgpu_vce: Can't load firmware \"%s\"\n",
128 r
= amdgpu_ucode_validate(adev
->vce
.fw
);
130 dev_err(adev
->dev
, "amdgpu_vce: Can't validate firmware \"%s\"\n",
132 release_firmware(adev
->vce
.fw
);
137 hdr
= (const struct common_firmware_header
*)adev
->vce
.fw
->data
;
139 ucode_version
= le32_to_cpu(hdr
->ucode_version
);
140 version_major
= (ucode_version
>> 20) & 0xfff;
141 version_minor
= (ucode_version
>> 8) & 0xfff;
142 binary_id
= ucode_version
& 0xff;
143 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
144 version_major
, version_minor
, binary_id
);
145 adev
->vce
.fw_version
= ((version_major
<< 24) | (version_minor
<< 16) |
148 /* allocate firmware, stack and heap BO */
150 r
= amdgpu_bo_create(adev
, size
, PAGE_SIZE
, true,
151 AMDGPU_GEM_DOMAIN_VRAM
,
152 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
153 NULL
, NULL
, &adev
->vce
.vcpu_bo
);
155 dev_err(adev
->dev
, "(%d) failed to allocate VCE bo\n", r
);
159 r
= amdgpu_bo_reserve(adev
->vce
.vcpu_bo
, false);
161 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
162 dev_err(adev
->dev
, "(%d) failed to reserve VCE bo\n", r
);
166 r
= amdgpu_bo_pin(adev
->vce
.vcpu_bo
, AMDGPU_GEM_DOMAIN_VRAM
,
167 &adev
->vce
.gpu_addr
);
168 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
170 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
171 dev_err(adev
->dev
, "(%d) VCE bo pin failed\n", r
);
176 ring
= &adev
->vce
.ring
[0];
177 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_NORMAL
];
178 r
= amd_sched_entity_init(&ring
->sched
, &adev
->vce
.entity
,
179 rq
, amdgpu_sched_jobs
);
181 DRM_ERROR("Failed setting up VCE run queue.\n");
185 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
186 atomic_set(&adev
->vce
.handles
[i
], 0);
187 adev
->vce
.filp
[i
] = NULL
;
194 * amdgpu_vce_fini - free memory
196 * @adev: amdgpu_device pointer
198 * Last step on VCE teardown, free firmware memory
200 int amdgpu_vce_sw_fini(struct amdgpu_device
*adev
)
202 if (adev
->vce
.vcpu_bo
== NULL
)
205 amd_sched_entity_fini(&adev
->vce
.ring
[0].sched
, &adev
->vce
.entity
);
207 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
209 amdgpu_ring_fini(&adev
->vce
.ring
[0]);
210 amdgpu_ring_fini(&adev
->vce
.ring
[1]);
212 release_firmware(adev
->vce
.fw
);
218 * amdgpu_vce_suspend - unpin VCE fw memory
220 * @adev: amdgpu_device pointer
223 int amdgpu_vce_suspend(struct amdgpu_device
*adev
)
227 if (adev
->vce
.vcpu_bo
== NULL
)
230 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
231 if (atomic_read(&adev
->vce
.handles
[i
]))
234 if (i
== AMDGPU_MAX_VCE_HANDLES
)
237 /* TODO: suspending running encoding sessions isn't supported */
242 * amdgpu_vce_resume - pin VCE fw memory
244 * @adev: amdgpu_device pointer
247 int amdgpu_vce_resume(struct amdgpu_device
*adev
)
250 const struct common_firmware_header
*hdr
;
254 if (adev
->vce
.vcpu_bo
== NULL
)
257 r
= amdgpu_bo_reserve(adev
->vce
.vcpu_bo
, false);
259 dev_err(adev
->dev
, "(%d) failed to reserve VCE bo\n", r
);
263 r
= amdgpu_bo_kmap(adev
->vce
.vcpu_bo
, &cpu_addr
);
265 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
266 dev_err(adev
->dev
, "(%d) VCE map failed\n", r
);
270 hdr
= (const struct common_firmware_header
*)adev
->vce
.fw
->data
;
271 offset
= le32_to_cpu(hdr
->ucode_array_offset_bytes
);
272 memcpy(cpu_addr
, (adev
->vce
.fw
->data
) + offset
,
273 (adev
->vce
.fw
->size
) - offset
);
275 amdgpu_bo_kunmap(adev
->vce
.vcpu_bo
);
277 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
283 * amdgpu_vce_idle_work_handler - power off VCE
285 * @work: pointer to work structure
287 * power of VCE when it's not used any more
289 static void amdgpu_vce_idle_work_handler(struct work_struct
*work
)
291 struct amdgpu_device
*adev
=
292 container_of(work
, struct amdgpu_device
, vce
.idle_work
.work
);
294 if ((amdgpu_fence_count_emitted(&adev
->vce
.ring
[0]) == 0) &&
295 (amdgpu_fence_count_emitted(&adev
->vce
.ring
[1]) == 0)) {
296 if (adev
->pm
.dpm_enabled
) {
297 amdgpu_dpm_enable_vce(adev
, false);
299 amdgpu_asic_set_vce_clocks(adev
, 0, 0);
302 schedule_delayed_work(&adev
->vce
.idle_work
,
303 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS
));
308 * amdgpu_vce_note_usage - power up VCE
310 * @adev: amdgpu_device pointer
312 * Make sure VCE is powerd up when we want to use it
314 static void amdgpu_vce_note_usage(struct amdgpu_device
*adev
)
316 bool streams_changed
= false;
317 bool set_clocks
= !cancel_delayed_work_sync(&adev
->vce
.idle_work
);
318 set_clocks
&= schedule_delayed_work(&adev
->vce
.idle_work
,
319 msecs_to_jiffies(VCE_IDLE_TIMEOUT_MS
));
321 if (adev
->pm
.dpm_enabled
) {
322 /* XXX figure out if the streams changed */
323 streams_changed
= false;
326 if (set_clocks
|| streams_changed
) {
327 if (adev
->pm
.dpm_enabled
) {
328 amdgpu_dpm_enable_vce(adev
, true);
330 amdgpu_asic_set_vce_clocks(adev
, 53300, 40000);
336 * amdgpu_vce_free_handles - free still open VCE handles
338 * @adev: amdgpu_device pointer
339 * @filp: drm file pointer
341 * Close all VCE handles still open by this file pointer
343 void amdgpu_vce_free_handles(struct amdgpu_device
*adev
, struct drm_file
*filp
)
345 struct amdgpu_ring
*ring
= &adev
->vce
.ring
[0];
347 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
348 uint32_t handle
= atomic_read(&adev
->vce
.handles
[i
]);
349 if (!handle
|| adev
->vce
.filp
[i
] != filp
)
352 amdgpu_vce_note_usage(adev
);
354 r
= amdgpu_vce_get_destroy_msg(ring
, handle
, false, NULL
);
356 DRM_ERROR("Error destroying VCE handle (%d)!\n", r
);
358 adev
->vce
.filp
[i
] = NULL
;
359 atomic_set(&adev
->vce
.handles
[i
], 0);
364 * amdgpu_vce_get_create_msg - generate a VCE create msg
366 * @adev: amdgpu_device pointer
367 * @ring: ring we should submit the msg to
368 * @handle: VCE session handle to use
369 * @fence: optional fence to return
371 * Open up a stream for HW test
373 int amdgpu_vce_get_create_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
374 struct fence
**fence
)
376 const unsigned ib_size_dw
= 1024;
377 struct amdgpu_job
*job
;
378 struct amdgpu_ib
*ib
;
379 struct fence
*f
= NULL
;
383 r
= amdgpu_job_alloc_with_ib(ring
->adev
, ib_size_dw
* 4, &job
);
389 dummy
= ib
->gpu_addr
+ 1024;
391 /* stitch together an VCE create msg */
393 ib
->ptr
[ib
->length_dw
++] = 0x0000000c; /* len */
394 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* session cmd */
395 ib
->ptr
[ib
->length_dw
++] = handle
;
397 if ((ring
->adev
->vce
.fw_version
>> 24) >= 52)
398 ib
->ptr
[ib
->length_dw
++] = 0x00000040; /* len */
400 ib
->ptr
[ib
->length_dw
++] = 0x00000030; /* len */
401 ib
->ptr
[ib
->length_dw
++] = 0x01000001; /* create cmd */
402 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
403 ib
->ptr
[ib
->length_dw
++] = 0x00000042;
404 ib
->ptr
[ib
->length_dw
++] = 0x0000000a;
405 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
406 ib
->ptr
[ib
->length_dw
++] = 0x00000080;
407 ib
->ptr
[ib
->length_dw
++] = 0x00000060;
408 ib
->ptr
[ib
->length_dw
++] = 0x00000100;
409 ib
->ptr
[ib
->length_dw
++] = 0x00000100;
410 ib
->ptr
[ib
->length_dw
++] = 0x0000000c;
411 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
412 if ((ring
->adev
->vce
.fw_version
>> 24) >= 52) {
413 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
414 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
415 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
416 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
419 ib
->ptr
[ib
->length_dw
++] = 0x00000014; /* len */
420 ib
->ptr
[ib
->length_dw
++] = 0x05000005; /* feedback buffer */
421 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dummy
);
422 ib
->ptr
[ib
->length_dw
++] = dummy
;
423 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
425 for (i
= ib
->length_dw
; i
< ib_size_dw
; ++i
)
428 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, &f
);
433 amdgpu_job_free(job
);
435 *fence
= fence_get(f
);
440 amdgpu_job_free(job
);
445 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
447 * @adev: amdgpu_device pointer
448 * @ring: ring we should submit the msg to
449 * @handle: VCE session handle to use
450 * @fence: optional fence to return
452 * Close up a stream for HW test or if userspace failed to do so
454 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
455 bool direct
, struct fence
**fence
)
457 const unsigned ib_size_dw
= 1024;
458 struct amdgpu_job
*job
;
459 struct amdgpu_ib
*ib
;
460 struct fence
*f
= NULL
;
464 r
= amdgpu_job_alloc_with_ib(ring
->adev
, ib_size_dw
* 4, &job
);
469 dummy
= ib
->gpu_addr
+ 1024;
471 /* stitch together an VCE destroy msg */
473 ib
->ptr
[ib
->length_dw
++] = 0x0000000c; /* len */
474 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* session cmd */
475 ib
->ptr
[ib
->length_dw
++] = handle
;
477 ib
->ptr
[ib
->length_dw
++] = 0x00000014; /* len */
478 ib
->ptr
[ib
->length_dw
++] = 0x05000005; /* feedback buffer */
479 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dummy
);
480 ib
->ptr
[ib
->length_dw
++] = dummy
;
481 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
483 ib
->ptr
[ib
->length_dw
++] = 0x00000008; /* len */
484 ib
->ptr
[ib
->length_dw
++] = 0x02000001; /* destroy cmd */
486 for (i
= ib
->length_dw
; i
< ib_size_dw
; ++i
)
490 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, &f
);
495 amdgpu_job_free(job
);
497 r
= amdgpu_job_submit(job
, ring
, &ring
->adev
->vce
.entity
,
498 AMDGPU_FENCE_OWNER_UNDEFINED
, &f
);
504 *fence
= fence_get(f
);
509 amdgpu_job_free(job
);
514 * amdgpu_vce_cs_reloc - command submission relocation
517 * @lo: address of lower dword
518 * @hi: address of higher dword
519 * @size: minimum size
521 * Patch relocation inside command stream with real buffer address
523 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
,
524 int lo
, int hi
, unsigned size
, uint32_t index
)
526 struct amdgpu_bo_va_mapping
*mapping
;
527 struct amdgpu_bo
*bo
;
530 if (index
== 0xffffffff)
533 addr
= ((uint64_t)amdgpu_get_ib_value(p
, ib_idx
, lo
)) |
534 ((uint64_t)amdgpu_get_ib_value(p
, ib_idx
, hi
)) << 32;
535 addr
+= ((uint64_t)size
) * ((uint64_t)index
);
537 mapping
= amdgpu_cs_find_mapping(p
, addr
, &bo
);
538 if (mapping
== NULL
) {
539 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
540 addr
, lo
, hi
, size
, index
);
544 if ((addr
+ (uint64_t)size
) >
545 ((uint64_t)mapping
->it
.last
+ 1) * AMDGPU_GPU_PAGE_SIZE
) {
546 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
551 addr
-= ((uint64_t)mapping
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
552 addr
+= amdgpu_bo_gpu_offset(bo
);
553 addr
-= ((uint64_t)size
) * ((uint64_t)index
);
555 amdgpu_set_ib_value(p
, ib_idx
, lo
, lower_32_bits(addr
));
556 amdgpu_set_ib_value(p
, ib_idx
, hi
, upper_32_bits(addr
));
562 * amdgpu_vce_validate_handle - validate stream handle
565 * @handle: handle to validate
566 * @allocated: allocated a new handle?
568 * Validates the handle and return the found session index or -EINVAL
569 * we we don't have another free session index.
571 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser
*p
,
572 uint32_t handle
, bool *allocated
)
578 /* validate the handle */
579 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
580 if (atomic_read(&p
->adev
->vce
.handles
[i
]) == handle
) {
581 if (p
->adev
->vce
.filp
[i
] != p
->filp
) {
582 DRM_ERROR("VCE handle collision detected!\n");
589 /* handle not found try to alloc a new one */
590 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
591 if (!atomic_cmpxchg(&p
->adev
->vce
.handles
[i
], 0, handle
)) {
592 p
->adev
->vce
.filp
[i
] = p
->filp
;
593 p
->adev
->vce
.img_size
[i
] = 0;
599 DRM_ERROR("No more free VCE handles!\n");
604 * amdgpu_vce_cs_parse - parse and validate the command stream
609 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
)
611 struct amdgpu_ib
*ib
= &p
->job
->ibs
[ib_idx
];
612 unsigned fb_idx
= 0, bs_idx
= 0;
613 int session_idx
= -1;
614 bool destroyed
= false;
615 bool created
= false;
616 bool allocated
= false;
617 uint32_t tmp
, handle
= 0;
618 uint32_t *size
= &tmp
;
619 int i
, r
= 0, idx
= 0;
621 amdgpu_vce_note_usage(p
->adev
);
623 while (idx
< ib
->length_dw
) {
624 uint32_t len
= amdgpu_get_ib_value(p
, ib_idx
, idx
);
625 uint32_t cmd
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 1);
627 if ((len
< 8) || (len
& 3)) {
628 DRM_ERROR("invalid VCE command length (%d)!\n", len
);
634 DRM_ERROR("No other command allowed after destroy!\n");
640 case 0x00000001: // session
641 handle
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 2);
642 session_idx
= amdgpu_vce_validate_handle(p
, handle
,
646 size
= &p
->adev
->vce
.img_size
[session_idx
];
649 case 0x00000002: // task info
650 fb_idx
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 6);
651 bs_idx
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 7);
654 case 0x01000001: // create
657 DRM_ERROR("Handle already in use!\n");
662 *size
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 8) *
663 amdgpu_get_ib_value(p
, ib_idx
, idx
+ 10) *
667 case 0x04000001: // config extension
668 case 0x04000002: // pic control
669 case 0x04000005: // rate control
670 case 0x04000007: // motion estimation
671 case 0x04000008: // rdo
672 case 0x04000009: // vui
673 case 0x05000002: // auxiliary buffer
676 case 0x03000001: // encode
677 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 10, idx
+ 9,
682 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 12, idx
+ 11,
688 case 0x02000001: // destroy
692 case 0x05000001: // context buffer
693 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
699 case 0x05000004: // video bitstream buffer
700 tmp
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 4);
701 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
707 case 0x05000005: // feedback buffer
708 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
715 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd
);
720 if (session_idx
== -1) {
721 DRM_ERROR("no session command at start of IB\n");
729 if (allocated
&& !created
) {
730 DRM_ERROR("New session without create command!\n");
735 if ((!r
&& destroyed
) || (r
&& allocated
)) {
737 * IB contains a destroy msg or we have allocated an
738 * handle and got an error, anyway free the handle
740 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
741 atomic_cmpxchg(&p
->adev
->vce
.handles
[i
], handle
, 0);
748 * amdgpu_vce_ring_emit_ib - execute indirect buffer
750 * @ring: engine to use
751 * @ib: the IB to execute
754 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
756 amdgpu_ring_write(ring
, VCE_CMD_IB
);
757 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
));
758 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
759 amdgpu_ring_write(ring
, ib
->length_dw
);
763 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
765 * @ring: engine to use
769 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
772 WARN_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
774 amdgpu_ring_write(ring
, VCE_CMD_FENCE
);
775 amdgpu_ring_write(ring
, addr
);
776 amdgpu_ring_write(ring
, upper_32_bits(addr
));
777 amdgpu_ring_write(ring
, seq
);
778 amdgpu_ring_write(ring
, VCE_CMD_TRAP
);
779 amdgpu_ring_write(ring
, VCE_CMD_END
);
783 * amdgpu_vce_ring_test_ring - test if VCE ring is working
785 * @ring: the engine to test on
788 int amdgpu_vce_ring_test_ring(struct amdgpu_ring
*ring
)
790 struct amdgpu_device
*adev
= ring
->adev
;
791 uint32_t rptr
= amdgpu_ring_get_rptr(ring
);
795 r
= amdgpu_ring_alloc(ring
, 16);
797 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
801 amdgpu_ring_write(ring
, VCE_CMD_END
);
802 amdgpu_ring_commit(ring
);
804 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
805 if (amdgpu_ring_get_rptr(ring
) != rptr
)
810 if (i
< adev
->usec_timeout
) {
811 DRM_INFO("ring test on %d succeeded in %d usecs\n",
814 DRM_ERROR("amdgpu: ring %d test failed\n",
823 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
825 * @ring: the engine to test on
828 int amdgpu_vce_ring_test_ib(struct amdgpu_ring
*ring
)
830 struct fence
*fence
= NULL
;
833 /* skip vce ring1 ib test for now, since it's not reliable */
834 if (ring
== &ring
->adev
->vce
.ring
[1])
837 r
= amdgpu_vce_get_create_msg(ring
, 1, NULL
);
839 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r
);
843 r
= amdgpu_vce_get_destroy_msg(ring
, 1, true, &fence
);
845 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r
);
849 r
= fence_wait(fence
, false);
851 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
853 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);