2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Local structure. Encapsulate some VM table update parameters to reduce
55 * the number of function parameters
57 struct amdgpu_pte_update_params
{
58 /* amdgpu device we do this update for */
59 struct amdgpu_device
*adev
;
60 /* address where to copy page table entries from */
62 /* indirect buffer to fill with commands */
64 /* Function which actually does the update */
65 void (*func
)(struct amdgpu_pte_update_params
*params
, uint64_t pe
,
66 uint64_t addr
, unsigned count
, uint32_t incr
,
68 /* indicate update pt or its shadow */
73 * amdgpu_vm_num_pde - return the number of page directory entries
75 * @adev: amdgpu_device pointer
77 * Calculate the number of page directory entries.
79 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
81 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
85 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
87 * @adev: amdgpu_device pointer
89 * Calculate the size of the page directory in bytes.
91 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
93 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
97 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
99 * @vm: vm providing the BOs
100 * @validated: head of validation list
101 * @entry: entry to add
103 * Add the page directory to the list of BOs to
104 * validate for command submission.
106 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
107 struct list_head
*validated
,
108 struct amdgpu_bo_list_entry
*entry
)
110 entry
->robj
= vm
->page_directory
;
112 entry
->tv
.bo
= &vm
->page_directory
->tbo
;
113 entry
->tv
.shared
= true;
114 entry
->user_pages
= NULL
;
115 list_add(&entry
->tv
.head
, validated
);
119 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
121 * @adev: amdgpu device pointer
122 * @vm: vm providing the BOs
123 * @duplicates: head of duplicates list
125 * Add the page directory to the BO duplicates list
126 * for command submission.
128 void amdgpu_vm_get_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
129 struct list_head
*duplicates
)
131 uint64_t num_evictions
;
134 /* We only need to validate the page tables
135 * if they aren't already valid.
137 num_evictions
= atomic64_read(&adev
->num_evictions
);
138 if (num_evictions
== vm
->last_eviction_counter
)
141 /* add the vm page table to the list */
142 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
143 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
148 list_add(&entry
->tv
.head
, duplicates
);
154 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
156 * @adev: amdgpu device instance
157 * @vm: vm providing the BOs
159 * Move the PT BOs to the tail of the LRU.
161 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
162 struct amdgpu_vm
*vm
)
164 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
167 spin_lock(&glob
->lru_lock
);
168 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
169 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
174 ttm_bo_move_to_lru_tail(&entry
->robj
->tbo
);
176 spin_unlock(&glob
->lru_lock
);
179 static bool amdgpu_vm_is_gpu_reset(struct amdgpu_device
*adev
,
180 struct amdgpu_vm_id
*id
)
182 return id
->current_gpu_reset_count
!=
183 atomic_read(&adev
->gpu_reset_counter
) ? true : false;
187 * amdgpu_vm_grab_id - allocate the next free VMID
189 * @vm: vm to allocate id for
190 * @ring: ring we want to submit job to
191 * @sync: sync object where we add dependencies
192 * @fence: fence protecting ID from reuse
194 * Allocate an id for the vm, adding fences to the sync obj as necessary.
196 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
197 struct amdgpu_sync
*sync
, struct fence
*fence
,
198 struct amdgpu_job
*job
)
200 struct amdgpu_device
*adev
= ring
->adev
;
201 uint64_t fence_context
= adev
->fence_context
+ ring
->idx
;
202 struct fence
*updates
= sync
->last_vm_update
;
203 struct amdgpu_vm_id
*id
, *idle
;
204 struct fence
**fences
;
208 fences
= kmalloc_array(sizeof(void *), adev
->vm_manager
.num_ids
,
213 mutex_lock(&adev
->vm_manager
.lock
);
215 /* Check if we have an idle VMID */
217 list_for_each_entry(idle
, &adev
->vm_manager
.ids_lru
, list
) {
218 fences
[i
] = amdgpu_sync_peek_fence(&idle
->active
, ring
);
224 /* If we can't find a idle VMID to use, wait till one becomes available */
225 if (&idle
->list
== &adev
->vm_manager
.ids_lru
) {
226 u64 fence_context
= adev
->vm_manager
.fence_context
+ ring
->idx
;
227 unsigned seqno
= ++adev
->vm_manager
.seqno
[ring
->idx
];
228 struct fence_array
*array
;
231 for (j
= 0; j
< i
; ++j
)
232 fence_get(fences
[j
]);
234 array
= fence_array_create(i
, fences
, fence_context
,
237 for (j
= 0; j
< i
; ++j
)
238 fence_put(fences
[j
]);
245 r
= amdgpu_sync_fence(ring
->adev
, sync
, &array
->base
);
246 fence_put(&array
->base
);
250 mutex_unlock(&adev
->vm_manager
.lock
);
256 job
->vm_needs_flush
= true;
257 /* Check if we can use a VMID already assigned to this VM */
260 struct fence
*flushed
;
263 if (i
== AMDGPU_MAX_RINGS
)
266 /* Check all the prerequisites to using this VMID */
269 if (amdgpu_vm_is_gpu_reset(adev
, id
))
272 if (atomic64_read(&id
->owner
) != vm
->client_id
)
275 if (job
->vm_pd_addr
!= id
->pd_gpu_addr
)
281 if (id
->last_flush
->context
!= fence_context
&&
282 !fence_is_signaled(id
->last_flush
))
285 flushed
= id
->flushed_updates
;
287 (!flushed
|| fence_is_later(updates
, flushed
)))
290 /* Good we can use this VMID. Remember this submission as
293 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
297 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
298 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
299 vm
->ids
[ring
->idx
] = id
;
301 job
->vm_id
= id
- adev
->vm_manager
.ids
;
302 job
->vm_needs_flush
= false;
303 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, job
);
305 mutex_unlock(&adev
->vm_manager
.lock
);
308 } while (i
!= ring
->idx
);
310 /* Still no ID to use? Then use the idle one found earlier */
313 /* Remember this submission as user of the VMID */
314 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
318 fence_put(id
->first
);
319 id
->first
= fence_get(fence
);
321 fence_put(id
->last_flush
);
322 id
->last_flush
= NULL
;
324 fence_put(id
->flushed_updates
);
325 id
->flushed_updates
= fence_get(updates
);
327 id
->pd_gpu_addr
= job
->vm_pd_addr
;
328 id
->current_gpu_reset_count
= atomic_read(&adev
->gpu_reset_counter
);
329 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
330 atomic64_set(&id
->owner
, vm
->client_id
);
331 vm
->ids
[ring
->idx
] = id
;
333 job
->vm_id
= id
- adev
->vm_manager
.ids
;
334 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, job
);
337 mutex_unlock(&adev
->vm_manager
.lock
);
341 static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring
*ring
)
343 struct amdgpu_device
*adev
= ring
->adev
;
344 const struct amdgpu_ip_block_version
*ip_block
;
346 if (ring
->type
!= AMDGPU_RING_TYPE_COMPUTE
)
347 /* only compute rings */
350 ip_block
= amdgpu_get_ip_block(adev
, AMD_IP_BLOCK_TYPE_GFX
);
354 if (ip_block
->major
<= 7) {
355 /* gfx7 has no workaround */
357 } else if (ip_block
->major
== 8) {
358 if (adev
->gfx
.mec_fw_version
>= 673)
359 /* gfx8 is fixed in MEC firmware 673 */
368 * amdgpu_vm_flush - hardware flush the vm
370 * @ring: ring to use for flush
371 * @vm_id: vmid number to use
372 * @pd_addr: address of the page directory
374 * Emit a VM flush when it is necessary.
376 int amdgpu_vm_flush(struct amdgpu_ring
*ring
, struct amdgpu_job
*job
)
378 struct amdgpu_device
*adev
= ring
->adev
;
379 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[job
->vm_id
];
380 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
381 id
->gds_base
!= job
->gds_base
||
382 id
->gds_size
!= job
->gds_size
||
383 id
->gws_base
!= job
->gws_base
||
384 id
->gws_size
!= job
->gws_size
||
385 id
->oa_base
!= job
->oa_base
||
386 id
->oa_size
!= job
->oa_size
);
389 if (ring
->funcs
->emit_pipeline_sync
&& (
390 job
->vm_needs_flush
|| gds_switch_needed
||
391 amdgpu_vm_ring_has_compute_vm_bug(ring
)))
392 amdgpu_ring_emit_pipeline_sync(ring
);
394 if (ring
->funcs
->emit_vm_flush
&& (job
->vm_needs_flush
||
395 amdgpu_vm_is_gpu_reset(adev
, id
))) {
398 trace_amdgpu_vm_flush(job
->vm_pd_addr
, ring
->idx
, job
->vm_id
);
399 amdgpu_ring_emit_vm_flush(ring
, job
->vm_id
, job
->vm_pd_addr
);
401 r
= amdgpu_fence_emit(ring
, &fence
);
405 mutex_lock(&adev
->vm_manager
.lock
);
406 fence_put(id
->last_flush
);
407 id
->last_flush
= fence
;
408 mutex_unlock(&adev
->vm_manager
.lock
);
411 if (gds_switch_needed
) {
412 id
->gds_base
= job
->gds_base
;
413 id
->gds_size
= job
->gds_size
;
414 id
->gws_base
= job
->gws_base
;
415 id
->gws_size
= job
->gws_size
;
416 id
->oa_base
= job
->oa_base
;
417 id
->oa_size
= job
->oa_size
;
418 amdgpu_ring_emit_gds_switch(ring
, job
->vm_id
,
419 job
->gds_base
, job
->gds_size
,
420 job
->gws_base
, job
->gws_size
,
421 job
->oa_base
, job
->oa_size
);
428 * amdgpu_vm_reset_id - reset VMID to zero
430 * @adev: amdgpu device structure
431 * @vm_id: vmid number to use
433 * Reset saved GDW, GWS and OA to force switch on next flush.
435 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
)
437 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
448 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
451 * @bo: requested buffer object
453 * Find @bo inside the requested vm.
454 * Search inside the @bos vm list for the requested vm
455 * Returns the found bo_va or NULL if none is found
457 * Object has to be reserved!
459 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
460 struct amdgpu_bo
*bo
)
462 struct amdgpu_bo_va
*bo_va
;
464 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
465 if (bo_va
->vm
== vm
) {
473 * amdgpu_vm_do_set_ptes - helper to call the right asic function
475 * @params: see amdgpu_pte_update_params definition
476 * @pe: addr of the page entry
477 * @addr: dst addr to write into pe
478 * @count: number of page entries to update
479 * @incr: increase next addr by incr bytes
480 * @flags: hw access flags
482 * Traces the parameters and calls the right asic functions
483 * to setup the page table using the DMA.
485 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params
*params
,
486 uint64_t pe
, uint64_t addr
,
487 unsigned count
, uint32_t incr
,
490 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
493 amdgpu_vm_write_pte(params
->adev
, params
->ib
, pe
,
494 addr
| flags
, count
, incr
);
497 amdgpu_vm_set_pte_pde(params
->adev
, params
->ib
, pe
, addr
,
503 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
505 * @params: see amdgpu_pte_update_params definition
506 * @pe: addr of the page entry
507 * @addr: dst addr to write into pe
508 * @count: number of page entries to update
509 * @incr: increase next addr by incr bytes
510 * @flags: hw access flags
512 * Traces the parameters and calls the DMA function to copy the PTEs.
514 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params
*params
,
515 uint64_t pe
, uint64_t addr
,
516 unsigned count
, uint32_t incr
,
519 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
521 amdgpu_vm_copy_pte(params
->adev
, params
->ib
, pe
,
522 (params
->src
+ (addr
>> 12) * 8), count
);
526 * amdgpu_vm_clear_bo - initially clear the page dir/table
528 * @adev: amdgpu_device pointer
531 * need to reserve bo first before calling it.
533 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
534 struct amdgpu_vm
*vm
,
535 struct amdgpu_bo
*bo
)
537 struct amdgpu_ring
*ring
;
538 struct fence
*fence
= NULL
;
539 struct amdgpu_job
*job
;
540 struct amdgpu_pte_update_params params
;
545 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
547 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
551 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
555 addr
= amdgpu_bo_gpu_offset(bo
);
556 entries
= amdgpu_bo_size(bo
) / 8;
558 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
562 memset(¶ms
, 0, sizeof(params
));
564 params
.ib
= &job
->ibs
[0];
565 amdgpu_vm_do_set_ptes(¶ms
, addr
, 0, entries
, 0, 0);
566 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
568 WARN_ON(job
->ibs
[0].length_dw
> 64);
569 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
570 AMDGPU_FENCE_OWNER_VM
, &fence
);
574 amdgpu_bo_fence(bo
, fence
, true);
579 amdgpu_job_free(job
);
586 * amdgpu_vm_map_gart - Resolve gart mapping of addr
588 * @pages_addr: optional DMA address to use for lookup
589 * @addr: the unmapped addr
591 * Look up the physical address of the page that the pte resolves
592 * to and return the pointer for the page table entry.
594 static uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
598 /* page table offset */
599 result
= pages_addr
[addr
>> PAGE_SHIFT
];
601 /* in case cpu page size != gpu page size*/
602 result
|= addr
& (~PAGE_MASK
);
604 result
&= 0xFFFFFFFFFFFFF000ULL
;
609 static int amdgpu_vm_update_pd_or_shadow(struct amdgpu_device
*adev
,
610 struct amdgpu_vm
*vm
,
613 struct amdgpu_ring
*ring
;
614 struct amdgpu_bo
*pd
= shadow
? vm
->page_directory
->shadow
:
617 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
618 uint64_t last_pde
= ~0, last_pt
= ~0;
619 unsigned count
= 0, pt_idx
, ndw
;
620 struct amdgpu_job
*job
;
621 struct amdgpu_pte_update_params params
;
622 struct fence
*fence
= NULL
;
628 pd_addr
= amdgpu_bo_gpu_offset(pd
);
629 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
634 /* assume the worst case */
635 ndw
+= vm
->max_pde_used
* 6;
637 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
641 memset(¶ms
, 0, sizeof(params
));
643 params
.ib
= &job
->ibs
[0];
645 /* walk over the address space and update the page directory */
646 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
647 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].entry
.robj
;
653 pt
= amdgpu_bo_gpu_offset(bo
);
655 if (vm
->page_tables
[pt_idx
].addr
== pt
)
657 vm
->page_tables
[pt_idx
].addr
= pt
;
659 if (vm
->page_tables
[pt_idx
].shadow_addr
== pt
)
661 vm
->page_tables
[pt_idx
].shadow_addr
= pt
;
664 pde
= pd_addr
+ pt_idx
* 8;
665 if (((last_pde
+ 8 * count
) != pde
) ||
666 ((last_pt
+ incr
* count
) != pt
) ||
667 (count
== AMDGPU_VM_MAX_UPDATE_SIZE
)) {
670 amdgpu_vm_do_set_ptes(¶ms
, last_pde
,
671 last_pt
, count
, incr
,
684 amdgpu_vm_do_set_ptes(¶ms
, last_pde
, last_pt
,
685 count
, incr
, AMDGPU_PTE_VALID
);
687 if (params
.ib
->length_dw
!= 0) {
688 amdgpu_ring_pad_ib(ring
, params
.ib
);
689 amdgpu_sync_resv(adev
, &job
->sync
, pd
->tbo
.resv
,
690 AMDGPU_FENCE_OWNER_VM
);
691 WARN_ON(params
.ib
->length_dw
> ndw
);
692 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
693 AMDGPU_FENCE_OWNER_VM
, &fence
);
697 amdgpu_bo_fence(pd
, fence
, true);
698 fence_put(vm
->page_directory_fence
);
699 vm
->page_directory_fence
= fence_get(fence
);
703 amdgpu_job_free(job
);
709 amdgpu_job_free(job
);
714 * amdgpu_vm_update_pdes - make sure that page directory is valid
716 * @adev: amdgpu_device pointer
718 * @start: start of GPU address range
719 * @end: end of GPU address range
721 * Allocates new page tables if necessary
722 * and updates the page directory.
723 * Returns 0 for success, error for failure.
725 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
726 struct amdgpu_vm
*vm
)
730 r
= amdgpu_vm_update_pd_or_shadow(adev
, vm
, true);
733 return amdgpu_vm_update_pd_or_shadow(adev
, vm
, false);
737 * amdgpu_vm_update_ptes - make sure that page tables are valid
739 * @params: see amdgpu_pte_update_params definition
741 * @start: start of GPU address range
742 * @end: end of GPU address range
743 * @dst: destination address to map to, the next dst inside the function
744 * @flags: mapping flags
746 * Update the page tables in the range @start - @end.
748 static void amdgpu_vm_update_ptes(struct amdgpu_pte_update_params
*params
,
749 struct amdgpu_vm
*vm
,
750 uint64_t start
, uint64_t end
,
751 uint64_t dst
, uint32_t flags
)
753 const uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
755 uint64_t cur_pe_start
, cur_nptes
, cur_dst
;
756 uint64_t addr
; /* next GPU address to be updated */
758 struct amdgpu_bo
*pt
;
759 unsigned nptes
; /* next number of ptes to be updated */
760 uint64_t next_pe_start
;
762 /* initialize the variables */
764 pt_idx
= addr
>> amdgpu_vm_block_size
;
765 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
766 if (params
->shadow
) {
769 pt
= vm
->page_tables
[pt_idx
].entry
.robj
->shadow
;
771 if ((addr
& ~mask
) == (end
& ~mask
))
774 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
776 cur_pe_start
= amdgpu_bo_gpu_offset(pt
);
777 cur_pe_start
+= (addr
& mask
) * 8;
783 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
785 /* walk over the address space and update the page tables */
787 pt_idx
= addr
>> amdgpu_vm_block_size
;
788 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
789 if (params
->shadow
) {
792 pt
= vm
->page_tables
[pt_idx
].entry
.robj
->shadow
;
795 if ((addr
& ~mask
) == (end
& ~mask
))
798 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
800 next_pe_start
= amdgpu_bo_gpu_offset(pt
);
801 next_pe_start
+= (addr
& mask
) * 8;
803 if ((cur_pe_start
+ 8 * cur_nptes
) == next_pe_start
&&
804 ((cur_nptes
+ nptes
) <= AMDGPU_VM_MAX_UPDATE_SIZE
)) {
805 /* The next ptb is consecutive to current ptb.
806 * Don't call the update function now.
807 * Will update two ptbs together in future.
811 params
->func(params
, cur_pe_start
, cur_dst
, cur_nptes
,
812 AMDGPU_GPU_PAGE_SIZE
, flags
);
814 cur_pe_start
= next_pe_start
;
821 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
824 params
->func(params
, cur_pe_start
, cur_dst
, cur_nptes
,
825 AMDGPU_GPU_PAGE_SIZE
, flags
);
829 * amdgpu_vm_frag_ptes - add fragment information to PTEs
831 * @params: see amdgpu_pte_update_params definition
833 * @start: first PTE to handle
834 * @end: last PTE to handle
835 * @dst: addr those PTEs should point to
836 * @flags: hw mapping flags
838 static void amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params
*params
,
839 struct amdgpu_vm
*vm
,
840 uint64_t start
, uint64_t end
,
841 uint64_t dst
, uint32_t flags
)
844 * The MC L1 TLB supports variable sized pages, based on a fragment
845 * field in the PTE. When this field is set to a non-zero value, page
846 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
847 * flags are considered valid for all PTEs within the fragment range
848 * and corresponding mappings are assumed to be physically contiguous.
850 * The L1 TLB can store a single PTE for the whole fragment,
851 * significantly increasing the space available for translation
852 * caching. This leads to large improvements in throughput when the
853 * TLB is under pressure.
855 * The L2 TLB distributes small and large fragments into two
856 * asymmetric partitions. The large fragment cache is significantly
857 * larger. Thus, we try to use large fragments wherever possible.
858 * Userspace can support this by aligning virtual base address and
859 * allocation size to the fragment size.
862 const uint64_t frag_align
= 1 << AMDGPU_LOG2_PAGES_PER_FRAG
;
864 uint64_t frag_start
= ALIGN(start
, frag_align
);
865 uint64_t frag_end
= end
& ~(frag_align
- 1);
869 /* system pages are non continuously */
870 if (params
->src
|| !(flags
& AMDGPU_PTE_VALID
) ||
871 (frag_start
>= frag_end
)) {
873 amdgpu_vm_update_ptes(params
, vm
, start
, end
, dst
, flags
);
877 /* use more than 64KB fragment size if possible */
878 frag
= lower_32_bits(frag_start
| frag_end
);
879 frag
= likely(frag
) ? __ffs(frag
) : 31;
881 /* handle the 4K area at the beginning */
882 if (start
!= frag_start
) {
883 amdgpu_vm_update_ptes(params
, vm
, start
, frag_start
,
885 dst
+= (frag_start
- start
) * AMDGPU_GPU_PAGE_SIZE
;
888 /* handle the area in the middle */
889 amdgpu_vm_update_ptes(params
, vm
, frag_start
, frag_end
, dst
,
890 flags
| AMDGPU_PTE_FRAG(frag
));
892 /* handle the 4K area at the end */
893 if (frag_end
!= end
) {
894 dst
+= (frag_end
- frag_start
) * AMDGPU_GPU_PAGE_SIZE
;
895 amdgpu_vm_update_ptes(params
, vm
, frag_end
, end
, dst
, flags
);
900 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
902 * @adev: amdgpu_device pointer
903 * @exclusive: fence we need to sync to
904 * @src: address where to copy page table entries from
905 * @pages_addr: DMA addresses to use for mapping
907 * @start: start of mapped range
908 * @last: last mapped entry
909 * @flags: flags for the entries
910 * @addr: addr to set the area to
911 * @fence: optional resulting fence
913 * Fill in the page table entries between @start and @last.
914 * Returns 0 for success, -EINVAL for failure.
916 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
917 struct fence
*exclusive
,
919 dma_addr_t
*pages_addr
,
920 struct amdgpu_vm
*vm
,
921 uint64_t start
, uint64_t last
,
922 uint32_t flags
, uint64_t addr
,
923 struct fence
**fence
)
925 struct amdgpu_ring
*ring
;
926 void *owner
= AMDGPU_FENCE_OWNER_VM
;
927 unsigned nptes
, ncmds
, ndw
;
928 struct amdgpu_job
*job
;
929 struct amdgpu_pte_update_params params
;
930 struct fence
*f
= NULL
;
933 memset(¶ms
, 0, sizeof(params
));
937 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
939 memset(¶ms
, 0, sizeof(params
));
943 /* sync to everything on unmapping */
944 if (!(flags
& AMDGPU_PTE_VALID
))
945 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
947 nptes
= last
- start
+ 1;
950 * reserve space for one command every (1 << BLOCK_SIZE)
951 * entries or 2k dwords (whatever is smaller)
953 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
959 /* only copy commands needed */
962 params
.func
= amdgpu_vm_do_copy_ptes
;
964 } else if (pages_addr
) {
965 /* copy commands needed */
971 params
.func
= amdgpu_vm_do_copy_ptes
;
974 /* set page commands needed */
977 /* two extra commands for begin/end of fragment */
980 params
.func
= amdgpu_vm_do_set_ptes
;
983 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
987 params
.ib
= &job
->ibs
[0];
989 if (!src
&& pages_addr
) {
993 /* Put the PTEs at the end of the IB. */
995 pte
= (uint64_t *)&(job
->ibs
->ptr
[i
]);
996 params
.src
= job
->ibs
->gpu_addr
+ i
* 4;
998 for (i
= 0; i
< nptes
; ++i
) {
999 pte
[i
] = amdgpu_vm_map_gart(pages_addr
, addr
+ i
*
1000 AMDGPU_GPU_PAGE_SIZE
);
1005 r
= amdgpu_sync_fence(adev
, &job
->sync
, exclusive
);
1009 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->page_directory
->tbo
.resv
,
1014 r
= reservation_object_reserve_shared(vm
->page_directory
->tbo
.resv
);
1018 params
.shadow
= true;
1019 amdgpu_vm_frag_ptes(¶ms
, vm
, start
, last
+ 1, addr
, flags
);
1020 params
.shadow
= false;
1021 amdgpu_vm_frag_ptes(¶ms
, vm
, start
, last
+ 1, addr
, flags
);
1023 amdgpu_ring_pad_ib(ring
, params
.ib
);
1024 WARN_ON(params
.ib
->length_dw
> ndw
);
1025 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
1026 AMDGPU_FENCE_OWNER_VM
, &f
);
1030 amdgpu_bo_fence(vm
->page_directory
, f
, true);
1033 *fence
= fence_get(f
);
1039 amdgpu_job_free(job
);
1044 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1046 * @adev: amdgpu_device pointer
1047 * @exclusive: fence we need to sync to
1048 * @gtt_flags: flags as they are used for GTT
1049 * @pages_addr: DMA addresses to use for mapping
1051 * @mapping: mapped range and flags to use for the update
1052 * @addr: addr to set the area to
1053 * @flags: HW flags for the mapping
1054 * @fence: optional resulting fence
1056 * Split the mapping into smaller chunks so that each update fits
1058 * Returns 0 for success, -EINVAL for failure.
1060 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
1061 struct fence
*exclusive
,
1063 dma_addr_t
*pages_addr
,
1064 struct amdgpu_vm
*vm
,
1065 struct amdgpu_bo_va_mapping
*mapping
,
1066 uint32_t flags
, uint64_t addr
,
1067 struct fence
**fence
)
1069 const uint64_t max_size
= 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE
;
1071 uint64_t src
= 0, start
= mapping
->it
.start
;
1074 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1075 * but in case of something, we filter the flags in first place
1077 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
1078 flags
&= ~AMDGPU_PTE_READABLE
;
1079 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
1080 flags
&= ~AMDGPU_PTE_WRITEABLE
;
1082 trace_amdgpu_vm_bo_update(mapping
);
1085 if (flags
== gtt_flags
)
1086 src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
1089 addr
+= mapping
->offset
;
1091 if (!pages_addr
|| src
)
1092 return amdgpu_vm_bo_update_mapping(adev
, exclusive
,
1093 src
, pages_addr
, vm
,
1094 start
, mapping
->it
.last
,
1095 flags
, addr
, fence
);
1097 while (start
!= mapping
->it
.last
+ 1) {
1100 last
= min((uint64_t)mapping
->it
.last
, start
+ max_size
- 1);
1101 r
= amdgpu_vm_bo_update_mapping(adev
, exclusive
,
1102 src
, pages_addr
, vm
,
1103 start
, last
, flags
, addr
,
1109 addr
+= max_size
* AMDGPU_GPU_PAGE_SIZE
;
1116 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1118 * @adev: amdgpu_device pointer
1119 * @bo_va: requested BO and VM object
1120 * @clear: if true clear the entries
1122 * Fill in the page table entries for @bo_va.
1123 * Returns 0 for success, -EINVAL for failure.
1125 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1126 struct amdgpu_bo_va
*bo_va
,
1129 struct amdgpu_vm
*vm
= bo_va
->vm
;
1130 struct amdgpu_bo_va_mapping
*mapping
;
1131 dma_addr_t
*pages_addr
= NULL
;
1132 uint32_t gtt_flags
, flags
;
1133 struct ttm_mem_reg
*mem
;
1134 struct fence
*exclusive
;
1143 struct ttm_dma_tt
*ttm
;
1145 mem
= &bo_va
->bo
->tbo
.mem
;
1146 addr
= (u64
)mem
->start
<< PAGE_SHIFT
;
1147 switch (mem
->mem_type
) {
1149 ttm
= container_of(bo_va
->bo
->tbo
.ttm
, struct
1151 pages_addr
= ttm
->dma_address
;
1155 addr
+= adev
->vm_manager
.vram_base_offset
;
1162 exclusive
= reservation_object_get_excl(bo_va
->bo
->tbo
.resv
);
1165 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
1166 gtt_flags
= (adev
== bo_va
->bo
->adev
) ? flags
: 0;
1168 spin_lock(&vm
->status_lock
);
1169 if (!list_empty(&bo_va
->vm_status
))
1170 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1171 spin_unlock(&vm
->status_lock
);
1173 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1174 r
= amdgpu_vm_bo_split_mapping(adev
, exclusive
,
1175 gtt_flags
, pages_addr
, vm
,
1176 mapping
, flags
, addr
,
1177 &bo_va
->last_pt_update
);
1182 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1183 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1184 trace_amdgpu_vm_bo_mapping(mapping
);
1186 list_for_each_entry(mapping
, &bo_va
->invalids
, list
)
1187 trace_amdgpu_vm_bo_mapping(mapping
);
1190 spin_lock(&vm
->status_lock
);
1191 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1192 list_del_init(&bo_va
->vm_status
);
1194 list_add(&bo_va
->vm_status
, &vm
->cleared
);
1195 spin_unlock(&vm
->status_lock
);
1201 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1203 * @adev: amdgpu_device pointer
1206 * Make sure all freed BOs are cleared in the PT.
1207 * Returns 0 for success.
1209 * PTs have to be reserved and mutex must be locked!
1211 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
1212 struct amdgpu_vm
*vm
)
1214 struct amdgpu_bo_va_mapping
*mapping
;
1217 while (!list_empty(&vm
->freed
)) {
1218 mapping
= list_first_entry(&vm
->freed
,
1219 struct amdgpu_bo_va_mapping
, list
);
1220 list_del(&mapping
->list
);
1222 r
= amdgpu_vm_bo_split_mapping(adev
, NULL
, 0, NULL
, vm
, mapping
,
1234 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1236 * @adev: amdgpu_device pointer
1239 * Make sure all invalidated BOs are cleared in the PT.
1240 * Returns 0 for success.
1242 * PTs have to be reserved and mutex must be locked!
1244 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
1245 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
1247 struct amdgpu_bo_va
*bo_va
= NULL
;
1250 spin_lock(&vm
->status_lock
);
1251 while (!list_empty(&vm
->invalidated
)) {
1252 bo_va
= list_first_entry(&vm
->invalidated
,
1253 struct amdgpu_bo_va
, vm_status
);
1254 spin_unlock(&vm
->status_lock
);
1256 r
= amdgpu_vm_bo_update(adev
, bo_va
, true);
1260 spin_lock(&vm
->status_lock
);
1262 spin_unlock(&vm
->status_lock
);
1265 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
1271 * amdgpu_vm_bo_add - add a bo to a specific vm
1273 * @adev: amdgpu_device pointer
1275 * @bo: amdgpu buffer object
1277 * Add @bo into the requested vm.
1278 * Add @bo to the list of bos associated with the vm
1279 * Returns newly added bo_va or NULL for failure
1281 * Object has to be reserved!
1283 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
1284 struct amdgpu_vm
*vm
,
1285 struct amdgpu_bo
*bo
)
1287 struct amdgpu_bo_va
*bo_va
;
1289 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
1290 if (bo_va
== NULL
) {
1295 bo_va
->ref_count
= 1;
1296 INIT_LIST_HEAD(&bo_va
->bo_list
);
1297 INIT_LIST_HEAD(&bo_va
->valids
);
1298 INIT_LIST_HEAD(&bo_va
->invalids
);
1299 INIT_LIST_HEAD(&bo_va
->vm_status
);
1301 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
1307 * amdgpu_vm_bo_map - map bo inside a vm
1309 * @adev: amdgpu_device pointer
1310 * @bo_va: bo_va to store the address
1311 * @saddr: where to map the BO
1312 * @offset: requested offset in the BO
1313 * @flags: attributes of pages (read/write/valid/etc.)
1315 * Add a mapping of the BO at the specefied addr into the VM.
1316 * Returns 0 for success, error for failure.
1318 * Object has to be reserved and unreserved outside!
1320 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1321 struct amdgpu_bo_va
*bo_va
,
1322 uint64_t saddr
, uint64_t offset
,
1323 uint64_t size
, uint32_t flags
)
1325 struct amdgpu_bo_va_mapping
*mapping
;
1326 struct amdgpu_vm
*vm
= bo_va
->vm
;
1327 struct interval_tree_node
*it
;
1328 unsigned last_pfn
, pt_idx
;
1332 /* validate the parameters */
1333 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1334 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
1337 /* make sure object fit at this offset */
1338 eaddr
= saddr
+ size
- 1;
1339 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
)))
1342 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1343 if (last_pfn
>= adev
->vm_manager
.max_pfn
) {
1344 dev_err(adev
->dev
, "va above limit (0x%08X >= 0x%08X)\n",
1345 last_pfn
, adev
->vm_manager
.max_pfn
);
1349 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1350 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1352 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
);
1354 struct amdgpu_bo_va_mapping
*tmp
;
1355 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1356 /* bo and tmp overlap, invalid addr */
1357 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1358 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1359 tmp
->it
.start
, tmp
->it
.last
+ 1);
1364 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1370 INIT_LIST_HEAD(&mapping
->list
);
1371 mapping
->it
.start
= saddr
;
1372 mapping
->it
.last
= eaddr
;
1373 mapping
->offset
= offset
;
1374 mapping
->flags
= flags
;
1376 list_add(&mapping
->list
, &bo_va
->invalids
);
1377 interval_tree_insert(&mapping
->it
, &vm
->va
);
1379 /* Make sure the page tables are allocated */
1380 saddr
>>= amdgpu_vm_block_size
;
1381 eaddr
>>= amdgpu_vm_block_size
;
1383 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1385 if (eaddr
> vm
->max_pde_used
)
1386 vm
->max_pde_used
= eaddr
;
1388 /* walk over the address space and allocate the page tables */
1389 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1390 struct reservation_object
*resv
= vm
->page_directory
->tbo
.resv
;
1391 struct amdgpu_bo_list_entry
*entry
;
1392 struct amdgpu_bo
*pt
;
1394 entry
= &vm
->page_tables
[pt_idx
].entry
;
1398 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1399 AMDGPU_GPU_PAGE_SIZE
, true,
1400 AMDGPU_GEM_DOMAIN_VRAM
,
1401 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
1402 AMDGPU_GEM_CREATE_SHADOW
,
1407 /* Keep a reference to the page table to avoid freeing
1408 * them up in the wrong order.
1410 pt
->parent
= amdgpu_bo_ref(vm
->page_directory
);
1412 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
);
1414 amdgpu_bo_unref(&pt
);
1419 entry
->priority
= 0;
1420 entry
->tv
.bo
= &entry
->robj
->tbo
;
1421 entry
->tv
.shared
= true;
1422 entry
->user_pages
= NULL
;
1423 vm
->page_tables
[pt_idx
].addr
= 0;
1429 list_del(&mapping
->list
);
1430 interval_tree_remove(&mapping
->it
, &vm
->va
);
1431 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1439 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1441 * @adev: amdgpu_device pointer
1442 * @bo_va: bo_va to remove the address from
1443 * @saddr: where to the BO is mapped
1445 * Remove a mapping of the BO at the specefied addr from the VM.
1446 * Returns 0 for success, error for failure.
1448 * Object has to be reserved and unreserved outside!
1450 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1451 struct amdgpu_bo_va
*bo_va
,
1454 struct amdgpu_bo_va_mapping
*mapping
;
1455 struct amdgpu_vm
*vm
= bo_va
->vm
;
1458 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1460 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1461 if (mapping
->it
.start
== saddr
)
1465 if (&mapping
->list
== &bo_va
->valids
) {
1468 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1469 if (mapping
->it
.start
== saddr
)
1473 if (&mapping
->list
== &bo_va
->invalids
)
1477 list_del(&mapping
->list
);
1478 interval_tree_remove(&mapping
->it
, &vm
->va
);
1479 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1482 list_add(&mapping
->list
, &vm
->freed
);
1490 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1492 * @adev: amdgpu_device pointer
1493 * @bo_va: requested bo_va
1495 * Remove @bo_va->bo from the requested vm.
1497 * Object have to be reserved!
1499 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1500 struct amdgpu_bo_va
*bo_va
)
1502 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1503 struct amdgpu_vm
*vm
= bo_va
->vm
;
1505 list_del(&bo_va
->bo_list
);
1507 spin_lock(&vm
->status_lock
);
1508 list_del(&bo_va
->vm_status
);
1509 spin_unlock(&vm
->status_lock
);
1511 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1512 list_del(&mapping
->list
);
1513 interval_tree_remove(&mapping
->it
, &vm
->va
);
1514 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1515 list_add(&mapping
->list
, &vm
->freed
);
1517 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1518 list_del(&mapping
->list
);
1519 interval_tree_remove(&mapping
->it
, &vm
->va
);
1523 fence_put(bo_va
->last_pt_update
);
1528 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1530 * @adev: amdgpu_device pointer
1532 * @bo: amdgpu buffer object
1534 * Mark @bo as invalid.
1536 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1537 struct amdgpu_bo
*bo
)
1539 struct amdgpu_bo_va
*bo_va
;
1541 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1542 spin_lock(&bo_va
->vm
->status_lock
);
1543 if (list_empty(&bo_va
->vm_status
))
1544 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1545 spin_unlock(&bo_va
->vm
->status_lock
);
1550 * amdgpu_vm_init - initialize a vm instance
1552 * @adev: amdgpu_device pointer
1557 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1559 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1560 AMDGPU_VM_PTE_COUNT
* 8);
1561 unsigned pd_size
, pd_entries
;
1562 unsigned ring_instance
;
1563 struct amdgpu_ring
*ring
;
1564 struct amd_sched_rq
*rq
;
1567 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1570 vm
->client_id
= atomic64_inc_return(&adev
->vm_manager
.client_counter
);
1571 spin_lock_init(&vm
->status_lock
);
1572 INIT_LIST_HEAD(&vm
->invalidated
);
1573 INIT_LIST_HEAD(&vm
->cleared
);
1574 INIT_LIST_HEAD(&vm
->freed
);
1576 pd_size
= amdgpu_vm_directory_size(adev
);
1577 pd_entries
= amdgpu_vm_num_pdes(adev
);
1579 /* allocate page table array */
1580 vm
->page_tables
= drm_calloc_large(pd_entries
, sizeof(struct amdgpu_vm_pt
));
1581 if (vm
->page_tables
== NULL
) {
1582 DRM_ERROR("Cannot allocate memory for page table array\n");
1586 /* create scheduler entity for page table updates */
1588 ring_instance
= atomic_inc_return(&adev
->vm_manager
.vm_pte_next_ring
);
1589 ring_instance
%= adev
->vm_manager
.vm_pte_num_rings
;
1590 ring
= adev
->vm_manager
.vm_pte_rings
[ring_instance
];
1591 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
1592 r
= amd_sched_entity_init(&ring
->sched
, &vm
->entity
,
1593 rq
, amdgpu_sched_jobs
);
1597 vm
->page_directory_fence
= NULL
;
1599 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1600 AMDGPU_GEM_DOMAIN_VRAM
,
1601 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
|
1602 AMDGPU_GEM_CREATE_SHADOW
,
1603 NULL
, NULL
, &vm
->page_directory
);
1605 goto error_free_sched_entity
;
1607 r
= amdgpu_bo_reserve(vm
->page_directory
, false);
1609 goto error_free_page_directory
;
1611 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->page_directory
);
1612 amdgpu_bo_unreserve(vm
->page_directory
);
1614 goto error_free_page_directory
;
1615 vm
->last_eviction_counter
= atomic64_read(&adev
->num_evictions
);
1619 error_free_page_directory
:
1620 amdgpu_bo_unref(&vm
->page_directory
);
1621 vm
->page_directory
= NULL
;
1623 error_free_sched_entity
:
1624 amd_sched_entity_fini(&ring
->sched
, &vm
->entity
);
1627 drm_free_large(vm
->page_tables
);
1633 * amdgpu_vm_fini - tear down a vm instance
1635 * @adev: amdgpu_device pointer
1639 * Unbind the VM and remove all bos from the vm bo list
1641 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1643 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1646 amd_sched_entity_fini(vm
->entity
.sched
, &vm
->entity
);
1648 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1649 dev_err(adev
->dev
, "still active bo inside vm\n");
1651 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1652 list_del(&mapping
->list
);
1653 interval_tree_remove(&mapping
->it
, &vm
->va
);
1656 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1657 list_del(&mapping
->list
);
1661 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++) {
1662 if (vm
->page_tables
[i
].entry
.robj
&&
1663 vm
->page_tables
[i
].entry
.robj
->shadow
)
1664 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
->shadow
);
1665 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
);
1667 drm_free_large(vm
->page_tables
);
1669 if (vm
->page_directory
->shadow
)
1670 amdgpu_bo_unref(&vm
->page_directory
->shadow
);
1671 amdgpu_bo_unref(&vm
->page_directory
);
1672 fence_put(vm
->page_directory_fence
);
1676 * amdgpu_vm_manager_init - init the VM manager
1678 * @adev: amdgpu_device pointer
1680 * Initialize the VM manager structures
1682 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
1686 INIT_LIST_HEAD(&adev
->vm_manager
.ids_lru
);
1688 /* skip over VMID 0, since it is the system VM */
1689 for (i
= 1; i
< adev
->vm_manager
.num_ids
; ++i
) {
1690 amdgpu_vm_reset_id(adev
, i
);
1691 amdgpu_sync_create(&adev
->vm_manager
.ids
[i
].active
);
1692 list_add_tail(&adev
->vm_manager
.ids
[i
].list
,
1693 &adev
->vm_manager
.ids_lru
);
1696 adev
->vm_manager
.fence_context
= fence_context_alloc(AMDGPU_MAX_RINGS
);
1697 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1698 adev
->vm_manager
.seqno
[i
] = 0;
1700 atomic_set(&adev
->vm_manager
.vm_pte_next_ring
, 0);
1701 atomic64_set(&adev
->vm_manager
.client_counter
, 0);
1705 * amdgpu_vm_manager_fini - cleanup VM manager
1707 * @adev: amdgpu_device pointer
1709 * Cleanup the VM manager and free resources.
1711 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
1715 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
) {
1716 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[i
];
1718 fence_put(adev
->vm_manager
.ids
[i
].first
);
1719 amdgpu_sync_free(&adev
->vm_manager
.ids
[i
].active
);
1720 fence_put(id
->flushed_updates
);