2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_11_0_d.h"
36 #include "dce/dce_11_0_sh_mask.h"
37 #include "dce/dce_11_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
);
44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
);
46 static const u32 crtc_offsets
[] =
48 CRTC0_REGISTER_OFFSET
,
49 CRTC1_REGISTER_OFFSET
,
50 CRTC2_REGISTER_OFFSET
,
51 CRTC3_REGISTER_OFFSET
,
52 CRTC4_REGISTER_OFFSET
,
53 CRTC5_REGISTER_OFFSET
,
57 static const u32 hpd_offsets
[] =
67 static const uint32_t dig_offsets
[] = {
85 } interrupt_status_offsets
[] = { {
86 .reg
= mmDISP_INTERRUPT_STATUS
,
87 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
88 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
89 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
92 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
93 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
94 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
97 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
98 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
99 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
102 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
103 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
104 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
107 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
108 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
109 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
112 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
113 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
114 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
117 static const u32 cz_golden_settings_a11
[] =
119 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
120 mmFBC_MISC
, 0x1f311fff, 0x14300000,
123 static const u32 cz_mgcg_cgcg_init
[] =
125 mmXDMA_CLOCK_GATING_CNTL
, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL
, 0x00000101, 0x00000000,
129 static const u32 stoney_golden_settings_a11
[] =
131 mmCRTC_DOUBLE_BUFFER_CONTROL
, 0x00010101, 0x00010000,
132 mmFBC_MISC
, 0x1f311fff, 0x14302000,
135 static const u32 polaris11_golden_settings_a11
[] =
137 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
139 mmFBC_DEBUG1
, 0xffffffff, 0x00000008,
140 mmFBC_MISC
, 0x9f313fff, 0x14302008,
141 mmHDMI_CONTROL
, 0x313f031f, 0x00000011,
144 static const u32 polaris10_golden_settings_a11
[] =
146 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
147 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
148 mmFBC_MISC
, 0x9f313fff, 0x14302008,
149 mmHDMI_CONTROL
, 0x313f031f, 0x00000011,
152 static void dce_v11_0_init_golden_registers(struct amdgpu_device
*adev
)
154 switch (adev
->asic_type
) {
156 amdgpu_program_register_sequence(adev
,
158 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
159 amdgpu_program_register_sequence(adev
,
160 cz_golden_settings_a11
,
161 (const u32
)ARRAY_SIZE(cz_golden_settings_a11
));
164 amdgpu_program_register_sequence(adev
,
165 stoney_golden_settings_a11
,
166 (const u32
)ARRAY_SIZE(stoney_golden_settings_a11
));
169 amdgpu_program_register_sequence(adev
,
170 polaris11_golden_settings_a11
,
171 (const u32
)ARRAY_SIZE(polaris11_golden_settings_a11
));
174 amdgpu_program_register_sequence(adev
,
175 polaris10_golden_settings_a11
,
176 (const u32
)ARRAY_SIZE(polaris10_golden_settings_a11
));
183 static u32
dce_v11_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
184 u32 block_offset
, u32 reg
)
189 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
191 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
192 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
198 u32 block_offset
, u32 reg
, u32 v
)
202 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
205 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
210 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
221 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
222 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
231 * dce_v11_0_vblank_wait - vblank wait asic callback.
233 * @adev: amdgpu_device pointer
234 * @crtc: crtc to wait for vblank on
236 * Wait for vblank on the requested crtc (evergreen+).
238 static void dce_v11_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
242 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
)
245 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
248 /* depending on when we hit vblank, we may be close to active; if so,
249 * wait for another frame.
251 while (dce_v11_0_is_in_vblank(adev
, crtc
)) {
254 if (!dce_v11_0_is_counter_moving(adev
, crtc
))
259 while (!dce_v11_0_is_in_vblank(adev
, crtc
)) {
262 if (!dce_v11_0_is_counter_moving(adev
, crtc
))
268 static u32
dce_v11_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
270 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
)
273 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
280 /* Enable pflip interrupts */
281 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
282 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
289 /* Disable pflip interrupts */
290 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
291 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
295 * dce_v11_0_page_flip - pageflip callback.
297 * @adev: amdgpu_device pointer
298 * @crtc_id: crtc to cleanup pageflip on
299 * @crtc_base: new address of the crtc (GPU MC address)
301 * Triggers the actual pageflip by updating the primary
302 * surface base address.
304 static void dce_v11_0_page_flip(struct amdgpu_device
*adev
,
305 int crtc_id
, u64 crtc_base
, bool async
)
307 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
310 /* flip immediate for async, default is vsync */
311 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
312 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
313 GRPH_SURFACE_UPDATE_IMMEDIATE_EN
, async
? 1 : 0);
314 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
315 /* update the scanout addresses */
316 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
317 upper_32_bits(crtc_base
));
318 /* writing to the low address triggers the update */
319 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
320 lower_32_bits(crtc_base
));
322 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
325 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
326 u32
*vbl
, u32
*position
)
328 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
331 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
332 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
338 * dce_v11_0_hpd_sense - hpd sense callback.
340 * @adev: amdgpu_device pointer
341 * @hpd: hpd (hotplug detect) pin
343 * Checks if a digital monitor is connected (evergreen+).
344 * Returns true if connected, false if not connected.
346 static bool dce_v11_0_hpd_sense(struct amdgpu_device
*adev
,
347 enum amdgpu_hpd_id hpd
)
350 bool connected
= false;
375 if (RREG32(mmDC_HPD_INT_STATUS
+ hpd_offsets
[idx
]) &
376 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
)
383 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
385 * @adev: amdgpu_device pointer
386 * @hpd: hpd (hotplug detect) pin
388 * Set the polarity of the hpd pin (evergreen+).
390 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device
*adev
,
391 enum amdgpu_hpd_id hpd
)
394 bool connected
= dce_v11_0_hpd_sense(adev
, hpd
);
420 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
]);
422 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 0);
424 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 1);
425 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
], tmp
);
429 * dce_v11_0_hpd_init - hpd setup callback.
431 * @adev: amdgpu_device pointer
433 * Setup the hpd pins used by the card (evergreen+).
434 * Enable the pin, set the polarity, and enable the hpd interrupts.
436 static void dce_v11_0_hpd_init(struct amdgpu_device
*adev
)
438 struct drm_device
*dev
= adev
->ddev
;
439 struct drm_connector
*connector
;
443 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
444 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
446 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
447 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
448 /* don't try to enable hpd on eDP or LVDS avoid breaking the
449 * aux dp channel on imac and help (but not completely fix)
450 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
451 * also avoid interrupt storms during dpms.
456 switch (amdgpu_connector
->hpd
.hpd
) {
479 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
480 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 1);
481 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
483 tmp
= RREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
]);
484 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
485 DC_HPD_CONNECT_INT_DELAY
,
486 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
);
487 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
488 DC_HPD_DISCONNECT_INT_DELAY
,
489 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
);
490 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
], tmp
);
492 dce_v11_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
493 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
498 * dce_v11_0_hpd_fini - hpd tear down callback.
500 * @adev: amdgpu_device pointer
502 * Tear down the hpd pins used by the card (evergreen+).
503 * Disable the hpd interrupts.
505 static void dce_v11_0_hpd_fini(struct amdgpu_device
*adev
)
507 struct drm_device
*dev
= adev
->ddev
;
508 struct drm_connector
*connector
;
512 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
513 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
515 switch (amdgpu_connector
->hpd
.hpd
) {
538 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
539 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 0);
540 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
542 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
546 static u32
dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
548 return mmDC_GPIO_HPD_A
;
551 static bool dce_v11_0_is_display_hung(struct amdgpu_device
*adev
)
557 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
558 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
559 if (REG_GET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
)) {
560 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
561 crtc_hung
|= (1 << i
);
565 for (j
= 0; j
< 10; j
++) {
566 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
567 if (crtc_hung
& (1 << i
)) {
568 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
569 if (tmp
!= crtc_status
[i
])
570 crtc_hung
&= ~(1 << i
);
581 static void dce_v11_0_stop_mc_access(struct amdgpu_device
*adev
,
582 struct amdgpu_mode_mc_save
*save
)
584 u32 crtc_enabled
, tmp
;
587 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
588 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
590 /* disable VGA render */
591 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
592 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
593 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
595 /* blank the display controllers */
596 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
597 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
598 CRTC_CONTROL
, CRTC_MASTER_EN
);
601 save
->crtc_enabled
[i
] = true;
602 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
603 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
604 /*it is correct only for RGB ; black is 0*/
605 WREG32(mmCRTC_BLANK_DATA_COLOR
+ crtc_offsets
[i
], 0);
606 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
607 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
610 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
611 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
612 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
613 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
614 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
615 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
616 save
->crtc_enabled
[i
] = false;
620 save
->crtc_enabled
[i
] = false;
625 static void dce_v11_0_resume_mc_access(struct amdgpu_device
*adev
,
626 struct amdgpu_mode_mc_save
*save
)
631 /* update crtc base addresses */
632 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
633 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
634 upper_32_bits(adev
->mc
.vram_start
));
635 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
636 (u32
)adev
->mc
.vram_start
);
638 if (save
->crtc_enabled
[i
]) {
639 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
640 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
641 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
645 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
646 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
648 /* Unlock vga access */
649 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
651 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
654 static void dce_v11_0_set_vga_render_state(struct amdgpu_device
*adev
,
659 /* Lockout access through VGA aperture*/
660 tmp
= RREG32(mmVGA_HDP_CONTROL
);
662 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
664 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
665 WREG32(mmVGA_HDP_CONTROL
, tmp
);
667 /* disable VGA render */
668 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
670 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
672 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
673 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
676 static int dce_v11_0_get_num_crtc (struct amdgpu_device
*adev
)
680 switch (adev
->asic_type
) {
699 void dce_v11_0_disable_dce(struct amdgpu_device
*adev
)
701 /*Disable VGA render and enabled crtc, if has DCE engine*/
702 if (amdgpu_atombios_has_dce_engine_info(adev
)) {
706 dce_v11_0_set_vga_render_state(adev
, false);
709 for (i
= 0; i
< dce_v11_0_get_num_crtc(adev
); i
++) {
710 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
711 CRTC_CONTROL
, CRTC_MASTER_EN
);
713 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
714 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
715 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
716 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
717 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
723 static void dce_v11_0_program_fmt(struct drm_encoder
*encoder
)
725 struct drm_device
*dev
= encoder
->dev
;
726 struct amdgpu_device
*adev
= dev
->dev_private
;
727 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
728 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
729 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
732 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
735 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
736 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
737 dither
= amdgpu_connector
->dither
;
740 /* LVDS/eDP FMT is set up by atom */
741 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
744 /* not needed for analog */
745 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
746 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
754 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
755 /* XXX sort out optimal dither settings */
756 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
757 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
758 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
759 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 0);
761 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
762 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 0);
766 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
767 /* XXX sort out optimal dither settings */
768 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
769 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
770 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
771 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
772 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 1);
774 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
775 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 1);
779 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
780 /* XXX sort out optimal dither settings */
781 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
782 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
783 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
784 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
785 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 2);
787 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
788 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 2);
796 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
800 /* display watermark setup */
802 * dce_v11_0_line_buffer_adjust - Set up the line buffer
804 * @adev: amdgpu_device pointer
805 * @amdgpu_crtc: the selected display controller
806 * @mode: the current display mode on the selected display
809 * Setup up the line buffer allocation for
810 * the selected display controller (CIK).
811 * Returns the line buffer size in pixels.
813 static u32
dce_v11_0_line_buffer_adjust(struct amdgpu_device
*adev
,
814 struct amdgpu_crtc
*amdgpu_crtc
,
815 struct drm_display_mode
*mode
)
817 u32 tmp
, buffer_alloc
, i
, mem_cfg
;
818 u32 pipe_offset
= amdgpu_crtc
->crtc_id
;
821 * There are 6 line buffers, one for each display controllers.
822 * There are 3 partitions per LB. Select the number of partitions
823 * to enable based on the display width. For display widths larger
824 * than 4096, you need use to use 2 display controllers and combine
825 * them using the stereo blender.
827 if (amdgpu_crtc
->base
.enabled
&& mode
) {
828 if (mode
->crtc_hdisplay
< 1920) {
831 } else if (mode
->crtc_hdisplay
< 2560) {
834 } else if (mode
->crtc_hdisplay
< 4096) {
836 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
838 DRM_DEBUG_KMS("Mode too big for LB!\n");
840 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
847 tmp
= RREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
);
848 tmp
= REG_SET_FIELD(tmp
, LB_MEMORY_CTRL
, LB_MEMORY_CONFIG
, mem_cfg
);
849 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
, tmp
);
851 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
852 tmp
= REG_SET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATED
, buffer_alloc
);
853 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
, tmp
);
855 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
856 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
857 if (REG_GET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATION_COMPLETED
))
862 if (amdgpu_crtc
->base
.enabled
&& mode
) {
874 /* controller not enabled, so no lb used */
879 * cik_get_number_of_dram_channels - get the number of dram channels
881 * @adev: amdgpu_device pointer
883 * Look up the number of video ram channels (CIK).
884 * Used for display watermark bandwidth calculations
885 * Returns the number of dram channels
887 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
889 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
891 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
914 struct dce10_wm_params
{
915 u32 dram_channels
; /* number of dram channels */
916 u32 yclk
; /* bandwidth per dram data pin in kHz */
917 u32 sclk
; /* engine clock in kHz */
918 u32 disp_clk
; /* display clock in kHz */
919 u32 src_width
; /* viewport width */
920 u32 active_time
; /* active display time in ns */
921 u32 blank_time
; /* blank time in ns */
922 bool interlaced
; /* mode is interlaced */
923 fixed20_12 vsc
; /* vertical scale ratio */
924 u32 num_heads
; /* number of active crtcs */
925 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
926 u32 lb_size
; /* line buffer allocated to pipe */
927 u32 vtaps
; /* vertical scaler taps */
931 * dce_v11_0_dram_bandwidth - get the dram bandwidth
933 * @wm: watermark calculation data
935 * Calculate the raw dram bandwidth (CIK).
936 * Used for display watermark bandwidth calculations
937 * Returns the dram bandwidth in MBytes/s
939 static u32
dce_v11_0_dram_bandwidth(struct dce10_wm_params
*wm
)
941 /* Calculate raw DRAM Bandwidth */
942 fixed20_12 dram_efficiency
; /* 0.7 */
943 fixed20_12 yclk
, dram_channels
, bandwidth
;
946 a
.full
= dfixed_const(1000);
947 yclk
.full
= dfixed_const(wm
->yclk
);
948 yclk
.full
= dfixed_div(yclk
, a
);
949 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
950 a
.full
= dfixed_const(10);
951 dram_efficiency
.full
= dfixed_const(7);
952 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
953 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
954 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
956 return dfixed_trunc(bandwidth
);
960 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
962 * @wm: watermark calculation data
964 * Calculate the dram bandwidth used for display (CIK).
965 * Used for display watermark bandwidth calculations
966 * Returns the dram bandwidth for display in MBytes/s
968 static u32
dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
970 /* Calculate DRAM Bandwidth and the part allocated to display. */
971 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
972 fixed20_12 yclk
, dram_channels
, bandwidth
;
975 a
.full
= dfixed_const(1000);
976 yclk
.full
= dfixed_const(wm
->yclk
);
977 yclk
.full
= dfixed_div(yclk
, a
);
978 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
979 a
.full
= dfixed_const(10);
980 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
981 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
982 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
983 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
985 return dfixed_trunc(bandwidth
);
989 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
991 * @wm: watermark calculation data
993 * Calculate the data return bandwidth used for display (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns the data return bandwidth in MBytes/s
997 static u32
dce_v11_0_data_return_bandwidth(struct dce10_wm_params
*wm
)
999 /* Calculate the display Data return Bandwidth */
1000 fixed20_12 return_efficiency
; /* 0.8 */
1001 fixed20_12 sclk
, bandwidth
;
1004 a
.full
= dfixed_const(1000);
1005 sclk
.full
= dfixed_const(wm
->sclk
);
1006 sclk
.full
= dfixed_div(sclk
, a
);
1007 a
.full
= dfixed_const(10);
1008 return_efficiency
.full
= dfixed_const(8);
1009 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
1010 a
.full
= dfixed_const(32);
1011 bandwidth
.full
= dfixed_mul(a
, sclk
);
1012 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
1014 return dfixed_trunc(bandwidth
);
1018 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
1020 * @wm: watermark calculation data
1022 * Calculate the dmif bandwidth used for display (CIK).
1023 * Used for display watermark bandwidth calculations
1024 * Returns the dmif bandwidth in MBytes/s
1026 static u32
dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params
*wm
)
1028 /* Calculate the DMIF Request Bandwidth */
1029 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
1030 fixed20_12 disp_clk
, bandwidth
;
1033 a
.full
= dfixed_const(1000);
1034 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
1035 disp_clk
.full
= dfixed_div(disp_clk
, a
);
1036 a
.full
= dfixed_const(32);
1037 b
.full
= dfixed_mul(a
, disp_clk
);
1039 a
.full
= dfixed_const(10);
1040 disp_clk_request_efficiency
.full
= dfixed_const(8);
1041 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
1043 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
1045 return dfixed_trunc(bandwidth
);
1049 * dce_v11_0_available_bandwidth - get the min available bandwidth
1051 * @wm: watermark calculation data
1053 * Calculate the min available bandwidth used for display (CIK).
1054 * Used for display watermark bandwidth calculations
1055 * Returns the min available bandwidth in MBytes/s
1057 static u32
dce_v11_0_available_bandwidth(struct dce10_wm_params
*wm
)
1059 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1060 u32 dram_bandwidth
= dce_v11_0_dram_bandwidth(wm
);
1061 u32 data_return_bandwidth
= dce_v11_0_data_return_bandwidth(wm
);
1062 u32 dmif_req_bandwidth
= dce_v11_0_dmif_request_bandwidth(wm
);
1064 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
1068 * dce_v11_0_average_bandwidth - get the average available bandwidth
1070 * @wm: watermark calculation data
1072 * Calculate the average available bandwidth used for display (CIK).
1073 * Used for display watermark bandwidth calculations
1074 * Returns the average available bandwidth in MBytes/s
1076 static u32
dce_v11_0_average_bandwidth(struct dce10_wm_params
*wm
)
1078 /* Calculate the display mode Average Bandwidth
1079 * DisplayMode should contain the source and destination dimensions,
1083 fixed20_12 line_time
;
1084 fixed20_12 src_width
;
1085 fixed20_12 bandwidth
;
1088 a
.full
= dfixed_const(1000);
1089 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1090 line_time
.full
= dfixed_div(line_time
, a
);
1091 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1092 src_width
.full
= dfixed_const(wm
->src_width
);
1093 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1094 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1095 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1097 return dfixed_trunc(bandwidth
);
1101 * dce_v11_0_latency_watermark - get the latency watermark
1103 * @wm: watermark calculation data
1105 * Calculate the latency watermark (CIK).
1106 * Used for display watermark bandwidth calculations
1107 * Returns the latency watermark in ns
1109 static u32
dce_v11_0_latency_watermark(struct dce10_wm_params
*wm
)
1111 /* First calculate the latency in ns */
1112 u32 mc_latency
= 2000; /* 2000 ns. */
1113 u32 available_bandwidth
= dce_v11_0_available_bandwidth(wm
);
1114 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1115 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1116 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1117 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1118 (wm
->num_heads
* cursor_line_pair_return_time
);
1119 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1120 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1121 u32 tmp
, dmif_size
= 12288;
1124 if (wm
->num_heads
== 0)
1127 a
.full
= dfixed_const(2);
1128 b
.full
= dfixed_const(1);
1129 if ((wm
->vsc
.full
> a
.full
) ||
1130 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1132 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1133 max_src_lines_per_dst_line
= 4;
1135 max_src_lines_per_dst_line
= 2;
1137 a
.full
= dfixed_const(available_bandwidth
);
1138 b
.full
= dfixed_const(wm
->num_heads
);
1139 a
.full
= dfixed_div(a
, b
);
1141 b
.full
= dfixed_const(mc_latency
+ 512);
1142 c
.full
= dfixed_const(wm
->disp_clk
);
1143 b
.full
= dfixed_div(b
, c
);
1145 c
.full
= dfixed_const(dmif_size
);
1146 b
.full
= dfixed_div(c
, b
);
1148 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1150 b
.full
= dfixed_const(1000);
1151 c
.full
= dfixed_const(wm
->disp_clk
);
1152 b
.full
= dfixed_div(c
, b
);
1153 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1154 b
.full
= dfixed_mul(b
, c
);
1156 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1158 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1159 b
.full
= dfixed_const(1000);
1160 c
.full
= dfixed_const(lb_fill_bw
);
1161 b
.full
= dfixed_div(c
, b
);
1162 a
.full
= dfixed_div(a
, b
);
1163 line_fill_time
= dfixed_trunc(a
);
1165 if (line_fill_time
< wm
->active_time
)
1168 return latency
+ (line_fill_time
- wm
->active_time
);
1173 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1174 * average and available dram bandwidth
1176 * @wm: watermark calculation data
1178 * Check if the display average bandwidth fits in the display
1179 * dram bandwidth (CIK).
1180 * Used for display watermark bandwidth calculations
1181 * Returns true if the display fits, false if not.
1183 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
1185 if (dce_v11_0_average_bandwidth(wm
) <=
1186 (dce_v11_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1193 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1194 * average and available bandwidth
1196 * @wm: watermark calculation data
1198 * Check if the display average bandwidth fits in the display
1199 * available bandwidth (CIK).
1200 * Used for display watermark bandwidth calculations
1201 * Returns true if the display fits, false if not.
1203 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params
*wm
)
1205 if (dce_v11_0_average_bandwidth(wm
) <=
1206 (dce_v11_0_available_bandwidth(wm
) / wm
->num_heads
))
1213 * dce_v11_0_check_latency_hiding - check latency hiding
1215 * @wm: watermark calculation data
1217 * Check latency hiding (CIK).
1218 * Used for display watermark bandwidth calculations
1219 * Returns true if the display fits, false if not.
1221 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params
*wm
)
1223 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1224 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1225 u32 latency_tolerant_lines
;
1229 a
.full
= dfixed_const(1);
1230 if (wm
->vsc
.full
> a
.full
)
1231 latency_tolerant_lines
= 1;
1233 if (lb_partitions
<= (wm
->vtaps
+ 1))
1234 latency_tolerant_lines
= 1;
1236 latency_tolerant_lines
= 2;
1239 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1241 if (dce_v11_0_latency_watermark(wm
) <= latency_hiding
)
1248 * dce_v11_0_program_watermarks - program display watermarks
1250 * @adev: amdgpu_device pointer
1251 * @amdgpu_crtc: the selected display controller
1252 * @lb_size: line buffer size
1253 * @num_heads: number of display controllers in use
1255 * Calculate and program the display watermarks for the
1256 * selected display controller (CIK).
1258 static void dce_v11_0_program_watermarks(struct amdgpu_device
*adev
,
1259 struct amdgpu_crtc
*amdgpu_crtc
,
1260 u32 lb_size
, u32 num_heads
)
1262 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1263 struct dce10_wm_params wm_low
, wm_high
;
1266 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1267 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1269 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1270 pixel_period
= 1000000 / (u32
)mode
->clock
;
1271 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1273 /* watermark for high clocks */
1274 if (adev
->pm
.dpm_enabled
) {
1276 amdgpu_dpm_get_mclk(adev
, false) * 10;
1278 amdgpu_dpm_get_sclk(adev
, false) * 10;
1280 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1281 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1284 wm_high
.disp_clk
= mode
->clock
;
1285 wm_high
.src_width
= mode
->crtc_hdisplay
;
1286 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1287 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1288 wm_high
.interlaced
= false;
1289 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1290 wm_high
.interlaced
= true;
1291 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1293 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1295 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1296 wm_high
.lb_size
= lb_size
;
1297 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1298 wm_high
.num_heads
= num_heads
;
1300 /* set for high clocks */
1301 latency_watermark_a
= min(dce_v11_0_latency_watermark(&wm_high
), (u32
)65535);
1303 /* possibly force display priority to high */
1304 /* should really do this at mode validation time... */
1305 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1306 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1307 !dce_v11_0_check_latency_hiding(&wm_high
) ||
1308 (adev
->mode_info
.disp_priority
== 2)) {
1309 DRM_DEBUG_KMS("force priority to high\n");
1312 /* watermark for low clocks */
1313 if (adev
->pm
.dpm_enabled
) {
1315 amdgpu_dpm_get_mclk(adev
, true) * 10;
1317 amdgpu_dpm_get_sclk(adev
, true) * 10;
1319 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1320 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1323 wm_low
.disp_clk
= mode
->clock
;
1324 wm_low
.src_width
= mode
->crtc_hdisplay
;
1325 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1326 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1327 wm_low
.interlaced
= false;
1328 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1329 wm_low
.interlaced
= true;
1330 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1332 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1334 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1335 wm_low
.lb_size
= lb_size
;
1336 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1337 wm_low
.num_heads
= num_heads
;
1339 /* set for low clocks */
1340 latency_watermark_b
= min(dce_v11_0_latency_watermark(&wm_low
), (u32
)65535);
1342 /* possibly force display priority to high */
1343 /* should really do this at mode validation time... */
1344 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1345 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1346 !dce_v11_0_check_latency_hiding(&wm_low
) ||
1347 (adev
->mode_info
.disp_priority
== 2)) {
1348 DRM_DEBUG_KMS("force priority to high\n");
1350 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1354 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1355 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 1);
1356 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1357 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1358 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1359 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1360 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1362 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 2);
1363 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1364 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1365 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_b
);
1366 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1367 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1368 /* restore original selection */
1369 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1371 /* save values for DPM */
1372 amdgpu_crtc
->line_time
= line_time
;
1373 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1374 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1375 /* Save number of lines the linebuffer leads before the scanout */
1376 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1380 * dce_v11_0_bandwidth_update - program display watermarks
1382 * @adev: amdgpu_device pointer
1384 * Calculate and program the display watermarks and line
1385 * buffer allocation (CIK).
1387 static void dce_v11_0_bandwidth_update(struct amdgpu_device
*adev
)
1389 struct drm_display_mode
*mode
= NULL
;
1390 u32 num_heads
= 0, lb_size
;
1393 amdgpu_update_display_priority(adev
);
1395 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1396 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1399 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1400 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1401 lb_size
= dce_v11_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1402 dce_v11_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1403 lb_size
, num_heads
);
1407 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1412 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1413 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1414 tmp
= RREG32_AUDIO_ENDPT(offset
,
1415 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1417 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1418 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1419 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1421 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1425 static struct amdgpu_audio_pin
*dce_v11_0_audio_get_pin(struct amdgpu_device
*adev
)
1429 dce_v11_0_audio_get_connected_pins(adev
);
1431 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1432 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1433 return &adev
->mode_info
.audio
.pin
[i
];
1435 DRM_ERROR("No connected audio pins found!\n");
1439 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1441 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1442 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1443 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1446 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1449 tmp
= RREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
);
1450 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_SRC_CONTROL
, AFMT_AUDIO_SRC_SELECT
, dig
->afmt
->pin
->id
);
1451 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
, tmp
);
1454 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1455 struct drm_display_mode
*mode
)
1457 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1458 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1459 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1460 struct drm_connector
*connector
;
1461 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1465 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1468 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1469 if (connector
->encoder
== encoder
) {
1470 amdgpu_connector
= to_amdgpu_connector(connector
);
1475 if (!amdgpu_connector
) {
1476 DRM_ERROR("Couldn't find encoder's connector\n");
1480 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1482 if (connector
->latency_present
[interlace
]) {
1483 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1484 VIDEO_LIPSYNC
, connector
->video_latency
[interlace
]);
1485 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1486 AUDIO_LIPSYNC
, connector
->audio_latency
[interlace
]);
1488 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1490 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1493 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1494 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1497 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1499 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1500 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1501 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1502 struct drm_connector
*connector
;
1503 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1508 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1511 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1512 if (connector
->encoder
== encoder
) {
1513 amdgpu_connector
= to_amdgpu_connector(connector
);
1518 if (!amdgpu_connector
) {
1519 DRM_ERROR("Couldn't find encoder's connector\n");
1523 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1524 if (sad_count
< 0) {
1525 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1529 /* program the speaker allocation */
1530 tmp
= RREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1531 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1532 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1535 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1536 HDMI_CONNECTION
, 1);
1538 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1539 SPEAKER_ALLOCATION
, sadb
[0]);
1541 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1542 SPEAKER_ALLOCATION
, 5); /* stereo */
1543 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1544 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1549 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1551 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1552 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1553 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1554 struct drm_connector
*connector
;
1555 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1556 struct cea_sad
*sads
;
1559 static const u16 eld_reg_to_type
[][2] = {
1560 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1561 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1562 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1563 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1564 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1565 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1566 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1567 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1568 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1569 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1570 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1571 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1574 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1577 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1578 if (connector
->encoder
== encoder
) {
1579 amdgpu_connector
= to_amdgpu_connector(connector
);
1584 if (!amdgpu_connector
) {
1585 DRM_ERROR("Couldn't find encoder's connector\n");
1589 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1590 if (sad_count
<= 0) {
1591 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1596 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1598 u8 stereo_freqs
= 0;
1599 int max_channels
= -1;
1602 for (j
= 0; j
< sad_count
; j
++) {
1603 struct cea_sad
*sad
= &sads
[j
];
1605 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1606 if (sad
->channels
> max_channels
) {
1607 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1608 MAX_CHANNELS
, sad
->channels
);
1609 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1610 DESCRIPTOR_BYTE_2
, sad
->byte2
);
1611 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1612 SUPPORTED_FREQUENCIES
, sad
->freq
);
1613 max_channels
= sad
->channels
;
1616 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1617 stereo_freqs
|= sad
->freq
;
1623 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1624 SUPPORTED_FREQUENCIES_STEREO
, stereo_freqs
);
1625 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
, eld_reg_to_type
[i
][0], tmp
);
1631 static void dce_v11_0_audio_enable(struct amdgpu_device
*adev
,
1632 struct amdgpu_audio_pin
*pin
,
1638 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1639 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1642 static const u32 pin_offsets
[] =
1644 AUD0_REGISTER_OFFSET
,
1645 AUD1_REGISTER_OFFSET
,
1646 AUD2_REGISTER_OFFSET
,
1647 AUD3_REGISTER_OFFSET
,
1648 AUD4_REGISTER_OFFSET
,
1649 AUD5_REGISTER_OFFSET
,
1650 AUD6_REGISTER_OFFSET
,
1651 AUD7_REGISTER_OFFSET
,
1654 static int dce_v11_0_audio_init(struct amdgpu_device
*adev
)
1661 adev
->mode_info
.audio
.enabled
= true;
1663 switch (adev
->asic_type
) {
1666 adev
->mode_info
.audio
.num_pins
= 7;
1668 case CHIP_POLARIS10
:
1669 adev
->mode_info
.audio
.num_pins
= 8;
1671 case CHIP_POLARIS11
:
1672 adev
->mode_info
.audio
.num_pins
= 6;
1678 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1679 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1680 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1681 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1682 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1683 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1684 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1685 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1686 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1687 /* disable audio. it will be set up later */
1688 /* XXX remove once we switch to ip funcs */
1689 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1695 static void dce_v11_0_audio_fini(struct amdgpu_device
*adev
)
1702 if (!adev
->mode_info
.audio
.enabled
)
1705 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1706 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1708 adev
->mode_info
.audio
.enabled
= false;
1712 * update the N and CTS parameters for a given pixel clock rate
1714 static void dce_v11_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1716 struct drm_device
*dev
= encoder
->dev
;
1717 struct amdgpu_device
*adev
= dev
->dev_private
;
1718 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1719 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1720 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1723 tmp
= RREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
);
1724 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, acr
.cts_32khz
);
1725 WREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
, tmp
);
1726 tmp
= RREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
);
1727 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_1
, HDMI_ACR_N_32
, acr
.n_32khz
);
1728 WREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
, tmp
);
1730 tmp
= RREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
);
1731 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, acr
.cts_44_1khz
);
1732 WREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
, tmp
);
1733 tmp
= RREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
);
1734 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_1
, HDMI_ACR_N_44
, acr
.n_44_1khz
);
1735 WREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
, tmp
);
1737 tmp
= RREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
);
1738 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, acr
.cts_48khz
);
1739 WREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
, tmp
);
1740 tmp
= RREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
);
1741 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_1
, HDMI_ACR_N_48
, acr
.n_48khz
);
1742 WREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
, tmp
);
1747 * build a HDMI Video Info Frame
1749 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1750 void *buffer
, size_t size
)
1752 struct drm_device
*dev
= encoder
->dev
;
1753 struct amdgpu_device
*adev
= dev
->dev_private
;
1754 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1755 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1756 uint8_t *frame
= buffer
+ 3;
1757 uint8_t *header
= buffer
;
1759 WREG32(mmAFMT_AVI_INFO0
+ dig
->afmt
->offset
,
1760 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1761 WREG32(mmAFMT_AVI_INFO1
+ dig
->afmt
->offset
,
1762 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1763 WREG32(mmAFMT_AVI_INFO2
+ dig
->afmt
->offset
,
1764 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1765 WREG32(mmAFMT_AVI_INFO3
+ dig
->afmt
->offset
,
1766 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1769 static void dce_v11_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1771 struct drm_device
*dev
= encoder
->dev
;
1772 struct amdgpu_device
*adev
= dev
->dev_private
;
1773 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1774 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1775 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1776 u32 dto_phase
= 24 * 1000;
1777 u32 dto_modulo
= clock
;
1780 if (!dig
|| !dig
->afmt
)
1783 /* XXX two dtos; generally use dto0 for hdmi */
1784 /* Express [24MHz / target pixel clock] as an exact rational
1785 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1786 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1788 tmp
= RREG32(mmDCCG_AUDIO_DTO_SOURCE
);
1789 tmp
= REG_SET_FIELD(tmp
, DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL
,
1790 amdgpu_crtc
->crtc_id
);
1791 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, tmp
);
1792 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1793 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1797 * update the info frames with the data from the current display mode
1799 static void dce_v11_0_afmt_setmode(struct drm_encoder
*encoder
,
1800 struct drm_display_mode
*mode
)
1802 struct drm_device
*dev
= encoder
->dev
;
1803 struct amdgpu_device
*adev
= dev
->dev_private
;
1804 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1805 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1806 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1807 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1808 struct hdmi_avi_infoframe frame
;
1813 if (!dig
|| !dig
->afmt
)
1816 /* Silent, r600_hdmi_enable will raise WARN for us */
1817 if (!dig
->afmt
->enabled
)
1820 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1821 if (encoder
->crtc
) {
1822 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1823 bpc
= amdgpu_crtc
->bpc
;
1826 /* disable audio prior to setting up hw */
1827 dig
->afmt
->pin
= dce_v11_0_audio_get_pin(adev
);
1828 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1830 dce_v11_0_audio_set_dto(encoder
, mode
->clock
);
1832 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1833 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1);
1834 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
); /* send null packets when required */
1836 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ dig
->afmt
->offset
, 0x1000);
1838 tmp
= RREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
);
1845 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 0);
1846 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
1847 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1848 connector
->name
, bpc
);
1851 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1852 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 1);
1853 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1857 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1858 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 2);
1859 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1863 WREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
, tmp
);
1865 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1866 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1); /* send null packets when required */
1867 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_SEND
, 1); /* send general control packets */
1868 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_CONT
, 1); /* send general control packets every frame */
1869 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1871 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1872 /* enable audio info frames (frames won't be set until audio is enabled) */
1873 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
1874 /* required for audio info values to be updated */
1875 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_CONT
, 1);
1876 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1878 tmp
= RREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1879 /* required for audio info values to be updated */
1880 tmp
= REG_SET_FIELD(tmp
, AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1881 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1883 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1884 /* anything other than 0 */
1885 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
, 2);
1886 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1888 WREG32(mmHDMI_GC
+ dig
->afmt
->offset
, 0); /* unset HDMI_GC_AVMUTE */
1890 tmp
= RREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1891 /* set the default audio delay */
1892 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_DELAY_EN
, 1);
1893 /* should be suffient for all audio modes and small enough for all hblanks */
1894 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_PACKETS_PER_LINE
, 3);
1895 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1897 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1898 /* allow 60958 channel status fields to be updated */
1899 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1900 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1902 tmp
= RREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
);
1904 /* clear SW CTS value */
1905 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 0);
1907 /* select SW CTS value */
1908 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 1);
1909 /* allow hw to sent ACR packets when required */
1910 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_AUTO_SEND
, 1);
1911 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1913 dce_v11_0_afmt_update_ACR(encoder
, mode
->clock
);
1915 tmp
= RREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
);
1916 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_0
, AFMT_60958_CS_CHANNEL_NUMBER_L
, 1);
1917 WREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
, tmp
);
1919 tmp
= RREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
);
1920 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1921 WREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
, tmp
);
1923 tmp
= RREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
);
1924 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_2
, 3);
1925 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_3
, 4);
1926 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_4
, 5);
1927 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_5
, 6);
1928 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_6
, 7);
1929 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1930 WREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
, tmp
);
1932 dce_v11_0_audio_write_speaker_allocation(encoder
);
1934 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ dig
->afmt
->offset
,
1935 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1937 dce_v11_0_afmt_audio_select_pin(encoder
);
1938 dce_v11_0_audio_write_sad_regs(encoder
);
1939 dce_v11_0_audio_write_latency_fields(encoder
, mode
);
1941 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1943 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1947 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1949 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1953 dce_v11_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1955 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1956 /* enable AVI info frames */
1957 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_SEND
, 1);
1958 /* required for audio info values to be updated */
1959 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_CONT
, 1);
1960 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1962 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1963 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
, 2);
1964 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1966 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1967 /* send audio packets */
1968 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, 1);
1969 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1971 WREG32(mmAFMT_RAMP_CONTROL0
+ dig
->afmt
->offset
, 0x00FFFFFF);
1972 WREG32(mmAFMT_RAMP_CONTROL1
+ dig
->afmt
->offset
, 0x007FFFFF);
1973 WREG32(mmAFMT_RAMP_CONTROL2
+ dig
->afmt
->offset
, 0x00000001);
1974 WREG32(mmAFMT_RAMP_CONTROL3
+ dig
->afmt
->offset
, 0x00000001);
1976 /* enable audio after to setting up hw */
1977 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1980 static void dce_v11_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1982 struct drm_device
*dev
= encoder
->dev
;
1983 struct amdgpu_device
*adev
= dev
->dev_private
;
1984 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1985 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1987 if (!dig
|| !dig
->afmt
)
1990 /* Silent, r600_hdmi_enable will raise WARN for us */
1991 if (enable
&& dig
->afmt
->enabled
)
1993 if (!enable
&& !dig
->afmt
->enabled
)
1996 if (!enable
&& dig
->afmt
->pin
) {
1997 dce_v11_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1998 dig
->afmt
->pin
= NULL
;
2001 dig
->afmt
->enabled
= enable
;
2003 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
2004 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
2007 static int dce_v11_0_afmt_init(struct amdgpu_device
*adev
)
2011 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
2012 adev
->mode_info
.afmt
[i
] = NULL
;
2014 /* DCE11 has audio blocks tied to DIG encoders */
2015 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
2016 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
2017 if (adev
->mode_info
.afmt
[i
]) {
2018 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
2019 adev
->mode_info
.afmt
[i
]->id
= i
;
2022 for (j
= 0; j
< i
; j
++) {
2023 kfree(adev
->mode_info
.afmt
[j
]);
2024 adev
->mode_info
.afmt
[j
] = NULL
;
2032 static void dce_v11_0_afmt_fini(struct amdgpu_device
*adev
)
2036 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
2037 kfree(adev
->mode_info
.afmt
[i
]);
2038 adev
->mode_info
.afmt
[i
] = NULL
;
2042 static const u32 vga_control_regs
[6] =
2052 static void dce_v11_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
2054 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2055 struct drm_device
*dev
= crtc
->dev
;
2056 struct amdgpu_device
*adev
= dev
->dev_private
;
2059 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
2061 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
2063 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
2066 static void dce_v11_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
2068 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2069 struct drm_device
*dev
= crtc
->dev
;
2070 struct amdgpu_device
*adev
= dev
->dev_private
;
2073 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
2075 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
2078 static int dce_v11_0_crtc_do_set_base(struct drm_crtc
*crtc
,
2079 struct drm_framebuffer
*fb
,
2080 int x
, int y
, int atomic
)
2082 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2083 struct drm_device
*dev
= crtc
->dev
;
2084 struct amdgpu_device
*adev
= dev
->dev_private
;
2085 struct amdgpu_framebuffer
*amdgpu_fb
;
2086 struct drm_framebuffer
*target_fb
;
2087 struct drm_gem_object
*obj
;
2088 struct amdgpu_bo
*rbo
;
2089 uint64_t fb_location
, tiling_flags
;
2090 uint32_t fb_format
, fb_pitch_pixels
;
2091 u32 fb_swap
= REG_SET_FIELD(0, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
, ENDIAN_NONE
);
2093 u32 tmp
, viewport_w
, viewport_h
;
2095 bool bypass_lut
= false;
2099 if (!atomic
&& !crtc
->primary
->fb
) {
2100 DRM_DEBUG_KMS("No FB bound\n");
2105 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2108 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2109 target_fb
= crtc
->primary
->fb
;
2112 /* If atomic, assume fb object is pinned & idle & fenced and
2113 * just update base pointers
2115 obj
= amdgpu_fb
->obj
;
2116 rbo
= gem_to_amdgpu_bo(obj
);
2117 r
= amdgpu_bo_reserve(rbo
, false);
2118 if (unlikely(r
!= 0))
2122 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2124 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2125 if (unlikely(r
!= 0)) {
2126 amdgpu_bo_unreserve(rbo
);
2131 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2132 amdgpu_bo_unreserve(rbo
);
2134 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2136 switch (target_fb
->pixel_format
) {
2138 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 0);
2139 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2141 case DRM_FORMAT_XRGB4444
:
2142 case DRM_FORMAT_ARGB4444
:
2143 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2144 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 2);
2146 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2150 case DRM_FORMAT_XRGB1555
:
2151 case DRM_FORMAT_ARGB1555
:
2152 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2153 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2155 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2159 case DRM_FORMAT_BGRX5551
:
2160 case DRM_FORMAT_BGRA5551
:
2161 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2162 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 5);
2164 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2168 case DRM_FORMAT_RGB565
:
2169 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2170 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2172 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2176 case DRM_FORMAT_XRGB8888
:
2177 case DRM_FORMAT_ARGB8888
:
2178 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2179 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2181 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2185 case DRM_FORMAT_XRGB2101010
:
2186 case DRM_FORMAT_ARGB2101010
:
2187 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2188 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2190 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2193 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2196 case DRM_FORMAT_BGRX1010102
:
2197 case DRM_FORMAT_BGRA1010102
:
2198 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2199 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 4);
2201 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2204 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2208 format_name
= drm_get_format_name(target_fb
->pixel_format
);
2209 DRM_ERROR("Unsupported screen format %s\n", format_name
);
2214 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2215 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2217 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2218 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2219 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2220 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2221 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2223 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_NUM_BANKS
, num_banks
);
2224 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2225 ARRAY_2D_TILED_THIN1
);
2226 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_TILE_SPLIT
,
2228 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_WIDTH
, bankw
);
2229 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_HEIGHT
, bankh
);
2230 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MACRO_TILE_ASPECT
,
2232 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MICRO_TILE_MODE
,
2233 ADDR_SURF_MICRO_TILING_DISPLAY
);
2234 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2235 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2236 ARRAY_1D_TILED_THIN1
);
2239 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_PIPE_CONFIG
,
2242 dce_v11_0_vga_enable(crtc
, false);
2244 /* Make sure surface address is updated at vertical blank rather than
2247 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2248 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
2249 GRPH_SURFACE_UPDATE_H_RETRACE_EN
, 0);
2250 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2252 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2253 upper_32_bits(fb_location
));
2254 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2255 upper_32_bits(fb_location
));
2256 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2257 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2258 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2259 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2260 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2261 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2264 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2265 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2266 * retain the full precision throughout the pipeline.
2268 tmp
= RREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
);
2270 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 1);
2272 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 0);
2273 WREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
, tmp
);
2276 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2278 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2279 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2280 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2281 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2282 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2283 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2285 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2286 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2288 dce_v11_0_grph_enable(crtc
, true);
2290 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2295 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2297 viewport_w
= crtc
->mode
.hdisplay
;
2298 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2299 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2300 (viewport_w
<< 16) | viewport_h
);
2302 /* set pageflip to happen anywhere in vblank interval */
2303 WREG32(mmCRTC_MASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2305 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2306 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2307 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2308 r
= amdgpu_bo_reserve(rbo
, false);
2309 if (unlikely(r
!= 0))
2311 amdgpu_bo_unpin(rbo
);
2312 amdgpu_bo_unreserve(rbo
);
2315 /* Bytes per pixel may have changed */
2316 dce_v11_0_bandwidth_update(adev
);
2321 static void dce_v11_0_set_interleave(struct drm_crtc
*crtc
,
2322 struct drm_display_mode
*mode
)
2324 struct drm_device
*dev
= crtc
->dev
;
2325 struct amdgpu_device
*adev
= dev
->dev_private
;
2326 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2329 tmp
= RREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
);
2330 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2331 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 1);
2333 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 0);
2334 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, tmp
);
2337 static void dce_v11_0_crtc_load_lut(struct drm_crtc
*crtc
)
2339 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2340 struct drm_device
*dev
= crtc
->dev
;
2341 struct amdgpu_device
*adev
= dev
->dev_private
;
2345 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2347 tmp
= RREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2348 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_GRPH_MODE
, 0);
2349 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2351 tmp
= RREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2352 tmp
= REG_SET_FIELD(tmp
, PRESCALE_GRPH_CONTROL
, GRPH_PRESCALE_BYPASS
, 1);
2353 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2355 tmp
= RREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2356 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, GRPH_INPUT_GAMMA_MODE
, 0);
2357 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2359 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2361 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2362 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2363 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2365 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2366 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2367 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2369 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2370 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2372 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2373 for (i
= 0; i
< 256; i
++) {
2374 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2375 (amdgpu_crtc
->lut_r
[i
] << 20) |
2376 (amdgpu_crtc
->lut_g
[i
] << 10) |
2377 (amdgpu_crtc
->lut_b
[i
] << 0));
2380 tmp
= RREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2381 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, GRPH_DEGAMMA_MODE
, 0);
2382 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR_DEGAMMA_MODE
, 0);
2383 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR2_DEGAMMA_MODE
, 0);
2384 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2386 tmp
= RREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2387 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, GRPH_GAMUT_REMAP_MODE
, 0);
2388 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2390 tmp
= RREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2391 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, GRPH_REGAMMA_MODE
, 0);
2392 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2394 tmp
= RREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2395 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_GRPH_MODE
, 0);
2396 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2398 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2399 WREG32(mmDENORM_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2400 /* XXX this only needs to be programmed once per crtc at startup,
2401 * not sure where the best place for it is
2403 tmp
= RREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2404 tmp
= REG_SET_FIELD(tmp
, ALPHA_CONTROL
, CURSOR_ALPHA_BLND_ENA
, 1);
2405 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2408 static int dce_v11_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2410 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2411 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2413 switch (amdgpu_encoder
->encoder_id
) {
2414 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2420 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2426 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2432 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2436 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2442 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2446 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2447 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2448 * monitors a dedicated PPLL must be used. If a particular board has
2449 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2450 * as there is no need to program the PLL itself. If we are not able to
2451 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2452 * avoid messing up an existing monitor.
2454 * Asic specific PLL information
2458 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2460 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2463 static u32
dce_v11_0_pick_pll(struct drm_crtc
*crtc
)
2465 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2466 struct drm_device
*dev
= crtc
->dev
;
2467 struct amdgpu_device
*adev
= dev
->dev_private
;
2471 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2472 (adev
->asic_type
== CHIP_POLARIS11
)) {
2473 struct amdgpu_encoder
*amdgpu_encoder
=
2474 to_amdgpu_encoder(amdgpu_crtc
->encoder
);
2475 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2477 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2480 switch (amdgpu_encoder
->encoder_id
) {
2481 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2483 return ATOM_COMBOPHY_PLL1
;
2485 return ATOM_COMBOPHY_PLL0
;
2487 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2489 return ATOM_COMBOPHY_PLL3
;
2491 return ATOM_COMBOPHY_PLL2
;
2493 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2495 return ATOM_COMBOPHY_PLL5
;
2497 return ATOM_COMBOPHY_PLL4
;
2500 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2501 return ATOM_PPLL_INVALID
;
2505 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2506 if (adev
->clock
.dp_extclk
)
2507 /* skip PPLL programming if using ext clock */
2508 return ATOM_PPLL_INVALID
;
2510 /* use the same PPLL for all DP monitors */
2511 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2512 if (pll
!= ATOM_PPLL_INVALID
)
2516 /* use the same PPLL for all monitors with the same clock */
2517 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2518 if (pll
!= ATOM_PPLL_INVALID
)
2522 /* XXX need to determine what plls are available on each DCE11 part */
2523 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2524 if (adev
->asic_type
== CHIP_CARRIZO
|| adev
->asic_type
== CHIP_STONEY
) {
2525 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2527 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2529 DRM_ERROR("unable to allocate a PPLL\n");
2530 return ATOM_PPLL_INVALID
;
2532 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2534 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2536 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2538 DRM_ERROR("unable to allocate a PPLL\n");
2539 return ATOM_PPLL_INVALID
;
2541 return ATOM_PPLL_INVALID
;
2544 static void dce_v11_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2546 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2547 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2550 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2552 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 1);
2554 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 0);
2555 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2558 static void dce_v11_0_hide_cursor(struct drm_crtc
*crtc
)
2560 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2561 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2564 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2565 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 0);
2566 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2569 static void dce_v11_0_show_cursor(struct drm_crtc
*crtc
)
2571 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2572 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2575 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2576 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2577 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2578 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2580 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2581 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 1);
2582 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_MODE
, 2);
2583 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2586 static int dce_v11_0_cursor_move_locked(struct drm_crtc
*crtc
,
2589 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2590 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2591 int xorigin
= 0, yorigin
= 0;
2593 /* avivo cursor are offset into the total surface */
2596 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2599 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2603 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2607 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2608 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2609 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2610 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2612 amdgpu_crtc
->cursor_x
= x
;
2613 amdgpu_crtc
->cursor_y
= y
;
2618 static int dce_v11_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2623 dce_v11_0_lock_cursor(crtc
, true);
2624 ret
= dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2625 dce_v11_0_lock_cursor(crtc
, false);
2630 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2631 struct drm_file
*file_priv
,
2638 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2639 struct drm_gem_object
*obj
;
2640 struct amdgpu_bo
*aobj
;
2644 /* turn off cursor */
2645 dce_v11_0_hide_cursor(crtc
);
2650 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2651 (height
> amdgpu_crtc
->max_cursor_height
)) {
2652 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2656 obj
= drm_gem_object_lookup(file_priv
, handle
);
2658 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2662 aobj
= gem_to_amdgpu_bo(obj
);
2663 ret
= amdgpu_bo_reserve(aobj
, false);
2665 drm_gem_object_unreference_unlocked(obj
);
2669 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
, &amdgpu_crtc
->cursor_addr
);
2670 amdgpu_bo_unreserve(aobj
);
2672 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2673 drm_gem_object_unreference_unlocked(obj
);
2677 amdgpu_crtc
->cursor_width
= width
;
2678 amdgpu_crtc
->cursor_height
= height
;
2680 dce_v11_0_lock_cursor(crtc
, true);
2682 if (hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2683 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2686 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2687 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2689 dce_v11_0_cursor_move_locked(crtc
, x
, y
);
2691 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2692 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2695 dce_v11_0_show_cursor(crtc
);
2696 dce_v11_0_lock_cursor(crtc
, false);
2699 if (amdgpu_crtc
->cursor_bo
) {
2700 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2701 ret
= amdgpu_bo_reserve(aobj
, false);
2702 if (likely(ret
== 0)) {
2703 amdgpu_bo_unpin(aobj
);
2704 amdgpu_bo_unreserve(aobj
);
2706 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2709 amdgpu_crtc
->cursor_bo
= obj
;
2713 static void dce_v11_0_cursor_reset(struct drm_crtc
*crtc
)
2715 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2717 if (amdgpu_crtc
->cursor_bo
) {
2718 dce_v11_0_lock_cursor(crtc
, true);
2720 dce_v11_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2721 amdgpu_crtc
->cursor_y
);
2723 dce_v11_0_show_cursor(crtc
);
2725 dce_v11_0_lock_cursor(crtc
, false);
2729 static int dce_v11_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2730 u16
*blue
, uint32_t size
)
2732 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2735 /* userspace palettes are always correct as is */
2736 for (i
= 0; i
< size
; i
++) {
2737 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2738 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2739 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2741 dce_v11_0_crtc_load_lut(crtc
);
2746 static void dce_v11_0_crtc_destroy(struct drm_crtc
*crtc
)
2748 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2750 drm_crtc_cleanup(crtc
);
2754 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs
= {
2755 .cursor_set2
= dce_v11_0_crtc_cursor_set2
,
2756 .cursor_move
= dce_v11_0_crtc_cursor_move
,
2757 .gamma_set
= dce_v11_0_crtc_gamma_set
,
2758 .set_config
= amdgpu_crtc_set_config
,
2759 .destroy
= dce_v11_0_crtc_destroy
,
2760 .page_flip_target
= amdgpu_crtc_page_flip_target
,
2763 static void dce_v11_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2765 struct drm_device
*dev
= crtc
->dev
;
2766 struct amdgpu_device
*adev
= dev
->dev_private
;
2767 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2771 case DRM_MODE_DPMS_ON
:
2772 amdgpu_crtc
->enabled
= true;
2773 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2774 dce_v11_0_vga_enable(crtc
, true);
2775 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2776 dce_v11_0_vga_enable(crtc
, false);
2777 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2778 type
= amdgpu_crtc_idx_to_irq_type(adev
, amdgpu_crtc
->crtc_id
);
2779 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2780 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2781 drm_crtc_vblank_on(crtc
);
2782 dce_v11_0_crtc_load_lut(crtc
);
2784 case DRM_MODE_DPMS_STANDBY
:
2785 case DRM_MODE_DPMS_SUSPEND
:
2786 case DRM_MODE_DPMS_OFF
:
2787 drm_crtc_vblank_off(crtc
);
2788 if (amdgpu_crtc
->enabled
) {
2789 dce_v11_0_vga_enable(crtc
, true);
2790 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2791 dce_v11_0_vga_enable(crtc
, false);
2793 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2794 amdgpu_crtc
->enabled
= false;
2797 /* adjust pm to dpms */
2798 amdgpu_pm_compute_clocks(adev
);
2801 static void dce_v11_0_crtc_prepare(struct drm_crtc
*crtc
)
2803 /* disable crtc pair power gating before programming */
2804 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2805 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2806 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2809 static void dce_v11_0_crtc_commit(struct drm_crtc
*crtc
)
2811 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2812 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2815 static void dce_v11_0_crtc_disable(struct drm_crtc
*crtc
)
2817 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2818 struct drm_device
*dev
= crtc
->dev
;
2819 struct amdgpu_device
*adev
= dev
->dev_private
;
2820 struct amdgpu_atom_ss ss
;
2823 dce_v11_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2824 if (crtc
->primary
->fb
) {
2826 struct amdgpu_framebuffer
*amdgpu_fb
;
2827 struct amdgpu_bo
*rbo
;
2829 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2830 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2831 r
= amdgpu_bo_reserve(rbo
, false);
2833 DRM_ERROR("failed to reserve rbo before unpin\n");
2835 amdgpu_bo_unpin(rbo
);
2836 amdgpu_bo_unreserve(rbo
);
2839 /* disable the GRPH */
2840 dce_v11_0_grph_enable(crtc
, false);
2842 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2844 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2845 if (adev
->mode_info
.crtcs
[i
] &&
2846 adev
->mode_info
.crtcs
[i
]->enabled
&&
2847 i
!= amdgpu_crtc
->crtc_id
&&
2848 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2849 /* one other crtc is using this pll don't turn
2856 switch (amdgpu_crtc
->pll_id
) {
2860 /* disable the ppll */
2861 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2862 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2864 case ATOM_COMBOPHY_PLL0
:
2865 case ATOM_COMBOPHY_PLL1
:
2866 case ATOM_COMBOPHY_PLL2
:
2867 case ATOM_COMBOPHY_PLL3
:
2868 case ATOM_COMBOPHY_PLL4
:
2869 case ATOM_COMBOPHY_PLL5
:
2870 /* disable the ppll */
2871 amdgpu_atombios_crtc_program_pll(crtc
, ATOM_CRTC_INVALID
, amdgpu_crtc
->pll_id
,
2872 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2878 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2879 amdgpu_crtc
->adjusted_clock
= 0;
2880 amdgpu_crtc
->encoder
= NULL
;
2881 amdgpu_crtc
->connector
= NULL
;
2884 static int dce_v11_0_crtc_mode_set(struct drm_crtc
*crtc
,
2885 struct drm_display_mode
*mode
,
2886 struct drm_display_mode
*adjusted_mode
,
2887 int x
, int y
, struct drm_framebuffer
*old_fb
)
2889 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2890 struct drm_device
*dev
= crtc
->dev
;
2891 struct amdgpu_device
*adev
= dev
->dev_private
;
2893 if (!amdgpu_crtc
->adjusted_clock
)
2896 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
2897 (adev
->asic_type
== CHIP_POLARIS11
)) {
2898 struct amdgpu_encoder
*amdgpu_encoder
=
2899 to_amdgpu_encoder(amdgpu_crtc
->encoder
);
2901 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
);
2903 /* SetPixelClock calculates the plls and ss values now */
2904 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
,
2905 amdgpu_crtc
->pll_id
,
2906 encoder_mode
, amdgpu_encoder
->encoder_id
,
2907 adjusted_mode
->clock
, 0, 0, 0, 0,
2908 amdgpu_crtc
->bpc
, amdgpu_crtc
->ss_enabled
, &amdgpu_crtc
->ss
);
2910 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2912 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2913 dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2914 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2915 amdgpu_atombios_crtc_scaler_setup(crtc
);
2916 dce_v11_0_cursor_reset(crtc
);
2917 /* update the hw version fpr dpm */
2918 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2923 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2924 const struct drm_display_mode
*mode
,
2925 struct drm_display_mode
*adjusted_mode
)
2927 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2928 struct drm_device
*dev
= crtc
->dev
;
2929 struct drm_encoder
*encoder
;
2931 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2932 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2933 if (encoder
->crtc
== crtc
) {
2934 amdgpu_crtc
->encoder
= encoder
;
2935 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2939 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2940 amdgpu_crtc
->encoder
= NULL
;
2941 amdgpu_crtc
->connector
= NULL
;
2944 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2946 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2949 amdgpu_crtc
->pll_id
= dce_v11_0_pick_pll(crtc
);
2950 /* if we can't get a PPLL for a non-DP encoder, fail */
2951 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2952 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2958 static int dce_v11_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2959 struct drm_framebuffer
*old_fb
)
2961 return dce_v11_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2964 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2965 struct drm_framebuffer
*fb
,
2966 int x
, int y
, enum mode_set_atomic state
)
2968 return dce_v11_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2971 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs
= {
2972 .dpms
= dce_v11_0_crtc_dpms
,
2973 .mode_fixup
= dce_v11_0_crtc_mode_fixup
,
2974 .mode_set
= dce_v11_0_crtc_mode_set
,
2975 .mode_set_base
= dce_v11_0_crtc_set_base
,
2976 .mode_set_base_atomic
= dce_v11_0_crtc_set_base_atomic
,
2977 .prepare
= dce_v11_0_crtc_prepare
,
2978 .commit
= dce_v11_0_crtc_commit
,
2979 .load_lut
= dce_v11_0_crtc_load_lut
,
2980 .disable
= dce_v11_0_crtc_disable
,
2983 static int dce_v11_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2985 struct amdgpu_crtc
*amdgpu_crtc
;
2988 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2989 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2990 if (amdgpu_crtc
== NULL
)
2993 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v11_0_crtc_funcs
);
2995 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2996 amdgpu_crtc
->crtc_id
= index
;
2997 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2999 amdgpu_crtc
->max_cursor_width
= 128;
3000 amdgpu_crtc
->max_cursor_height
= 128;
3001 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
3002 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
3004 for (i
= 0; i
< 256; i
++) {
3005 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
3006 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
3007 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
3010 switch (amdgpu_crtc
->crtc_id
) {
3013 amdgpu_crtc
->crtc_offset
= CRTC0_REGISTER_OFFSET
;
3016 amdgpu_crtc
->crtc_offset
= CRTC1_REGISTER_OFFSET
;
3019 amdgpu_crtc
->crtc_offset
= CRTC2_REGISTER_OFFSET
;
3022 amdgpu_crtc
->crtc_offset
= CRTC3_REGISTER_OFFSET
;
3025 amdgpu_crtc
->crtc_offset
= CRTC4_REGISTER_OFFSET
;
3028 amdgpu_crtc
->crtc_offset
= CRTC5_REGISTER_OFFSET
;
3032 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
3033 amdgpu_crtc
->adjusted_clock
= 0;
3034 amdgpu_crtc
->encoder
= NULL
;
3035 amdgpu_crtc
->connector
= NULL
;
3036 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v11_0_crtc_helper_funcs
);
3041 static int dce_v11_0_early_init(void *handle
)
3043 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3045 adev
->audio_endpt_rreg
= &dce_v11_0_audio_endpt_rreg
;
3046 adev
->audio_endpt_wreg
= &dce_v11_0_audio_endpt_wreg
;
3048 dce_v11_0_set_display_funcs(adev
);
3049 dce_v11_0_set_irq_funcs(adev
);
3051 adev
->mode_info
.num_crtc
= dce_v11_0_get_num_crtc(adev
);
3053 switch (adev
->asic_type
) {
3055 adev
->mode_info
.num_hpd
= 6;
3056 adev
->mode_info
.num_dig
= 9;
3059 adev
->mode_info
.num_hpd
= 6;
3060 adev
->mode_info
.num_dig
= 9;
3062 case CHIP_POLARIS10
:
3063 adev
->mode_info
.num_hpd
= 6;
3064 adev
->mode_info
.num_dig
= 6;
3066 case CHIP_POLARIS11
:
3067 adev
->mode_info
.num_hpd
= 5;
3068 adev
->mode_info
.num_dig
= 5;
3071 /* FIXME: not supported yet */
3078 static int dce_v11_0_sw_init(void *handle
)
3081 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3083 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
3084 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
3089 for (i
= 8; i
< 20; i
+= 2) {
3090 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
3096 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
3100 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
3102 adev
->ddev
->mode_config
.async_page_flip
= true;
3104 adev
->ddev
->mode_config
.max_width
= 16384;
3105 adev
->ddev
->mode_config
.max_height
= 16384;
3107 adev
->ddev
->mode_config
.preferred_depth
= 24;
3108 adev
->ddev
->mode_config
.prefer_shadow
= 1;
3110 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
3112 r
= amdgpu_modeset_create_props(adev
);
3116 adev
->ddev
->mode_config
.max_width
= 16384;
3117 adev
->ddev
->mode_config
.max_height
= 16384;
3120 /* allocate crtcs */
3121 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
3122 r
= dce_v11_0_crtc_init(adev
, i
);
3127 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
3128 amdgpu_print_display_setup(adev
->ddev
);
3133 r
= dce_v11_0_afmt_init(adev
);
3137 r
= dce_v11_0_audio_init(adev
);
3141 drm_kms_helper_poll_init(adev
->ddev
);
3143 adev
->mode_info
.mode_config_initialized
= true;
3147 static int dce_v11_0_sw_fini(void *handle
)
3149 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3151 kfree(adev
->mode_info
.bios_hardcoded_edid
);
3153 drm_kms_helper_poll_fini(adev
->ddev
);
3155 dce_v11_0_audio_fini(adev
);
3157 dce_v11_0_afmt_fini(adev
);
3159 adev
->mode_info
.mode_config_initialized
= false;
3164 static int dce_v11_0_hw_init(void *handle
)
3167 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3169 dce_v11_0_init_golden_registers(adev
);
3171 /* init dig PHYs, disp eng pll */
3172 amdgpu_atombios_crtc_powergate_init(adev
);
3173 amdgpu_atombios_encoder_init_dig(adev
);
3174 if ((adev
->asic_type
== CHIP_POLARIS10
) ||
3175 (adev
->asic_type
== CHIP_POLARIS11
)) {
3176 amdgpu_atombios_crtc_set_dce_clock(adev
, adev
->clock
.default_dispclk
,
3177 DCE_CLOCK_TYPE_DISPCLK
, ATOM_GCK_DFS
);
3178 amdgpu_atombios_crtc_set_dce_clock(adev
, 0,
3179 DCE_CLOCK_TYPE_DPREFCLK
, ATOM_GCK_DFS
);
3181 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
3184 /* initialize hpd */
3185 dce_v11_0_hpd_init(adev
);
3187 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3188 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3191 dce_v11_0_pageflip_interrupt_init(adev
);
3196 static int dce_v11_0_hw_fini(void *handle
)
3199 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3201 dce_v11_0_hpd_fini(adev
);
3203 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3204 dce_v11_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3207 dce_v11_0_pageflip_interrupt_fini(adev
);
3212 static int dce_v11_0_suspend(void *handle
)
3214 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3216 amdgpu_atombios_scratch_regs_save(adev
);
3218 return dce_v11_0_hw_fini(handle
);
3221 static int dce_v11_0_resume(void *handle
)
3223 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3226 ret
= dce_v11_0_hw_init(handle
);
3228 amdgpu_atombios_scratch_regs_restore(adev
);
3230 /* turn on the BL */
3231 if (adev
->mode_info
.bl_encoder
) {
3232 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3233 adev
->mode_info
.bl_encoder
);
3234 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3241 static bool dce_v11_0_is_idle(void *handle
)
3246 static int dce_v11_0_wait_for_idle(void *handle
)
3251 static int dce_v11_0_soft_reset(void *handle
)
3253 u32 srbm_soft_reset
= 0, tmp
;
3254 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3256 if (dce_v11_0_is_display_hung(adev
))
3257 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3259 if (srbm_soft_reset
) {
3260 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3261 tmp
|= srbm_soft_reset
;
3262 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3263 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3264 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3268 tmp
&= ~srbm_soft_reset
;
3269 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3270 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3272 /* Wait a little for things to settle down */
3278 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3280 enum amdgpu_interrupt_state state
)
3282 u32 lb_interrupt_mask
;
3284 if (crtc
>= adev
->mode_info
.num_crtc
) {
3285 DRM_DEBUG("invalid crtc %d\n", crtc
);
3290 case AMDGPU_IRQ_STATE_DISABLE
:
3291 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3292 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3293 VBLANK_INTERRUPT_MASK
, 0);
3294 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3296 case AMDGPU_IRQ_STATE_ENABLE
:
3297 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3298 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3299 VBLANK_INTERRUPT_MASK
, 1);
3300 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3307 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3309 enum amdgpu_interrupt_state state
)
3311 u32 lb_interrupt_mask
;
3313 if (crtc
>= adev
->mode_info
.num_crtc
) {
3314 DRM_DEBUG("invalid crtc %d\n", crtc
);
3319 case AMDGPU_IRQ_STATE_DISABLE
:
3320 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3321 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3322 VLINE_INTERRUPT_MASK
, 0);
3323 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3325 case AMDGPU_IRQ_STATE_ENABLE
:
3326 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3327 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3328 VLINE_INTERRUPT_MASK
, 1);
3329 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3336 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device
*adev
,
3337 struct amdgpu_irq_src
*source
,
3339 enum amdgpu_interrupt_state state
)
3343 if (hpd
>= adev
->mode_info
.num_hpd
) {
3344 DRM_DEBUG("invalid hdp %d\n", hpd
);
3349 case AMDGPU_IRQ_STATE_DISABLE
:
3350 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3351 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
3352 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3354 case AMDGPU_IRQ_STATE_ENABLE
:
3355 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3356 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 1);
3357 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3366 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device
*adev
,
3367 struct amdgpu_irq_src
*source
,
3369 enum amdgpu_interrupt_state state
)
3372 case AMDGPU_CRTC_IRQ_VBLANK1
:
3373 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3375 case AMDGPU_CRTC_IRQ_VBLANK2
:
3376 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3378 case AMDGPU_CRTC_IRQ_VBLANK3
:
3379 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3381 case AMDGPU_CRTC_IRQ_VBLANK4
:
3382 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3384 case AMDGPU_CRTC_IRQ_VBLANK5
:
3385 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3387 case AMDGPU_CRTC_IRQ_VBLANK6
:
3388 dce_v11_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3390 case AMDGPU_CRTC_IRQ_VLINE1
:
3391 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3393 case AMDGPU_CRTC_IRQ_VLINE2
:
3394 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3396 case AMDGPU_CRTC_IRQ_VLINE3
:
3397 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3399 case AMDGPU_CRTC_IRQ_VLINE4
:
3400 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3402 case AMDGPU_CRTC_IRQ_VLINE5
:
3403 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3405 case AMDGPU_CRTC_IRQ_VLINE6
:
3406 dce_v11_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3414 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device
*adev
,
3415 struct amdgpu_irq_src
*src
,
3417 enum amdgpu_interrupt_state state
)
3421 if (type
>= adev
->mode_info
.num_crtc
) {
3422 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3426 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3427 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3428 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3429 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3431 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3432 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3437 static int dce_v11_0_pageflip_irq(struct amdgpu_device
*adev
,
3438 struct amdgpu_irq_src
*source
,
3439 struct amdgpu_iv_entry
*entry
)
3441 unsigned long flags
;
3443 struct amdgpu_crtc
*amdgpu_crtc
;
3444 struct amdgpu_flip_work
*works
;
3446 crtc_id
= (entry
->src_id
- 8) >> 1;
3447 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3449 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3450 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3454 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3455 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3456 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3457 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3459 /* IRQ could occur when in initial stage */
3460 if(amdgpu_crtc
== NULL
)
3463 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3464 works
= amdgpu_crtc
->pflip_works
;
3465 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3466 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3467 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3468 amdgpu_crtc
->pflip_status
,
3469 AMDGPU_FLIP_SUBMITTED
);
3470 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3474 /* page flip completed. clean up */
3475 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3476 amdgpu_crtc
->pflip_works
= NULL
;
3478 /* wakeup usersapce */
3480 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, works
->event
);
3482 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3484 drm_crtc_vblank_put(&amdgpu_crtc
->base
);
3485 schedule_work(&works
->unpin_work
);
3490 static void dce_v11_0_hpd_int_ack(struct amdgpu_device
*adev
,
3495 if (hpd
>= adev
->mode_info
.num_hpd
) {
3496 DRM_DEBUG("invalid hdp %d\n", hpd
);
3500 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3501 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_ACK
, 1);
3502 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3505 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device
*adev
,
3510 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
3511 DRM_DEBUG("invalid crtc %d\n", crtc
);
3515 tmp
= RREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
]);
3516 tmp
= REG_SET_FIELD(tmp
, LB_VBLANK_STATUS
, VBLANK_ACK
, 1);
3517 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], tmp
);
3520 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device
*adev
,
3525 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
3526 DRM_DEBUG("invalid crtc %d\n", crtc
);
3530 tmp
= RREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
]);
3531 tmp
= REG_SET_FIELD(tmp
, LB_VLINE_STATUS
, VLINE_ACK
, 1);
3532 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], tmp
);
3535 static int dce_v11_0_crtc_irq(struct amdgpu_device
*adev
,
3536 struct amdgpu_irq_src
*source
,
3537 struct amdgpu_iv_entry
*entry
)
3539 unsigned crtc
= entry
->src_id
- 1;
3540 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3541 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3543 switch (entry
->src_data
) {
3544 case 0: /* vblank */
3545 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3546 dce_v11_0_crtc_vblank_int_ack(adev
, crtc
);
3548 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3550 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3551 drm_handle_vblank(adev
->ddev
, crtc
);
3553 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3557 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3558 dce_v11_0_crtc_vline_int_ack(adev
, crtc
);
3560 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3562 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3566 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3573 static int dce_v11_0_hpd_irq(struct amdgpu_device
*adev
,
3574 struct amdgpu_irq_src
*source
,
3575 struct amdgpu_iv_entry
*entry
)
3577 uint32_t disp_int
, mask
;
3580 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3581 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3585 hpd
= entry
->src_data
;
3586 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3587 mask
= interrupt_status_offsets
[hpd
].hpd
;
3589 if (disp_int
& mask
) {
3590 dce_v11_0_hpd_int_ack(adev
, hpd
);
3591 schedule_work(&adev
->hotplug_work
);
3592 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3598 static int dce_v11_0_set_clockgating_state(void *handle
,
3599 enum amd_clockgating_state state
)
3604 static int dce_v11_0_set_powergating_state(void *handle
,
3605 enum amd_powergating_state state
)
3610 const struct amd_ip_funcs dce_v11_0_ip_funcs
= {
3611 .name
= "dce_v11_0",
3612 .early_init
= dce_v11_0_early_init
,
3614 .sw_init
= dce_v11_0_sw_init
,
3615 .sw_fini
= dce_v11_0_sw_fini
,
3616 .hw_init
= dce_v11_0_hw_init
,
3617 .hw_fini
= dce_v11_0_hw_fini
,
3618 .suspend
= dce_v11_0_suspend
,
3619 .resume
= dce_v11_0_resume
,
3620 .is_idle
= dce_v11_0_is_idle
,
3621 .wait_for_idle
= dce_v11_0_wait_for_idle
,
3622 .soft_reset
= dce_v11_0_soft_reset
,
3623 .set_clockgating_state
= dce_v11_0_set_clockgating_state
,
3624 .set_powergating_state
= dce_v11_0_set_powergating_state
,
3628 dce_v11_0_encoder_mode_set(struct drm_encoder
*encoder
,
3629 struct drm_display_mode
*mode
,
3630 struct drm_display_mode
*adjusted_mode
)
3632 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3634 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3636 /* need to call this here rather than in prepare() since we need some crtc info */
3637 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3639 /* set scaler clears this on some chips */
3640 dce_v11_0_set_interleave(encoder
->crtc
, mode
);
3642 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3643 dce_v11_0_afmt_enable(encoder
, true);
3644 dce_v11_0_afmt_setmode(encoder
, adjusted_mode
);
3648 static void dce_v11_0_encoder_prepare(struct drm_encoder
*encoder
)
3650 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3651 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3652 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3654 if ((amdgpu_encoder
->active_device
&
3655 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3656 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3657 ENCODER_OBJECT_ID_NONE
)) {
3658 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3660 dig
->dig_encoder
= dce_v11_0_pick_dig_encoder(encoder
);
3661 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3662 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3666 amdgpu_atombios_scratch_regs_lock(adev
, true);
3669 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3671 /* select the clock/data port if it uses a router */
3672 if (amdgpu_connector
->router
.cd_valid
)
3673 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3675 /* turn eDP panel on for mode set */
3676 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3677 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3678 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3681 /* this is needed for the pll/ss setup to work correctly in some cases */
3682 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3683 /* set up the FMT blocks */
3684 dce_v11_0_program_fmt(encoder
);
3687 static void dce_v11_0_encoder_commit(struct drm_encoder
*encoder
)
3689 struct drm_device
*dev
= encoder
->dev
;
3690 struct amdgpu_device
*adev
= dev
->dev_private
;
3692 /* need to call this here as we need the crtc set up */
3693 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3694 amdgpu_atombios_scratch_regs_lock(adev
, false);
3697 static void dce_v11_0_encoder_disable(struct drm_encoder
*encoder
)
3699 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3700 struct amdgpu_encoder_atom_dig
*dig
;
3702 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3704 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3705 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3706 dce_v11_0_afmt_enable(encoder
, false);
3707 dig
= amdgpu_encoder
->enc_priv
;
3708 dig
->dig_encoder
= -1;
3710 amdgpu_encoder
->active_device
= 0;
3713 /* these are handled by the primary encoders */
3714 static void dce_v11_0_ext_prepare(struct drm_encoder
*encoder
)
3719 static void dce_v11_0_ext_commit(struct drm_encoder
*encoder
)
3725 dce_v11_0_ext_mode_set(struct drm_encoder
*encoder
,
3726 struct drm_display_mode
*mode
,
3727 struct drm_display_mode
*adjusted_mode
)
3732 static void dce_v11_0_ext_disable(struct drm_encoder
*encoder
)
3738 dce_v11_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3743 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs
= {
3744 .dpms
= dce_v11_0_ext_dpms
,
3745 .prepare
= dce_v11_0_ext_prepare
,
3746 .mode_set
= dce_v11_0_ext_mode_set
,
3747 .commit
= dce_v11_0_ext_commit
,
3748 .disable
= dce_v11_0_ext_disable
,
3749 /* no detect for TMDS/LVDS yet */
3752 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs
= {
3753 .dpms
= amdgpu_atombios_encoder_dpms
,
3754 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3755 .prepare
= dce_v11_0_encoder_prepare
,
3756 .mode_set
= dce_v11_0_encoder_mode_set
,
3757 .commit
= dce_v11_0_encoder_commit
,
3758 .disable
= dce_v11_0_encoder_disable
,
3759 .detect
= amdgpu_atombios_encoder_dig_detect
,
3762 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs
= {
3763 .dpms
= amdgpu_atombios_encoder_dpms
,
3764 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3765 .prepare
= dce_v11_0_encoder_prepare
,
3766 .mode_set
= dce_v11_0_encoder_mode_set
,
3767 .commit
= dce_v11_0_encoder_commit
,
3768 .detect
= amdgpu_atombios_encoder_dac_detect
,
3771 static void dce_v11_0_encoder_destroy(struct drm_encoder
*encoder
)
3773 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3774 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3775 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3776 kfree(amdgpu_encoder
->enc_priv
);
3777 drm_encoder_cleanup(encoder
);
3778 kfree(amdgpu_encoder
);
3781 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs
= {
3782 .destroy
= dce_v11_0_encoder_destroy
,
3785 static void dce_v11_0_encoder_add(struct amdgpu_device
*adev
,
3786 uint32_t encoder_enum
,
3787 uint32_t supported_device
,
3790 struct drm_device
*dev
= adev
->ddev
;
3791 struct drm_encoder
*encoder
;
3792 struct amdgpu_encoder
*amdgpu_encoder
;
3794 /* see if we already added it */
3795 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3796 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3797 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3798 amdgpu_encoder
->devices
|= supported_device
;
3805 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3806 if (!amdgpu_encoder
)
3809 encoder
= &amdgpu_encoder
->base
;
3810 switch (adev
->mode_info
.num_crtc
) {
3812 encoder
->possible_crtcs
= 0x1;
3816 encoder
->possible_crtcs
= 0x3;
3819 encoder
->possible_crtcs
= 0xf;
3822 encoder
->possible_crtcs
= 0x3f;
3826 amdgpu_encoder
->enc_priv
= NULL
;
3828 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3829 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3830 amdgpu_encoder
->devices
= supported_device
;
3831 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3832 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3833 amdgpu_encoder
->is_ext_encoder
= false;
3834 amdgpu_encoder
->caps
= caps
;
3836 switch (amdgpu_encoder
->encoder_id
) {
3837 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3838 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3839 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3840 DRM_MODE_ENCODER_DAC
, NULL
);
3841 drm_encoder_helper_add(encoder
, &dce_v11_0_dac_helper_funcs
);
3843 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3844 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3845 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3846 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3847 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3848 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3849 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3850 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3851 DRM_MODE_ENCODER_LVDS
, NULL
);
3852 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3853 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3854 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3855 DRM_MODE_ENCODER_DAC
, NULL
);
3856 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3858 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3859 DRM_MODE_ENCODER_TMDS
, NULL
);
3860 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3862 drm_encoder_helper_add(encoder
, &dce_v11_0_dig_helper_funcs
);
3864 case ENCODER_OBJECT_ID_SI170B
:
3865 case ENCODER_OBJECT_ID_CH7303
:
3866 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3867 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3868 case ENCODER_OBJECT_ID_TITFP513
:
3869 case ENCODER_OBJECT_ID_VT1623
:
3870 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3871 case ENCODER_OBJECT_ID_TRAVIS
:
3872 case ENCODER_OBJECT_ID_NUTMEG
:
3873 /* these are handled by the primary encoders */
3874 amdgpu_encoder
->is_ext_encoder
= true;
3875 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3876 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3877 DRM_MODE_ENCODER_LVDS
, NULL
);
3878 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3879 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3880 DRM_MODE_ENCODER_DAC
, NULL
);
3882 drm_encoder_init(dev
, encoder
, &dce_v11_0_encoder_funcs
,
3883 DRM_MODE_ENCODER_TMDS
, NULL
);
3884 drm_encoder_helper_add(encoder
, &dce_v11_0_ext_helper_funcs
);
3889 static const struct amdgpu_display_funcs dce_v11_0_display_funcs
= {
3890 .set_vga_render_state
= &dce_v11_0_set_vga_render_state
,
3891 .bandwidth_update
= &dce_v11_0_bandwidth_update
,
3892 .vblank_get_counter
= &dce_v11_0_vblank_get_counter
,
3893 .vblank_wait
= &dce_v11_0_vblank_wait
,
3894 .is_display_hung
= &dce_v11_0_is_display_hung
,
3895 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3896 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3897 .hpd_sense
= &dce_v11_0_hpd_sense
,
3898 .hpd_set_polarity
= &dce_v11_0_hpd_set_polarity
,
3899 .hpd_get_gpio_reg
= &dce_v11_0_hpd_get_gpio_reg
,
3900 .page_flip
= &dce_v11_0_page_flip
,
3901 .page_flip_get_scanoutpos
= &dce_v11_0_crtc_get_scanoutpos
,
3902 .add_encoder
= &dce_v11_0_encoder_add
,
3903 .add_connector
= &amdgpu_connector_add
,
3904 .stop_mc_access
= &dce_v11_0_stop_mc_access
,
3905 .resume_mc_access
= &dce_v11_0_resume_mc_access
,
3908 static void dce_v11_0_set_display_funcs(struct amdgpu_device
*adev
)
3910 if (adev
->mode_info
.funcs
== NULL
)
3911 adev
->mode_info
.funcs
= &dce_v11_0_display_funcs
;
3914 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs
= {
3915 .set
= dce_v11_0_set_crtc_irq_state
,
3916 .process
= dce_v11_0_crtc_irq
,
3919 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs
= {
3920 .set
= dce_v11_0_set_pageflip_irq_state
,
3921 .process
= dce_v11_0_pageflip_irq
,
3924 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs
= {
3925 .set
= dce_v11_0_set_hpd_irq_state
,
3926 .process
= dce_v11_0_hpd_irq
,
3929 static void dce_v11_0_set_irq_funcs(struct amdgpu_device
*adev
)
3931 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3932 adev
->crtc_irq
.funcs
= &dce_v11_0_crtc_irq_funcs
;
3934 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3935 adev
->pageflip_irq
.funcs
= &dce_v11_0_pageflip_irq_funcs
;
3937 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3938 adev
->hpd_irq
.funcs
= &dce_v11_0_hpd_irq_funcs
;