2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "gca/gfx_7_2_enum.h"
40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
43 #include "oss/oss_2_0_d.h"
44 #include "oss/oss_2_0_sh_mask.h"
46 static void dce_v8_0_set_display_funcs(struct amdgpu_device
*adev
);
47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device
*adev
);
49 static const u32 crtc_offsets
[6] =
51 CRTC0_REGISTER_OFFSET
,
52 CRTC1_REGISTER_OFFSET
,
53 CRTC2_REGISTER_OFFSET
,
54 CRTC3_REGISTER_OFFSET
,
55 CRTC4_REGISTER_OFFSET
,
59 static const uint32_t dig_offsets
[] = {
60 CRTC0_REGISTER_OFFSET
,
61 CRTC1_REGISTER_OFFSET
,
62 CRTC2_REGISTER_OFFSET
,
63 CRTC3_REGISTER_OFFSET
,
64 CRTC4_REGISTER_OFFSET
,
65 CRTC5_REGISTER_OFFSET
,
66 (0x13830 - 0x7030) >> 2,
75 } interrupt_status_offsets
[6] = { {
76 .reg
= mmDISP_INTERRUPT_STATUS
,
77 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
78 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
79 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
81 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
82 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
83 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
84 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
86 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
87 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
88 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
89 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
91 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
92 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
93 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
94 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
96 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
97 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
98 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
99 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
101 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
102 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
103 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
104 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
107 static const uint32_t hpd_int_control_offsets
[6] = {
108 mmDC_HPD1_INT_CONTROL
,
109 mmDC_HPD2_INT_CONTROL
,
110 mmDC_HPD3_INT_CONTROL
,
111 mmDC_HPD4_INT_CONTROL
,
112 mmDC_HPD5_INT_CONTROL
,
113 mmDC_HPD6_INT_CONTROL
,
116 static u32
dce_v8_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
117 u32 block_offset
, u32 reg
)
122 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
124 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
125 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
131 u32 block_offset
, u32 reg
, u32 v
)
135 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
138 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
143 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
154 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
155 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
169 * Wait for vblank on the requested crtc (evergreen+).
171 static void dce_v8_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
175 if (crtc
>= adev
->mode_info
.num_crtc
)
178 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
184 while (dce_v8_0_is_in_vblank(adev
, crtc
)) {
185 if (i
++ % 100 == 0) {
186 if (!dce_v8_0_is_counter_moving(adev
, crtc
))
191 while (!dce_v8_0_is_in_vblank(adev
, crtc
)) {
192 if (i
++ % 100 == 0) {
193 if (!dce_v8_0_is_counter_moving(adev
, crtc
))
199 static u32
dce_v8_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
201 if (crtc
>= adev
->mode_info
.num_crtc
)
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
211 /* Enable pflip interrupts */
212 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
213 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
220 /* Disable pflip interrupts */
221 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
222 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
226 * dce_v8_0_page_flip - pageflip callback.
228 * @adev: amdgpu_device pointer
229 * @crtc_id: crtc to cleanup pageflip on
230 * @crtc_base: new address of the crtc (GPU MC address)
232 * Triggers the actual pageflip by updating the primary
233 * surface base address.
235 static void dce_v8_0_page_flip(struct amdgpu_device
*adev
,
236 int crtc_id
, u64 crtc_base
, bool async
)
238 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
240 /* flip at hsync for async, default is vsync */
241 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, async
?
242 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
: 0);
243 /* update the primary scanout addresses */
244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
245 upper_32_bits(crtc_base
));
246 /* writing to the low address triggers the update */
247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
248 lower_32_bits(crtc_base
));
250 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
253 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
254 u32
*vbl
, u32
*position
)
256 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
259 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
260 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
266 * dce_v8_0_hpd_sense - hpd sense callback.
268 * @adev: amdgpu_device pointer
269 * @hpd: hpd (hotplug detect) pin
271 * Checks if a digital monitor is connected (evergreen+).
272 * Returns true if connected, false if not connected.
274 static bool dce_v8_0_hpd_sense(struct amdgpu_device
*adev
,
275 enum amdgpu_hpd_id hpd
)
277 bool connected
= false;
281 if (RREG32(mmDC_HPD1_INT_STATUS
) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK
)
285 if (RREG32(mmDC_HPD2_INT_STATUS
) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK
)
289 if (RREG32(mmDC_HPD3_INT_STATUS
) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK
)
293 if (RREG32(mmDC_HPD4_INT_STATUS
) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK
)
297 if (RREG32(mmDC_HPD5_INT_STATUS
) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK
)
301 if (RREG32(mmDC_HPD6_INT_STATUS
) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK
)
312 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
314 * @adev: amdgpu_device pointer
315 * @hpd: hpd (hotplug detect) pin
317 * Set the polarity of the hpd pin (evergreen+).
319 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device
*adev
,
320 enum amdgpu_hpd_id hpd
)
323 bool connected
= dce_v8_0_hpd_sense(adev
, hpd
);
327 tmp
= RREG32(mmDC_HPD1_INT_CONTROL
);
329 tmp
&= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
;
331 tmp
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
;
332 WREG32(mmDC_HPD1_INT_CONTROL
, tmp
);
335 tmp
= RREG32(mmDC_HPD2_INT_CONTROL
);
337 tmp
&= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
;
339 tmp
|= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
;
340 WREG32(mmDC_HPD2_INT_CONTROL
, tmp
);
343 tmp
= RREG32(mmDC_HPD3_INT_CONTROL
);
345 tmp
&= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
;
347 tmp
|= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
;
348 WREG32(mmDC_HPD3_INT_CONTROL
, tmp
);
351 tmp
= RREG32(mmDC_HPD4_INT_CONTROL
);
353 tmp
&= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
;
355 tmp
|= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
;
356 WREG32(mmDC_HPD4_INT_CONTROL
, tmp
);
359 tmp
= RREG32(mmDC_HPD5_INT_CONTROL
);
361 tmp
&= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
;
363 tmp
|= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
;
364 WREG32(mmDC_HPD5_INT_CONTROL
, tmp
);
367 tmp
= RREG32(mmDC_HPD6_INT_CONTROL
);
369 tmp
&= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
;
371 tmp
|= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
;
372 WREG32(mmDC_HPD6_INT_CONTROL
, tmp
);
380 * dce_v8_0_hpd_init - hpd setup callback.
382 * @adev: amdgpu_device pointer
384 * Setup the hpd pins used by the card (evergreen+).
385 * Enable the pin, set the polarity, and enable the hpd interrupts.
387 static void dce_v8_0_hpd_init(struct amdgpu_device
*adev
)
389 struct drm_device
*dev
= adev
->ddev
;
390 struct drm_connector
*connector
;
391 u32 tmp
= (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT
) |
392 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT
) |
393 DC_HPD1_CONTROL__DC_HPD1_EN_MASK
;
395 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
396 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
398 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
399 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
400 /* don't try to enable hpd on eDP or LVDS avoid breaking the
401 * aux dp channel on imac and help (but not completely fix)
402 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
403 * also avoid interrupt storms during dpms.
407 switch (amdgpu_connector
->hpd
.hpd
) {
409 WREG32(mmDC_HPD1_CONTROL
, tmp
);
412 WREG32(mmDC_HPD2_CONTROL
, tmp
);
415 WREG32(mmDC_HPD3_CONTROL
, tmp
);
418 WREG32(mmDC_HPD4_CONTROL
, tmp
);
421 WREG32(mmDC_HPD5_CONTROL
, tmp
);
424 WREG32(mmDC_HPD6_CONTROL
, tmp
);
429 dce_v8_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
430 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
435 * dce_v8_0_hpd_fini - hpd tear down callback.
437 * @adev: amdgpu_device pointer
439 * Tear down the hpd pins used by the card (evergreen+).
440 * Disable the hpd interrupts.
442 static void dce_v8_0_hpd_fini(struct amdgpu_device
*adev
)
444 struct drm_device
*dev
= adev
->ddev
;
445 struct drm_connector
*connector
;
447 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
448 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
450 switch (amdgpu_connector
->hpd
.hpd
) {
452 WREG32(mmDC_HPD1_CONTROL
, 0);
455 WREG32(mmDC_HPD2_CONTROL
, 0);
458 WREG32(mmDC_HPD3_CONTROL
, 0);
461 WREG32(mmDC_HPD4_CONTROL
, 0);
464 WREG32(mmDC_HPD5_CONTROL
, 0);
467 WREG32(mmDC_HPD6_CONTROL
, 0);
472 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
476 static u32
dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
478 return mmDC_GPIO_HPD_A
;
481 static bool dce_v8_0_is_display_hung(struct amdgpu_device
*adev
)
487 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
488 if (RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
) {
489 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
490 crtc_hung
|= (1 << i
);
494 for (j
= 0; j
< 10; j
++) {
495 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
496 if (crtc_hung
& (1 << i
)) {
497 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
498 if (tmp
!= crtc_status
[i
])
499 crtc_hung
&= ~(1 << i
);
510 static void dce_v8_0_stop_mc_access(struct amdgpu_device
*adev
,
511 struct amdgpu_mode_mc_save
*save
)
513 u32 crtc_enabled
, tmp
;
516 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
517 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
519 /* disable VGA render */
520 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
521 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
522 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
524 /* blank the display controllers */
525 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
526 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
527 CRTC_CONTROL
, CRTC_MASTER_EN
);
530 save
->crtc_enabled
[i
] = true;
531 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
532 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
533 /*it is correct only for RGB ; black is 0*/
534 WREG32(mmCRTC_BLANK_DATA_COLOR
+ crtc_offsets
[i
], 0);
535 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
536 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
540 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
541 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
542 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
543 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
544 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
545 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
546 save
->crtc_enabled
[i
] = false;
550 save
->crtc_enabled
[i
] = false;
555 static void dce_v8_0_resume_mc_access(struct amdgpu_device
*adev
,
556 struct amdgpu_mode_mc_save
*save
)
561 /* update crtc base addresses */
562 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
563 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
564 upper_32_bits(adev
->mc
.vram_start
));
565 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
566 (u32
)adev
->mc
.vram_start
);
568 if (save
->crtc_enabled
[i
]) {
569 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
570 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
571 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
576 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
577 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
579 /* Unlock vga access */
580 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
582 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
585 static void dce_v8_0_set_vga_render_state(struct amdgpu_device
*adev
,
590 /* Lockout access through VGA aperture*/
591 tmp
= RREG32(mmVGA_HDP_CONTROL
);
593 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
595 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
596 WREG32(mmVGA_HDP_CONTROL
, tmp
);
598 /* disable VGA render */
599 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
601 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
603 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
604 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
607 static int dce_v8_0_get_num_crtc(struct amdgpu_device
*adev
)
611 switch (adev
->asic_type
) {
629 void dce_v8_0_disable_dce(struct amdgpu_device
*adev
)
631 /*Disable VGA render and enabled crtc, if has DCE engine*/
632 if (amdgpu_atombios_has_dce_engine_info(adev
)) {
636 dce_v8_0_set_vga_render_state(adev
, false);
639 for (i
= 0; i
< dce_v8_0_get_num_crtc(adev
); i
++) {
640 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
641 CRTC_CONTROL
, CRTC_MASTER_EN
);
643 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
644 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
645 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
646 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
647 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
653 static void dce_v8_0_program_fmt(struct drm_encoder
*encoder
)
655 struct drm_device
*dev
= encoder
->dev
;
656 struct amdgpu_device
*adev
= dev
->dev_private
;
657 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
658 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
659 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
662 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
665 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
666 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
667 dither
= amdgpu_connector
->dither
;
670 /* LVDS/eDP FMT is set up by atom */
671 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
674 /* not needed for analog */
675 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
676 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
684 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
685 /* XXX sort out optimal dither settings */
686 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
687 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
688 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
689 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
691 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
692 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
695 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
696 /* XXX sort out optimal dither settings */
697 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
698 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
699 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK
|
700 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
701 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
703 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
704 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
707 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
708 /* XXX sort out optimal dither settings */
709 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
710 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
711 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK
|
712 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
713 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
715 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
716 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
723 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
727 /* display watermark setup */
729 * dce_v8_0_line_buffer_adjust - Set up the line buffer
731 * @adev: amdgpu_device pointer
732 * @amdgpu_crtc: the selected display controller
733 * @mode: the current display mode on the selected display
736 * Setup up the line buffer allocation for
737 * the selected display controller (CIK).
738 * Returns the line buffer size in pixels.
740 static u32
dce_v8_0_line_buffer_adjust(struct amdgpu_device
*adev
,
741 struct amdgpu_crtc
*amdgpu_crtc
,
742 struct drm_display_mode
*mode
)
744 u32 tmp
, buffer_alloc
, i
;
745 u32 pipe_offset
= amdgpu_crtc
->crtc_id
* 0x8;
748 * There are 6 line buffers, one for each display controllers.
749 * There are 3 partitions per LB. Select the number of partitions
750 * to enable based on the display width. For display widths larger
751 * than 4096, you need use to use 2 display controllers and combine
752 * them using the stereo blender.
754 if (amdgpu_crtc
->base
.enabled
&& mode
) {
755 if (mode
->crtc_hdisplay
< 1920) {
758 } else if (mode
->crtc_hdisplay
< 2560) {
761 } else if (mode
->crtc_hdisplay
< 4096) {
763 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
765 DRM_DEBUG_KMS("Mode too big for LB!\n");
767 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
774 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
,
775 (tmp
<< LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT
) |
776 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT
));
778 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
,
779 (buffer_alloc
<< PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
));
780 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
781 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
) &
782 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
)
787 if (amdgpu_crtc
->base
.enabled
&& mode
) {
799 /* controller not enabled, so no lb used */
804 * cik_get_number_of_dram_channels - get the number of dram channels
806 * @adev: amdgpu_device pointer
808 * Look up the number of video ram channels (CIK).
809 * Used for display watermark bandwidth calculations
810 * Returns the number of dram channels
812 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
814 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
816 switch ((tmp
& MC_SHARED_CHMAP__NOOFCHAN_MASK
) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT
) {
839 struct dce8_wm_params
{
840 u32 dram_channels
; /* number of dram channels */
841 u32 yclk
; /* bandwidth per dram data pin in kHz */
842 u32 sclk
; /* engine clock in kHz */
843 u32 disp_clk
; /* display clock in kHz */
844 u32 src_width
; /* viewport width */
845 u32 active_time
; /* active display time in ns */
846 u32 blank_time
; /* blank time in ns */
847 bool interlaced
; /* mode is interlaced */
848 fixed20_12 vsc
; /* vertical scale ratio */
849 u32 num_heads
; /* number of active crtcs */
850 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
851 u32 lb_size
; /* line buffer allocated to pipe */
852 u32 vtaps
; /* vertical scaler taps */
856 * dce_v8_0_dram_bandwidth - get the dram bandwidth
858 * @wm: watermark calculation data
860 * Calculate the raw dram bandwidth (CIK).
861 * Used for display watermark bandwidth calculations
862 * Returns the dram bandwidth in MBytes/s
864 static u32
dce_v8_0_dram_bandwidth(struct dce8_wm_params
*wm
)
866 /* Calculate raw DRAM Bandwidth */
867 fixed20_12 dram_efficiency
; /* 0.7 */
868 fixed20_12 yclk
, dram_channels
, bandwidth
;
871 a
.full
= dfixed_const(1000);
872 yclk
.full
= dfixed_const(wm
->yclk
);
873 yclk
.full
= dfixed_div(yclk
, a
);
874 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
875 a
.full
= dfixed_const(10);
876 dram_efficiency
.full
= dfixed_const(7);
877 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
878 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
879 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
881 return dfixed_trunc(bandwidth
);
885 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
887 * @wm: watermark calculation data
889 * Calculate the dram bandwidth used for display (CIK).
890 * Used for display watermark bandwidth calculations
891 * Returns the dram bandwidth for display in MBytes/s
893 static u32
dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params
*wm
)
895 /* Calculate DRAM Bandwidth and the part allocated to display. */
896 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
897 fixed20_12 yclk
, dram_channels
, bandwidth
;
900 a
.full
= dfixed_const(1000);
901 yclk
.full
= dfixed_const(wm
->yclk
);
902 yclk
.full
= dfixed_div(yclk
, a
);
903 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
904 a
.full
= dfixed_const(10);
905 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
906 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
907 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
908 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
910 return dfixed_trunc(bandwidth
);
914 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
916 * @wm: watermark calculation data
918 * Calculate the data return bandwidth used for display (CIK).
919 * Used for display watermark bandwidth calculations
920 * Returns the data return bandwidth in MBytes/s
922 static u32
dce_v8_0_data_return_bandwidth(struct dce8_wm_params
*wm
)
924 /* Calculate the display Data return Bandwidth */
925 fixed20_12 return_efficiency
; /* 0.8 */
926 fixed20_12 sclk
, bandwidth
;
929 a
.full
= dfixed_const(1000);
930 sclk
.full
= dfixed_const(wm
->sclk
);
931 sclk
.full
= dfixed_div(sclk
, a
);
932 a
.full
= dfixed_const(10);
933 return_efficiency
.full
= dfixed_const(8);
934 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
935 a
.full
= dfixed_const(32);
936 bandwidth
.full
= dfixed_mul(a
, sclk
);
937 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
939 return dfixed_trunc(bandwidth
);
943 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
945 * @wm: watermark calculation data
947 * Calculate the dmif bandwidth used for display (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns the dmif bandwidth in MBytes/s
951 static u32
dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params
*wm
)
953 /* Calculate the DMIF Request Bandwidth */
954 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
955 fixed20_12 disp_clk
, bandwidth
;
958 a
.full
= dfixed_const(1000);
959 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
960 disp_clk
.full
= dfixed_div(disp_clk
, a
);
961 a
.full
= dfixed_const(32);
962 b
.full
= dfixed_mul(a
, disp_clk
);
964 a
.full
= dfixed_const(10);
965 disp_clk_request_efficiency
.full
= dfixed_const(8);
966 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
968 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
970 return dfixed_trunc(bandwidth
);
974 * dce_v8_0_available_bandwidth - get the min available bandwidth
976 * @wm: watermark calculation data
978 * Calculate the min available bandwidth used for display (CIK).
979 * Used for display watermark bandwidth calculations
980 * Returns the min available bandwidth in MBytes/s
982 static u32
dce_v8_0_available_bandwidth(struct dce8_wm_params
*wm
)
984 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
985 u32 dram_bandwidth
= dce_v8_0_dram_bandwidth(wm
);
986 u32 data_return_bandwidth
= dce_v8_0_data_return_bandwidth(wm
);
987 u32 dmif_req_bandwidth
= dce_v8_0_dmif_request_bandwidth(wm
);
989 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
993 * dce_v8_0_average_bandwidth - get the average available bandwidth
995 * @wm: watermark calculation data
997 * Calculate the average available bandwidth used for display (CIK).
998 * Used for display watermark bandwidth calculations
999 * Returns the average available bandwidth in MBytes/s
1001 static u32
dce_v8_0_average_bandwidth(struct dce8_wm_params
*wm
)
1003 /* Calculate the display mode Average Bandwidth
1004 * DisplayMode should contain the source and destination dimensions,
1008 fixed20_12 line_time
;
1009 fixed20_12 src_width
;
1010 fixed20_12 bandwidth
;
1013 a
.full
= dfixed_const(1000);
1014 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1015 line_time
.full
= dfixed_div(line_time
, a
);
1016 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1017 src_width
.full
= dfixed_const(wm
->src_width
);
1018 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1019 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1020 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1022 return dfixed_trunc(bandwidth
);
1026 * dce_v8_0_latency_watermark - get the latency watermark
1028 * @wm: watermark calculation data
1030 * Calculate the latency watermark (CIK).
1031 * Used for display watermark bandwidth calculations
1032 * Returns the latency watermark in ns
1034 static u32
dce_v8_0_latency_watermark(struct dce8_wm_params
*wm
)
1036 /* First calculate the latency in ns */
1037 u32 mc_latency
= 2000; /* 2000 ns. */
1038 u32 available_bandwidth
= dce_v8_0_available_bandwidth(wm
);
1039 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1040 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1041 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1042 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1043 (wm
->num_heads
* cursor_line_pair_return_time
);
1044 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1045 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1046 u32 tmp
, dmif_size
= 12288;
1049 if (wm
->num_heads
== 0)
1052 a
.full
= dfixed_const(2);
1053 b
.full
= dfixed_const(1);
1054 if ((wm
->vsc
.full
> a
.full
) ||
1055 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1057 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1058 max_src_lines_per_dst_line
= 4;
1060 max_src_lines_per_dst_line
= 2;
1062 a
.full
= dfixed_const(available_bandwidth
);
1063 b
.full
= dfixed_const(wm
->num_heads
);
1064 a
.full
= dfixed_div(a
, b
);
1066 b
.full
= dfixed_const(mc_latency
+ 512);
1067 c
.full
= dfixed_const(wm
->disp_clk
);
1068 b
.full
= dfixed_div(b
, c
);
1070 c
.full
= dfixed_const(dmif_size
);
1071 b
.full
= dfixed_div(c
, b
);
1073 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1075 b
.full
= dfixed_const(1000);
1076 c
.full
= dfixed_const(wm
->disp_clk
);
1077 b
.full
= dfixed_div(c
, b
);
1078 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1079 b
.full
= dfixed_mul(b
, c
);
1081 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1083 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1084 b
.full
= dfixed_const(1000);
1085 c
.full
= dfixed_const(lb_fill_bw
);
1086 b
.full
= dfixed_div(c
, b
);
1087 a
.full
= dfixed_div(a
, b
);
1088 line_fill_time
= dfixed_trunc(a
);
1090 if (line_fill_time
< wm
->active_time
)
1093 return latency
+ (line_fill_time
- wm
->active_time
);
1098 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1099 * average and available dram bandwidth
1101 * @wm: watermark calculation data
1103 * Check if the display average bandwidth fits in the display
1104 * dram bandwidth (CIK).
1105 * Used for display watermark bandwidth calculations
1106 * Returns true if the display fits, false if not.
1108 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params
*wm
)
1110 if (dce_v8_0_average_bandwidth(wm
) <=
1111 (dce_v8_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1118 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1119 * average and available bandwidth
1121 * @wm: watermark calculation data
1123 * Check if the display average bandwidth fits in the display
1124 * available bandwidth (CIK).
1125 * Used for display watermark bandwidth calculations
1126 * Returns true if the display fits, false if not.
1128 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params
*wm
)
1130 if (dce_v8_0_average_bandwidth(wm
) <=
1131 (dce_v8_0_available_bandwidth(wm
) / wm
->num_heads
))
1138 * dce_v8_0_check_latency_hiding - check latency hiding
1140 * @wm: watermark calculation data
1142 * Check latency hiding (CIK).
1143 * Used for display watermark bandwidth calculations
1144 * Returns true if the display fits, false if not.
1146 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params
*wm
)
1148 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1149 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1150 u32 latency_tolerant_lines
;
1154 a
.full
= dfixed_const(1);
1155 if (wm
->vsc
.full
> a
.full
)
1156 latency_tolerant_lines
= 1;
1158 if (lb_partitions
<= (wm
->vtaps
+ 1))
1159 latency_tolerant_lines
= 1;
1161 latency_tolerant_lines
= 2;
1164 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1166 if (dce_v8_0_latency_watermark(wm
) <= latency_hiding
)
1173 * dce_v8_0_program_watermarks - program display watermarks
1175 * @adev: amdgpu_device pointer
1176 * @amdgpu_crtc: the selected display controller
1177 * @lb_size: line buffer size
1178 * @num_heads: number of display controllers in use
1180 * Calculate and program the display watermarks for the
1181 * selected display controller (CIK).
1183 static void dce_v8_0_program_watermarks(struct amdgpu_device
*adev
,
1184 struct amdgpu_crtc
*amdgpu_crtc
,
1185 u32 lb_size
, u32 num_heads
)
1187 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1188 struct dce8_wm_params wm_low
, wm_high
;
1191 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1192 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1194 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1195 pixel_period
= 1000000 / (u32
)mode
->clock
;
1196 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1198 /* watermark for high clocks */
1199 if (adev
->pm
.dpm_enabled
) {
1201 amdgpu_dpm_get_mclk(adev
, false) * 10;
1203 amdgpu_dpm_get_sclk(adev
, false) * 10;
1205 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1206 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1209 wm_high
.disp_clk
= mode
->clock
;
1210 wm_high
.src_width
= mode
->crtc_hdisplay
;
1211 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1212 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1213 wm_high
.interlaced
= false;
1214 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1215 wm_high
.interlaced
= true;
1216 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1218 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1220 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1221 wm_high
.lb_size
= lb_size
;
1222 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1223 wm_high
.num_heads
= num_heads
;
1225 /* set for high clocks */
1226 latency_watermark_a
= min(dce_v8_0_latency_watermark(&wm_high
), (u32
)65535);
1228 /* possibly force display priority to high */
1229 /* should really do this at mode validation time... */
1230 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1231 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1232 !dce_v8_0_check_latency_hiding(&wm_high
) ||
1233 (adev
->mode_info
.disp_priority
== 2)) {
1234 DRM_DEBUG_KMS("force priority to high\n");
1237 /* watermark for low clocks */
1238 if (adev
->pm
.dpm_enabled
) {
1240 amdgpu_dpm_get_mclk(adev
, true) * 10;
1242 amdgpu_dpm_get_sclk(adev
, true) * 10;
1244 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1245 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1248 wm_low
.disp_clk
= mode
->clock
;
1249 wm_low
.src_width
= mode
->crtc_hdisplay
;
1250 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1251 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1252 wm_low
.interlaced
= false;
1253 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1254 wm_low
.interlaced
= true;
1255 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1257 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1259 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1260 wm_low
.lb_size
= lb_size
;
1261 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1262 wm_low
.num_heads
= num_heads
;
1264 /* set for low clocks */
1265 latency_watermark_b
= min(dce_v8_0_latency_watermark(&wm_low
), (u32
)65535);
1267 /* possibly force display priority to high */
1268 /* should really do this at mode validation time... */
1269 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1270 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1271 !dce_v8_0_check_latency_hiding(&wm_low
) ||
1272 (adev
->mode_info
.disp_priority
== 2)) {
1273 DRM_DEBUG_KMS("force priority to high\n");
1275 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1279 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1281 tmp
&= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1282 tmp
|= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1283 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1284 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
,
1285 ((latency_watermark_a
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
) |
1286 (line_time
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
)));
1288 tmp
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1289 tmp
&= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1290 tmp
|= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1291 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1292 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
,
1293 ((latency_watermark_b
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
) |
1294 (line_time
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
)));
1295 /* restore original selection */
1296 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1298 /* save values for DPM */
1299 amdgpu_crtc
->line_time
= line_time
;
1300 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1301 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1302 /* Save number of lines the linebuffer leads before the scanout */
1303 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1307 * dce_v8_0_bandwidth_update - program display watermarks
1309 * @adev: amdgpu_device pointer
1311 * Calculate and program the display watermarks and line
1312 * buffer allocation (CIK).
1314 static void dce_v8_0_bandwidth_update(struct amdgpu_device
*adev
)
1316 struct drm_display_mode
*mode
= NULL
;
1317 u32 num_heads
= 0, lb_size
;
1320 amdgpu_update_display_priority(adev
);
1322 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1323 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1326 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1327 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1328 lb_size
= dce_v8_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1329 dce_v8_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1330 lb_size
, num_heads
);
1334 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1339 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1340 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1341 tmp
= RREG32_AUDIO_ENDPT(offset
,
1342 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1344 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1345 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1346 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1348 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1352 static struct amdgpu_audio_pin
*dce_v8_0_audio_get_pin(struct amdgpu_device
*adev
)
1356 dce_v8_0_audio_get_connected_pins(adev
);
1358 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1359 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1360 return &adev
->mode_info
.audio
.pin
[i
];
1362 DRM_ERROR("No connected audio pins found!\n");
1366 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1368 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1369 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1370 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1373 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1376 offset
= dig
->afmt
->offset
;
1378 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ offset
,
1379 (dig
->afmt
->pin
->id
<< AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
));
1382 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1383 struct drm_display_mode
*mode
)
1385 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1386 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1387 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1388 struct drm_connector
*connector
;
1389 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1390 u32 tmp
= 0, offset
;
1392 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1395 offset
= dig
->afmt
->pin
->offset
;
1397 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1398 if (connector
->encoder
== encoder
) {
1399 amdgpu_connector
= to_amdgpu_connector(connector
);
1404 if (!amdgpu_connector
) {
1405 DRM_ERROR("Couldn't find encoder's connector\n");
1409 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
1410 if (connector
->latency_present
[1])
1412 (connector
->video_latency
[1] <<
1413 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1414 (connector
->audio_latency
[1] <<
1415 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1419 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1421 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1423 if (connector
->latency_present
[0])
1425 (connector
->video_latency
[0] <<
1426 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1427 (connector
->audio_latency
[0] <<
1428 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1432 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1434 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1437 WREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1440 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1442 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1443 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1444 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1445 struct drm_connector
*connector
;
1446 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1451 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1454 offset
= dig
->afmt
->pin
->offset
;
1456 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1457 if (connector
->encoder
== encoder
) {
1458 amdgpu_connector
= to_amdgpu_connector(connector
);
1463 if (!amdgpu_connector
) {
1464 DRM_ERROR("Couldn't find encoder's connector\n");
1468 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1469 if (sad_count
< 0) {
1470 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1474 /* program the speaker allocation */
1475 tmp
= RREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1476 tmp
&= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
|
1477 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
);
1479 tmp
|= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
;
1481 tmp
|= (sadb
[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
);
1483 tmp
|= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
); /* stereo */
1484 WREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1489 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1491 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1492 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1493 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1495 struct drm_connector
*connector
;
1496 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1497 struct cea_sad
*sads
;
1500 static const u16 eld_reg_to_type
[][2] = {
1501 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1502 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1503 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1504 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1505 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1506 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1507 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1515 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1518 offset
= dig
->afmt
->pin
->offset
;
1520 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1521 if (connector
->encoder
== encoder
) {
1522 amdgpu_connector
= to_amdgpu_connector(connector
);
1527 if (!amdgpu_connector
) {
1528 DRM_ERROR("Couldn't find encoder's connector\n");
1532 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1533 if (sad_count
<= 0) {
1534 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1539 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1541 u8 stereo_freqs
= 0;
1542 int max_channels
= -1;
1545 for (j
= 0; j
< sad_count
; j
++) {
1546 struct cea_sad
*sad
= &sads
[j
];
1548 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1549 if (sad
->channels
> max_channels
) {
1550 value
= (sad
->channels
<<
1551 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
) |
1553 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
) |
1555 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
);
1556 max_channels
= sad
->channels
;
1559 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1560 stereo_freqs
|= sad
->freq
;
1566 value
|= (stereo_freqs
<<
1567 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
);
1569 WREG32_AUDIO_ENDPT(offset
, eld_reg_to_type
[i
][0], value
);
1575 static void dce_v8_0_audio_enable(struct amdgpu_device
*adev
,
1576 struct amdgpu_audio_pin
*pin
,
1582 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1583 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1586 static const u32 pin_offsets
[7] =
1597 static int dce_v8_0_audio_init(struct amdgpu_device
*adev
)
1604 adev
->mode_info
.audio
.enabled
= true;
1606 if (adev
->asic_type
== CHIP_KAVERI
) /* KV: 4 streams, 7 endpoints */
1607 adev
->mode_info
.audio
.num_pins
= 7;
1608 else if ((adev
->asic_type
== CHIP_KABINI
) ||
1609 (adev
->asic_type
== CHIP_MULLINS
)) /* KB/ML: 2 streams, 3 endpoints */
1610 adev
->mode_info
.audio
.num_pins
= 3;
1611 else if ((adev
->asic_type
== CHIP_BONAIRE
) ||
1612 (adev
->asic_type
== CHIP_HAWAII
))/* BN/HW: 6 streams, 7 endpoints */
1613 adev
->mode_info
.audio
.num_pins
= 7;
1615 adev
->mode_info
.audio
.num_pins
= 3;
1617 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1618 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1619 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1620 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1621 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1622 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1623 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1624 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1625 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1626 /* disable audio. it will be set up later */
1627 /* XXX remove once we switch to ip funcs */
1628 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1634 static void dce_v8_0_audio_fini(struct amdgpu_device
*adev
)
1641 if (!adev
->mode_info
.audio
.enabled
)
1644 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1645 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1647 adev
->mode_info
.audio
.enabled
= false;
1651 * update the N and CTS parameters for a given pixel clock rate
1653 static void dce_v8_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1655 struct drm_device
*dev
= encoder
->dev
;
1656 struct amdgpu_device
*adev
= dev
->dev_private
;
1657 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1658 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1659 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1660 uint32_t offset
= dig
->afmt
->offset
;
1662 WREG32(mmHDMI_ACR_32_0
+ offset
, (acr
.cts_32khz
<< HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
));
1663 WREG32(mmHDMI_ACR_32_1
+ offset
, acr
.n_32khz
);
1665 WREG32(mmHDMI_ACR_44_0
+ offset
, (acr
.cts_44_1khz
<< HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
));
1666 WREG32(mmHDMI_ACR_44_1
+ offset
, acr
.n_44_1khz
);
1668 WREG32(mmHDMI_ACR_48_0
+ offset
, (acr
.cts_48khz
<< HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
));
1669 WREG32(mmHDMI_ACR_48_1
+ offset
, acr
.n_48khz
);
1673 * build a HDMI Video Info Frame
1675 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1676 void *buffer
, size_t size
)
1678 struct drm_device
*dev
= encoder
->dev
;
1679 struct amdgpu_device
*adev
= dev
->dev_private
;
1680 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1681 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1682 uint32_t offset
= dig
->afmt
->offset
;
1683 uint8_t *frame
= buffer
+ 3;
1684 uint8_t *header
= buffer
;
1686 WREG32(mmAFMT_AVI_INFO0
+ offset
,
1687 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1688 WREG32(mmAFMT_AVI_INFO1
+ offset
,
1689 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1690 WREG32(mmAFMT_AVI_INFO2
+ offset
,
1691 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1692 WREG32(mmAFMT_AVI_INFO3
+ offset
,
1693 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1696 static void dce_v8_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1698 struct drm_device
*dev
= encoder
->dev
;
1699 struct amdgpu_device
*adev
= dev
->dev_private
;
1700 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1701 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1702 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1703 u32 dto_phase
= 24 * 1000;
1704 u32 dto_modulo
= clock
;
1706 if (!dig
|| !dig
->afmt
)
1709 /* XXX two dtos; generally use dto0 for hdmi */
1710 /* Express [24MHz / target pixel clock] as an exact rational
1711 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1712 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1714 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, (amdgpu_crtc
->crtc_id
<< DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT
));
1715 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1716 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1720 * update the info frames with the data from the current display mode
1722 static void dce_v8_0_afmt_setmode(struct drm_encoder
*encoder
,
1723 struct drm_display_mode
*mode
)
1725 struct drm_device
*dev
= encoder
->dev
;
1726 struct amdgpu_device
*adev
= dev
->dev_private
;
1727 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1728 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1729 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1730 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1731 struct hdmi_avi_infoframe frame
;
1732 uint32_t offset
, val
;
1736 if (!dig
|| !dig
->afmt
)
1739 /* Silent, r600_hdmi_enable will raise WARN for us */
1740 if (!dig
->afmt
->enabled
)
1743 offset
= dig
->afmt
->offset
;
1745 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1746 if (encoder
->crtc
) {
1747 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1748 bpc
= amdgpu_crtc
->bpc
;
1751 /* disable audio prior to setting up hw */
1752 dig
->afmt
->pin
= dce_v8_0_audio_get_pin(adev
);
1753 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1755 dce_v8_0_audio_set_dto(encoder
, mode
->clock
);
1757 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ offset
,
1758 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
); /* send null packets when required */
1760 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ offset
, 0x1000);
1762 val
= RREG32(mmHDMI_CONTROL
+ offset
);
1763 val
&= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1764 val
&= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
;
1772 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1773 connector
->name
, bpc
);
1776 val
|= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1777 val
|= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
;
1778 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1782 val
|= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1783 val
|= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
;
1784 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1789 WREG32(mmHDMI_CONTROL
+ offset
, val
);
1791 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ offset
,
1792 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
| /* send null packets when required */
1793 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
| /* send general control packets */
1794 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
); /* send general control packets every frame */
1796 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ offset
,
1797 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
| /* enable audio info frames (frames won't be set until audio is enabled) */
1798 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
); /* required for audio info values to be updated */
1800 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ offset
,
1801 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
); /* required for audio info values to be updated */
1803 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ offset
,
1804 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
)); /* anything other than 0 */
1806 WREG32(mmHDMI_GC
+ offset
, 0); /* unset HDMI_GC_AVMUTE */
1808 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ offset
,
1809 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
) | /* set the default audio delay */
1810 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
)); /* should be suffient for all audio modes and small enough for all hblanks */
1812 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ offset
,
1813 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
); /* allow 60958 channel status fields to be updated */
1815 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1818 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ offset
,
1819 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
); /* allow hw to sent ACR packets when required */
1821 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ offset
,
1822 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
| /* select SW CTS value */
1823 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
); /* allow hw to sent ACR packets when required */
1825 dce_v8_0_afmt_update_ACR(encoder
, mode
->clock
);
1827 WREG32(mmAFMT_60958_0
+ offset
,
1828 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
));
1830 WREG32(mmAFMT_60958_1
+ offset
,
1831 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
));
1833 WREG32(mmAFMT_60958_2
+ offset
,
1834 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
) |
1835 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
) |
1836 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
) |
1837 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
) |
1838 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
) |
1839 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
));
1841 dce_v8_0_audio_write_speaker_allocation(encoder
);
1844 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ offset
,
1845 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1847 dce_v8_0_afmt_audio_select_pin(encoder
);
1848 dce_v8_0_audio_write_sad_regs(encoder
);
1849 dce_v8_0_audio_write_latency_fields(encoder
, mode
);
1851 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1853 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1857 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1859 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1863 dce_v8_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1865 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0
+ offset
,
1866 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
| /* enable AVI info frames */
1867 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
); /* required for audio info values to be updated */
1869 WREG32_P(mmHDMI_INFOFRAME_CONTROL1
+ offset
,
1870 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
), /* anything other than 0 */
1871 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
);
1873 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL
+ offset
,
1874 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
); /* send audio packets */
1876 WREG32(mmAFMT_RAMP_CONTROL0
+ offset
, 0x00FFFFFF);
1877 WREG32(mmAFMT_RAMP_CONTROL1
+ offset
, 0x007FFFFF);
1878 WREG32(mmAFMT_RAMP_CONTROL2
+ offset
, 0x00000001);
1879 WREG32(mmAFMT_RAMP_CONTROL3
+ offset
, 0x00000001);
1881 /* enable audio after setting up hw */
1882 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1885 static void dce_v8_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1887 struct drm_device
*dev
= encoder
->dev
;
1888 struct amdgpu_device
*adev
= dev
->dev_private
;
1889 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1890 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1892 if (!dig
|| !dig
->afmt
)
1895 /* Silent, r600_hdmi_enable will raise WARN for us */
1896 if (enable
&& dig
->afmt
->enabled
)
1898 if (!enable
&& !dig
->afmt
->enabled
)
1901 if (!enable
&& dig
->afmt
->pin
) {
1902 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1903 dig
->afmt
->pin
= NULL
;
1906 dig
->afmt
->enabled
= enable
;
1908 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1909 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1912 static int dce_v8_0_afmt_init(struct amdgpu_device
*adev
)
1916 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1917 adev
->mode_info
.afmt
[i
] = NULL
;
1919 /* DCE8 has audio blocks tied to DIG encoders */
1920 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1921 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1922 if (adev
->mode_info
.afmt
[i
]) {
1923 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1924 adev
->mode_info
.afmt
[i
]->id
= i
;
1927 for (j
= 0; j
< i
; j
++) {
1928 kfree(adev
->mode_info
.afmt
[j
]);
1929 adev
->mode_info
.afmt
[j
] = NULL
;
1937 static void dce_v8_0_afmt_fini(struct amdgpu_device
*adev
)
1941 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1942 kfree(adev
->mode_info
.afmt
[i
]);
1943 adev
->mode_info
.afmt
[i
] = NULL
;
1947 static const u32 vga_control_regs
[6] =
1957 static void dce_v8_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
1959 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1960 struct drm_device
*dev
= crtc
->dev
;
1961 struct amdgpu_device
*adev
= dev
->dev_private
;
1964 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
1966 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
1968 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
1971 static void dce_v8_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
1973 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1974 struct drm_device
*dev
= crtc
->dev
;
1975 struct amdgpu_device
*adev
= dev
->dev_private
;
1978 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
1980 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
1983 static int dce_v8_0_crtc_do_set_base(struct drm_crtc
*crtc
,
1984 struct drm_framebuffer
*fb
,
1985 int x
, int y
, int atomic
)
1987 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1988 struct drm_device
*dev
= crtc
->dev
;
1989 struct amdgpu_device
*adev
= dev
->dev_private
;
1990 struct amdgpu_framebuffer
*amdgpu_fb
;
1991 struct drm_framebuffer
*target_fb
;
1992 struct drm_gem_object
*obj
;
1993 struct amdgpu_bo
*rbo
;
1994 uint64_t fb_location
, tiling_flags
;
1995 uint32_t fb_format
, fb_pitch_pixels
;
1996 u32 fb_swap
= (GRPH_ENDIAN_NONE
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
1998 u32 viewport_w
, viewport_h
;
2000 bool bypass_lut
= false;
2004 if (!atomic
&& !crtc
->primary
->fb
) {
2005 DRM_DEBUG_KMS("No FB bound\n");
2010 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2013 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2014 target_fb
= crtc
->primary
->fb
;
2017 /* If atomic, assume fb object is pinned & idle & fenced and
2018 * just update base pointers
2020 obj
= amdgpu_fb
->obj
;
2021 rbo
= gem_to_amdgpu_bo(obj
);
2022 r
= amdgpu_bo_reserve(rbo
, false);
2023 if (unlikely(r
!= 0))
2027 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2029 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2030 if (unlikely(r
!= 0)) {
2031 amdgpu_bo_unreserve(rbo
);
2036 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2037 amdgpu_bo_unreserve(rbo
);
2039 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2041 switch (target_fb
->pixel_format
) {
2043 fb_format
= ((GRPH_DEPTH_8BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2044 (GRPH_FORMAT_INDEXED
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2046 case DRM_FORMAT_XRGB4444
:
2047 case DRM_FORMAT_ARGB4444
:
2048 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2049 (GRPH_FORMAT_ARGB4444
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2051 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2054 case DRM_FORMAT_XRGB1555
:
2055 case DRM_FORMAT_ARGB1555
:
2056 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2057 (GRPH_FORMAT_ARGB1555
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2059 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2062 case DRM_FORMAT_BGRX5551
:
2063 case DRM_FORMAT_BGRA5551
:
2064 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2065 (GRPH_FORMAT_BGRA5551
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2067 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2070 case DRM_FORMAT_RGB565
:
2071 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2072 (GRPH_FORMAT_ARGB565
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2074 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2077 case DRM_FORMAT_XRGB8888
:
2078 case DRM_FORMAT_ARGB8888
:
2079 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2080 (GRPH_FORMAT_ARGB8888
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2082 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2085 case DRM_FORMAT_XRGB2101010
:
2086 case DRM_FORMAT_ARGB2101010
:
2087 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2088 (GRPH_FORMAT_ARGB2101010
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2090 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2092 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2095 case DRM_FORMAT_BGRX1010102
:
2096 case DRM_FORMAT_BGRA1010102
:
2097 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2098 (GRPH_FORMAT_BGRA1010102
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2100 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2102 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2106 format_name
= drm_get_format_name(target_fb
->pixel_format
);
2107 DRM_ERROR("Unsupported screen format %s\n", format_name
);
2112 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2113 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2115 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2116 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2117 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2118 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2119 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2121 fb_format
|= (num_banks
<< GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
);
2122 fb_format
|= (GRPH_ARRAY_2D_TILED_THIN1
<< GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
);
2123 fb_format
|= (tile_split
<< GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT
);
2124 fb_format
|= (bankw
<< GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT
);
2125 fb_format
|= (bankh
<< GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT
);
2126 fb_format
|= (mtaspect
<< GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT
);
2127 fb_format
|= (DISPLAY_MICRO_TILING
<< GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT
);
2128 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2129 fb_format
|= (GRPH_ARRAY_1D_TILED_THIN1
<< GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
);
2132 fb_format
|= (pipe_config
<< GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
);
2134 dce_v8_0_vga_enable(crtc
, false);
2136 /* Make sure surface address is updated at vertical blank rather than
2139 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2141 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2142 upper_32_bits(fb_location
));
2143 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2144 upper_32_bits(fb_location
));
2145 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2146 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2147 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2148 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2149 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2150 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2153 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2154 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2155 * retain the full precision throughout the pipeline.
2157 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2158 (bypass_lut
? LUT_10BIT_BYPASS_EN
: 0),
2159 ~LUT_10BIT_BYPASS_EN
);
2162 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2164 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2165 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2166 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2167 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2168 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2169 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2171 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2172 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2174 dce_v8_0_grph_enable(crtc
, true);
2176 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2181 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2183 viewport_w
= crtc
->mode
.hdisplay
;
2184 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2185 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2186 (viewport_w
<< 16) | viewport_h
);
2188 /* set pageflip to happen anywhere in vblank interval */
2189 WREG32(mmMASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2191 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2192 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2193 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2194 r
= amdgpu_bo_reserve(rbo
, false);
2195 if (unlikely(r
!= 0))
2197 amdgpu_bo_unpin(rbo
);
2198 amdgpu_bo_unreserve(rbo
);
2201 /* Bytes per pixel may have changed */
2202 dce_v8_0_bandwidth_update(adev
);
2207 static void dce_v8_0_set_interleave(struct drm_crtc
*crtc
,
2208 struct drm_display_mode
*mode
)
2210 struct drm_device
*dev
= crtc
->dev
;
2211 struct amdgpu_device
*adev
= dev
->dev_private
;
2212 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2214 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2215 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
,
2216 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
);
2218 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, 0);
2221 static void dce_v8_0_crtc_load_lut(struct drm_crtc
*crtc
)
2223 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2224 struct drm_device
*dev
= crtc
->dev
;
2225 struct amdgpu_device
*adev
= dev
->dev_private
;
2228 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2230 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2231 ((INPUT_CSC_BYPASS
<< INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
) |
2232 (INPUT_CSC_BYPASS
<< INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT
)));
2233 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2234 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
);
2235 WREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2236 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK
);
2237 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2238 ((INPUT_GAMMA_USE_LUT
<< INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
) |
2239 (INPUT_GAMMA_USE_LUT
<< INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT
)));
2241 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2243 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2244 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2245 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2247 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2248 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2249 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2251 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2252 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2254 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2255 for (i
= 0; i
< 256; i
++) {
2256 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2257 (amdgpu_crtc
->lut_r
[i
] << 20) |
2258 (amdgpu_crtc
->lut_g
[i
] << 10) |
2259 (amdgpu_crtc
->lut_b
[i
] << 0));
2262 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2263 ((DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
) |
2264 (DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT
) |
2265 (DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
)));
2266 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2267 ((GAMUT_REMAP_BYPASS
<< GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
) |
2268 (GAMUT_REMAP_BYPASS
<< GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT
)));
2269 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2270 ((REGAMMA_BYPASS
<< REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
) |
2271 (REGAMMA_BYPASS
<< REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT
)));
2272 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2273 ((OUTPUT_CSC_BYPASS
<< OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
) |
2274 (OUTPUT_CSC_BYPASS
<< OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT
)));
2275 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2276 WREG32(0x1a50 + amdgpu_crtc
->crtc_offset
, 0);
2277 /* XXX this only needs to be programmed once per crtc at startup,
2278 * not sure where the best place for it is
2280 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2281 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
);
2284 static int dce_v8_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2286 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2287 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2289 switch (amdgpu_encoder
->encoder_id
) {
2290 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2296 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2312 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2318 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2322 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2323 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2324 * monitors a dedicated PPLL must be used. If a particular board has
2325 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2326 * as there is no need to program the PLL itself. If we are not able to
2327 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2328 * avoid messing up an existing monitor.
2330 * Asic specific PLL information
2334 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2336 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2339 static u32
dce_v8_0_pick_pll(struct drm_crtc
*crtc
)
2341 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2342 struct drm_device
*dev
= crtc
->dev
;
2343 struct amdgpu_device
*adev
= dev
->dev_private
;
2347 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2348 if (adev
->clock
.dp_extclk
)
2349 /* skip PPLL programming if using ext clock */
2350 return ATOM_PPLL_INVALID
;
2352 /* use the same PPLL for all DP monitors */
2353 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2354 if (pll
!= ATOM_PPLL_INVALID
)
2358 /* use the same PPLL for all monitors with the same clock */
2359 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2360 if (pll
!= ATOM_PPLL_INVALID
)
2363 /* otherwise, pick one of the plls */
2364 if ((adev
->asic_type
== CHIP_KABINI
) ||
2365 (adev
->asic_type
== CHIP_MULLINS
)) {
2366 /* KB/ML has PPLL1 and PPLL2 */
2367 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2368 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2370 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2372 DRM_ERROR("unable to allocate a PPLL\n");
2373 return ATOM_PPLL_INVALID
;
2375 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2376 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2377 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2379 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2381 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2383 DRM_ERROR("unable to allocate a PPLL\n");
2384 return ATOM_PPLL_INVALID
;
2386 return ATOM_PPLL_INVALID
;
2389 static void dce_v8_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2391 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2392 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2395 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2397 cur_lock
|= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
;
2399 cur_lock
&= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
;
2400 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2403 static void dce_v8_0_hide_cursor(struct drm_crtc
*crtc
)
2405 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2406 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2408 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2409 (CURSOR_24_8_PRE_MULT
<< CUR_CONTROL__CURSOR_MODE__SHIFT
) |
2410 (CURSOR_URGENT_1_2
<< CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
));
2413 static void dce_v8_0_show_cursor(struct drm_crtc
*crtc
)
2415 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2416 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2418 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2419 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2420 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2421 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2423 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2424 CUR_CONTROL__CURSOR_EN_MASK
|
2425 (CURSOR_24_8_PRE_MULT
<< CUR_CONTROL__CURSOR_MODE__SHIFT
) |
2426 (CURSOR_URGENT_1_2
<< CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
));
2429 static int dce_v8_0_cursor_move_locked(struct drm_crtc
*crtc
,
2432 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2433 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2434 int xorigin
= 0, yorigin
= 0;
2436 /* avivo cursor are offset into the total surface */
2439 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2442 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2446 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2450 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2451 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2452 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2453 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2455 amdgpu_crtc
->cursor_x
= x
;
2456 amdgpu_crtc
->cursor_y
= y
;
2461 static int dce_v8_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2466 dce_v8_0_lock_cursor(crtc
, true);
2467 ret
= dce_v8_0_cursor_move_locked(crtc
, x
, y
);
2468 dce_v8_0_lock_cursor(crtc
, false);
2473 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2474 struct drm_file
*file_priv
,
2481 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2482 struct drm_gem_object
*obj
;
2483 struct amdgpu_bo
*aobj
;
2487 /* turn off cursor */
2488 dce_v8_0_hide_cursor(crtc
);
2493 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2494 (height
> amdgpu_crtc
->max_cursor_height
)) {
2495 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2499 obj
= drm_gem_object_lookup(file_priv
, handle
);
2501 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2505 aobj
= gem_to_amdgpu_bo(obj
);
2506 ret
= amdgpu_bo_reserve(aobj
, false);
2508 drm_gem_object_unreference_unlocked(obj
);
2512 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
, &amdgpu_crtc
->cursor_addr
);
2513 amdgpu_bo_unreserve(aobj
);
2515 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2516 drm_gem_object_unreference_unlocked(obj
);
2520 amdgpu_crtc
->cursor_width
= width
;
2521 amdgpu_crtc
->cursor_height
= height
;
2523 dce_v8_0_lock_cursor(crtc
, true);
2525 if (hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2526 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2529 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2530 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2532 dce_v8_0_cursor_move_locked(crtc
, x
, y
);
2534 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2535 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2538 dce_v8_0_show_cursor(crtc
);
2539 dce_v8_0_lock_cursor(crtc
, false);
2542 if (amdgpu_crtc
->cursor_bo
) {
2543 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2544 ret
= amdgpu_bo_reserve(aobj
, false);
2545 if (likely(ret
== 0)) {
2546 amdgpu_bo_unpin(aobj
);
2547 amdgpu_bo_unreserve(aobj
);
2549 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2552 amdgpu_crtc
->cursor_bo
= obj
;
2556 static void dce_v8_0_cursor_reset(struct drm_crtc
*crtc
)
2558 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2560 if (amdgpu_crtc
->cursor_bo
) {
2561 dce_v8_0_lock_cursor(crtc
, true);
2563 dce_v8_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2564 amdgpu_crtc
->cursor_y
);
2566 dce_v8_0_show_cursor(crtc
);
2568 dce_v8_0_lock_cursor(crtc
, false);
2572 static int dce_v8_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2573 u16
*blue
, uint32_t size
)
2575 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2578 /* userspace palettes are always correct as is */
2579 for (i
= 0; i
< size
; i
++) {
2580 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2581 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2582 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2584 dce_v8_0_crtc_load_lut(crtc
);
2589 static void dce_v8_0_crtc_destroy(struct drm_crtc
*crtc
)
2591 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2593 drm_crtc_cleanup(crtc
);
2597 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs
= {
2598 .cursor_set2
= dce_v8_0_crtc_cursor_set2
,
2599 .cursor_move
= dce_v8_0_crtc_cursor_move
,
2600 .gamma_set
= dce_v8_0_crtc_gamma_set
,
2601 .set_config
= amdgpu_crtc_set_config
,
2602 .destroy
= dce_v8_0_crtc_destroy
,
2603 .page_flip_target
= amdgpu_crtc_page_flip_target
,
2606 static void dce_v8_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2608 struct drm_device
*dev
= crtc
->dev
;
2609 struct amdgpu_device
*adev
= dev
->dev_private
;
2610 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2614 case DRM_MODE_DPMS_ON
:
2615 amdgpu_crtc
->enabled
= true;
2616 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2617 dce_v8_0_vga_enable(crtc
, true);
2618 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2619 dce_v8_0_vga_enable(crtc
, false);
2620 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2621 type
= amdgpu_crtc_idx_to_irq_type(adev
, amdgpu_crtc
->crtc_id
);
2622 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2623 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2624 drm_crtc_vblank_on(crtc
);
2625 dce_v8_0_crtc_load_lut(crtc
);
2627 case DRM_MODE_DPMS_STANDBY
:
2628 case DRM_MODE_DPMS_SUSPEND
:
2629 case DRM_MODE_DPMS_OFF
:
2630 drm_crtc_vblank_off(crtc
);
2631 if (amdgpu_crtc
->enabled
) {
2632 dce_v8_0_vga_enable(crtc
, true);
2633 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2634 dce_v8_0_vga_enable(crtc
, false);
2636 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2637 amdgpu_crtc
->enabled
= false;
2640 /* adjust pm to dpms */
2641 amdgpu_pm_compute_clocks(adev
);
2644 static void dce_v8_0_crtc_prepare(struct drm_crtc
*crtc
)
2646 /* disable crtc pair power gating before programming */
2647 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2648 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2649 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2652 static void dce_v8_0_crtc_commit(struct drm_crtc
*crtc
)
2654 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2655 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2658 static void dce_v8_0_crtc_disable(struct drm_crtc
*crtc
)
2660 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2661 struct drm_device
*dev
= crtc
->dev
;
2662 struct amdgpu_device
*adev
= dev
->dev_private
;
2663 struct amdgpu_atom_ss ss
;
2666 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2667 if (crtc
->primary
->fb
) {
2669 struct amdgpu_framebuffer
*amdgpu_fb
;
2670 struct amdgpu_bo
*rbo
;
2672 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2673 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2674 r
= amdgpu_bo_reserve(rbo
, false);
2676 DRM_ERROR("failed to reserve rbo before unpin\n");
2678 amdgpu_bo_unpin(rbo
);
2679 amdgpu_bo_unreserve(rbo
);
2682 /* disable the GRPH */
2683 dce_v8_0_grph_enable(crtc
, false);
2685 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2687 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2688 if (adev
->mode_info
.crtcs
[i
] &&
2689 adev
->mode_info
.crtcs
[i
]->enabled
&&
2690 i
!= amdgpu_crtc
->crtc_id
&&
2691 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2692 /* one other crtc is using this pll don't turn
2699 switch (amdgpu_crtc
->pll_id
) {
2702 /* disable the ppll */
2703 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2704 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2707 /* disable the ppll */
2708 if ((adev
->asic_type
== CHIP_KAVERI
) ||
2709 (adev
->asic_type
== CHIP_BONAIRE
) ||
2710 (adev
->asic_type
== CHIP_HAWAII
))
2711 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2712 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2718 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2719 amdgpu_crtc
->adjusted_clock
= 0;
2720 amdgpu_crtc
->encoder
= NULL
;
2721 amdgpu_crtc
->connector
= NULL
;
2724 static int dce_v8_0_crtc_mode_set(struct drm_crtc
*crtc
,
2725 struct drm_display_mode
*mode
,
2726 struct drm_display_mode
*adjusted_mode
,
2727 int x
, int y
, struct drm_framebuffer
*old_fb
)
2729 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2731 if (!amdgpu_crtc
->adjusted_clock
)
2734 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2735 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2736 dce_v8_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2737 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2738 amdgpu_atombios_crtc_scaler_setup(crtc
);
2739 dce_v8_0_cursor_reset(crtc
);
2740 /* update the hw version fpr dpm */
2741 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2746 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2747 const struct drm_display_mode
*mode
,
2748 struct drm_display_mode
*adjusted_mode
)
2750 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2751 struct drm_device
*dev
= crtc
->dev
;
2752 struct drm_encoder
*encoder
;
2754 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2755 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2756 if (encoder
->crtc
== crtc
) {
2757 amdgpu_crtc
->encoder
= encoder
;
2758 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2762 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2763 amdgpu_crtc
->encoder
= NULL
;
2764 amdgpu_crtc
->connector
= NULL
;
2767 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2769 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2772 amdgpu_crtc
->pll_id
= dce_v8_0_pick_pll(crtc
);
2773 /* if we can't get a PPLL for a non-DP encoder, fail */
2774 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2775 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2781 static int dce_v8_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2782 struct drm_framebuffer
*old_fb
)
2784 return dce_v8_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2787 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2788 struct drm_framebuffer
*fb
,
2789 int x
, int y
, enum mode_set_atomic state
)
2791 return dce_v8_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2794 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs
= {
2795 .dpms
= dce_v8_0_crtc_dpms
,
2796 .mode_fixup
= dce_v8_0_crtc_mode_fixup
,
2797 .mode_set
= dce_v8_0_crtc_mode_set
,
2798 .mode_set_base
= dce_v8_0_crtc_set_base
,
2799 .mode_set_base_atomic
= dce_v8_0_crtc_set_base_atomic
,
2800 .prepare
= dce_v8_0_crtc_prepare
,
2801 .commit
= dce_v8_0_crtc_commit
,
2802 .load_lut
= dce_v8_0_crtc_load_lut
,
2803 .disable
= dce_v8_0_crtc_disable
,
2806 static int dce_v8_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2808 struct amdgpu_crtc
*amdgpu_crtc
;
2811 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2812 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2813 if (amdgpu_crtc
== NULL
)
2816 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v8_0_crtc_funcs
);
2818 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2819 amdgpu_crtc
->crtc_id
= index
;
2820 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2822 amdgpu_crtc
->max_cursor_width
= CIK_CURSOR_WIDTH
;
2823 amdgpu_crtc
->max_cursor_height
= CIK_CURSOR_HEIGHT
;
2824 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2825 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2827 for (i
= 0; i
< 256; i
++) {
2828 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
2829 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
2830 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
2833 amdgpu_crtc
->crtc_offset
= crtc_offsets
[amdgpu_crtc
->crtc_id
];
2835 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2836 amdgpu_crtc
->adjusted_clock
= 0;
2837 amdgpu_crtc
->encoder
= NULL
;
2838 amdgpu_crtc
->connector
= NULL
;
2839 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v8_0_crtc_helper_funcs
);
2844 static int dce_v8_0_early_init(void *handle
)
2846 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2848 adev
->audio_endpt_rreg
= &dce_v8_0_audio_endpt_rreg
;
2849 adev
->audio_endpt_wreg
= &dce_v8_0_audio_endpt_wreg
;
2851 dce_v8_0_set_display_funcs(adev
);
2852 dce_v8_0_set_irq_funcs(adev
);
2854 adev
->mode_info
.num_crtc
= dce_v8_0_get_num_crtc(adev
);
2856 switch (adev
->asic_type
) {
2859 adev
->mode_info
.num_hpd
= 6;
2860 adev
->mode_info
.num_dig
= 6;
2863 adev
->mode_info
.num_hpd
= 6;
2864 adev
->mode_info
.num_dig
= 7;
2868 adev
->mode_info
.num_hpd
= 6;
2869 adev
->mode_info
.num_dig
= 6; /* ? */
2872 /* FIXME: not supported yet */
2879 static int dce_v8_0_sw_init(void *handle
)
2882 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2884 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2885 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
2890 for (i
= 8; i
< 20; i
+= 2) {
2891 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
2897 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
2901 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2903 adev
->ddev
->mode_config
.async_page_flip
= true;
2905 adev
->ddev
->mode_config
.max_width
= 16384;
2906 adev
->ddev
->mode_config
.max_height
= 16384;
2908 adev
->ddev
->mode_config
.preferred_depth
= 24;
2909 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2911 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
2913 r
= amdgpu_modeset_create_props(adev
);
2917 adev
->ddev
->mode_config
.max_width
= 16384;
2918 adev
->ddev
->mode_config
.max_height
= 16384;
2920 /* allocate crtcs */
2921 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2922 r
= dce_v8_0_crtc_init(adev
, i
);
2927 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2928 amdgpu_print_display_setup(adev
->ddev
);
2933 r
= dce_v8_0_afmt_init(adev
);
2937 r
= dce_v8_0_audio_init(adev
);
2941 drm_kms_helper_poll_init(adev
->ddev
);
2943 adev
->mode_info
.mode_config_initialized
= true;
2947 static int dce_v8_0_sw_fini(void *handle
)
2949 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2951 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2953 drm_kms_helper_poll_fini(adev
->ddev
);
2955 dce_v8_0_audio_fini(adev
);
2957 dce_v8_0_afmt_fini(adev
);
2959 drm_mode_config_cleanup(adev
->ddev
);
2960 adev
->mode_info
.mode_config_initialized
= false;
2965 static int dce_v8_0_hw_init(void *handle
)
2968 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2970 /* init dig PHYs, disp eng pll */
2971 amdgpu_atombios_encoder_init_dig(adev
);
2972 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
2974 /* initialize hpd */
2975 dce_v8_0_hpd_init(adev
);
2977 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2978 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2981 dce_v8_0_pageflip_interrupt_init(adev
);
2986 static int dce_v8_0_hw_fini(void *handle
)
2989 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2991 dce_v8_0_hpd_fini(adev
);
2993 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2994 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2997 dce_v8_0_pageflip_interrupt_fini(adev
);
3002 static int dce_v8_0_suspend(void *handle
)
3004 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3006 amdgpu_atombios_scratch_regs_save(adev
);
3008 return dce_v8_0_hw_fini(handle
);
3011 static int dce_v8_0_resume(void *handle
)
3013 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3016 ret
= dce_v8_0_hw_init(handle
);
3018 amdgpu_atombios_scratch_regs_restore(adev
);
3020 /* turn on the BL */
3021 if (adev
->mode_info
.bl_encoder
) {
3022 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3023 adev
->mode_info
.bl_encoder
);
3024 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3031 static bool dce_v8_0_is_idle(void *handle
)
3036 static int dce_v8_0_wait_for_idle(void *handle
)
3041 static int dce_v8_0_soft_reset(void *handle
)
3043 u32 srbm_soft_reset
= 0, tmp
;
3044 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3046 if (dce_v8_0_is_display_hung(adev
))
3047 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3049 if (srbm_soft_reset
) {
3050 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3051 tmp
|= srbm_soft_reset
;
3052 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3053 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3054 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3058 tmp
&= ~srbm_soft_reset
;
3059 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3060 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3062 /* Wait a little for things to settle down */
3068 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3070 enum amdgpu_interrupt_state state
)
3072 u32 reg_block
, lb_interrupt_mask
;
3074 if (crtc
>= adev
->mode_info
.num_crtc
) {
3075 DRM_DEBUG("invalid crtc %d\n", crtc
);
3081 reg_block
= CRTC0_REGISTER_OFFSET
;
3084 reg_block
= CRTC1_REGISTER_OFFSET
;
3087 reg_block
= CRTC2_REGISTER_OFFSET
;
3090 reg_block
= CRTC3_REGISTER_OFFSET
;
3093 reg_block
= CRTC4_REGISTER_OFFSET
;
3096 reg_block
= CRTC5_REGISTER_OFFSET
;
3099 DRM_DEBUG("invalid crtc %d\n", crtc
);
3104 case AMDGPU_IRQ_STATE_DISABLE
:
3105 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3106 lb_interrupt_mask
&= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK
;
3107 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3109 case AMDGPU_IRQ_STATE_ENABLE
:
3110 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3111 lb_interrupt_mask
|= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK
;
3112 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3119 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3121 enum amdgpu_interrupt_state state
)
3123 u32 reg_block
, lb_interrupt_mask
;
3125 if (crtc
>= adev
->mode_info
.num_crtc
) {
3126 DRM_DEBUG("invalid crtc %d\n", crtc
);
3132 reg_block
= CRTC0_REGISTER_OFFSET
;
3135 reg_block
= CRTC1_REGISTER_OFFSET
;
3138 reg_block
= CRTC2_REGISTER_OFFSET
;
3141 reg_block
= CRTC3_REGISTER_OFFSET
;
3144 reg_block
= CRTC4_REGISTER_OFFSET
;
3147 reg_block
= CRTC5_REGISTER_OFFSET
;
3150 DRM_DEBUG("invalid crtc %d\n", crtc
);
3155 case AMDGPU_IRQ_STATE_DISABLE
:
3156 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3157 lb_interrupt_mask
&= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
;
3158 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3160 case AMDGPU_IRQ_STATE_ENABLE
:
3161 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3162 lb_interrupt_mask
|= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
;
3163 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3170 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device
*adev
,
3171 struct amdgpu_irq_src
*src
,
3173 enum amdgpu_interrupt_state state
)
3175 u32 dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
;
3179 dc_hpd_int_cntl_reg
= mmDC_HPD1_INT_CONTROL
;
3182 dc_hpd_int_cntl_reg
= mmDC_HPD2_INT_CONTROL
;
3185 dc_hpd_int_cntl_reg
= mmDC_HPD3_INT_CONTROL
;
3188 dc_hpd_int_cntl_reg
= mmDC_HPD4_INT_CONTROL
;
3191 dc_hpd_int_cntl_reg
= mmDC_HPD5_INT_CONTROL
;
3194 dc_hpd_int_cntl_reg
= mmDC_HPD6_INT_CONTROL
;
3197 DRM_DEBUG("invalid hdp %d\n", type
);
3202 case AMDGPU_IRQ_STATE_DISABLE
:
3203 dc_hpd_int_cntl
= RREG32(dc_hpd_int_cntl_reg
);
3204 dc_hpd_int_cntl
&= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
;
3205 WREG32(dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
);
3207 case AMDGPU_IRQ_STATE_ENABLE
:
3208 dc_hpd_int_cntl
= RREG32(dc_hpd_int_cntl_reg
);
3209 dc_hpd_int_cntl
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
;
3210 WREG32(dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
);
3219 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device
*adev
,
3220 struct amdgpu_irq_src
*src
,
3222 enum amdgpu_interrupt_state state
)
3225 case AMDGPU_CRTC_IRQ_VBLANK1
:
3226 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3228 case AMDGPU_CRTC_IRQ_VBLANK2
:
3229 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3231 case AMDGPU_CRTC_IRQ_VBLANK3
:
3232 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3234 case AMDGPU_CRTC_IRQ_VBLANK4
:
3235 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3237 case AMDGPU_CRTC_IRQ_VBLANK5
:
3238 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3240 case AMDGPU_CRTC_IRQ_VBLANK6
:
3241 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3243 case AMDGPU_CRTC_IRQ_VLINE1
:
3244 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3246 case AMDGPU_CRTC_IRQ_VLINE2
:
3247 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3249 case AMDGPU_CRTC_IRQ_VLINE3
:
3250 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3252 case AMDGPU_CRTC_IRQ_VLINE4
:
3253 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3255 case AMDGPU_CRTC_IRQ_VLINE5
:
3256 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3258 case AMDGPU_CRTC_IRQ_VLINE6
:
3259 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3267 static int dce_v8_0_crtc_irq(struct amdgpu_device
*adev
,
3268 struct amdgpu_irq_src
*source
,
3269 struct amdgpu_iv_entry
*entry
)
3271 unsigned crtc
= entry
->src_id
- 1;
3272 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3273 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3275 switch (entry
->src_data
) {
3276 case 0: /* vblank */
3277 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3278 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], LB_VBLANK_STATUS__VBLANK_ACK_MASK
);
3280 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3282 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3283 drm_handle_vblank(adev
->ddev
, crtc
);
3285 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3288 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3289 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], LB_VLINE_STATUS__VLINE_ACK_MASK
);
3291 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3293 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3296 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3303 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device
*adev
,
3304 struct amdgpu_irq_src
*src
,
3306 enum amdgpu_interrupt_state state
)
3310 if (type
>= adev
->mode_info
.num_crtc
) {
3311 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3315 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3316 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3317 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3318 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3320 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3321 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3326 static int dce_v8_0_pageflip_irq(struct amdgpu_device
*adev
,
3327 struct amdgpu_irq_src
*source
,
3328 struct amdgpu_iv_entry
*entry
)
3330 unsigned long flags
;
3332 struct amdgpu_crtc
*amdgpu_crtc
;
3333 struct amdgpu_flip_work
*works
;
3335 crtc_id
= (entry
->src_id
- 8) >> 1;
3336 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3338 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3339 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3343 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3344 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3345 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3346 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3348 /* IRQ could occur when in initial stage */
3349 if (amdgpu_crtc
== NULL
)
3352 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3353 works
= amdgpu_crtc
->pflip_works
;
3354 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3355 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3356 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3357 amdgpu_crtc
->pflip_status
,
3358 AMDGPU_FLIP_SUBMITTED
);
3359 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3363 /* page flip completed. clean up */
3364 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3365 amdgpu_crtc
->pflip_works
= NULL
;
3367 /* wakeup usersapce */
3369 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, works
->event
);
3371 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3373 drm_crtc_vblank_put(&amdgpu_crtc
->base
);
3374 schedule_work(&works
->unpin_work
);
3379 static int dce_v8_0_hpd_irq(struct amdgpu_device
*adev
,
3380 struct amdgpu_irq_src
*source
,
3381 struct amdgpu_iv_entry
*entry
)
3383 uint32_t disp_int
, mask
, int_control
, tmp
;
3386 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3387 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3391 hpd
= entry
->src_data
;
3392 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3393 mask
= interrupt_status_offsets
[hpd
].hpd
;
3394 int_control
= hpd_int_control_offsets
[hpd
];
3396 if (disp_int
& mask
) {
3397 tmp
= RREG32(int_control
);
3398 tmp
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK
;
3399 WREG32(int_control
, tmp
);
3400 schedule_work(&adev
->hotplug_work
);
3401 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3408 static int dce_v8_0_set_clockgating_state(void *handle
,
3409 enum amd_clockgating_state state
)
3414 static int dce_v8_0_set_powergating_state(void *handle
,
3415 enum amd_powergating_state state
)
3420 const struct amd_ip_funcs dce_v8_0_ip_funcs
= {
3422 .early_init
= dce_v8_0_early_init
,
3424 .sw_init
= dce_v8_0_sw_init
,
3425 .sw_fini
= dce_v8_0_sw_fini
,
3426 .hw_init
= dce_v8_0_hw_init
,
3427 .hw_fini
= dce_v8_0_hw_fini
,
3428 .suspend
= dce_v8_0_suspend
,
3429 .resume
= dce_v8_0_resume
,
3430 .is_idle
= dce_v8_0_is_idle
,
3431 .wait_for_idle
= dce_v8_0_wait_for_idle
,
3432 .soft_reset
= dce_v8_0_soft_reset
,
3433 .set_clockgating_state
= dce_v8_0_set_clockgating_state
,
3434 .set_powergating_state
= dce_v8_0_set_powergating_state
,
3438 dce_v8_0_encoder_mode_set(struct drm_encoder
*encoder
,
3439 struct drm_display_mode
*mode
,
3440 struct drm_display_mode
*adjusted_mode
)
3442 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3444 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3446 /* need to call this here rather than in prepare() since we need some crtc info */
3447 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3449 /* set scaler clears this on some chips */
3450 dce_v8_0_set_interleave(encoder
->crtc
, mode
);
3452 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3453 dce_v8_0_afmt_enable(encoder
, true);
3454 dce_v8_0_afmt_setmode(encoder
, adjusted_mode
);
3458 static void dce_v8_0_encoder_prepare(struct drm_encoder
*encoder
)
3460 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3461 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3462 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3464 if ((amdgpu_encoder
->active_device
&
3465 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3466 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3467 ENCODER_OBJECT_ID_NONE
)) {
3468 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3470 dig
->dig_encoder
= dce_v8_0_pick_dig_encoder(encoder
);
3471 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3472 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3476 amdgpu_atombios_scratch_regs_lock(adev
, true);
3479 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3481 /* select the clock/data port if it uses a router */
3482 if (amdgpu_connector
->router
.cd_valid
)
3483 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3485 /* turn eDP panel on for mode set */
3486 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3487 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3488 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3491 /* this is needed for the pll/ss setup to work correctly in some cases */
3492 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3493 /* set up the FMT blocks */
3494 dce_v8_0_program_fmt(encoder
);
3497 static void dce_v8_0_encoder_commit(struct drm_encoder
*encoder
)
3499 struct drm_device
*dev
= encoder
->dev
;
3500 struct amdgpu_device
*adev
= dev
->dev_private
;
3502 /* need to call this here as we need the crtc set up */
3503 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3504 amdgpu_atombios_scratch_regs_lock(adev
, false);
3507 static void dce_v8_0_encoder_disable(struct drm_encoder
*encoder
)
3509 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3510 struct amdgpu_encoder_atom_dig
*dig
;
3512 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3514 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3515 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3516 dce_v8_0_afmt_enable(encoder
, false);
3517 dig
= amdgpu_encoder
->enc_priv
;
3518 dig
->dig_encoder
= -1;
3520 amdgpu_encoder
->active_device
= 0;
3523 /* these are handled by the primary encoders */
3524 static void dce_v8_0_ext_prepare(struct drm_encoder
*encoder
)
3529 static void dce_v8_0_ext_commit(struct drm_encoder
*encoder
)
3535 dce_v8_0_ext_mode_set(struct drm_encoder
*encoder
,
3536 struct drm_display_mode
*mode
,
3537 struct drm_display_mode
*adjusted_mode
)
3542 static void dce_v8_0_ext_disable(struct drm_encoder
*encoder
)
3548 dce_v8_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3553 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs
= {
3554 .dpms
= dce_v8_0_ext_dpms
,
3555 .prepare
= dce_v8_0_ext_prepare
,
3556 .mode_set
= dce_v8_0_ext_mode_set
,
3557 .commit
= dce_v8_0_ext_commit
,
3558 .disable
= dce_v8_0_ext_disable
,
3559 /* no detect for TMDS/LVDS yet */
3562 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs
= {
3563 .dpms
= amdgpu_atombios_encoder_dpms
,
3564 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3565 .prepare
= dce_v8_0_encoder_prepare
,
3566 .mode_set
= dce_v8_0_encoder_mode_set
,
3567 .commit
= dce_v8_0_encoder_commit
,
3568 .disable
= dce_v8_0_encoder_disable
,
3569 .detect
= amdgpu_atombios_encoder_dig_detect
,
3572 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs
= {
3573 .dpms
= amdgpu_atombios_encoder_dpms
,
3574 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3575 .prepare
= dce_v8_0_encoder_prepare
,
3576 .mode_set
= dce_v8_0_encoder_mode_set
,
3577 .commit
= dce_v8_0_encoder_commit
,
3578 .detect
= amdgpu_atombios_encoder_dac_detect
,
3581 static void dce_v8_0_encoder_destroy(struct drm_encoder
*encoder
)
3583 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3584 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3585 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3586 kfree(amdgpu_encoder
->enc_priv
);
3587 drm_encoder_cleanup(encoder
);
3588 kfree(amdgpu_encoder
);
3591 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs
= {
3592 .destroy
= dce_v8_0_encoder_destroy
,
3595 static void dce_v8_0_encoder_add(struct amdgpu_device
*adev
,
3596 uint32_t encoder_enum
,
3597 uint32_t supported_device
,
3600 struct drm_device
*dev
= adev
->ddev
;
3601 struct drm_encoder
*encoder
;
3602 struct amdgpu_encoder
*amdgpu_encoder
;
3604 /* see if we already added it */
3605 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3606 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3607 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3608 amdgpu_encoder
->devices
|= supported_device
;
3615 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3616 if (!amdgpu_encoder
)
3619 encoder
= &amdgpu_encoder
->base
;
3620 switch (adev
->mode_info
.num_crtc
) {
3622 encoder
->possible_crtcs
= 0x1;
3626 encoder
->possible_crtcs
= 0x3;
3629 encoder
->possible_crtcs
= 0xf;
3632 encoder
->possible_crtcs
= 0x3f;
3636 amdgpu_encoder
->enc_priv
= NULL
;
3638 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3639 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3640 amdgpu_encoder
->devices
= supported_device
;
3641 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3642 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3643 amdgpu_encoder
->is_ext_encoder
= false;
3644 amdgpu_encoder
->caps
= caps
;
3646 switch (amdgpu_encoder
->encoder_id
) {
3647 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3648 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3649 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3650 DRM_MODE_ENCODER_DAC
, NULL
);
3651 drm_encoder_helper_add(encoder
, &dce_v8_0_dac_helper_funcs
);
3653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3655 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3656 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3657 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3658 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3659 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3660 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3661 DRM_MODE_ENCODER_LVDS
, NULL
);
3662 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3663 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3664 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3665 DRM_MODE_ENCODER_DAC
, NULL
);
3666 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3668 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3669 DRM_MODE_ENCODER_TMDS
, NULL
);
3670 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3672 drm_encoder_helper_add(encoder
, &dce_v8_0_dig_helper_funcs
);
3674 case ENCODER_OBJECT_ID_SI170B
:
3675 case ENCODER_OBJECT_ID_CH7303
:
3676 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3677 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3678 case ENCODER_OBJECT_ID_TITFP513
:
3679 case ENCODER_OBJECT_ID_VT1623
:
3680 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3681 case ENCODER_OBJECT_ID_TRAVIS
:
3682 case ENCODER_OBJECT_ID_NUTMEG
:
3683 /* these are handled by the primary encoders */
3684 amdgpu_encoder
->is_ext_encoder
= true;
3685 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3686 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3687 DRM_MODE_ENCODER_LVDS
, NULL
);
3688 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3689 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3690 DRM_MODE_ENCODER_DAC
, NULL
);
3692 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3693 DRM_MODE_ENCODER_TMDS
, NULL
);
3694 drm_encoder_helper_add(encoder
, &dce_v8_0_ext_helper_funcs
);
3699 static const struct amdgpu_display_funcs dce_v8_0_display_funcs
= {
3700 .set_vga_render_state
= &dce_v8_0_set_vga_render_state
,
3701 .bandwidth_update
= &dce_v8_0_bandwidth_update
,
3702 .vblank_get_counter
= &dce_v8_0_vblank_get_counter
,
3703 .vblank_wait
= &dce_v8_0_vblank_wait
,
3704 .is_display_hung
= &dce_v8_0_is_display_hung
,
3705 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3706 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3707 .hpd_sense
= &dce_v8_0_hpd_sense
,
3708 .hpd_set_polarity
= &dce_v8_0_hpd_set_polarity
,
3709 .hpd_get_gpio_reg
= &dce_v8_0_hpd_get_gpio_reg
,
3710 .page_flip
= &dce_v8_0_page_flip
,
3711 .page_flip_get_scanoutpos
= &dce_v8_0_crtc_get_scanoutpos
,
3712 .add_encoder
= &dce_v8_0_encoder_add
,
3713 .add_connector
= &amdgpu_connector_add
,
3714 .stop_mc_access
= &dce_v8_0_stop_mc_access
,
3715 .resume_mc_access
= &dce_v8_0_resume_mc_access
,
3718 static void dce_v8_0_set_display_funcs(struct amdgpu_device
*adev
)
3720 if (adev
->mode_info
.funcs
== NULL
)
3721 adev
->mode_info
.funcs
= &dce_v8_0_display_funcs
;
3724 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs
= {
3725 .set
= dce_v8_0_set_crtc_interrupt_state
,
3726 .process
= dce_v8_0_crtc_irq
,
3729 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs
= {
3730 .set
= dce_v8_0_set_pageflip_interrupt_state
,
3731 .process
= dce_v8_0_pageflip_irq
,
3734 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs
= {
3735 .set
= dce_v8_0_set_hpd_interrupt_state
,
3736 .process
= dce_v8_0_hpd_irq
,
3739 static void dce_v8_0_set_irq_funcs(struct amdgpu_device
*adev
)
3741 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3742 adev
->crtc_irq
.funcs
= &dce_v8_0_crtc_irq_funcs
;
3744 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3745 adev
->pageflip_irq
.funcs
= &dce_v8_0_pageflip_irq_funcs
;
3747 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3748 adev
->hpd_irq
.funcs
= &dce_v8_0_hpd_irq_funcs
;