2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_7_1_d.h"
36 #include "gmc/gmc_7_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device
*adev
);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device
*adev
);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device
*adev
);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device
*adev
);
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
55 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
57 SDMA0_REGISTER_OFFSET
,
61 static const u32 golden_settings_iceland_a11
[] =
63 mmSDMA0_CHICKEN_BITS
, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL
, 0xff000fff, 0x00000000,
65 mmSDMA1_CHICKEN_BITS
, 0xfc910007, 0x00810007,
66 mmSDMA1_CLK_CTRL
, 0xff000fff, 0x00000000,
69 static const u32 iceland_mgcg_cgcg_init
[] =
71 mmSDMA0_CLK_CTRL
, 0xff000ff0, 0x00000100,
72 mmSDMA1_CLK_CTRL
, 0xff000ff0, 0x00000100
77 * Starting with CIK, the GPU has new asynchronous
78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
81 * and 2 queues used for compute.
83 * The programming model is very similar to the CP
84 * (ring buffer, IBs, etc.), but sDMA has it's own
85 * packet format that is different from the PM4 format
86 * used by the CP. sDMA supports copying data, writing
87 * embedded data, solid fills, and a number of other
88 * things. It also has support for tiling/detiling of
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device
*adev
)
94 switch (adev
->asic_type
) {
96 amdgpu_program_register_sequence(adev
,
97 iceland_mgcg_cgcg_init
,
98 (const u32
)ARRAY_SIZE(iceland_mgcg_cgcg_init
));
99 amdgpu_program_register_sequence(adev
,
100 golden_settings_iceland_a11
,
101 (const u32
)ARRAY_SIZE(golden_settings_iceland_a11
));
108 static void sdma_v2_4_free_microcode(struct amdgpu_device
*adev
)
111 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
112 release_firmware(adev
->sdma
.instance
[i
].fw
);
113 adev
->sdma
.instance
[i
].fw
= NULL
;
118 * sdma_v2_4_init_microcode - load ucode images from disk
120 * @adev: amdgpu_device pointer
122 * Use the firmware interface to load the ucode images into
123 * the driver (not loaded into hw).
124 * Returns 0 on success, error on failure.
126 static int sdma_v2_4_init_microcode(struct amdgpu_device
*adev
)
128 const char *chip_name
;
131 struct amdgpu_firmware_info
*info
= NULL
;
132 const struct common_firmware_header
*header
= NULL
;
133 const struct sdma_firmware_header_v1_0
*hdr
;
137 switch (adev
->asic_type
) {
144 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
146 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma.bin", chip_name
);
148 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_sdma1.bin", chip_name
);
149 err
= request_firmware(&adev
->sdma
.instance
[i
].fw
, fw_name
, adev
->dev
);
152 err
= amdgpu_ucode_validate(adev
->sdma
.instance
[i
].fw
);
155 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
156 adev
->sdma
.instance
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
157 adev
->sdma
.instance
[i
].feature_version
= le32_to_cpu(hdr
->ucode_feature_version
);
158 if (adev
->sdma
.instance
[i
].feature_version
>= 20)
159 adev
->sdma
.instance
[i
].burst_nop
= true;
161 if (adev
->firmware
.smu_load
) {
162 info
= &adev
->firmware
.ucode
[AMDGPU_UCODE_ID_SDMA0
+ i
];
163 info
->ucode_id
= AMDGPU_UCODE_ID_SDMA0
+ i
;
164 info
->fw
= adev
->sdma
.instance
[i
].fw
;
165 header
= (const struct common_firmware_header
*)info
->fw
->data
;
166 adev
->firmware
.fw_size
+=
167 ALIGN(le32_to_cpu(header
->ucode_size_bytes
), PAGE_SIZE
);
174 "sdma_v2_4: Failed to load firmware \"%s\"\n",
176 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
177 release_firmware(adev
->sdma
.instance
[i
].fw
);
178 adev
->sdma
.instance
[i
].fw
= NULL
;
185 * sdma_v2_4_ring_get_rptr - get the current read pointer
187 * @ring: amdgpu ring pointer
189 * Get the current rptr from the hardware (VI+).
191 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring
*ring
)
195 /* XXX check if swapping is necessary on BE */
196 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
] >> 2;
202 * sdma_v2_4_ring_get_wptr - get the current write pointer
204 * @ring: amdgpu ring pointer
206 * Get the current wptr from the hardware (VI+).
208 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring
*ring
)
210 struct amdgpu_device
*adev
= ring
->adev
;
211 int me
= (ring
== &ring
->adev
->sdma
.instance
[0].ring
) ? 0 : 1;
212 u32 wptr
= RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) >> 2;
218 * sdma_v2_4_ring_set_wptr - commit the write pointer
220 * @ring: amdgpu ring pointer
222 * Write the wptr back to the hardware (VI+).
224 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring
*ring
)
226 struct amdgpu_device
*adev
= ring
->adev
;
227 int me
= (ring
== &ring
->adev
->sdma
.instance
[0].ring
) ? 0 : 1;
229 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], ring
->wptr
<< 2);
232 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
)
234 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
237 for (i
= 0; i
< count
; i
++)
238 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
239 amdgpu_ring_write(ring
, ring
->nop
|
240 SDMA_PKT_NOP_HEADER_COUNT(count
- 1));
242 amdgpu_ring_write(ring
, ring
->nop
);
246 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
248 * @ring: amdgpu ring pointer
249 * @ib: IB object to schedule
251 * Schedule an IB in the DMA ring (VI).
253 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring
*ring
,
254 struct amdgpu_ib
*ib
,
255 unsigned vm_id
, bool ctx_switch
)
257 u32 vmid
= vm_id
& 0xf;
259 /* IB packet must end on a 8 DW boundary */
260 sdma_v2_4_ring_insert_nop(ring
, (10 - (ring
->wptr
& 7)) % 8);
262 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT
) |
263 SDMA_PKT_INDIRECT_HEADER_VMID(vmid
));
264 /* base must be 32 byte aligned */
265 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
) & 0xffffffe0);
266 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
267 amdgpu_ring_write(ring
, ib
->length_dw
);
268 amdgpu_ring_write(ring
, 0);
269 amdgpu_ring_write(ring
, 0);
274 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
276 * @ring: amdgpu ring pointer
278 * Emit an hdp flush packet on the requested DMA ring.
280 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
282 u32 ref_and_mask
= 0;
284 if (ring
== &ring
->adev
->sdma
.instance
[0].ring
)
285 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA0
, 1);
287 ref_and_mask
= REG_SET_FIELD(ref_and_mask
, GPU_HDP_FLUSH_DONE
, SDMA1
, 1);
289 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
290 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
291 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
292 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
293 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
294 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
295 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
296 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
297 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
300 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring
*ring
)
302 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
303 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
304 amdgpu_ring_write(ring
, mmHDP_DEBUG0
);
305 amdgpu_ring_write(ring
, 1);
308 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
310 * @ring: amdgpu ring pointer
311 * @fence: amdgpu fence object
313 * Add a DMA fence packet to the ring to write
314 * the fence seq number and DMA trap packet to generate
315 * an interrupt if needed (VI).
317 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
320 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
321 /* write the fence */
322 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
323 amdgpu_ring_write(ring
, lower_32_bits(addr
));
324 amdgpu_ring_write(ring
, upper_32_bits(addr
));
325 amdgpu_ring_write(ring
, lower_32_bits(seq
));
327 /* optionally write high bits as well */
330 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE
));
331 amdgpu_ring_write(ring
, lower_32_bits(addr
));
332 amdgpu_ring_write(ring
, upper_32_bits(addr
));
333 amdgpu_ring_write(ring
, upper_32_bits(seq
));
336 /* generate an interrupt */
337 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP
));
338 amdgpu_ring_write(ring
, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
342 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
344 * @adev: amdgpu_device pointer
346 * Stop the gfx async dma ring buffers (VI).
348 static void sdma_v2_4_gfx_stop(struct amdgpu_device
*adev
)
350 struct amdgpu_ring
*sdma0
= &adev
->sdma
.instance
[0].ring
;
351 struct amdgpu_ring
*sdma1
= &adev
->sdma
.instance
[1].ring
;
352 u32 rb_cntl
, ib_cntl
;
355 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
356 (adev
->mman
.buffer_funcs_ring
== sdma1
))
357 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
359 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
360 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
361 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 0);
362 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
363 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
364 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 0);
365 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
367 sdma0
->ready
= false;
368 sdma1
->ready
= false;
372 * sdma_v2_4_rlc_stop - stop the compute async dma engines
374 * @adev: amdgpu_device pointer
376 * Stop the compute async dma queues (VI).
378 static void sdma_v2_4_rlc_stop(struct amdgpu_device
*adev
)
384 * sdma_v2_4_enable - stop the async dma engines
386 * @adev: amdgpu_device pointer
387 * @enable: enable/disable the DMA MEs.
389 * Halt or unhalt the async dma engines (VI).
391 static void sdma_v2_4_enable(struct amdgpu_device
*adev
, bool enable
)
397 sdma_v2_4_gfx_stop(adev
);
398 sdma_v2_4_rlc_stop(adev
);
401 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
402 f32_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
404 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 0);
406 f32_cntl
= REG_SET_FIELD(f32_cntl
, SDMA0_F32_CNTL
, HALT
, 1);
407 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], f32_cntl
);
412 * sdma_v2_4_gfx_resume - setup and start the async dma engines
414 * @adev: amdgpu_device pointer
416 * Set up the gfx DMA ring buffers and enable them (VI).
417 * Returns 0 for success, error for failure.
419 static int sdma_v2_4_gfx_resume(struct amdgpu_device
*adev
)
421 struct amdgpu_ring
*ring
;
422 u32 rb_cntl
, ib_cntl
;
427 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
428 ring
= &adev
->sdma
.instance
[i
].ring
;
429 wb_offset
= (ring
->rptr_offs
* 4);
431 mutex_lock(&adev
->srbm_mutex
);
432 for (j
= 0; j
< 16; j
++) {
433 vi_srbm_select(adev
, 0, 0, 0, j
);
435 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
436 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
438 vi_srbm_select(adev
, 0, 0, 0, 0);
439 mutex_unlock(&adev
->srbm_mutex
);
441 WREG32(mmSDMA0_TILING_CONFIG
+ sdma_offsets
[i
],
442 adev
->gfx
.config
.gb_addr_config
& 0x70);
444 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
446 /* Set ring buffer size in dwords */
447 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
448 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
449 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SIZE
, rb_bufsz
);
451 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_SWAP_ENABLE
, 1);
452 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
,
453 RPTR_WRITEBACK_SWAP_ENABLE
, 1);
455 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
457 /* Initialize the ring buffer's read and write pointers */
458 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
459 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
460 WREG32(mmSDMA0_GFX_IB_RPTR
+ sdma_offsets
[i
], 0);
461 WREG32(mmSDMA0_GFX_IB_OFFSET
+ sdma_offsets
[i
], 0);
463 /* set the wb address whether it's enabled or not */
464 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
465 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
466 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
467 lower_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC);
469 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RPTR_WRITEBACK_ENABLE
, 1);
471 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
472 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
475 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
478 rb_cntl
= REG_SET_FIELD(rb_cntl
, SDMA0_GFX_RB_CNTL
, RB_ENABLE
, 1);
479 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
481 ib_cntl
= RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]);
482 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_ENABLE
, 1);
484 ib_cntl
= REG_SET_FIELD(ib_cntl
, SDMA0_GFX_IB_CNTL
, IB_SWAP_ENABLE
, 1);
487 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
492 sdma_v2_4_enable(adev
, true);
493 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
494 ring
= &adev
->sdma
.instance
[i
].ring
;
495 r
= amdgpu_ring_test_ring(ring
);
501 if (adev
->mman
.buffer_funcs_ring
== ring
)
502 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
509 * sdma_v2_4_rlc_resume - setup and start the async dma engines
511 * @adev: amdgpu_device pointer
513 * Set up the compute DMA queues and enable them (VI).
514 * Returns 0 for success, error for failure.
516 static int sdma_v2_4_rlc_resume(struct amdgpu_device
*adev
)
523 * sdma_v2_4_load_microcode - load the sDMA ME ucode
525 * @adev: amdgpu_device pointer
527 * Loads the sDMA0/1 ucode.
528 * Returns 0 for success, -EINVAL if the ucode is not available.
530 static int sdma_v2_4_load_microcode(struct amdgpu_device
*adev
)
532 const struct sdma_firmware_header_v1_0
*hdr
;
533 const __le32
*fw_data
;
538 sdma_v2_4_enable(adev
, false);
540 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
541 if (!adev
->sdma
.instance
[i
].fw
)
543 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
.instance
[i
].fw
->data
;
544 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
545 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
546 fw_data
= (const __le32
*)
547 (adev
->sdma
.instance
[i
].fw
->data
+
548 le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
549 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
550 for (j
= 0; j
< fw_size
; j
++)
551 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
552 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
.instance
[i
].fw_version
);
559 * sdma_v2_4_start - setup and start the async dma engines
561 * @adev: amdgpu_device pointer
563 * Set up the DMA engines and enable them (VI).
564 * Returns 0 for success, error for failure.
566 static int sdma_v2_4_start(struct amdgpu_device
*adev
)
570 if (!adev
->pp_enabled
) {
571 if (!adev
->firmware
.smu_load
) {
572 r
= sdma_v2_4_load_microcode(adev
);
576 r
= adev
->smu
.smumgr_funcs
->check_fw_load_finish(adev
,
577 AMDGPU_UCODE_ID_SDMA0
);
580 r
= adev
->smu
.smumgr_funcs
->check_fw_load_finish(adev
,
581 AMDGPU_UCODE_ID_SDMA1
);
587 /* halt the engine before programing */
588 sdma_v2_4_enable(adev
, false);
590 /* start the gfx rings and rlc compute queues */
591 r
= sdma_v2_4_gfx_resume(adev
);
594 r
= sdma_v2_4_rlc_resume(adev
);
602 * sdma_v2_4_ring_test_ring - simple async dma engine test
604 * @ring: amdgpu_ring structure holding ring information
606 * Test the DMA engine by writing using it to write an
607 * value to memory. (VI).
608 * Returns 0 for success, error for failure.
610 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring
*ring
)
612 struct amdgpu_device
*adev
= ring
->adev
;
619 r
= amdgpu_wb_get(adev
, &index
);
621 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
625 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
627 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
629 r
= amdgpu_ring_alloc(ring
, 5);
631 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
632 amdgpu_wb_free(adev
, index
);
636 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
637 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
));
638 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
639 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
640 amdgpu_ring_write(ring
, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
641 amdgpu_ring_write(ring
, 0xDEADBEEF);
642 amdgpu_ring_commit(ring
);
644 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
645 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
646 if (tmp
== 0xDEADBEEF)
651 if (i
< adev
->usec_timeout
) {
652 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
654 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
658 amdgpu_wb_free(adev
, index
);
664 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
666 * @ring: amdgpu_ring structure holding ring information
668 * Test a simple IB in the DMA ring (VI).
669 * Returns 0 on success, error on failure.
671 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
673 struct amdgpu_device
*adev
= ring
->adev
;
675 struct fence
*f
= NULL
;
681 r
= amdgpu_wb_get(adev
, &index
);
683 dev_err(adev
->dev
, "(%ld) failed to allocate wb slot\n", r
);
687 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
689 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
690 memset(&ib
, 0, sizeof(ib
));
691 r
= amdgpu_ib_get(adev
, NULL
, 256, &ib
);
693 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r
);
697 ib
.ptr
[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
698 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR
);
699 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
700 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
701 ib
.ptr
[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
702 ib
.ptr
[4] = 0xDEADBEEF;
703 ib
.ptr
[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
704 ib
.ptr
[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
705 ib
.ptr
[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
708 r
= amdgpu_ib_schedule(ring
, 1, &ib
, NULL
, NULL
, &f
);
712 r
= fence_wait_timeout(f
, false, timeout
);
714 DRM_ERROR("amdgpu: IB test timed out\n");
718 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
721 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
722 if (tmp
== 0xDEADBEEF) {
723 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);
726 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
731 amdgpu_ib_free(adev
, &ib
, NULL
);
734 amdgpu_wb_free(adev
, index
);
739 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
741 * @ib: indirect buffer to fill with commands
742 * @pe: addr of the page entry
743 * @src: src addr to copy from
744 * @count: number of page entries to update
746 * Update PTEs by copying them from the GART using sDMA (CIK).
748 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib
*ib
,
749 uint64_t pe
, uint64_t src
,
752 unsigned bytes
= count
* 8;
754 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
755 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
756 ib
->ptr
[ib
->length_dw
++] = bytes
;
757 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
758 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
759 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
760 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
761 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
765 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
767 * @ib: indirect buffer to fill with commands
768 * @pe: addr of the page entry
769 * @value: dst addr to write into pe
770 * @count: number of page entries to update
771 * @incr: increase next addr by incr bytes
773 * Update PTEs by writing them manually using sDMA (CIK).
775 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib
*ib
, uint64_t pe
,
776 uint64_t value
, unsigned count
,
779 unsigned ndw
= count
* 2;
781 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE
) |
782 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
783 ib
->ptr
[ib
->length_dw
++] = pe
;
784 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
785 ib
->ptr
[ib
->length_dw
++] = ndw
;
786 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
787 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(value
);
788 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
794 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
796 * @ib: indirect buffer to fill with commands
797 * @pe: addr of the page entry
798 * @addr: dst addr to write into pe
799 * @count: number of page entries to update
800 * @incr: increase next addr by incr bytes
801 * @flags: access flags
803 * Update the page tables using sDMA (CIK).
805 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib
*ib
, uint64_t pe
,
806 uint64_t addr
, unsigned count
,
807 uint32_t incr
, uint32_t flags
)
809 /* for physically contiguous pages (vram) */
810 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE
);
811 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
); /* dst addr */
812 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
813 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
814 ib
->ptr
[ib
->length_dw
++] = 0;
815 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(addr
); /* value */
816 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(addr
);
817 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
818 ib
->ptr
[ib
->length_dw
++] = 0;
819 ib
->ptr
[ib
->length_dw
++] = count
; /* number of entries */
823 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
825 * @ib: indirect buffer to fill with padding
828 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
)
830 struct amdgpu_sdma_instance
*sdma
= amdgpu_get_sdma_instance(ring
);
834 pad_count
= (8 - (ib
->length_dw
& 0x7)) % 8;
835 for (i
= 0; i
< pad_count
; i
++)
836 if (sdma
&& sdma
->burst_nop
&& (i
== 0))
837 ib
->ptr
[ib
->length_dw
++] =
838 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
) |
839 SDMA_PKT_NOP_HEADER_COUNT(pad_count
- 1);
841 ib
->ptr
[ib
->length_dw
++] =
842 SDMA_PKT_HEADER_OP(SDMA_OP_NOP
);
846 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
848 * @ring: amdgpu_ring pointer
850 * Make sure all previous operations are completed (CIK).
852 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring
*ring
)
854 uint32_t seq
= ring
->fence_drv
.sync_seq
;
855 uint64_t addr
= ring
->fence_drv
.gpu_addr
;
858 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
859 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
860 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
861 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
862 amdgpu_ring_write(ring
, addr
& 0xfffffffc);
863 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
864 amdgpu_ring_write(ring
, seq
); /* reference */
865 amdgpu_ring_write(ring
, 0xfffffff); /* mask */
866 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
867 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
871 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
873 * @ring: amdgpu_ring pointer
874 * @vm: amdgpu_vm pointer
876 * Update the page table base and flush the VM TLB
879 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
880 unsigned vm_id
, uint64_t pd_addr
)
882 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
883 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
885 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
887 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
889 amdgpu_ring_write(ring
, pd_addr
>> 12);
892 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE
) |
893 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
894 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
895 amdgpu_ring_write(ring
, 1 << vm_id
);
898 amdgpu_ring_write(ring
, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM
) |
899 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
900 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
901 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
902 amdgpu_ring_write(ring
, 0);
903 amdgpu_ring_write(ring
, 0); /* reference */
904 amdgpu_ring_write(ring
, 0); /* mask */
905 amdgpu_ring_write(ring
, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
906 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
909 static int sdma_v2_4_early_init(void *handle
)
911 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
913 adev
->sdma
.num_instances
= SDMA_MAX_INSTANCE
;
915 sdma_v2_4_set_ring_funcs(adev
);
916 sdma_v2_4_set_buffer_funcs(adev
);
917 sdma_v2_4_set_vm_pte_funcs(adev
);
918 sdma_v2_4_set_irq_funcs(adev
);
923 static int sdma_v2_4_sw_init(void *handle
)
925 struct amdgpu_ring
*ring
;
927 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
929 /* SDMA trap event */
930 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma
.trap_irq
);
934 /* SDMA Privileged inst */
935 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma
.illegal_inst_irq
);
939 /* SDMA Privileged inst */
940 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma
.illegal_inst_irq
);
944 r
= sdma_v2_4_init_microcode(adev
);
946 DRM_ERROR("Failed to load sdma firmware!\n");
950 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++) {
951 ring
= &adev
->sdma
.instance
[i
].ring
;
952 ring
->ring_obj
= NULL
;
953 ring
->use_doorbell
= false;
954 sprintf(ring
->name
, "sdma%d", i
);
955 r
= amdgpu_ring_init(adev
, ring
, 1024,
956 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP
), 0xf,
957 &adev
->sdma
.trap_irq
,
959 AMDGPU_SDMA_IRQ_TRAP0
: AMDGPU_SDMA_IRQ_TRAP1
,
960 AMDGPU_RING_TYPE_SDMA
);
968 static int sdma_v2_4_sw_fini(void *handle
)
970 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
973 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
974 amdgpu_ring_fini(&adev
->sdma
.instance
[i
].ring
);
976 sdma_v2_4_free_microcode(adev
);
980 static int sdma_v2_4_hw_init(void *handle
)
983 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
985 sdma_v2_4_init_golden_registers(adev
);
987 r
= sdma_v2_4_start(adev
);
994 static int sdma_v2_4_hw_fini(void *handle
)
996 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
998 sdma_v2_4_enable(adev
, false);
1003 static int sdma_v2_4_suspend(void *handle
)
1005 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1007 return sdma_v2_4_hw_fini(adev
);
1010 static int sdma_v2_4_resume(void *handle
)
1012 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1014 return sdma_v2_4_hw_init(adev
);
1017 static bool sdma_v2_4_is_idle(void *handle
)
1019 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1020 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1022 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1023 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1029 static int sdma_v2_4_wait_for_idle(void *handle
)
1033 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1035 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1036 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1037 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1046 static int sdma_v2_4_soft_reset(void *handle
)
1048 u32 srbm_soft_reset
= 0;
1049 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1050 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1052 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1054 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1055 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 0);
1056 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1057 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1059 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1061 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1062 tmp
= REG_SET_FIELD(tmp
, SDMA0_F32_CNTL
, HALT
, 0);
1063 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1064 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1067 if (srbm_soft_reset
) {
1068 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1069 tmp
|= srbm_soft_reset
;
1070 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1071 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1072 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1076 tmp
&= ~srbm_soft_reset
;
1077 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1078 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1080 /* Wait a little for things to settle down */
1087 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device
*adev
,
1088 struct amdgpu_irq_src
*src
,
1090 enum amdgpu_interrupt_state state
)
1095 case AMDGPU_SDMA_IRQ_TRAP0
:
1097 case AMDGPU_IRQ_STATE_DISABLE
:
1098 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1099 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1100 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1102 case AMDGPU_IRQ_STATE_ENABLE
:
1103 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1104 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1105 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1111 case AMDGPU_SDMA_IRQ_TRAP1
:
1113 case AMDGPU_IRQ_STATE_DISABLE
:
1114 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1115 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 0);
1116 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1118 case AMDGPU_IRQ_STATE_ENABLE
:
1119 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1120 sdma_cntl
= REG_SET_FIELD(sdma_cntl
, SDMA0_CNTL
, TRAP_ENABLE
, 1);
1121 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1133 static int sdma_v2_4_process_trap_irq(struct amdgpu_device
*adev
,
1134 struct amdgpu_irq_src
*source
,
1135 struct amdgpu_iv_entry
*entry
)
1137 u8 instance_id
, queue_id
;
1139 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1140 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1141 DRM_DEBUG("IH: SDMA trap\n");
1142 switch (instance_id
) {
1146 amdgpu_fence_process(&adev
->sdma
.instance
[0].ring
);
1159 amdgpu_fence_process(&adev
->sdma
.instance
[1].ring
);
1173 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1174 struct amdgpu_irq_src
*source
,
1175 struct amdgpu_iv_entry
*entry
)
1177 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1178 schedule_work(&adev
->reset_work
);
1182 static int sdma_v2_4_set_clockgating_state(void *handle
,
1183 enum amd_clockgating_state state
)
1185 /* XXX handled via the smc on VI */
1189 static int sdma_v2_4_set_powergating_state(void *handle
,
1190 enum amd_powergating_state state
)
1195 const struct amd_ip_funcs sdma_v2_4_ip_funcs
= {
1196 .name
= "sdma_v2_4",
1197 .early_init
= sdma_v2_4_early_init
,
1199 .sw_init
= sdma_v2_4_sw_init
,
1200 .sw_fini
= sdma_v2_4_sw_fini
,
1201 .hw_init
= sdma_v2_4_hw_init
,
1202 .hw_fini
= sdma_v2_4_hw_fini
,
1203 .suspend
= sdma_v2_4_suspend
,
1204 .resume
= sdma_v2_4_resume
,
1205 .is_idle
= sdma_v2_4_is_idle
,
1206 .wait_for_idle
= sdma_v2_4_wait_for_idle
,
1207 .soft_reset
= sdma_v2_4_soft_reset
,
1208 .set_clockgating_state
= sdma_v2_4_set_clockgating_state
,
1209 .set_powergating_state
= sdma_v2_4_set_powergating_state
,
1212 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs
= {
1213 .get_rptr
= sdma_v2_4_ring_get_rptr
,
1214 .get_wptr
= sdma_v2_4_ring_get_wptr
,
1215 .set_wptr
= sdma_v2_4_ring_set_wptr
,
1217 .emit_ib
= sdma_v2_4_ring_emit_ib
,
1218 .emit_fence
= sdma_v2_4_ring_emit_fence
,
1219 .emit_pipeline_sync
= sdma_v2_4_ring_emit_pipeline_sync
,
1220 .emit_vm_flush
= sdma_v2_4_ring_emit_vm_flush
,
1221 .emit_hdp_flush
= sdma_v2_4_ring_emit_hdp_flush
,
1222 .emit_hdp_invalidate
= sdma_v2_4_ring_emit_hdp_invalidate
,
1223 .test_ring
= sdma_v2_4_ring_test_ring
,
1224 .test_ib
= sdma_v2_4_ring_test_ib
,
1225 .insert_nop
= sdma_v2_4_ring_insert_nop
,
1226 .pad_ib
= sdma_v2_4_ring_pad_ib
,
1229 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device
*adev
)
1233 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1234 adev
->sdma
.instance
[i
].ring
.funcs
= &sdma_v2_4_ring_funcs
;
1237 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs
= {
1238 .set
= sdma_v2_4_set_trap_irq_state
,
1239 .process
= sdma_v2_4_process_trap_irq
,
1242 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs
= {
1243 .process
= sdma_v2_4_process_illegal_inst_irq
,
1246 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device
*adev
)
1248 adev
->sdma
.trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1249 adev
->sdma
.trap_irq
.funcs
= &sdma_v2_4_trap_irq_funcs
;
1250 adev
->sdma
.illegal_inst_irq
.funcs
= &sdma_v2_4_illegal_inst_irq_funcs
;
1254 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1256 * @ring: amdgpu_ring structure holding ring information
1257 * @src_offset: src GPU address
1258 * @dst_offset: dst GPU address
1259 * @byte_count: number of bytes to xfer
1261 * Copy GPU buffers using the DMA engine (VI).
1262 * Used by the amdgpu ttm implementation to move pages if
1263 * registered as the asic copy callback.
1265 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib
*ib
,
1266 uint64_t src_offset
,
1267 uint64_t dst_offset
,
1268 uint32_t byte_count
)
1270 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY
) |
1271 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR
);
1272 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1273 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
1274 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src_offset
);
1275 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src_offset
);
1276 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1277 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1281 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1283 * @ring: amdgpu_ring structure holding ring information
1284 * @src_data: value to write to buffer
1285 * @dst_offset: dst GPU address
1286 * @byte_count: number of bytes to xfer
1288 * Fill GPU buffers using the DMA engine (VI).
1290 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib
*ib
,
1292 uint64_t dst_offset
,
1293 uint32_t byte_count
)
1295 ib
->ptr
[ib
->length_dw
++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL
);
1296 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(dst_offset
);
1297 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dst_offset
);
1298 ib
->ptr
[ib
->length_dw
++] = src_data
;
1299 ib
->ptr
[ib
->length_dw
++] = byte_count
;
1302 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs
= {
1303 .copy_max_bytes
= 0x1fffff,
1305 .emit_copy_buffer
= sdma_v2_4_emit_copy_buffer
,
1307 .fill_max_bytes
= 0x1fffff,
1309 .emit_fill_buffer
= sdma_v2_4_emit_fill_buffer
,
1312 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device
*adev
)
1314 if (adev
->mman
.buffer_funcs
== NULL
) {
1315 adev
->mman
.buffer_funcs
= &sdma_v2_4_buffer_funcs
;
1316 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
.instance
[0].ring
;
1320 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs
= {
1321 .copy_pte
= sdma_v2_4_vm_copy_pte
,
1322 .write_pte
= sdma_v2_4_vm_write_pte
,
1323 .set_pte_pde
= sdma_v2_4_vm_set_pte_pde
,
1326 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1330 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1331 adev
->vm_manager
.vm_pte_funcs
= &sdma_v2_4_vm_pte_funcs
;
1332 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
1333 adev
->vm_manager
.vm_pte_rings
[i
] =
1334 &adev
->sdma
.instance
[i
].ring
;
1336 adev
->vm_manager
.vm_pte_num_rings
= adev
->sdma
.num_instances
;